From 9c9ea291579c2b278687e14b63844916aaea6266 Mon Sep 17 00:00:00 2001 From: imi415 Date: Sat, 6 Aug 2022 10:41:07 +0800 Subject: [PATCH] Seperated initialization to bootloader. --- .gitmodules | 3 + CMakeLists.txt | 6 +- include/stx7105.h | 20 +- include/stx7105_utils.h | 11 + lib/printf | 1 + src/main.c | 99 ++----- src/stx7105_utils.c | 41 +++ startup_stx7105.S | 337 +---------------------- startup_stx7105_init_ram.S | 281 ------------------- stx7105.ld | 7 +- vendor/pdk7105.romgen | 549 ------------------------------------- 11 files changed, 117 insertions(+), 1238 deletions(-) create mode 100644 .gitmodules create mode 100644 include/stx7105_utils.h create mode 160000 lib/printf create mode 100644 src/stx7105_utils.c delete mode 100644 startup_stx7105_init_ram.S delete mode 100755 vendor/pdk7105.romgen diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..4de5efe --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "lib/printf"] + path = lib/printf + url = https://github.com/mpaland/printf.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 2bbc3ae..a95f8de 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -7,17 +7,19 @@ project(hello) set(TARGET_LDSCRIPT "${CMAKE_SOURCE_DIR}/stx7105.ld") set(TARGET_SOURCES + "lib/printf/printf.c" "src/main.c" "src/stx7105_exc.c" + "src/stx7105_utils.c" "startup_stx7105.S" - "startup_stx7105_init_ram.S" ) set(TARGET_INCLUDES "include" + "lib/printf" ) -set(TARGET_FLAGS_HARDWARE "-m4a -ml") +set(TARGET_FLAGS_HARDWARE "-m4-300 -ml") set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -g -O0") set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -g -O0") diff --git a/include/stx7105.h b/include/stx7105.h index bed27ed..8653529 100644 --- a/include/stx7105.h +++ b/include/stx7105.h @@ -6,7 +6,7 @@ #define __PACKED __attribute__((packed, aligned(1))) #define __IO volatile -typedef struct __PACKED { +typedef struct { __IO uint8_t POUT; /* Offset: 0x00, GPIO pin output register */ __IO uint8_t UNUSED0[3]; /* Offset: 0x01 */ __IO uint8_t SET_POUT; /* Offset: 0x04, GPIO pin output set register */ @@ -46,7 +46,7 @@ typedef struct __PACKED { __IO uint8_t CLR_PMASK; /* Offset: 0x68, GPIO pin input comparison mask clear regiser */ } PIO_TypeDef; -typedef struct __PACKED { +typedef struct { __IO uint32_t BAUDRATE; /* Offset: 0x00, ASCn baud rate generator register */ __IO uint32_t TX_BUF; /* Offset: 0x04, ASCn transmit buffer register */ __IO uint32_t RX_BUF; /* Offset: 0x08, ASCn receive buffer register */ @@ -60,26 +60,28 @@ typedef struct __PACKED { __IO uint32_t RETRIES; /* Offset: 0x28, ASCn number of retries on transmission register */ } ASC_TypeDef; -typedef struct __PACKED { +typedef struct { __IO uint8_t TOCR; /* Offset: 0x00, Timer output control register */ - __IO uint8_t UNUSED0[3]; /* Offset: 0x01 */ + uint8_t UNUSED0[3]; /* Offset: 0x01 */ __IO uint8_t TSTR; /* Offset: 0x04, Timer start register */ - __IO uint8_t UNUSED1[3]; /* Offset: 0x05 */ + uint8_t UNUSED1[3]; /* Offset: 0x05 */ __IO uint32_t TCOR0; /* Offset: 0x08, Timer constant register 0 */ __IO uint32_t TCNT0; /* Offset: 0x0C, Timer counter 0 */ __IO uint16_t TCR0; /* Offset: 0x10, Timer control register 0 */ - __IO uint8_t UNUSED2[2]; /* Offset: 0x11 */ + uint8_t UNUSED2[2]; /* Offset: 0x11 */ __IO uint32_t TCOR1; /* Offset: 0x14, Timer constant register 1 */ __IO uint32_t TCNT1; /* Offset: 0x18, Timer counter 1 */ __IO uint16_t TCR1; /* Offset: 0x1C, Timer control register 1 */ - __IO uint8_t UNUSED3[2]; /* Offset: 0x1D */ + uint8_t UNUSED3[2]; /* Offset: 0x1E */ __IO uint32_t TCOR2; /* Offset: 0x20, Timer constant register 2 */ __IO uint32_t TCNT2; /* Offset: 0x24, Timer counter 2 */ __IO uint16_t TCR2; /* Offset: 0x28, Timer control register 2 */ - __IO uint8_t UNUSED4[2]; /* Offset: 0x29 */ - __IO uint32_t TCPR2; /* Offset: 0x2C */ + __IO uint8_t UNUSED4[2]; /* Offset: 0x2A */ + uint32_t TCPR2; /* Offset: 0x2C */ } TMU_TypeDef; +#define XX sizeof(TMU_TypeDef) + #define PIO0_BASE (0xFD020000U) #define PIO4_BASE (0xFD024000U) #define ASC0_BASE (0xFD030000U) diff --git a/include/stx7105_utils.h b/include/stx7105_utils.h new file mode 100644 index 0000000..5cc2b2b --- /dev/null +++ b/include/stx7105_utils.h @@ -0,0 +1,11 @@ +#ifndef STX7105_UTILS_H +#define STX7105_UTILS_H + +#include + +void init_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t init_value); +void set_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t val); + +void delay_ms(uint32_t msec); + +#endif \ No newline at end of file diff --git a/lib/printf b/lib/printf new file mode 160000 index 0000000..d3b9846 --- /dev/null +++ b/lib/printf @@ -0,0 +1 @@ +Subproject commit d3b984684bb8a8bdc48cc7a1abecb93ce59bbe3e diff --git a/src/main.c b/src/main.c index 72a830e..58982f6 100644 --- a/src/main.c +++ b/src/main.c @@ -1,7 +1,9 @@ #include #include +#include "printf.h" #include "stx7105.h" +#include "stx7105_utils.h" #define LED_RED_GPIO PIO0 #define LED_RED_PIN 5U @@ -14,88 +16,43 @@ #define SYSTEM_CONFIG34 (0xFE001188U) /* PIO4 */ #define SYSTEM_CONFIG7 (0xFE00111CU) /* RXSEL */ -static void set_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t val); +void uart_init(void) { + PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */ + PIO4->SET_PC1 = 1U; + PIO4->SET_PC2 = 1U; -static void init_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t init_value) { - gpiox->CLR_PC0 = 1 << pin; - gpiox->SET_PC1 = 1 << pin; - gpiox->CLR_PC2 = 1 << pin; + *(uint32_t *)SYSTEM_CONFIG34 = 0x00000100UL; /* BIT[8,0] = 10, AF 3 */ + *(uint32_t *)SYSTEM_CONFIG7 &= ~(0x00000006UL); /* BIT[2:1], UART2 RX SEL */ - set_led(gpiox, pin, init_value); -} - -static void set_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t val) { - if (val) { - gpiox->SET_POUT = (1 << pin); - - } else { - gpiox->CLR_POUT = (1 << pin); - } -} - -static void delay_ms(uint32_t msec) { - /* Initialize TMU and count to zero */ - /* TMU clock is from Peripheral clock, approx. 66MHz */ - /* Prescale to 66kHz for convenience (TMUs can only divide by max. 1024) */ - - uint32_t reload_value = msec * 66 - 1; - - TMU->TSTR &= ~1U; /* Stop counter */ - TMU->TCR0 = 0x04U; /* 1024 prescale */ - TMU->TCNT0 = reload_value; /* 66kHz */ - TMU->TCOR0 = reload_value; /* Reload register */ - TMU->TSTR |= 1U; /* Start counter */ - - /* Wait until underflow occurs */ - uint16_t tcr0 = 0U; - do { - tcr0 = TMU->TCR0; - } while ((tcr0 & 0x100) == 0); - - TMU->TSTR &= ~1U; /* Stop counter */ -} - -static void uart_init(void) { - // PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */ - // PIO4->SET_PC1 = 1U; - // PIO4->SET_PC2 = 1U; - - // *(uint32_t *)SYSTEM_CONFIG34 = 0x00000100UL; /* BIT[8,0] = 10, AF 3 */ - // *(uint32_t *)SYSTEM_CONFIG7 &= ~(0x00000006UL); /* BIT[2:1], UART2 RX SEL */ - - // CONSOLE_ASC->CTRL = 0x1509UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */ - // CONSOLE_ASC->BAUDRATE = 0x04B8UL; /* 115200 in baud mode 1, assuming Fcomm=100MHz */ - // CONSOLE_ASC->TX_RST = 0x01UL; /* Reset TX FIFO, any value OK */ - // CONSOLE_ASC->RX_RST = 0x01UL; /* Reset RX FIFO, any value OK */ - // CONSOLE_ASC->CTRL = 0x1589UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */ + CONSOLE_ASC->CTRL = 0x1509UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */ + CONSOLE_ASC->BAUDRATE = 0x04B8UL; /* 115200 in baud mode 1, assuming Fcomm=100MHz */ + CONSOLE_ASC->TX_RST = 0x01UL; /* Reset TX FIFO, any value OK */ + CONSOLE_ASC->RX_RST = 0x01UL; /* Reset RX FIFO, any value OK */ + CONSOLE_ASC->CTRL = 0x1589UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */ } int main(void) { - // init_led(LED_RED_GPIO, LED_RED_PIN, 0U); - // init_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U); - - // if(*(uint32_t *)SYSTEM_DEVID != 0x2D43E041UL) { - // set_led(LED_RED_GPIO, LED_RED_PIN, 1U); - // } + init_led(LED_RED_GPIO, LED_RED_PIN, 0U); + init_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U); uart_init(); - // for (uint16_t i = 0; i < 65534; i++) { - // CONSOLE_ASC->TX_BUF = i; - // while (CONSOLE_ASC->STA & 0x200) { - // /**/ - // } - // } - - // printf("Hello world\r\n"); + printf("Hello world\r\n"); for (;;) { - /* Dead loop */ - // set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 1); - // delay_ms(1000); - // set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0); - // delay_ms(1000); + set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 1U); + delay_ms(500); + printf("Hello ?\r\n"); + set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U); + delay_ms(500); } return 0; +} + +void _putchar(char ch) { + while(CONSOLE_ASC->STA & 1 << 9U) { + // wait for TX FIFO slot. + } + CONSOLE_ASC->TX_BUF = ch; } \ No newline at end of file diff --git a/src/stx7105_utils.c b/src/stx7105_utils.c new file mode 100644 index 0000000..20a0912 --- /dev/null +++ b/src/stx7105_utils.c @@ -0,0 +1,41 @@ +#include "stx7105.h" +#include "stx7105_utils.h" + +void init_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t init_value) { + gpiox->CLR_PC0 = 1 << pin; + gpiox->SET_PC1 = 1 << pin; + gpiox->CLR_PC2 = 1 << pin; + + set_led(gpiox, pin, init_value); +} + +void set_led(PIO_TypeDef *gpiox, uint8_t pin, uint8_t val) { + if (val) { + gpiox->SET_POUT = (1 << pin); + + } else { + gpiox->CLR_POUT = (1 << pin); + } +} + +void delay_ms(uint32_t msec) { + /* Initialize TMU and count to zero */ + /* TMU clock is from Peripheral clock, approx. 66MHz */ + /* Prescale to 66kHz for convenience (TMUs can only divide by max. 1024) */ + + uint32_t reload_value = msec * 66 - 1; + + TMU->TSTR &= ~1U; /* Stop counter */ + TMU->TCR0 = 0x04U; /* 1024 prescale */ + TMU->TCNT0 = reload_value; /* 66kHz */ + TMU->TCOR0 = reload_value; /* Reload register */ + TMU->TSTR |= 1U; /* Start counter */ + + /* Wait until underflow occurs */ + uint16_t tcr0 = 0U; + do { + tcr0 = TMU->TCR0; + } while ((tcr0 & 0x100) == 0); + + TMU->TSTR &= ~1U; /* Stop counter */ +} \ No newline at end of file diff --git a/startup_stx7105.S b/startup_stx7105.S index b0cbfda..896a7c1 100644 --- a/startup_stx7105.S +++ b/startup_stx7105.S @@ -1,163 +1,25 @@ +/* + * This section is read by bootloader, then the application will be copied. + * DO NOT REMOVE. + * See SPL README for details. + */ + + .section .text.vtors, "ax" +_vtors: + .long _eidata + .long _start + /* Startup code, we can't use non-PIC code nor RAM before the LMI is initialized: * The CPU starts with physical address 0x0, however the linker is linked to virtual * addresses and LMI. * Non-PIC code means any indirect addressing other than relative to PC. */ - .section .text.init, "ax" + .section .text.init .global _start _start: - nop - nop -/* Initialize Blue LED P0_4 */ - mov #16, r0 - mov.l _gpio_clr_k, r1 - mov.l r0, @r1 - mov.l _gpio_clr_pc0_k, r1 - mov.l r0, @r1 - mov.l _gpio_set_pc1_k, r1 - mov.l r0, @r1 - mov.l _gpio_clr_pc2_k, r1 - mov.l r0, @r1 - -/* Initialize Red LED P0_5 */ - mov #32, r0 - mov.l _gpio_clr_k, r1 - mov.l r0, @r1 - mov.l _gpio_clr_pc0_k, r1 - mov.l r0, @r1 - mov.l _gpio_set_pc1_k, r1 - mov.l r0, @r1 - mov.l _gpio_clr_pc2_k, r1 - mov.l r0, @r1 - mov.l _sr_k, r0 - ldc r0, sr mov.l _stack_k, sp /* Setup R15(SP) */ -_disable_wdt: - mov.l _cpg_wdt_wtcsr_k, r0 - mov.l _cpg_wdt_wtcsr_value_k, r1 - mov.w r1, @r0 - -_configure_spinor: - mov.l _emi_spinor_config_data_k, r0 - mov.l _emi_spinor_config_data_value_k, r1 - mov.l r1, @r0 - mov.l _emi_spinor_modeselect_k, r0 - mov.l _emi_spinor_modeselect_value_k, r1 - mov.l r1, @r0 - -/* TODO: Initialize PMB, setup caches !! */ - -/* - * We need PMBs for LMI and EMI, both cached and uncached. - * To configure an PMB region, two register writes need to be issued: - * 1: Write to PMB address array, with region virtual address. - * The PMB address array entry is calculated as follows: - * - PMB_SLOT_X_ADDR=0xF610_0X00, X=0-F, with a maximum of 16 regions. - * The slot contents are defined as follows: - * - 0xAA00_0100, AA=Virtual page number, bit 31:30 has to be 0b10 - * i.e. VA should located in range 0x8000_0000 - 0xBFFF_FFFF - * Note: VA needs to align with its configured size. - * 2: Write to PMB data array, with region size and cache modes. - * The PMB data array entry is calculated as follows: - * PMB_SLOT_X_DATA=0xF710_0X00, X=0-F, with a maximum of 16 regions. - */ -_invalidate_pmb: - mov.l _pmb_address_base, r1 /* PMB address slot base address */ - mov #0, r2 /* Value to be written to PMB address slot */ - mov #1, r3 /* PMB address stride, 0x100 */ - shll8 r3 /* See above */ - mov #0, r0 /* Counter */ - -_loop_invalid_pmb: - mov.l r2, @r1 /* Clear slot N */ - add r3, r1 /* Slot += 1 */ - cmp/eq #15, r0 /* Counter == 15? */ - bf/s _loop_invalid_pmb /* Note: this is a delayed branch, be careful. */ - add #1, r0 /* Counter += 1 */ - -_setup_pmb: - mova _pmb_poke_start_k, r0 - mov r0, r1 - mova _pmb_poke_end_k, r0 - mov r0, r2 - -_loop_setup_pmb: - mov.l @r1+, r0 /* 1st word, register address */ - mov.l @r1+, r3 /* 2nd word, register value */ - mov.l r3, @r0 - cmp/gt r1, r2 - bt _loop_setup_pmb - -_invalidate_caches: - mov.l _ccn_ccr_k, r0 - mov #0, r1 - mov.l r1, @r0 /* Clear all bits */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - -_setup_caches: - mov.l _ccn_ccr_value_k, r1 - mov.l r1, @r0 - nop - nop - nop - nop - nop - nop - nop - nop - nop - -_enter_p0: - mova _init_lmi, r0 - mov #0xE0, r1 - shll16 r1 - shll8 r1 - not r1, r1 /* MASK is 0x1fffffff */ - and r1, r0 /* unset top 3-bits */ - jmp @r0 - nop - - .balign 4 -/* TODO: Initialize LMI */ -_init_lmi: - mov.l _init_ram_k, r1 /* Load actual function address to r1 */ - jsr @r1 /* Jump to the init_ram function */ - nop - -/* TODO: Switch to 32-bit mode */ -_enable_se_mode: - mov.l _ccn_mmucr_k, r0 - mov #4, r1 /* SH4_MMUCR_TI */ - mov.l r1, @r0 - - mov.l _ccn_pascr_k, r0 - mov.l _ccn_pascr_value_k, r1 - mov.l r1, @r0 - -_setup_irq: - mov.l _exc_base_k, r0 - ldc r0, vbr - -_go_non_privileged: - mov.l _crt0_entry, r0 - ldc r0, spc - stc sr, r0 - ldc r0, ssr - rte - nop - -/* RTE has to be aligned */ - .align 4 _copy_data: mov.l _sidata_k, r0 mov.l _sdata_k, r1 @@ -181,80 +43,14 @@ _loop_zero_bss: cmp/gt r0, r1 bt _loop_zero_bss -/* Turn on Blue LED */ - mov #16, r7 - mov.l _gpio_set_k, r8 - mov.l r7, @r8 - _setup_fpu: mov.l _set_fpscr_k, r1 jsr @r1 mov #0, r4 lds r3, fpscr -/* Try to enable UART from Assembly... */ - mov.l _system_config_34_k, r0 - mov.l _system_config_34_value_k, r1 - mov.l r1, @r0 - - mov.l _gpio4_clr_pc0_k, r0 - mov #1, r1 - mov.b r1, @r0 - mov.l _gpio4_set_pc1_k, r0 - mov.b r1, @r0 - mov.l _gpio4_set_pc2_k, r0 - mov.b r1, @r0 - - mov.l _asc2_baud_k, r0 - mov.l _asc2_baud_value_k, r1 - mov.l r1, @r0 - mov.l _asc2_ctrl_k, r0 - mov.l _asc2_ctrl_value_k, r1 - mov.l r1, @r0 - mov.l _asc2_tx_buf_k, r0 - mov #65, r1 - mov.b r1, @r0 - - -_memory_test: - mov.l _sdata_k, r0 - mov.l _stack_k, r1 - -_loop_memory_write: - mov.l r1, @-r1 - cmp/gt r0, r1 - bt _loop_memory_write - -_memory_compare: - mov.l _stack_k, r1 -_loop_memory_compare: - mov r1, r3 - mov.l @r1+, r2 - cmp/eq r2, r3 - bt _loop_memory_compare_addr - mova _memory_fail_set_led, r0 - jmp @r0 - nop -_loop_memory_compare_addr: - cmp/gt r0, r1 - bt _loop_memory_compare - mova _main_entry, r0 - jmp @r0 - nop - .align 2 -_memory_fail_set_led: -/* Turn on Red LED */ - mov #32, r7 - mov.l _gpio_set_k, r8 - mov.l r7, @r8 - .align 2 _main_entry: -/* Turn off Blue LED */ - mov #16, r7 - mov.l _gpio_clr_k, r8 - mov.l r7, @r8 - mov.l _main_k, r0 jsr @r0 or r0, r0 @@ -264,112 +60,7 @@ _main_entry: jsr @r0 or r0, r0 -/* It would be more efficient by using indirect addressing instead of 8 instructions... */ -/* Align to 4 byte boundary since we are loading the whole word */ - .align 4 - -/* PMB address register */ -_pmb_address_base: - .long 0xF6100000 - -/* PMB poke tables */ -_pmb_poke_start_k: - .long 0xF6100000 /* Address entry #0 register : LMI lower half, 128MB, mapped to 0x8000_0000 */ - .long 0x80000100 /* Address entry #0 data : LMI lower half, 128MB, mapped to 0x8000_0000 */ - .long 0xF6100100 /* Address entry #1 register : LMI higher half, 128MB, mapped to 0x8800_0000 */ - .long 0x88000100 /* Address entry #1 data : LMI higher half, 128MB, mapped to 0x8800_0000 */ - .long 0xF6100200 /* Address entry #2 register : LMI lower half, 128MB, mapped to 0x9000_0000 */ - .long 0x90000100 /* Address entry #2 data : LMI lower half, 128MB, mapped to 0x9000_0000 */ - .long 0xF6100300 /* Address entry #3 register : LMI higher half, 128MB, mapped to 0x9800_0000 */ - .long 0x98000100 /* Address entry #3 data : LMI higher half, 128MB, mapped to 0x9800_0000 */ - .long 0xF6100400 /* Address entry #4 register : EMI NOR uncached, 64MB, mapped to 0xA000_0000 */ - .long 0xA0000100 /* Address entry #4 data : EMI NOR uncached, 64MB, mapped to 0xA000_0000 */ - .long 0xF6100500 /* Address entry #5 register : EMI NOR cached, 64MB, mapped to 0xA400_0000 */ - .long 0xA4000100 /* Address entry #5 data : EMI NOR cached, 64MB, mapped to 0xA400_0000 */ - .long 0xF7100000 /* Data entry #0 register : LMI lower half, 128MB, uncached, unbuffered */ - .long 0x40000380 /* Data entry #0 data : LMI lower half, 128MB, uncached, unbuffered */ - .long 0xF7100100 /* Data entry #1 register : LMI higher half, 128MB, uncached, unbuffered */ - .long 0x48000380 /* Data entry #1 data : LMI higher half, 128MB, uncached, unbuffered */ - .long 0xF7100200 /* Data entry #2 register : LMI lower half, 128MB, uncached, unbuffered */ - .long 0x40000380 /* Data entry #2 data : LMI lower half, 128MB, uncached, unbuffered */ - .long 0xF7100300 /* Data entry #3 register : LMI higher half, 128MB, uncached, unbuffered */ - .long 0x48000380 /* Data entry #3 data : LMI higher half, 128MB, uncached, unbuffered */ - .long 0xF7100400 /* Data entry #4 register : EMI NOR uncached, 64MB, uncached, unbuffered */ - .long 0x00000310 /* Data entry #4 data : EMI NOR uncached, 64MB, uncached, unbuffered */ - .long 0xF7100500 /* Data entry #5 register : EMI NOR cached, 64MB, cached, buffered */ - .long 0x00000118 /* Data entry #5 data : EMI NOR cached, 64MB, cached, buffered */ - -_pmb_poke_end_k: - .long 0x0000000 - -/* CCN CCR address */ -_ccn_ccr_k: - .long 0xFF00001C -_ccn_ccr_value_k: - .long 0x8000090D -_ccn_mmucr_k: - .long 0xFF000010 -_ccn_pascr_k: - .long 0xFF000070 -_ccn_pascr_value_k: - .long 0x80000000 - -/* SR content */ -_sr_k: - .long 0x400000F0 - -/* WDT */ -_cpg_wdt_wtcsr_k: - .long 0xFFC0000C -_cpg_wdt_wtcsr_value_k: - .long 0x0000A500 - -/* EMI SPI NOR configuration registers */ -_emi_spinor_config_data_k: - .long 0xFE702020 -_emi_spinor_config_data_value_k: - .long 0x00020011 -_emi_spinor_modeselect_k: - .long 0xFE702018 -_emi_spinor_modeselect_value_k: - .long 0x00000002 - -/* PIO registers for debugging */ -_gpio_set_k: - .long 0xFD020004 -_gpio_clr_k: - .long 0xFD020008 -_gpio_clr_pc0_k: - .long 0xFD020028 -_gpio_set_pc1_k: - .long 0xFD020034 -_gpio_clr_pc2_k: - .long 0xFD020048 - -_system_config_34_k: - .long 0xFE001188 -_system_config_34_value_k: - .long 0x00000F00 -_gpio4_clr_pc0_k: - .long 0xFD024028 -_gpio4_set_pc1_k: - .long 0xFD024034 -_gpio4_set_pc2_k: - .long 0xFD024044 -_asc2_baud_k: - .long 0xFD032000 -_asc2_baud_value_k: - .long 0x000004B8 -_asc2_tx_buf_k: - .long 0xFD032004 -_asc2_ctrl_k: - .long 0xFD03200C -_asc2_ctrl_value_k: - .long 0x00001589 - -_crt0_entry: - .long _copy_data - + .balign 4 /* libc FPU routine */ _set_fpscr_k: .long ___set_fpscr @@ -387,8 +78,6 @@ _end_k: .long _end /* Function pointers */ -_init_ram_k: - .long _memory_setup_init_ram _main_k: .long _main /* Same address as main */ _exit_k: diff --git a/startup_stx7105_init_ram.S b/startup_stx7105_init_ram.S deleted file mode 100644 index 01acbd9..0000000 --- a/startup_stx7105_init_ram.S +++ /dev/null @@ -1,281 +0,0 @@ -/* - * (C) Copyright 2004-2009 STMicroelectronics. - * - * Andy Sturges - * Start Menefy - * Sean McGoogan - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* These macros are compatible to STLinux U-boot. */ - -#define POKE32(addr, value) .long 0x00000004, addr, value -#define UPDATE32(addr, mask, value) .long 0x00000006, addr, mask, value -#define WHILE_NE32(addr, mask, value) .long 0x00000007, addr, mask, value -#define DELAY(val) /* ST did nothing */ -#define END_MARKER .long 0x00000000, 0x00000000, 0x00000000 - - -/* Poke operation list */ - .section .rodata.init, "a" -__memory_setup_table: - #include "vendor/pdk7105.romgen" - - /* - * Note that we also manually need to move the LMI base addresses to - * their 32-bit SE mode locations as defined in the datasheet and change the - * 'upper bound addresses' (in row attribute registers) for the LMIs. - */ - - /* STX7105_SYSCONF_SYS_CFG38 */ - UPDATE32(0xfe001000 + 0x0198, 0xFFFFFF00, 0x00000040) - - /* - * Change LMI upper bound addresses - * Upper LMI addr=0x40000000 + 512MiB=0x60000000 - */ - - /* ST40_LMI_SDRA0_0 -> ST40_LMI_REGS_BASE + 0x000030 */ - UPDATE32(0xFE901000 + 0x30, 0x001FFFFF, 0x60000000) - - /* ST40_LMI_SDRA1_0 -> ST40_LMI_REGS_BASE + 0x000038 */ - UPDATE32(0xFE901000 + 0x38, 0x001FFFFF, 0x60000000) - - END_MARKER - -__memory_setup_table_end: - .long 0x00000000 - -/* - * NOTE: ALL THIS CODE MUST BE PIC !!!! - * - * This code expects to be run with the caches enabled. - */ - - .section .text.init, "ax" - .global _memory_setup_init_ram - -_memory_setup_init_ram: - /* Stash the pr somewhere safe */ - sts pr, r14 - - /* - * We need to get the poke loop & associated data - * into caches. The poke loop is structured so that it is - * all pulled into cache on it 1st iteration. - * To get the poke table into D-cache, we simply read it all. - */ - - mova _init_ram_poke_loop_address, r0 /* R6: &poke_loop() */ - mov.l @r0, r6 - add r0, r6 - mov.l _init_ram_p2_to_p1_mask, r3 /* R3: P2 -> P1 mapping */ - and r3, r6 /* convert to P1 addresses */ - mov.l _init_ram_data_start_address, r1 /* R1 = start address */ - add r0, r1 - mov.l _init_ram_data_end_address, r2 /* R2 = end address */ - add r0, r2 - and r3, r1 /* convert to a P1 addresses */ - and r3, r2 - mov r1, r5 /* R5 = scratch data ptr */ - -1: - mov.l @r5+, r4 /* Load poke table in D$ */ - cmp/eq r5, r2 - bf 1b - - /* - * Its now safe to call the poke loop with real data, since it - * and its associated data table are in onchip caches. Setting - * up the memory interfaces may cause the EMI (where this FLASH - * image resides) to briefly hang - but the CPU will be safely - * executing from cache should this happen. - */ -do_pokes: - jsr @r6 /* R6 still points poke_loop() */ - nop - - /* Restore the PR */ - lds r14, pr - rts - nop - - - .balign 4 -_init_ram_poke_loop_address: .long _init_ram_poke_loop - _init_ram_poke_loop_address -_init_ram_data_start_address: .long __memory_setup_table - _init_ram_poke_loop_address -_init_ram_data_end_address: .long __memory_setup_table_end - _init_ram_poke_loop_address -_init_ram_p2_to_p1_mask: .long ~0x20000000 - - -/* - * This is derived from STMicroelectronics gnu toolchain example: - * sh-superh-elf/examples/os21/romdynamic/bootstrap.S - * but it is not identical, because concurrently U-Boot added the - * IF_DEVID, IF_NOT_DEVID, ELSE and ENDIF commands, while the toolset - * added IF. This merged version supports both. - */ - -/* - * The poke table is a series of long words, in the format - * - * opcode, address, operand, ... - * - * An opcode of 0 marks the table end - */ - -/* - * Routine to setup peripheral registers. - * It is executed from within the I-cache, - * with all its data in the D-cache - */ -_init_ram_poke_loop: - mov.l @r1+, r0 /* opcode */ - mov.l @r1+, r2 /* address */ - mov.l @r1+, r3 /* value */ - - cmp/eq #0, r0 /* End marker ? */ - bf 1f - - rts /* Return point */ - nop - -1: - cmp/eq #4, r0 /* 4 byte write... */ - bf 1f - mov.l r3, @r2 - -1: - cmp/eq #2, r0 /* 2 byte write... */ - bf 1f - mov.w r3, @r2 - -1: - cmp/eq #1, r0 /* 1 byte write... */ - bf 1f - mov.b r3, @r2 - -1: - cmp/eq #5, r0 /* 4 byte OR... */ - bf 1f - mov.l @r2,r4 - or r3,r4 - mov.l r4,@r2 - -1: - cmp/eq #6, r0 /* 4 byte UPDATE... */ - bf 1f - mov.l @r2,r4 - and r3,r4 - mov.l @r1+,r3 - or r3,r4 - mov.l r4,@r2 - -1: - cmp/eq #8, r0 /* 4 byte write UPDATE... */ - bf 1f - mov.l @r3,r4 - mov.l @r1+,r3 - and r3,r4 - mov.l @r1+,r3 - shld r3,r4 - mov.l @r1+,r3 - or r3,r4 - mov.l r4,@r2 - -1: - cmp/eq #7, r0 /* WHILE != ... */ - bf 1f - mov.l @r1+,r5 - -2: - mov.l @r2,r4 - and r3,r4 - cmp/eq r4,r5 - bf 2b - -1: - cmp/eq #9, r0 /* IF_DEVID */ - bf 1f /* r2 skip offset, r3 condition, r7 holds out cut value */ - cmp/eq r3, r7 - bt _init_ram_poke_loop /* go ahead with these pokes */ - add r2, r1 - bra _init_ram_poke_loop - nop - -1: - cmp/eq #10, r0 /* IF_NOT_DEVID */ - bf 1f /* r2 skip offset, r3 condition, r7 holds out cut value */ - cmp/eq r3, r7 - bf _init_ram_poke_loop /* go ahead with these pokes */ - add r2, r1 - bra _init_ram_poke_loop - nop - -1: cmp/eq #11, r0 /* ELSE */ - bf 1f /* r2 skip offset, r3 condition, r7 holds out cut value */ - add r2, r1 - bra _init_ram_poke_loop - nop - -1: - cmp/eq #12,r0 /* IF == ... next op */ - bf _init_ram_delay - mov.l @r1+,r5 - mov.l @r2,r4 - and r3,r4 - cmp/eq r4,r5 - bt _init_ram_poke_loop /* Compare succeeded - perform next op */ - -2: /* Skip the next operation (read past it) */ - mov.l @r1+,r0 /* R0 = opcode */ - mov.l @r1+,r2 /* skip address */ - mov.l @r1+,r2 /* skip value */ - /* How many further reads do we need to skip? */ - cmp/eq #12,r0 /* If it's another IF, skip 1 and go back to start of skip loop */ - bf 3f - mov.l @r1+,r2 - bra 2b - nop - -3: - mov #5,r2 - cmp/gt r2,r0 - bf 5f /* 0 further reads */ - - cmp/eq #8,r0 /* Is it number 8 (3 reads, otherwise 1 read) */ - bf 4f - mov.l @r1+,r2 /* Skip 1 read */ - mov.l @r1+,r2 /* Skip 1 read */ -4: - mov.l @r1+,r2 /* Skip 1 read and continue */ -5: - bra _init_ram_poke_loop - nop - -_init_ram_delay: - mov #1,r0 /* small delay after EACH opcode */ - swap.w r0, r0 /* 0x10000 iterations (~65k) */ - -2: - add #-1,r0 - cmp/eq #0, r0 - bf 2b - bt _init_ram_poke_loop diff --git a/stx7105.ld b/stx7105.ld index aba13de..e9617f8 100644 --- a/stx7105.ld +++ b/stx7105.ld @@ -7,13 +7,14 @@ ENTRY(_start) /* We don't use 29-bit mode since PMB and LMI initialization has to be done anyway. */ MEMORY { - EMI (rx) : ORIGIN = 0xA0000000, LENGTH = 0x00100000 /* EMI virtual address: 0xA000_0000 */ - LMI (rwx) : ORIGIN = 0x80000000, LENGTH = 0x10000000 /* LMI virtual address: 0x8000_0000 */ + EMI (rx) : ORIGIN = 0x80000000, LENGTH = 0x01000000 /* LMI virtual address: 0x8000_0000 */ + LMI (rwx) : ORIGIN = 0x81000000, LENGTH = 0x0F000000 /* LMI virtual address: 0x8100_0000 */ } SECTIONS { .text : { . = ALIGN(4); + KEEP(*(.text.vtors)) *(.text.init) *(.text.exc) *(.text) @@ -34,6 +35,8 @@ SECTIONS { _edata = .; } >LMI AT >EMI + _eidata = (_sidata + _edata - _sdata); + .bss : { . = ALIGN(4); __bss_start = .; diff --git a/vendor/pdk7105.romgen b/vendor/pdk7105.romgen deleted file mode 100755 index 6eb0262..0000000 --- a/vendor/pdk7105.romgen +++ /dev/null @@ -1,549 +0,0 @@ - -/* -sdk7105 connect start - parameters {'no_devid_validate': '1', 'no_convertor_abort': '1', 'no_devid_abort': '1'} -Initialization TCK frequency set to 1562500 Hz -Device id 0x1d43e041 -tapmux connect(): boot mode single core setup -tapmux setup to bypass to core st40, channel 1 -sdk7105 initialization start ... -sdk7105_setup - parameters {'tapmux_bypass_init': u'st40', 'no_devid_validate': '1', 'no_convertor_abort': '1', 'reset_low_period': 360000, 'no_devid_abort': '1'} -Chip infos -*/ - - -/* -stx7105_sysconf_regs.SYSCONF_DEVICEID0 -PEEK(0xfe001000) (used target peek value 0x1d43e041) -Device ID = 0x1D43E041 ==> STi7105 cut 2 -*/ - - -/* -stx7105_sysconf_regs.SYSCONF_STA1 -PEEK(0xfe00100c) (used target peek value 0x00001015) -Mode pins = 0x00001015 ==> ClockgenA ref : SYSCLKIN/OSC - Boot mode ... : ST40 first - Boot port size: 16-bits - Boot device . : NOR flash -*/ - - -/*stx7105_sysconf_regs.SYSCONF_CFG40*/ -POKE32(0xfe0011a0, 0x00000005) -POKE32(0xfe0011a0, 0x00000005) - -/*stx7105_sysconf_regs.SYSCONF_CFG04*/ -POKE32(0xfe001110, 0x000001a6) - -/* Magic sequence to configure the ClockGenA switch control to reset values*/ -/* These do not appear to be correctly reset on WDT reset so do it here */ -/* CLOCKGEN A CKGA_CLKOPSRC_SWITCH_CFG reset=0 */ -POKE32(0xfe213014, 0x00000000) -/* CLOCKGEN A CKGA_CLKOPSRC_SWITCH_CFG2 reset=0 */ -POKE32(0xfe213024, 0x00000000) - -/*stx7105_clockgena_regs.CKGA_PLL0_ENABLE_FB*/ -WHILE_NE32(0xfe21301c, 0xffffffff, 0x00000000) - -/*stx7105_clockgena_regs.CKGA_PLL1_ENABLE_FB*/ -WHILE_NE32(0xfe213020, 0xffffffff, 0x00000000) - -/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/ -POKE32(0xfe213000, 0x80101e02) - -/*stx7105_clockgena_regs.CKGA_POWER_CFG*/ -POKE32(0xfe213010, 0x00000001) - - -/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/ -POKE32(0xfe213000, 0x00180f01) - -/*stx7105_clockgena_regs.CKGA_POWER_CFG*/ -POKE32(0xfe213010, 0x00000000) - - -/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/ -WHILE_NE32(0xfe213000, 0x80000000, 0x80000000) - - -/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/ -POKE32(0xfe213000, 0x80000f01) - - -/*stx7105_clockgena_regs.CKGA_PLL1_CFG*/ -POKE32(0xfe213004, 0x80102803) - - -POKE32(0xfe213b00, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV0_CFG*/ -POKE32(0xfe213b04, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV1_CFG*/ -POKE32(0xfe213b08, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV2_CFG*/ -POKE32(0xfe213b0c, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV3_CFG*/ -POKE32(0xfe213a10, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV4_CFG*/ -POKE32(0xfe213b14, 0x00000307) /*stx7105_clockgena_regs.CKGA_PLL1_DIV5_CFG*/ -POKE32(0xfe213a18, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV6_CFG*/ -POKE32(0xfe213a1c, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV7_CFG*/ -POKE32(0xfe213b20, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV8_CFG*/ -POKE32(0xfe213b24, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV9_CFG*/ -POKE32(0xfe213b28, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV10_CFG*/ -POKE32(0xfe213b2c, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV11_CFG*/ -POKE32(0xfe213b30, 0x00000102) /*stx7105_clockgena_regs.CKGA_PLL1_DIV12_CFG*/ -POKE32(0xfe213a34, 0x00000811) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV13_CFG*/ -POKE32(0xfe213b38, 0x0000050b) /*stx7105_clockgena_regs.CKGA_PLL1_DIV14_CFG*/ -POKE32(0xfe213b3c, 0x00000307) /*stx7105_clockgena_regs.CKGA_PLL1_DIV15_CFG*/ -POKE32(0xfe213b40, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV16_CFG*/ -POKE32(0xfe213b44, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV17_CFG*/ - - -POKE32(0xfe213010, 0x00000002) /*stx7105_clockgena_regs.CKGA_POWER_CFG*/ -POKE32(0xfe213004, 0x00182803) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/ -POKE32(0xfe213010, 0x00000000) /*stx7105_clockgena_regs.CKGA_POWER_CFG*/ -WHILE_NE32(0xfe213004, 0x80000000, 0x80000000) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/ -POKE32(0xfe213004, 0x80002803) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/ -POKE32(0xfe213014, 0xa6aa59aa) /*stx7105_clockgena_regs.CKGA_CLKOPSRC_SWITCH_CFG*/ -POKE32(0xfe213024, 0x0000000a) /*stx7105_clockgena_regs.CKGA_CLKOPSRC_SWITCH_CFG2*/ - - -/*stx7105_sysconf_regs.SYSCONF_CFG11*/ -POKE32(0xfe00112c, 0x00001d28) -POKE32(0xfe00112c, 0x00001af4) -POKE32(0xfe00112c, 0x00000af4) - -/*stx7105_sysconf_regs.SYSCONF_STA3*/ -WHILE_NE32(0xfe001014, 0x00000001, 0x00000000) - - -/*set_lmi2x_freq: freq=800.000 rdiv=0x3, ddiv=0x50 Clock frequencies*/ -/*stx7105_sysconf_regs.SYSCONF_CFG04*/ -POKE32(0xfe001110, 0x000001a2) - - -/*stx7105_sysconf_regs.SYSCONF_CFG11*/ -POKE32(0xfe00112c, 0x08000af5) - -/*stx7105_sysconf_regs.SYSCONF_CFG12*/ -POKE32(0xfe001130, 0xa000380f) -POKE32(0xfe001130, 0xa000380f) -POKE32(0xfe001130, 0xa000380f) -POKE32(0xfe001130, 0xa000380f) -POKE32(0xfe001130, 0xa000380f) -POKE32(0xfe001130, 0xa000380f) -POKE32(0xfe001130, 0xa200380f) -POKE32(0xfe001130, 0xa200380f) -POKE32(0xfe001130, 0xa200380f) -POKE32(0xfe001130, 0xa200380f) -POKE32(0xfe001130, 0xa200380f) -POKE32(0xfe001130, 0xa200780f) -POKE32(0xfe001130, 0xa200780f) -POKE32(0xfe001130, 0xa200680f) -POKE32(0xfe001130, 0xa200680f) -POKE32(0xfe001130, 0xa200680f) -POKE32(0xfe001130, 0xa200680f) -POKE32(0xfe001130, 0xa200680f) -POKE32(0xfe001130, 0xa200684f) -POKE32(0xfe001130, 0xa200686f) -/* -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -*/ - -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) -POKE32(0xfe001130, 0xa200687f) - - - -/*stx7105_sysconf_regs.SYSCONF_CFG13*/ -POKE32(0xfe001134, 0x00400000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) -POKE32(0xfe001134, 0x00600000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG14*/ -POKE32(0xfe001138, 0x00000000) -POKE32(0xfe001138, 0x00000000) -POKE32(0xfe001138, 0x00000000) -POKE32(0xfe001138, 0x00000000) -POKE32(0xfe001138, 0x00000000) -POKE32(0xfe001138, 0x00000000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG38*/ -POKE32(0xfe001198, 0x0000fe00) -POKE32(0xfe001198, 0x0000fe00) -POKE32(0xfe001198, 0x0000fe00) -POKE32(0xfe001198, 0x0020fe00) -POKE32(0xfe001198, 0x0020fe00) -POKE32(0xfe001198, 0x002cfe00) -POKE32(0xfe001198, 0x002ffe00) -POKE32(0xfe001198, 0x002ffe0c) - - -/*stx7105_sysconf_regs.SYSCONF_CFG40*/ -POKE32(0xfe0011a0, 0x00000005) - - -/*stx7105_sysconf_regs.SYSCONF_CFG42*/ -POKE32(0xfe0011a8, 0x20000000) -POKE32(0xfe0011a8, 0x28000000) -POKE32(0xfe0011a8, 0x2fb80000) -POKE32(0xfe0011a8, 0x2fbbdc00) -POKE32(0xfe0011a8, 0x2fbbddee) - - -/*stx7105_sysconf_regs.SYSCONF_CFG43*/ -POKE32(0xfe0011ac, 0x00000000) -POKE32(0xfe0011ac, 0x18000000) -POKE32(0xfe0011ac, 0x18a00000) -POKE32(0xfe0011ac, 0x18a001ee) - - -/*stx7105_sysconf_regs.SYSCONF_CFG51*/ -POKE32(0xfe0011cc, 0x00000000) -POKE32(0xfe0011cc, 0x00000000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG52*/ -POKE32(0xfe0011d0, 0x00000000) -POKE32(0xfe0011d0, 0x00000000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG55*/ -POKE32(0xfe0011dc, 0x00002000) -POKE32(0xfe0011dc, 0x00002000) -POKE32(0xfe0011dc, 0x00002000) -POKE32(0xfe0011dc, 0x07fc2000) -POKE32(0xfe0011dc, 0x07fc2000) -POKE32(0xfe0011dc, 0x07fc2000) -POKE32(0xfe0011dc, 0x07fc2000) -POKE32(0xfe0011dc, 0x07fc2280) -POKE32(0xfe0011dc, 0x07fc22c0) -POKE32(0xfe0011dc, 0x07fc22c0) -POKE32(0xfe0011dc, 0x07fc22c4) - -/*stx7105_sysconf_regs.SYSCONF_CFG04*/ -POKE32(0xfe001110, 0x000001a6) -DELAY(10) - - - -/*stx7105_sysconf_regs.SYSCONF_CFG13*/ -POKE32(0xfe001134, 0x00600000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG14*/ -POKE32(0xfe001138, 0x00000000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG42*/ -POKE32(0xfe0011a8, 0x2fbbddee) -POKE32(0xfe0011a8, 0x2fbbddee) -POKE32(0xfe0011a8, 0x2fbbddee) - - -/*stx7105_sysconf_regs.SYSCONF_CFG43*/ -POKE32(0xfe0011ac, 0x18a001ee) -POKE32(0xfe0011ac, 0x18a001ee) - -/*stx7105_sysconf_regs.SYSCONF_CFG51*/ -POKE32(0xfe0011cc, 0x00000000) -POKE32(0xfe0011cc, 0x00000000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG52*/ -POKE32(0xfe0011d0, 0x00000000) -POKE32(0xfe0011d0, 0x00000000) - - -/*stx7105_sysconf_regs.SYSCONF_CFG55*/ -POKE32(0xfe0011dc, 0x07fc22c4) - - -/*stx7105_sysconf_regs.SYSCONF_CFG04*/ -POKE32(0xfe001110, 0x000001a2) - - -/*stx7105_sysconf_regs.SYSCONF_CFG11*/ -POKE32(0xfe00112c, 0x00000af5) -POKE32(0xfe00112c, 0x00000af4) -DELAY(10) -POKE32(0xfe00112c, 0x08000af4) -POKE32(0xfe00112c, 0x08000af5) -DELAY(10) - - -/*stx7105_sysconf_regs.SYSCONF_CFG04*/ -POKE32(0xfe001110, 0x000001a6) -DELAY(10) - - -/*st40_emi_regs.EMI_BANK_ENABLE*/ -POKE32(0xfe700860, 0x00000005) - -POKE32(0xfe700800, 0x00000000) /*st40_emi_regs.EMI_BANK0_BASEADDRESS*/ -POKE32(0xfe700810, 0x00000010) /*st40_emi_regs.EMI_BANK1_BASEADDRESS*/ -POKE32(0xfe700820, 0x00000018) /*st40_emi_regs.EMI_BANK2_BASEADDRESS*/ -POKE32(0xfe700830, 0x0000001a) /*st40_emi_regs.EMI_BANK3_BASEADDRESS*/ -POKE32(0xfe700840, 0x0000001c) /*st40_emi_regs.EMI_BANK4_BASEADDRESS*/ - - - -/*st40_emi_regs.EMI_BANK0_EMICONFIGDATA0-3*/ -POKE32(0xfe700100, 0x001016d1) -POKE32(0xfe700108, 0x9d200000) -POKE32(0xfe700110, 0x9d220000) -POKE32(0xfe700118, 0x00000000) - - -/*st40_emi_regs.EMI_BANK1_EMICONFIGDATA0-3*/ -POKE32(0xfe700140, 0x002016d1) -POKE32(0xfe700148, 0x9d222200) -POKE32(0xfe700150, 0x9d220044) -POKE32(0xfe700158, 0x00000000) - - -/*st40_emi_regs.EMI_BANK2_EMICONFIGDATA0-3*/ -POKE32(0xfe700180, 0x002046f9) -POKE32(0xfe700188, 0xa5a00000) -POKE32(0xfe700190, 0xa5a20000) -POKE32(0xfe700198, 0x00000000) - - -/*st40_emi_regs.EMI_BANK3_EMICONFIGDATA0-3*/ -POKE32(0xfe7001c0, 0x002016d1) -POKE32(0xfe7001c8, 0x9d222200) -POKE32(0xfe7001d0, 0x9d220044) -POKE32(0xfe7001d8, 0x00000000) - - -/*st40_emi_regs.EMI_BANK4_EMICONFIGDATA0-3*/ -POKE32(0xfe700200, 0x002016d1) -POKE32(0xfe700208, 0x9d222200) -POKE32(0xfe700210, 0x9d220044) -POKE32(0xfe700218, 0x00000000) - - -/*st40_emi_regs.EMI_GENCFG*/ -POKE32(0xfe700028, 0x00000010) - - -/*st40_lmigp_regs.LMI_MIM_0-1*/ -POKE32(0xfe901008, 0x0b30017b) -POKE32(0xfe90100c, 0x000000b0) - - -/*st40_lmigp_regs.LMI_STR_0-1*/ -POKE32(0xfe901018, 0xcf35b424) -POKE32(0xfe90101c, 0x00242ed8) - -/*st40_lmigp_regs.LMI_SDRA0_0-1*/ -POKE32(0xfe901030, 0x1c001a20) -POKE32(0xfe901038, 0x1c001a20) -DELAY(200000) - - -/*st40_lmigp_regs.LMI_SCR_0*/ -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020023) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020022) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) - - -/*st40_lmigp_regs.LMI_SDMR0_0*/ -POKE32(0xfe901048, 0x00010000) - -/*st40_lmigp_regs.LMI_SDMR0_0*/ -POKE32(0xfe901048, 0x00018000) - -/*st40_lmigp_regs.LMI_SDMR0_0*/ -POKE32(0xfe901048, 0x00008006) - -/*st40_lmigp_regs.LMI_SDMR0_0*/ -POKE32(0xfe901048, 0x00004363) - -/*st40_lmigp_regs.LMI_SCR_0*/ -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020022) -POKE32(0xfe901010, 0x00020024) -POKE32(0xfe901010, 0x00020024) - - -/*st40_lmigp_regs.LMI_SDMR0_0*/ -POKE32(0xfe901048, 0x00004263) - -/*st40_lmigp_regs.LMI_MIM_0*/ -POKE32(0xfe901008, 0x0b30037b) -POKE32(0xfe901008, 0x0b30037b) - - -/*st40_lmigp_regs.LMI_SCR_0*/ -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) -POKE32(0xfe901010, 0x00020021) - - -/*st40_lmigp_regs.LMI_GCC_0*/ -POKE32(0xfe901028, 0x00000000) - -/*Info: correcting interco reset setup*/ -POKE32(0xfe20d200, 0x00000005) -POKE32(0xfe20d204, 0x00000004) -POKE32(0xfe20d208, 0x00000003) -POKE32(0xfe20d20c, 0x00000002) -POKE32(0xfe20d210, 0x00000001) -POKE32(0xfe20d214, 0x00000001) -POKE32(0xfe20d218, 0x00000001) -POKE32(0xfe20d21c, 0x00000001) -POKE32(0xfe20d220, 0x00000001) -POKE32(0xfe2410fc, 0x00000005) -POKE32(0xfe20a0ec, 0x00000002) -POKE32(0xfe20a0f0, 0x00000005) -POKE32(0xfe20a0f4, 0x00000003) -POKE32(0xfe20a0f8, 0x00000003) -POKE32(0xfe20a1ec, 0x00000002) -POKE32(0xfe20a1f0, 0x00000005) -POKE32(0xfe20a1f4, 0x00000003) -POKE32(0xfe20a1f8, 0x00000003) -POKE32(0xfe20a1fc, 0x00000000) -POKE32(0xfe20a2ec, 0x00000002) -POKE32(0xfe20a2f0, 0x00000005) -POKE32(0xfe20a2f4, 0x00000003) -POKE32(0xfe20a2f8, 0x00000003) -POKE32(0xfe20a2fc, 0x00000000) -POKE32(0xfe20a3ec, 0x00000002) -POKE32(0xfe20a3f0, 0x00000005) -POKE32(0xfe20a3f4, 0x00000003) -POKE32(0xfe20a3f8, 0x00000003) -POKE32(0xfe20a3fc, 0x00000000) -POKE32(0xfe20aefc, 0x00000005) -POKE32(0xfe540034, 0x00000003) -POKE32(0xfe540038, 0x00000000) -POKE32(0xfe540110, 0x00010303) -POKE32(0xfe540114, 0x00000000) -POKE32(0xfe540030, 0x00000005) -POKE32(0xfe54010c, 0x00000005) -POKE32(0xfe540600, 0x00000006) -POKE32(0xfe540604, 0x00000005) -POKE32(0xfe540608, 0x00000004) -POKE32(0xfe54060c, 0x00000003) -POKE32(0xfe540610, 0x00000002) -POKE32(0xfe540614, 0x00000001) -POKE32(0xfe540618, 0x00000000) -POKE32(0xfe540680, 0x00000001) -POKE32(0xfe540684, 0x00000000) -POKE32(0xfe20bb04, 0x00000005) -POKE32(0xfe20bb08, 0x00000003) -POKE32(0xfe20bb10, 0x00000002) -POKE32(0xfe20bb24, 0x00000005) -POKE32(0xfe20bb28, 0x00000003) -POKE32(0xfe20bb2c, 0x00000000) -POKE32(0xfe20bb30, 0x00000002) -POKE32(0xfe20bb44, 0x00000005) -POKE32(0xfe20bb48, 0x00000003) -POKE32(0xfe20bb4c, 0x00000000) -POKE32(0xfe20bb50, 0x00000002) -POKE32(0xfe20bb84, 0x00000005) -POKE32(0xfe20bb88, 0x00000003) -POKE32(0xfe20bb8c, 0x00000000) -POKE32(0xfe20bb90, 0x00000002) -POKE32(0xfe20a0fc, 0x00000000) -POKE32(0xfe20bb0c, 0x00000000) -POKE32(0xfe231010, 0x00000008) -POKE32(0xfe231080, 0x00000221) -POKE32(0xfe261010, 0x00000008) -POKE32(0xfe261080, 0x00000221) -POKE32(0xfd101024, 0x0003c000) -POKE32(0xfd101824, 0x0003c000) -POKE32(0xfd104d24, 0x0003c000) -POKE32(0xfd102024, 0x0003c000) -/* PEEK(0xfe001180) (used target peek value 0x00000b35) */ -POKE32(0xfe001180, 0x00000b05) -POKE32(0xfe1fff04, 0x00254608) -POKE32(0xfeafff04, 0x00254608) -/* PEEK(0xfe00111c) (used target peek value 0x08081508) */ -POKE32(0xfe00111c, 0x08091508) -POKE32(0xfd117000, 0x0025c608) -POKE32(0xfd111000, 0x00201004) -/* PEEK(0xfe001180) (used target peek value 0x00000b05) */ -POKE32(0xfe001180, 0x00000b01) -POKE32(0xfe401744, 0x0025c005) - - -/*st40_ccn_regs.CCN_CCR*/ -POKE32(0xff00001c, 0x8000090d) - - -/*stx7105_sysconf_regs.SYSCONF_CFG09*/ -POKE32(0xfe001124, 0x08000a8c) - -/*stx7105_sysconf_regs.SYSCONF_CFG05*/ -POKE32(0xfe001114, 0x04000040) - -/*stx7105_sysconf_regs.SYSCONF_CFG26*/ -POKE32(0xfe001168, 0xfe804001) - -/*stx7105_sysconf_regs.SYSCONF_CFG27*/ -POKE32(0xfe00116c, 0x00001fd1) -POKE32(0xfe00116c, 0x00001fd0) - -/*stx7105: booted audio companion*/ -/*stx7105_sysconf_regs.SYSCONF_CFG09*/ -POKE32(0xfe001124, 0x08000a8c) - - -/*stx7105_sysconf_regs.SYSCONF_CFG05*/ -POKE32(0xfe001114, 0x04000040) - - -/*stx7105_sysconf_regs.SYSCONF_CFG28*/ -POKE32(0xfe001170, 0xfe604001) - -/*stx7105_sysconf_regs.SYSCONF_CFG29*/ -POKE32(0xfe001174, 0x00001fcd) - - -/*stx7105_sysconf_regs.SYSCONF_CFG29*/ -POKE32(0xfe001174, 0x00001fcc) - -/* stx7105: booted video companion*/ -/* TCK frequency set to 12500000 Hz*/ -/* tapmux complete_connect(): single core setup*/ -/* sdk7105 initialization complete*/