251 lines
13 KiB
C
251 lines
13 KiB
C
#ifndef STX7105_H
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#define STX7105_H
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#include <stdint.h>
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#include "sh4_core.h"
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#define __PACKED __attribute__((packed, aligned(1)))
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#define __IO volatile
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typedef struct {
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__IO uint8_t POUT; /* Offset: 0x00, GPIO pin output register */
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uint8_t UNUSED0[3]; /* Offset: 0x01 */
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__IO uint8_t SET_POUT; /* Offset: 0x04, GPIO pin output set register */
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uint8_t UNUSED1[3]; /* Offset: 0x05 */
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__IO uint8_t CLR_POUT; /* Offset: 0x08, GPIO pin output clear register */
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uint8_t UNUSED2[7]; /* Offset: 0x09 */
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__IO uint8_t PIN; /* Offset: 0x10, GPIO pin input register */
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uint8_t UNUSED3[15]; /* Offset: 0x11 */
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__IO uint8_t PC0; /* Offset: 0x20, GPIO pin config register 0 */
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uint8_t UNUSED4[3]; /* Offset: 0x21 */
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__IO uint8_t SET_PC0; /* Offset: 0x24, GPIO pin config set register 0 */
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uint8_t UNUSED5[3]; /* Offset: 0x25 */
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__IO uint8_t CLR_PC0; /* Offset: 0x28, GPIO pin config clear register 0 */
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uint8_t UNUSED6[7]; /* Offset: 0x29 */
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__IO uint8_t PC1; /* Offset: 0x30, GPIO pin config register 1 */
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uint8_t UNUSED7[3]; /* Offset: 0x31 */
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__IO uint8_t SET_PC1; /* Offset: 0x34, GPIO pin config set register 1 */
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uint8_t UNUSED8[3]; /* Offset: 0x35 */
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__IO uint8_t CLR_PC1; /* Offset: 0x38, GPIO pin config clear register 1 */
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uint8_t UNUSED9[7]; /* Offset: 0x39 */
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__IO uint8_t PC2; /* Offset: 0x40, GPIO pin config register 2 */
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uint8_t UNUSED10[3]; /* Offset: 0x41 */
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__IO uint8_t SET_PC2; /* Offset: 0x44, GPIO pin config set register 2 */
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uint8_t UNUSED11[3]; /* Offset: 0x45 */
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__IO uint8_t CLR_PC2; /* Offset: 0x48, GPIO pin config clear register 2 */
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uint8_t UNUSED12[7]; /* Offset: 0x49 */
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__IO uint8_t PCOMP; /* Offset: 0x50, GPIO pin input comparison register */
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uint8_t UNUSED13[3]; /* Offset: 0x51 */
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__IO uint8_t SET_PCOMP; /* Offset: 0x54, GPIO pin input comparison set regiser */
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uint8_t UNUSED14[3]; /* Offset: 0x55 */
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__IO uint8_t CLR_PCOMP; /* Offset: 0x58, GPIO pin input comparison clear regiser */
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uint8_t UNUSED15[7]; /* Offset: 0x59 */
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__IO uint8_t PMASK; /* Offset: 0x60, GPIO pin input comparison mask register */
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uint8_t UNUSED16[3]; /* Offset: 0x61 */
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__IO uint8_t SET_PMASK; /* Offset: 0x64, GPIO pin input comparison mask set regiser */
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uint8_t UNUSED17[3]; /* Offset: 0x65 */
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__IO uint8_t CLR_PMASK; /* Offset: 0x68, GPIO pin input comparison mask clear regiser */
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} PIO_TypeDef;
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typedef struct {
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__IO uint32_t BAUDRATE; /* Offset: 0x00, ASCn baud rate generator register */
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__IO uint32_t TX_BUF; /* Offset: 0x04, ASCn transmit buffer register */
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__IO uint32_t RX_BUF; /* Offset: 0x08, ASCn receive buffer register */
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__IO uint32_t CTRL; /* Offset: 0x0C, ASCn control register */
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__IO uint32_t INT_EN; /* Offset: 0x10, ASCn interrupt enable register */
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__IO uint32_t STA; /* Offset: 0x14, ASCn interrupt status register */
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__IO uint32_t GUARDTIME; /* Offset: 0x18, ASCn guard time register */
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__IO uint32_t TIMEOUT; /* Offset: 0x1C, ASCn time out register */
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__IO uint32_t TX_RST; /* Offset: 0x20, ASCn transmit FIFO reset register */
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__IO uint32_t RX_RST; /* Offset: 0x24, ASCn receive FIFO reset register */
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__IO uint32_t RETRIES; /* Offset: 0x28, ASCn number of retries on transmission register */
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} ASC_TypeDef;
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typedef struct {
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__IO uint16_t ICR; /* Offset: 0x00, Interrupt control register */
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uint8_t UNUSED0[2]; /* Offset: 0x02 */
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__IO uint16_t IPRA; /* Offset: 0x04, Interrupt priority level A register */
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uint8_t UNUSED1[2]; /* Offset: 0x06 */
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__IO uint16_t IPRB; /* Offset: 0x08, Interrupt priority level B register */
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uint8_t UNUSED2[2]; /* Offset: 0x0A */
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__IO uint16_t IPRC; /* Offset: 0x0C, Interrupt priority level C register */
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uint8_t UNUSED3[2]; /* Offset: 0x0E */
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__IO uint16_t IPRD; /* Offset: 0x10, Interrupt priority level D register */
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uint8_t UNUSED4[2]; /* Offset: 0x12 */
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} INTC_TypeDef;
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typedef struct {
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__IO uint8_t TOCR; /* Offset: 0x00, Timer output control register */
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uint8_t UNUSED0[3]; /* Offset: 0x01 */
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__IO uint8_t TSTR; /* Offset: 0x04, Timer start register */
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uint8_t UNUSED1[3]; /* Offset: 0x05 */
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__IO uint32_t TCOR0; /* Offset: 0x08, Timer constant register 0 */
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__IO uint32_t TCNT0; /* Offset: 0x0C, Timer counter 0 */
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__IO uint16_t TCR0; /* Offset: 0x10, Timer control register 0 */
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uint8_t UNUSED2[2]; /* Offset: 0x11 */
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__IO uint32_t TCOR1; /* Offset: 0x14, Timer constant register 1 */
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__IO uint32_t TCNT1; /* Offset: 0x18, Timer counter 1 */
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__IO uint16_t TCR1; /* Offset: 0x1C, Timer control register 1 */
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uint8_t UNUSED3[2]; /* Offset: 0x1E */
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__IO uint32_t TCOR2; /* Offset: 0x20, Timer constant register 2 */
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__IO uint32_t TCNT2; /* Offset: 0x24, Timer counter 2 */
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__IO uint16_t TCR2; /* Offset: 0x28, Timer control register 2 */
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__IO uint8_t UNUSED4[2]; /* Offset: 0x2A */
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uint32_t TCPR2; /* Offset: 0x2C */
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} TMU_TypeDef;
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typedef struct {
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__IO uint32_t PTEH; /* Offset: 0x00000, Page table entry high register */
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__IO uint32_t PTEL; /* Offset: 0x00004, Page table entry low register */
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__IO uint32_t TTB; /* Offset: 0x00008, Translation table base register */
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__IO uint32_t TEA; /* Offset: 0x0000C, TLB exception address register */
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__IO uint32_t MMUCR; /* Offset: 0x00010, MMU control register */
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__IO uint8_t BASRA; /* Offset: 0x00014, Break ASID register A*/
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uint8_t UNUSED0[3]; /* Offset: 0x00015 */
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__IO uint8_t BASRB; /* Offset: 0x00018, Break ASID register B*/
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uint8_t UNUSED1[3]; /* Offset: 0x00019 */
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__IO uint32_t CCR; /* Offset: 0x0001C, Cache control register */
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__IO uint32_t TRA; /* Offset: 0x00020, TRAPA exception register */
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__IO uint32_t EXPEVT; /* Offset: 0x00024, Exception event register */
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__IO uint32_t INTEVT; /* Offset: 0x00028, Interrupt event register */
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uint32_t UNUSED2[3]; /* Offset: 0x0002C */
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__IO uint32_t QACR0; /* Offset: 0x00038, Queue address control register 0 */
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__IO uint32_t QACR1; /* Offset: 0x0003C, Queue address control register 1 */
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uint32_t UNUSED3[12]; /* Offset: 0x00040 */
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__IO uint32_t PASCR; /* Offset: 0x00070, Physical address space control register */
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__IO uint32_t RAMCR; /* Offset: 0x00074, On-chip memory control register */
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__IO uint32_t IRMCR; /* Offset: 0x00078, Instruction refetch inhibit control register */
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uint32_t UNUSED4[2097028]; /* Offset: 0x0007C, Am I serious? */
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__IO uint32_t BARA; /* Offset: 0x20000, Break address register A */
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__IO uint8_t BAMRA; /* Offset: 0x20004, Break address mask register A */
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uint8_t UNUSED5[3]; /* Offset: 0x20005 */
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__IO uint16_t BBRA; /* Offset: 0x20008, Break bus cycle register A */
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uint8_t UNUSED6[2]; /* Offset: 0x2000A */
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__IO uint32_t BARB; /* Offset: 0x2000B, Break address register B */
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__IO uint8_t BAMRB; /* Offset: 0x20010, Break address mask register B */
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uint8_t UNUSED7[3]; /* Offset: 0x20011 */
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__IO uint16_t BBRB; /* Offset: 0x20014, Break bus cycle register B */
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uint8_t UNUSED8[2]; /* Offset: 0x20016 */
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__IO uint32_t BDRB; /* Offset: 0x20018, Break data register B */
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__IO uint32_t BDMRB; /* Offset: 0x2001C, Break data mask register B */
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__IO uint16_t BRCR; /* Offset: 0x20020, Break control register */
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uint8_t UNUSED9[2]; /* Offset: 0x20022 */
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} CSP_TypeDef;
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/* drivers/stm/stx7105.c */
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typedef struct {
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__IO uint32_t SLIM_ID; /* Offset: 0x0000, SLIM CPU ID register */
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__IO uint32_t SLIM_VER; /* Offset: 0x0004, SLIM CPU version register */
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__IO uint32_t SLIM_EN; /* Offset: 0x0008, SLIM CPU enable control register */
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__IO uint32_t SLIM_CLK_GATE; /* Offset: 0x000C, SLIM CPU clock gate register */
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uint32_t UNUSED0[8188]; /* Offset: 0x0010 */
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__IO uint8_t SLIM_DMEM[8192]; /* Offset: 0x8000, SLIM CPU data memory */
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uint32_t UNUSED1[2018]; /* Offset: 0xA000 */
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__IO uint32_t PERIPH_STBUS_SYNC; /* Offset: 0xBF88, STBus sync control register */
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uint32_t UNUSED2[13]; /* Offset: 0xBF8C */
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__IO uint32_t PERIPH_CMD_STA; /* Offset: 0xBFC0, Command mailbox */
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__IO uint32_t PERIPH_CMD_SET; /* Offset: 0xBFC4, Command mailbox */
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__IO uint32_t PERIPH_CMD_CLR; /* Offset: 0xBFC8, Command mailbox */
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__IO uint32_t PERIPH_CMD_MASK; /* Offset: 0xBFCC, Command mailbox */
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__IO uint32_t PERIPH_INT_STA; /* Offset: 0xBFD0, Interrupt mailbox */
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__IO uint32_t PERIPH_INT_SET; /* Offset: 0xBFD4, Interrupt mailbox */
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__IO uint32_t PERIPH_INT_CLR; /* Offset: 0xBFD8, Interrupt mailbox */
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__IO uint32_t PERIPH_INT_MASK; /* Offset: 0xBFDC, Interrupt mailbox */
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uint32_t UNUSED3[8]; /* Offset: 0xBFE0 */
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__IO uint8_t SLIM_IMEM[16384]; /* Offset: 0xC000, SLIM CPU instruction memory */
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} FDMA_TypeDef;
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/* WARNING: THE CLKGENA is different from other ST40s' */
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typedef struct {
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__IO uint32_t PLL0_CFG; /* Offset: 0x0000 */
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__IO uint32_t PLL1_CFG; /* Offset: 0x0004 */
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uint32_t UNUSED0[2]; /* Offset: 0x0008 */
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__IO uint32_t POWER_CFG; /* Offset: 0x0010 */
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__IO uint32_t CLKOPSRC_SWITCH_CFG; /* Offset: 0x0014 */
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uint32_t UNUSED1[4]; /* Offset: 0x0018 */
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__IO uint32_t CLKOPSRC_SWITCH_CFG2; /* Offset: 0x0024 */
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uint32_t UNUSED2[2]; /* Offset: 0x0028 */
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__IO uint32_t CLKOBS_MUX1_CFG; /* Offset: 0x0030 */
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__IO uint32_t CLKOBS_MASTER_MAXCOUNT; /* Offset: 0x0034 */
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__IO uint32_t CLKOBS_CMD; /* Offset: 0x0038 */
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__IO uint32_t CLKOBS_STATUS; /* Offset: 0x003C */
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__IO uint32_t CLKOBS_SLAVE0_COUNT; /* Offset: 0x0040 */
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__IO uint32_t OSCMUX_DEBUG; /* Offset: 0x0044 */
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__IO uint32_t CLKOBS_MUX2_CFG; /* Offset: 0x0048 */
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__IO uint32_t LOW_POWER_CTRL; /* Offset: 0x004C */
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} CKGA_TypeDef;
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#define PIO0_BASE (0xFD020000U)
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#define PIO1_BASE (0xFD021000U)
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#define PIO2_BASE (0xFD022000U)
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#define PIO3_BASE (0xFD023000U)
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#define PIO4_BASE (0xFD024000U)
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#define PIO5_BASE (0xFD025000U)
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#define PIO6_BASE (0xFD026000U)
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#define ASC0_BASE (0xFD030000U)
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#define ASC1_BASE (0xFD031000U)
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#define ASC2_BASE (0xFD032000U)
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#define ASC3_BASE (0xFD033000U)
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#define CKGA_BASE (0xFE213000U)
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#define FDMA0_BASE (0xFE220000U)
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#define FDMA1_BASE (0xFE410000U)
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#define CSP_BASE (0xFF000000U)
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#define INTC_BASE (0xFFD00000U)
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#define TMU_BASE (0xFFD80000U)
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#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
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#define PIO1 ((PIO_TypeDef *)PIO1_BASE)
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#define PIO2 ((PIO_TypeDef *)PIO2_BASE)
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#define PIO3 ((PIO_TypeDef *)PIO3_BASE)
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#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
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#define PIO5 ((PIO_TypeDef *)PIO5_BASE)
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#define PIO6 ((PIO_TypeDef *)PIO6_BASE)
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#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
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#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
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#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
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#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
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#define CKGA ((CKGA_TypeDef *)CKGA_BASE)
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#define FDMA0 ((FDMA_TypeDef *)FDMA0_BASE)
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#define FDMA1 ((FDMA_TypeDef *)FDMA1_BASE)
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#define CSP ((CSP_TypeDef *)CSP_BASE)
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#define INTC ((INTC_TypeDef *)INTC_BASE)
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#define TMU ((TMU_TypeDef *)TMU_BASE)
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#define TMU_TSTR_STR0_Pos 0
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#define TMU_TSTR_STR0_Msk (1U << TMU_TSTR_STR0_Pos)
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#define TMU_TSTR_STR1_Pos 1
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#define TMU_TSTR_STR1_Msk (1U << TMU_TSTR_STR1_Pos)
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#define TMU_TSTR_STR2_Pos 2
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#define TMU_TSTR_STR3_Msk (1U << TMU_TSTR_STR2_Pos)
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#define TMU_TCR_UNIE_Pos 5
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#define TMU_TCR_UNIE_Msk (1U << TMU_TCR_UNIE_Pos)
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#define TMU_TCR_UNF_Pos 8
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#define TMU_TCR_UNF_Msk (1U << TMU_TCR_UNF_Pos)
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#define INTC_IPRA_IPR_TMU0_Pos 12
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#define INTC_IPRA_IPR_TMU0_Msk (0x0FU << INTC_IPRA_IPR_TMU0_Pos)
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#define FDMA_SLIM_EN_RUN_Pos 0
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#define FDMA_SLIM_EN_RUN_Msk (1U << FDMA_SLIM_EN_RUN_Pos)
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#define FDMA_SLIM_CLK_GATE_DIS_Pos 0
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#define FDMA_SLIM_CLK_GATE_DIS_Msk (1U << FDMA_SLIM_CLK_GATE_DIS_Pos)
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#define FDMA_SLIM_CLK_GATE_RESET_Pos 2
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#define FDMA_SLIM_CLK_GATE_RESET_Msk (1U << FDMA_SLIM_CLK_GATE_RESET_Pos)
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#define FDMA_PERIPH_STBUS_SYNC_DIS_Pos 0
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#define FDMA_PERIPH_STBUS_SYNC_DIS_Msk (1U << FDMA_PERIPH_STBUS_SYNC_DIS_Pos)
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#endif |