127 lines
2.2 KiB
ArmAsm
127 lines
2.2 KiB
ArmAsm
/*
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* This section is read by bootloader,
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* then the application will be copied according to the contents.
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* !!DO NOT REMOVE!!
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* See SPL project README for details.
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*/
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.section .text.vtors, "ax"
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_vtors:
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.long _stext
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.long _eidata
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.long _start
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/*
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* Startup code (CRT0)
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*/
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.section .text.init, "ax"
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.global _start
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_start:
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mov.l _stack_k, sp /* Setup R15(SP) */
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_copy_data:
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mov.l _sidata_k, r0
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mov.l _sdata_k, r1
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mov.l _edata_k, r2
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_loop_copy_data:
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mov.l @r0+, r3 /* Load a word to r3 from [sidata], with post-increment of 4 */
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mov.l r3, @r1 /* Store the word in r3 to [sdata] */
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add #4, r1 /* Increment sdata pointer */
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cmp/gt r1, r2 /* r2 greater or equal than r1? */
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bt _loop_copy_data
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_zero_bss:
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mov.l _edata_k, r0
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mov.l _end_k, r1
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mov #0, r2
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_loop_zero_bss:
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mov.l r2, @r0
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add #4, r0
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cmp/gt r0, r1
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bt _loop_zero_bss
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_setup_fpu:
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mov.l _set_fpscr_k, r1
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jsr @r1
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mov #0, r4
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lds r3, fpscr
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_setup_irq:
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mov.l _exc_base_k, r0
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ldc r0, vbr
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stc sr, r0 /* Store SR into R0 */
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mov.l _exc_imask_k, r1
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and r1, r0
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ldc r0, sr
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.align 2
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_main_entry:
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mov.l _main_k, r0
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jsr @r0
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or r0, r0
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mov.l _exit_loop_k, r0
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_exit_loop:
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sleep
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jmp @r0
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nop
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.balign 4
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/* libc FPU routine */
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_set_fpscr_k:
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.long ___set_fpscr
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/* C library consts */
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_stack_k:
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.long _stack
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_sidata_k:
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.long _sidata
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_sdata_k:
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.long _sdata
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_edata_k:
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.long _edata
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_end_k:
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.long _end
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/* Function pointers */
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_main_k:
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.long _main /* Same address as main */
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_exit_loop_k:
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.long _exit_loop
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_exc_base_k:
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.long _exc_base
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_exc_imask_k:
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.long 0xEFFFFF0F /* Clear IMASK (SR[7:4]) to 0 and BL bit, enable all exception levels */
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/*
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* Exception handlers
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* These handlers are placed at VBR related addresses
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*/
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.section .text.exc, "ax"
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.align 4
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_exc_base:
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.org 0x100, 0x00
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_exc_grnl_vector:
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mov.l _exc_grnl_entry_k, r0
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jmp @r0
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nop
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.align 4
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_exc_grnl_entry_k:
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.long _general_exc_handler
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_int_base:
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.org 0x600, 0x00
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_int_grnl_vector:
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mov.l _int_grnl_entry_k, r0
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jmp @r0
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nop
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.align 4
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_int_grnl_entry_k:
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.long _general_int_handler |