126 lines
6.6 KiB
C
126 lines
6.6 KiB
C
#ifndef STX7105_H
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#define STX7105_H
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#include <stdint.h>
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#define __PACKED __attribute__((packed, aligned(1)))
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#define __IO volatile
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typedef struct {
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__IO uint8_t POUT; /* Offset: 0x00, GPIO pin output register */
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__IO uint8_t UNUSED0[3]; /* Offset: 0x01 */
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__IO uint8_t SET_POUT; /* Offset: 0x04, GPIO pin output set register */
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__IO uint8_t UNUSED1[3]; /* Offset: 0x05 */
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__IO uint8_t CLR_POUT; /* Offset: 0x08, GPIO pin output clear register */
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__IO uint8_t UNUSED2[7]; /* Offset: 0x09 */
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__IO uint8_t PIN; /* Offset: 0x10, GPIO pin input register */
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__IO uint8_t UNUSED3[15]; /* Offset: 0x11 */
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__IO uint8_t PC0; /* Offset: 0x20, GPIO pin config register 0 */
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__IO uint8_t UNUSED4[3]; /* Offset: 0x21 */
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__IO uint8_t SET_PC0; /* Offset: 0x24, GPIO pin config set register 0 */
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__IO uint8_t UNUSED5[3]; /* Offset: 0x25 */
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__IO uint8_t CLR_PC0; /* Offset: 0x28, GPIO pin config clear register 0 */
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__IO uint8_t UNUSED6[7]; /* Offset: 0x29 */
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__IO uint8_t PC1; /* Offset: 0x30, GPIO pin config register 1 */
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__IO uint8_t UNUSED7[3]; /* Offset: 0x31 */
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__IO uint8_t SET_PC1; /* Offset: 0x34, GPIO pin config set register 1 */
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__IO uint8_t UNUSED8[3]; /* Offset: 0x35 */
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__IO uint8_t CLR_PC1; /* Offset: 0x38, GPIO pin config clear register 1 */
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__IO uint8_t UNUSED9[7]; /* Offset: 0x39 */
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__IO uint8_t PC2; /* Offset: 0x40, GPIO pin config register 2 */
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__IO uint8_t UNUSED10[3]; /* Offset: 0x41 */
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__IO uint8_t SET_PC2; /* Offset: 0x44, GPIO pin config set register 2 */
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__IO uint8_t UNUSED11[3]; /* Offset: 0x45 */
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__IO uint8_t CLR_PC2; /* Offset: 0x48, GPIO pin config clear register 2 */
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__IO uint8_t UNUSED12[7]; /* Offset: 0x49 */
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__IO uint8_t PCOMP; /* Offset: 0x50, GPIO pin input comparison register */
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__IO uint8_t UNUSED13[3]; /* Offset: 0x51 */
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__IO uint8_t SET_PCOMP; /* Offset: 0x54, GPIO pin input comparison set regiser */
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__IO uint8_t UNUSED14[3]; /* Offset: 0x55 */
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__IO uint8_t CLR_PCOMP; /* Offset: 0x58, GPIO pin input comparison clear regiser */
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__IO uint8_t UNUSED15[7]; /* Offset: 0x59 */
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__IO uint8_t PMASK; /* Offset: 0x60, GPIO pin input comparison mask register */
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__IO uint8_t UNUSED16[3]; /* Offset: 0x61 */
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__IO uint8_t SET_PMASK; /* Offset: 0x64, GPIO pin input comparison mask set regiser */
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__IO uint8_t UNUSED17[3]; /* Offset: 0x65 */
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__IO uint8_t CLR_PMASK; /* Offset: 0x68, GPIO pin input comparison mask clear regiser */
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} PIO_TypeDef;
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typedef struct {
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__IO uint32_t BAUDRATE; /* Offset: 0x00, ASCn baud rate generator register */
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__IO uint32_t TX_BUF; /* Offset: 0x04, ASCn transmit buffer register */
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__IO uint32_t RX_BUF; /* Offset: 0x08, ASCn receive buffer register */
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__IO uint32_t CTRL; /* Offset: 0x0C, ASCn control register */
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__IO uint32_t INT_EN; /* Offset: 0x10, ASCn interrupt enable register */
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__IO uint32_t STA; /* Offset: 0x14, ASCn interrupt status register */
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__IO uint32_t GUARDTIME; /* Offset: 0x18, ASCn guard time register */
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__IO uint32_t TIMEOUT; /* Offset: 0x1C, ASCn time out register */
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__IO uint32_t TX_RST; /* Offset: 0x20, ASCn transmit FIFO reset register */
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__IO uint32_t RX_RST; /* Offset: 0x24, ASCn receive FIFO reset register */
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__IO uint32_t RETRIES; /* Offset: 0x28, ASCn number of retries on transmission register */
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} ASC_TypeDef;
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typedef struct {
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__IO uint8_t TOCR; /* Offset: 0x00, Timer output control register */
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uint8_t UNUSED0[3]; /* Offset: 0x01 */
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__IO uint8_t TSTR; /* Offset: 0x04, Timer start register */
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uint8_t UNUSED1[3]; /* Offset: 0x05 */
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__IO uint32_t TCOR0; /* Offset: 0x08, Timer constant register 0 */
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__IO uint32_t TCNT0; /* Offset: 0x0C, Timer counter 0 */
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__IO uint16_t TCR0; /* Offset: 0x10, Timer control register 0 */
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uint8_t UNUSED2[2]; /* Offset: 0x11 */
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__IO uint32_t TCOR1; /* Offset: 0x14, Timer constant register 1 */
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__IO uint32_t TCNT1; /* Offset: 0x18, Timer counter 1 */
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__IO uint16_t TCR1; /* Offset: 0x1C, Timer control register 1 */
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uint8_t UNUSED3[2]; /* Offset: 0x1E */
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__IO uint32_t TCOR2; /* Offset: 0x20, Timer constant register 2 */
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__IO uint32_t TCNT2; /* Offset: 0x24, Timer counter 2 */
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__IO uint16_t TCR2; /* Offset: 0x28, Timer control register 2 */
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__IO uint8_t UNUSED4[2]; /* Offset: 0x2A */
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uint32_t TCPR2; /* Offset: 0x2C */
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} TMU_TypeDef;
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typedef struct {
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__IO uint32_t PTEH; /* Offset: 0x00, Page table entry high register */
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__IO uint32_t PTEL; /* Offset: 0x04, Page table entry low register */
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__IO uint32_t TTB; /* Offset: 0x08, Translation table base register */
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__IO uint32_t TEA; /* Offset: 0x0C, TLB exception address register */
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__IO uint32_t MMUCR; /* Offset: 0x10, MMU control register */
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__IO uint8_t BASRA; /* Offset: 0x14, Break ASID register A*/
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uint8_t UNUSED0[3]; /* Offset: 0x15 */
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__IO uint8_t BASRB; /* Offset: 0x18, Break ASID register B*/
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uint8_t UNUSED1[3]; /* Offset: 0x19 */
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__IO uint32_t CCR; /* Offset: 0x1C, Cache control register */
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__IO uint32_t TRA; /* Offset: 0x20, TRAPA exception register */
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__IO uint32_t EXPEVT; /* Offset: 0x24, Exception event register */
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__IO uint32_t INTEVT; /* Offset: 0x28, Interrupt event register */
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uint32_t UNUSED2[3]; /* Offset: 0x2C */
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__IO uint32_t QACR0; /* Offset: 0x38, Queue address control register 0 */
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__IO uint32_t QACR1; /* Offset: 0x3C, Queue address control register 1 */
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uint32_t UNUSED3[12]; /* Offset: 0x40 */
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__IO uint32_t PASCR; /* Offset: 0x70, Physical address space control register */
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__IO uint32_t RAMCR; /* Offset: 0x74, On-chip memory control register */
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__IO uint32_t IRMCR; /* Offset: 0x78, Instruction refetch inhibit control register */
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} CSR_TypeDef;
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#define XX sizeof(TMU_TypeDef)
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#define PIO0_BASE (0xFD020000U)
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#define PIO4_BASE (0xFD024000U)
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#define ASC0_BASE (0xFD030000U)
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#define ASC1_BASE (0xFD031000U)
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#define ASC2_BASE (0xFD032000U)
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#define ASC3_BASE (0xFD033000U)
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#define CSR_BASE (0xFF000000U)
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#define TMU_BASE (0xFFD80000U)
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#define PIO0 ((PIO_TypeDef *)PIO0_BASE)
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#define PIO4 ((PIO_TypeDef *)PIO4_BASE)
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#define ASC0 ((ASC_TypeDef *)ASC0_BASE)
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#define ASC1 ((ASC_TypeDef *)ASC1_BASE)
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#define ASC2 ((ASC_TypeDef *)ASC2_BASE)
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#define ASC3 ((ASC_TypeDef *)ASC3_BASE)
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#define CSR ((CSR_TypeDef *)CSR_BASE)
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#define TMU ((TMU_TypeDef *)TMU_BASE)
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#endif |