69 lines
2.5 KiB
C
69 lines
2.5 KiB
C
#ifndef STX7105_FDMA_H
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#define STX7105_FDMA_H
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#include "stx7105.h"
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typedef enum {
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FDMA_CMD_START_CHANNEL = 1U,
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FDMA_CMD_PAUSE_CHANNEL = 2U,
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FDMA_CMD_FLUSH_CHANNEL = 3U,
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} FDMA_Command_TypeDef;
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typedef enum {
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FDMA_STAT_CHANNEL_IDLE = 0U,
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FDMA_STAT_CHANNEL_RUNNING = 2U,
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FDMA_STAT_CHANNEL_PAUSED = 3U,
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} FDMA_Status_TypeDef;
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typedef enum {
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FDMA_REQ_CTL_OP_LDST1 = 0U,
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FDMA_REQ_CTL_OP_LDST2 = 1U,
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FDMA_REQ_CTL_OP_LDST4 = 2U,
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FDMA_REQ_CTL_OP_LDST8 = 3U,
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FDMA_REQ_CTL_OP_LDST16 = 4U,
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FDMA_REQ_CTL_OP_LDST32 = 5U,
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} FDMA_ReqCtl_Opcode_TypeDef;
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typedef struct {
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__IO uint32_t NEXT; /* Offset: 0x0000, Next node in the list */
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__IO uint32_t CTRL; /* Offset: 0x0004, Control register */
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__IO uint32_t NBYTES; /* Offset: 0x0008, Number of bytes */
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__IO uint32_t SADDR; /* Offset: 0x000C, Source address */
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__IO uint32_t DADDR; /* Offset: 0x0010, Destination address */
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__IO uint32_t LENGTH; /* Offset: 0x0014, Burst length */
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__IO uint32_t S_STRIDE; /* Offset: 0x0018, Source stride */
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__IO uint32_t D_STRIDE; /* Offset: 0x001C, Destination stride */
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} FDMA_FwRegs_Channel_TypeDef;
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/* Firmware regs, implemented on the base of DMEM */
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typedef struct {
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__IO uint32_t REVID; /* Offset: 0x8000 */
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uint32_t UNUSED0[1103]; /* Offset: 0x8004 */
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__IO uint32_t CMD_STAT[16]; /* Offset: 0x9140 */
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__IO uint32_t REQ_CTRL[16]; /* Offset: 0x9180 */
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uint32_t UNUSED1[240]; /* Offset: 0x91C0 */
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FDMA_FwRegs_Channel_TypeDef CHANNEL[16]; /* Offset: 0x9580 */
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} FDMA_FWRegs_TypeDef;
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#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_Pos 0U
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#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_
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#define FDMA_FwRegs_REQ_CTLN_OPCODE_Pos 4U
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#define FDMA_FwRegs_REQ_CTLN_OPCODE_Msk (0x0FU << FDMA_FwRegs_REQ_CTLN_OPCODE_Pos)
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#define FDMA_FwRegs_REQ_CTLN_WNR_Pos 14U
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#define FDMA_FwRegs_REQ_CTLN_WNR_Msk (1U << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
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#define FDMA_FwRegs_REQ_CTLN_DATA_SWAP_Pos 17U
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#define FDMA_FwRegs_REQ_CTLN_DATA_SWAP_Msk (1U << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
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#define FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos 21U
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#define FDMA_FwRegs_REQ_CTLN_INC_ADDR_Msk (1U << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
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#define FDMA_FwRegs_REQ_CTLN_INITIATOR_Pos 22U
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#define FDMA_FwRegs_REQ_CTLN_INITIATOR_Msk (1U << FDMA_FwRegs_REQ_CTLN_INITIATOR_Pos)
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#define FDMA_FwRegs_REQ_CTLN_NUM_OPS_Pos 24U
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#define FDMA_FwRegs_REQ_CTLN_NUM_OPS_Msk (0xFFU << FDMA_FwRegs_REQ_CTLN_INC_ADDR_Pos)
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#endif |