125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include "stx7105.h"
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#include "stx7105_fdma.h"
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#include "stx7105_fdma_fw.h"
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#include "stx7105_utils.h"
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#define LED_RED_GPIO PIO0
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#define LED_RED_PIN 5U
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#define LED_BLUE_GPIO PIO0
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#define LED_BLUE_PIN 4U
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#define CONSOLE_ASC ASC2
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#define SYSTEM_DEVID (0xFE001000U) /* DEVID */
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#define SYSTEM_CONFIG34 (0xFE001188U) /* PIO4 */
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#define SYSTEM_CONFIG7 (0xFE00111CU) /* RXSEL */
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#define MEMTEST_START 0x82000000
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#define MEMTEST_END 0x8F000000
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#define DMA_BUFFER_SIZE 16
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uint8_t src_buffer[DMA_BUFFER_SIZE];
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void uart_init(void) {
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PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */
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PIO4->SET_PC1 = 1U;
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PIO4->SET_PC2 = 1U;
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*(uint32_t *)SYSTEM_CONFIG34 = 0x00000100UL; /* BIT[8,0] = 10, AF 3 */
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*(uint32_t *)SYSTEM_CONFIG7 &= ~(0x00000006UL); /* BIT[2:1], UART2 RX SEL */
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CONSOLE_ASC->CTRL = 0x1509UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */
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CONSOLE_ASC->BAUDRATE = 0x04B8UL; /* 115200 in baud mode 1, assuming Fcomm=100MHz */
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CONSOLE_ASC->TX_RST = 0x01UL; /* Reset TX FIFO, any value OK */
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CONSOLE_ASC->RX_RST = 0x01UL; /* Reset RX FIFO, any value OK */
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CONSOLE_ASC->CTRL = 0x1589UL; /* 8N1, RX enable, FIFO enable, Baud mode 1 */
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}
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static void configure_fdma0(void) {
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FDMA0->SLIM_CLK_GATE |= (FDMA_SLIM_CLK_GATE_DIS_Msk | FDMA_SLIM_CLK_GATE_RESET_Msk);
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FDMA0->PERIPH_STBUS_SYNC |= FDMA_PERIPH_STBUS_SYNC_DIS_Msk;
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for (uint32_t i = 0; i < stx7105_fdma0_fw.text_size; i++) {
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FDMA0->SLIM_IMEM[i] = stx7105_fdma0_fw.text[i];
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}
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for (uint32_t i = 0; i < stx7105_fdma0_fw.data_size; i++) {
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FDMA0->SLIM_DMEM[i] = stx7105_fdma0_fw.data[i];
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}
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FDMA0->SLIM_CLK_GATE &= ~FDMA_SLIM_CLK_GATE_DIS_Msk;
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FDMA0->PERIPH_INT_CLR = 0xFFFFFFFFU;
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FDMA0->PERIPH_CMD_CLR = 0xFFFFFFFFU;
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FDMA0->SLIM_EN |= FDMA_SLIM_EN_RUN_Msk;
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printf("FDMA0 SLIM ID: 0x%08lx\r\n", FDMA0->SLIM_ID);
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printf("FDMA0 SLIM Version: 0x%08lx\r\n", FDMA0->SLIM_VER);
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}
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static void configure_fdma1(void) {
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FDMA1->SLIM_CLK_GATE |= (FDMA_SLIM_CLK_GATE_DIS_Msk | FDMA_SLIM_CLK_GATE_RESET_Msk);
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FDMA1->PERIPH_STBUS_SYNC |= FDMA_PERIPH_STBUS_SYNC_DIS_Msk;
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for (uint32_t i = 0; i < stx7105_fdma1_fw.text_size; i++) {
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FDMA1->SLIM_IMEM[i] = stx7105_fdma1_fw.text[i];
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}
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for (uint32_t i = 0; i < stx7105_fdma1_fw.data_size; i++) {
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FDMA1->SLIM_DMEM[i] = stx7105_fdma1_fw.data[i];
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}
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FDMA1->SLIM_CLK_GATE &= ~FDMA_SLIM_CLK_GATE_DIS_Msk;
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FDMA1->PERIPH_INT_CLR = 0xFFFFFFFFU;
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FDMA1->PERIPH_CMD_CLR = 0xFFFFFFFFU;
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FDMA1->SLIM_EN |= FDMA_SLIM_EN_RUN_Msk;
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printf("FDMA1 SLIM ID: 0x%08lx\r\n", FDMA1->SLIM_ID);
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printf("FDMA1 SLIM Version: 0x%08lx\r\n", FDMA1->SLIM_VER);
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}
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int main(void) {
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init_led(LED_RED_GPIO, LED_RED_PIN, 0U);
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init_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U);
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setbuf(stdout, NULL);
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setbuf(stderr, NULL);
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uart_init();
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printf("Hello world\r\n");
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printf("CKGA Opts 1: 0x%08lx\r\n", CKGA->CLKOPSRC_SWITCH_CFG);
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printf("CKGA Opts 2: 0x%08lx\r\n", CKGA->CLKOPSRC_SWITCH_CFG2);
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configure_fdma0();
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configure_fdma1();
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FDMA_FWRegs_TypeDef *fdma0_fwregs = (FDMA_FWRegs_TypeDef *)(FDMA0->SLIM_DMEM);
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fdma0_fwregs->CHANNEL[0].NEXT = (uint32_t)NULL;
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fdma0_fwregs->CHANNEL[0].NBYTES = DMA_BUFFER_SIZE;
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fdma0_fwregs->CHANNEL[0].LENGTH = DMA_BUFFER_SIZE;
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fdma0_fwregs->CHANNEL[0].SADDR = (uint32_t)src_buffer;
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fdma0_fwregs->CHANNEL[0].DADDR = CONSOLE_ASC->TX_BUF;
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fdma0_fwregs->CHANNEL[0].S_STRIDE = 0U;
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fdma0_fwregs->CHANNEL[0].D_STRIDE = 0U;
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fdma0_fwregs->REQ_CTRL[0] = (1U << FDMA_FwRegs_REQ_CTLN_NUM_OPS_Pos) | FDMA_FwRegs_REQ_CTLN_INC_ADDR_Msk;
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delay_ms(5000);
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for (;;) {
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set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 1U);
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delay_ms(500);
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set_led(LED_BLUE_GPIO, LED_BLUE_PIN, 0U);
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delay_ms(500);
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}
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return 0;
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}
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