411 lines
10 KiB
ArmAsm
411 lines
10 KiB
ArmAsm
/* Startup code, we can't use non-PIC code nor RAM before the LMI is initialized:
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* The CPU starts with physical address 0x0, however the linker is linked to virtual
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* addresses and LMI.
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* Non-PIC code means any indirect addressing other than relative to PC.
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*/
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.section .text.init, "ax"
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.global _start
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_start:
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nop
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nop
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/* Initialize Blue LED P0_4 */
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mov #16, r0
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mov.l _gpio_clr_k, r1
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mov.l r0, @r1
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mov.l _gpio_clr_pc0_k, r1
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mov.l r0, @r1
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mov.l _gpio_set_pc1_k, r1
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mov.l r0, @r1
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mov.l _gpio_clr_pc2_k, r1
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mov.l r0, @r1
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/* Initialize Red LED P0_5 */
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mov #32, r0
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mov.l _gpio_clr_k, r1
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mov.l r0, @r1
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mov.l _gpio_clr_pc0_k, r1
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mov.l r0, @r1
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mov.l _gpio_set_pc1_k, r1
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mov.l r0, @r1
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mov.l _gpio_clr_pc2_k, r1
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mov.l r0, @r1
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mov.l _sr_k, r0
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ldc r0, sr
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mov.l _stack_k, sp /* Setup R15(SP) */
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_disable_wdt:
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mov.l _cpg_wdt_wtcsr_k, r0
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mov.l _cpg_wdt_wtcsr_value_k, r1
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mov.w r1, @r0
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_configure_spinor:
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mov.l _emi_spinor_config_data_k, r0
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mov.l _emi_spinor_config_data_value_k, r1
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mov.l r1, @r0
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mov.l _emi_spinor_modeselect_k, r0
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mov.l _emi_spinor_modeselect_value_k, r1
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mov.l r1, @r0
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/* TODO: Initialize PMB, setup caches !! */
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/*
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* We need PMBs for LMI and EMI, both cached and uncached.
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* To configure an PMB region, two register writes need to be issued:
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* 1: Write to PMB address array, with region virtual address.
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* The PMB address array entry is calculated as follows:
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* - PMB_SLOT_X_ADDR=0xF610_0X00, X=0-F, with a maximum of 16 regions.
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* The slot contents are defined as follows:
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* - 0xAA00_0100, AA=Virtual page number, bit 31:30 has to be 0b10
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* i.e. VA should located in range 0x8000_0000 - 0xBFFF_FFFF
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* Note: VA needs to align with its configured size.
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* 2: Write to PMB data array, with region size and cache modes.
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* The PMB data array entry is calculated as follows:
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* PMB_SLOT_X_DATA=0xF710_0X00, X=0-F, with a maximum of 16 regions.
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*/
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_invalidate_pmb:
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mov.l _pmb_address_base, r1 /* PMB address slot base address */
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mov #0, r2 /* Value to be written to PMB address slot */
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mov #1, r3 /* PMB address stride, 0x100 */
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shll8 r3 /* See above */
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mov #0, r0 /* Counter */
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_loop_invalid_pmb:
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mov.l r2, @r1 /* Clear slot N */
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add r3, r1 /* Slot += 1 */
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cmp/eq #15, r0 /* Counter == 15? */
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bf/s _loop_invalid_pmb /* Note: this is a delayed branch, be careful. */
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add #1, r0 /* Counter += 1 */
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_setup_pmb:
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mova _pmb_poke_start_k, r0
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mov r0, r1
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mova _pmb_poke_end_k, r0
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mov r0, r2
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_loop_setup_pmb:
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mov.l @r1+, r0 /* 1st word, register address */
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mov.l @r1+, r3 /* 2nd word, register value */
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mov.l r3, @r0
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cmp/gt r1, r2
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bt _loop_setup_pmb
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_invalidate_caches:
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mov.l _ccn_ccr_k, r0
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mov #0, r1
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mov.l r1, @r0 /* Clear all bits */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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_setup_caches:
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mov.l _ccn_ccr_value_k, r1
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mov.l r1, @r0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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_enter_p0:
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mova _init_lmi, r0
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mov #0xE0, r1
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shll16 r1
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shll8 r1
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not r1, r1 /* MASK is 0x1fffffff */
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and r1, r0 /* unset top 3-bits */
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jmp @r0
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nop
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.balign 4
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/* TODO: Initialize LMI */
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_init_lmi:
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mov.l _init_ram_k, r1 /* Load actual function address to r1 */
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jsr @r1 /* Jump to the init_ram function */
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nop
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/* TODO: Switch to 32-bit mode */
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_enable_se_mode:
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mov.l _ccn_mmucr_k, r0
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mov #4, r1 /* SH4_MMUCR_TI */
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mov.l r1, @r0
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mov.l _ccn_pascr_k, r0
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mov.l _ccn_pascr_value_k, r1
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mov.l r1, @r0
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_setup_irq:
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mov.l _exc_base_k, r0
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ldc r0, vbr
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_go_non_privileged:
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mov.l _crt0_entry, r0
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ldc r0, spc
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stc sr, r0
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ldc r0, ssr
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rte
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nop
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/* RTE has to be aligned */
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.align 4
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_copy_data:
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mov.l _sidata_k, r0
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mov.l _sdata_k, r1
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mov.l _edata_k, r2
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_loop_copy_data:
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mov.l @r0+, r3 /* Load a word to r3 from [sidata], with post-increment of 4 */
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mov.l r3, @r1 /* Store the word in r3 to [sdata] */
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add #4, r1 /* Increment sdata pointer */
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cmp/gt r1, r2 /* r2 greater or equal than r1? */
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bt _loop_copy_data
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_zero_bss:
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mov.l _edata_k, r0
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mov.l _end_k, r1
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mov #0, r2
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_loop_zero_bss:
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mov.l r2, @r0
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add #4, r0
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cmp/gt r0, r1
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bt _loop_zero_bss
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/* Turn on Blue LED */
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mov #16, r7
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mov.l _gpio_set_k, r8
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mov.l r7, @r8
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_setup_fpu:
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mov.l _set_fpscr_k, r1
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jsr @r1
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mov #0, r4
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lds r3, fpscr
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/* Try to enable UART from Assembly... */
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mov.l _system_config_34_k, r0
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mov.l _system_config_34_value_k, r1
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mov.l r1, @r0
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mov.l _gpio4_clr_pc0_k, r0
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mov #1, r1
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mov.b r1, @r0
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mov.l _gpio4_set_pc1_k, r0
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mov.b r1, @r0
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mov.l _gpio4_set_pc2_k, r0
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mov.b r1, @r0
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mov.l _asc2_baud_k, r0
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mov.l _asc2_baud_value_k, r1
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mov.l r1, @r0
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mov.l _asc2_ctrl_k, r0
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mov.l _asc2_ctrl_value_k, r1
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mov.l r1, @r0
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mov.l _asc2_tx_buf_k, r0
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mov #65, r1
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mov.b r1, @r0
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_memory_test:
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mov.l _sdata_k, r0
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mov.l _stack_k, r1
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_loop_memory_write:
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mov.l r1, @-r1
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cmp/gt r0, r1
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bt _loop_memory_write
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_memory_compare:
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mov.l _stack_k, r1
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_loop_memory_compare:
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mov r1, r3
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mov.l @r1+, r2
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cmp/eq r2, r3
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bt _loop_memory_compare_addr
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mova _memory_fail_set_led, r0
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jmp @r0
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nop
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_loop_memory_compare_addr:
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cmp/gt r0, r1
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bt _loop_memory_compare
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mova _main_entry, r0
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jmp @r0
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nop
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.align 2
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_memory_fail_set_led:
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/* Turn on Red LED */
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mov #32, r7
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mov.l _gpio_set_k, r8
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mov.l r7, @r8
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.align 2
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_main_entry:
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/* Turn off Blue LED */
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mov #16, r7
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mov.l _gpio_clr_k, r8
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mov.l r7, @r8
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mov.l _main_k, r0
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jsr @r0
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or r0, r0
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mov r0, r4
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mov.l _exit_k, r0
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jsr @r0
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or r0, r0
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/* It would be more efficient by using indirect addressing instead of 8 instructions... */
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/* Align to 4 byte boundary since we are loading the whole word */
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.align 4
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/* PMB address register */
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_pmb_address_base:
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.long 0xF6100000
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/* PMB poke tables */
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_pmb_poke_start_k:
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.long 0xF6100000 /* Address entry #0 register : LMI lower half, 128MB, mapped to 0x8000_0000 */
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.long 0x80000100 /* Address entry #0 data : LMI lower half, 128MB, mapped to 0x8000_0000 */
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.long 0xF6100100 /* Address entry #1 register : LMI higher half, 128MB, mapped to 0x8800_0000 */
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.long 0x88000100 /* Address entry #1 data : LMI higher half, 128MB, mapped to 0x8800_0000 */
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.long 0xF6100200 /* Address entry #2 register : LMI lower half, 128MB, mapped to 0x9000_0000 */
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.long 0x90000100 /* Address entry #2 data : LMI lower half, 128MB, mapped to 0x9000_0000 */
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.long 0xF6100300 /* Address entry #3 register : LMI higher half, 128MB, mapped to 0x9800_0000 */
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.long 0x98000100 /* Address entry #3 data : LMI higher half, 128MB, mapped to 0x9800_0000 */
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.long 0xF6100400 /* Address entry #4 register : EMI NOR uncached, 64MB, mapped to 0xA000_0000 */
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.long 0xA0000100 /* Address entry #4 data : EMI NOR uncached, 64MB, mapped to 0xA000_0000 */
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.long 0xF6100500 /* Address entry #5 register : EMI NOR cached, 64MB, mapped to 0xA400_0000 */
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.long 0xA4000100 /* Address entry #5 data : EMI NOR cached, 64MB, mapped to 0xA400_0000 */
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.long 0xF7100000 /* Data entry #0 register : LMI lower half, 128MB, uncached, unbuffered */
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.long 0x40000380 /* Data entry #0 data : LMI lower half, 128MB, uncached, unbuffered */
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.long 0xF7100100 /* Data entry #1 register : LMI higher half, 128MB, uncached, unbuffered */
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.long 0x48000380 /* Data entry #1 data : LMI higher half, 128MB, uncached, unbuffered */
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.long 0xF7100200 /* Data entry #2 register : LMI lower half, 128MB, uncached, unbuffered */
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.long 0x40000380 /* Data entry #2 data : LMI lower half, 128MB, uncached, unbuffered */
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.long 0xF7100300 /* Data entry #3 register : LMI higher half, 128MB, uncached, unbuffered */
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.long 0x48000380 /* Data entry #3 data : LMI higher half, 128MB, uncached, unbuffered */
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.long 0xF7100400 /* Data entry #4 register : EMI NOR uncached, 64MB, uncached, unbuffered */
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.long 0x00000310 /* Data entry #4 data : EMI NOR uncached, 64MB, uncached, unbuffered */
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.long 0xF7100500 /* Data entry #5 register : EMI NOR cached, 64MB, cached, buffered */
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.long 0x00000118 /* Data entry #5 data : EMI NOR cached, 64MB, cached, buffered */
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_pmb_poke_end_k:
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.long 0x0000000
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/* CCN CCR address */
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_ccn_ccr_k:
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.long 0xFF00001C
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_ccn_ccr_value_k:
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.long 0x8000090D
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_ccn_mmucr_k:
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.long 0xFF000010
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_ccn_pascr_k:
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.long 0xFF000070
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_ccn_pascr_value_k:
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.long 0x80000000
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/* SR content */
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_sr_k:
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.long 0x400000F0
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/* WDT */
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_cpg_wdt_wtcsr_k:
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.long 0xFFC0000C
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_cpg_wdt_wtcsr_value_k:
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.long 0x0000A500
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/* EMI SPI NOR configuration registers */
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_emi_spinor_config_data_k:
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.long 0xFE702020
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_emi_spinor_config_data_value_k:
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.long 0x00020011
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_emi_spinor_modeselect_k:
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.long 0xFE702018
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_emi_spinor_modeselect_value_k:
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.long 0x00000002
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/* PIO registers for debugging */
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_gpio_set_k:
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.long 0xFD020004
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_gpio_clr_k:
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.long 0xFD020008
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_gpio_clr_pc0_k:
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.long 0xFD020028
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_gpio_set_pc1_k:
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.long 0xFD020034
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_gpio_clr_pc2_k:
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.long 0xFD020048
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_system_config_34_k:
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.long 0xFE001188
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_system_config_34_value_k:
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.long 0x00000F00
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_gpio4_clr_pc0_k:
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.long 0xFD024028
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_gpio4_set_pc1_k:
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.long 0xFD024034
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_gpio4_set_pc2_k:
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.long 0xFD024044
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_asc2_baud_k:
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.long 0xFD032000
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_asc2_baud_value_k:
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.long 0x000004B8
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_asc2_tx_buf_k:
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.long 0xFD032004
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_asc2_ctrl_k:
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.long 0xFD03200C
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_asc2_ctrl_value_k:
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.long 0x00001589
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_crt0_entry:
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.long _copy_data
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/* libc FPU routine */
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_set_fpscr_k:
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.long ___set_fpscr
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/* C library consts */
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_stack_k:
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.long _stack
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_sidata_k:
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.long _sidata
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_sdata_k:
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.long _sdata
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_edata_k:
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.long _edata
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_end_k:
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.long _end
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/* Function pointers */
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_init_ram_k:
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.long _memory_setup_init_ram
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_main_k:
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.long _main /* Same address as main */
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_exit_k:
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.long _exit
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_exc_base_k:
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.long _exc_base
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.section .text.exc, "ax"
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.align 4
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_exc_base:
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.org 0x100, 0x00
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_exc_grnl_vector:
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mov.l _exc_grnl_entry, r0
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jmp @r0
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nop
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.align 4
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_exc_grnl_entry:
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.long _general_exc_handler |