550 lines
15 KiB
Plaintext
Executable File
550 lines
15 KiB
Plaintext
Executable File
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/*
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sdk7105 connect start - parameters {'no_devid_validate': '1', 'no_convertor_abort': '1', 'no_devid_abort': '1'}
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Initialization TCK frequency set to 1562500 Hz
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Device id 0x1d43e041
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tapmux connect(): boot mode single core setup
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tapmux setup to bypass to core st40, channel 1
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sdk7105 initialization start ...
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sdk7105_setup - parameters {'tapmux_bypass_init': u'st40', 'no_devid_validate': '1', 'no_convertor_abort': '1', 'reset_low_period': 360000, 'no_devid_abort': '1'}
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Chip infos
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*/
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/*
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stx7105_sysconf_regs.SYSCONF_DEVICEID0
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PEEK(0xfe001000) (used target peek value 0x1d43e041)
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Device ID = 0x1D43E041 ==> STi7105 cut 2
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*/
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/*
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stx7105_sysconf_regs.SYSCONF_STA1
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PEEK(0xfe00100c) (used target peek value 0x00001015)
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Mode pins = 0x00001015 ==> ClockgenA ref : SYSCLKIN/OSC
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Boot mode ... : ST40 first
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Boot port size: 16-bits
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Boot device . : NOR flash
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*/
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/*stx7105_sysconf_regs.SYSCONF_CFG40*/
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POKE32(0xfe0011a0, 0x00000005)
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POKE32(0xfe0011a0, 0x00000005)
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/*stx7105_sysconf_regs.SYSCONF_CFG04*/
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POKE32(0xfe001110, 0x000001a6)
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/* Magic sequence to configure the ClockGenA switch control to reset values*/
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/* These do not appear to be correctly reset on WDT reset so do it here */
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/* CLOCKGEN A CKGA_CLKOPSRC_SWITCH_CFG reset=0 */
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POKE32(0xfe213014, 0x00000000)
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/* CLOCKGEN A CKGA_CLKOPSRC_SWITCH_CFG2 reset=0 */
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POKE32(0xfe213024, 0x00000000)
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/*stx7105_clockgena_regs.CKGA_PLL0_ENABLE_FB*/
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WHILE_NE32(0xfe21301c, 0xffffffff, 0x00000000)
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/*stx7105_clockgena_regs.CKGA_PLL1_ENABLE_FB*/
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WHILE_NE32(0xfe213020, 0xffffffff, 0x00000000)
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/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
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POKE32(0xfe213000, 0x80101e02)
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/*stx7105_clockgena_regs.CKGA_POWER_CFG*/
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POKE32(0xfe213010, 0x00000001)
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/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
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POKE32(0xfe213000, 0x00180f01)
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/*stx7105_clockgena_regs.CKGA_POWER_CFG*/
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POKE32(0xfe213010, 0x00000000)
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/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
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WHILE_NE32(0xfe213000, 0x80000000, 0x80000000)
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/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
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POKE32(0xfe213000, 0x80000f01)
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/*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
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POKE32(0xfe213004, 0x80102803)
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POKE32(0xfe213b00, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV0_CFG*/
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POKE32(0xfe213b04, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV1_CFG*/
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POKE32(0xfe213b08, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV2_CFG*/
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POKE32(0xfe213b0c, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV3_CFG*/
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POKE32(0xfe213a10, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV4_CFG*/
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POKE32(0xfe213b14, 0x00000307) /*stx7105_clockgena_regs.CKGA_PLL1_DIV5_CFG*/
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POKE32(0xfe213a18, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV6_CFG*/
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POKE32(0xfe213a1c, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV7_CFG*/
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POKE32(0xfe213b20, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV8_CFG*/
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POKE32(0xfe213b24, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV9_CFG*/
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POKE32(0xfe213b28, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV10_CFG*/
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POKE32(0xfe213b2c, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV11_CFG*/
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POKE32(0xfe213b30, 0x00000102) /*stx7105_clockgena_regs.CKGA_PLL1_DIV12_CFG*/
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POKE32(0xfe213a34, 0x00000811) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV13_CFG*/
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POKE32(0xfe213b38, 0x0000050b) /*stx7105_clockgena_regs.CKGA_PLL1_DIV14_CFG*/
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POKE32(0xfe213b3c, 0x00000307) /*stx7105_clockgena_regs.CKGA_PLL1_DIV15_CFG*/
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POKE32(0xfe213b40, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV16_CFG*/
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POKE32(0xfe213b44, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV17_CFG*/
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POKE32(0xfe213010, 0x00000002) /*stx7105_clockgena_regs.CKGA_POWER_CFG*/
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POKE32(0xfe213004, 0x00182803) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
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POKE32(0xfe213010, 0x00000000) /*stx7105_clockgena_regs.CKGA_POWER_CFG*/
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WHILE_NE32(0xfe213004, 0x80000000, 0x80000000) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
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POKE32(0xfe213004, 0x80002803) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
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POKE32(0xfe213014, 0xa6aa59aa) /*stx7105_clockgena_regs.CKGA_CLKOPSRC_SWITCH_CFG*/
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POKE32(0xfe213024, 0x0000000a) /*stx7105_clockgena_regs.CKGA_CLKOPSRC_SWITCH_CFG2*/
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/*stx7105_sysconf_regs.SYSCONF_CFG11*/
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POKE32(0xfe00112c, 0x00001d28)
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POKE32(0xfe00112c, 0x00001af4)
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POKE32(0xfe00112c, 0x00000af4)
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/*stx7105_sysconf_regs.SYSCONF_STA3*/
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WHILE_NE32(0xfe001014, 0x00000001, 0x00000000)
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/*set_lmi2x_freq: freq=800.000 rdiv=0x3, ddiv=0x50 Clock frequencies*/
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/*stx7105_sysconf_regs.SYSCONF_CFG04*/
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POKE32(0xfe001110, 0x000001a2)
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/*stx7105_sysconf_regs.SYSCONF_CFG11*/
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POKE32(0xfe00112c, 0x08000af5)
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/*stx7105_sysconf_regs.SYSCONF_CFG12*/
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POKE32(0xfe001130, 0xa000380f)
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POKE32(0xfe001130, 0xa000380f)
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POKE32(0xfe001130, 0xa000380f)
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POKE32(0xfe001130, 0xa000380f)
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POKE32(0xfe001130, 0xa000380f)
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POKE32(0xfe001130, 0xa000380f)
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POKE32(0xfe001130, 0xa200380f)
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POKE32(0xfe001130, 0xa200380f)
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POKE32(0xfe001130, 0xa200380f)
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POKE32(0xfe001130, 0xa200380f)
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POKE32(0xfe001130, 0xa200380f)
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POKE32(0xfe001130, 0xa200780f)
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POKE32(0xfe001130, 0xa200780f)
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POKE32(0xfe001130, 0xa200680f)
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POKE32(0xfe001130, 0xa200680f)
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POKE32(0xfe001130, 0xa200680f)
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POKE32(0xfe001130, 0xa200680f)
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POKE32(0xfe001130, 0xa200680f)
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POKE32(0xfe001130, 0xa200684f)
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POKE32(0xfe001130, 0xa200686f)
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/*
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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*/
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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POKE32(0xfe001130, 0xa200687f)
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/*stx7105_sysconf_regs.SYSCONF_CFG13*/
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POKE32(0xfe001134, 0x00400000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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POKE32(0xfe001134, 0x00600000)
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/*stx7105_sysconf_regs.SYSCONF_CFG14*/
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POKE32(0xfe001138, 0x00000000)
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POKE32(0xfe001138, 0x00000000)
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POKE32(0xfe001138, 0x00000000)
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POKE32(0xfe001138, 0x00000000)
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POKE32(0xfe001138, 0x00000000)
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POKE32(0xfe001138, 0x00000000)
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/*stx7105_sysconf_regs.SYSCONF_CFG38*/
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POKE32(0xfe001198, 0x0000fe00)
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POKE32(0xfe001198, 0x0000fe00)
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POKE32(0xfe001198, 0x0000fe00)
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POKE32(0xfe001198, 0x0020fe00)
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POKE32(0xfe001198, 0x0020fe00)
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POKE32(0xfe001198, 0x002cfe00)
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POKE32(0xfe001198, 0x002ffe00)
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POKE32(0xfe001198, 0x002ffe0c)
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/*stx7105_sysconf_regs.SYSCONF_CFG40*/
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POKE32(0xfe0011a0, 0x00000005)
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/*stx7105_sysconf_regs.SYSCONF_CFG42*/
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POKE32(0xfe0011a8, 0x20000000)
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POKE32(0xfe0011a8, 0x28000000)
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POKE32(0xfe0011a8, 0x2fb80000)
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POKE32(0xfe0011a8, 0x2fbbdc00)
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POKE32(0xfe0011a8, 0x2fbbddee)
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/*stx7105_sysconf_regs.SYSCONF_CFG43*/
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POKE32(0xfe0011ac, 0x00000000)
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POKE32(0xfe0011ac, 0x18000000)
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POKE32(0xfe0011ac, 0x18a00000)
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POKE32(0xfe0011ac, 0x18a001ee)
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/*stx7105_sysconf_regs.SYSCONF_CFG51*/
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POKE32(0xfe0011cc, 0x00000000)
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POKE32(0xfe0011cc, 0x00000000)
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/*stx7105_sysconf_regs.SYSCONF_CFG52*/
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POKE32(0xfe0011d0, 0x00000000)
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POKE32(0xfe0011d0, 0x00000000)
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/*stx7105_sysconf_regs.SYSCONF_CFG55*/
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POKE32(0xfe0011dc, 0x00002000)
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POKE32(0xfe0011dc, 0x00002000)
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POKE32(0xfe0011dc, 0x00002000)
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POKE32(0xfe0011dc, 0x07fc2000)
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POKE32(0xfe0011dc, 0x07fc2000)
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POKE32(0xfe0011dc, 0x07fc2000)
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POKE32(0xfe0011dc, 0x07fc2000)
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POKE32(0xfe0011dc, 0x07fc2280)
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POKE32(0xfe0011dc, 0x07fc22c0)
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POKE32(0xfe0011dc, 0x07fc22c0)
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POKE32(0xfe0011dc, 0x07fc22c4)
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/*stx7105_sysconf_regs.SYSCONF_CFG04*/
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POKE32(0xfe001110, 0x000001a6)
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DELAY(10)
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/*stx7105_sysconf_regs.SYSCONF_CFG13*/
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POKE32(0xfe001134, 0x00600000)
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/*stx7105_sysconf_regs.SYSCONF_CFG14*/
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POKE32(0xfe001138, 0x00000000)
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/*stx7105_sysconf_regs.SYSCONF_CFG42*/
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POKE32(0xfe0011a8, 0x2fbbddee)
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POKE32(0xfe0011a8, 0x2fbbddee)
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POKE32(0xfe0011a8, 0x2fbbddee)
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/*stx7105_sysconf_regs.SYSCONF_CFG43*/
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POKE32(0xfe0011ac, 0x18a001ee)
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POKE32(0xfe0011ac, 0x18a001ee)
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/*stx7105_sysconf_regs.SYSCONF_CFG51*/
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POKE32(0xfe0011cc, 0x00000000)
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POKE32(0xfe0011cc, 0x00000000)
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/*stx7105_sysconf_regs.SYSCONF_CFG52*/
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POKE32(0xfe0011d0, 0x00000000)
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POKE32(0xfe0011d0, 0x00000000)
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/*stx7105_sysconf_regs.SYSCONF_CFG55*/
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POKE32(0xfe0011dc, 0x07fc22c4)
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/*stx7105_sysconf_regs.SYSCONF_CFG04*/
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POKE32(0xfe001110, 0x000001a2)
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/*stx7105_sysconf_regs.SYSCONF_CFG11*/
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POKE32(0xfe00112c, 0x00000af5)
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POKE32(0xfe00112c, 0x00000af4)
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DELAY(10)
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POKE32(0xfe00112c, 0x08000af4)
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POKE32(0xfe00112c, 0x08000af5)
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DELAY(10)
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/*stx7105_sysconf_regs.SYSCONF_CFG04*/
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POKE32(0xfe001110, 0x000001a6)
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DELAY(10)
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/*st40_emi_regs.EMI_BANK_ENABLE*/
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POKE32(0xfe700860, 0x00000005)
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POKE32(0xfe700800, 0x00000000) /*st40_emi_regs.EMI_BANK0_BASEADDRESS*/
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POKE32(0xfe700810, 0x00000010) /*st40_emi_regs.EMI_BANK1_BASEADDRESS*/
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POKE32(0xfe700820, 0x00000018) /*st40_emi_regs.EMI_BANK2_BASEADDRESS*/
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POKE32(0xfe700830, 0x0000001a) /*st40_emi_regs.EMI_BANK3_BASEADDRESS*/
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POKE32(0xfe700840, 0x0000001c) /*st40_emi_regs.EMI_BANK4_BASEADDRESS*/
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/*st40_emi_regs.EMI_BANK0_EMICONFIGDATA0-3*/
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POKE32(0xfe700100, 0x001016d1)
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POKE32(0xfe700108, 0x9d200000)
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POKE32(0xfe700110, 0x9d220000)
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POKE32(0xfe700118, 0x00000000)
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/*st40_emi_regs.EMI_BANK1_EMICONFIGDATA0-3*/
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POKE32(0xfe700140, 0x002016d1)
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POKE32(0xfe700148, 0x9d222200)
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POKE32(0xfe700150, 0x9d220044)
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POKE32(0xfe700158, 0x00000000)
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/*st40_emi_regs.EMI_BANK2_EMICONFIGDATA0-3*/
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POKE32(0xfe700180, 0x002046f9)
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POKE32(0xfe700188, 0xa5a00000)
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POKE32(0xfe700190, 0xa5a20000)
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POKE32(0xfe700198, 0x00000000)
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/*st40_emi_regs.EMI_BANK3_EMICONFIGDATA0-3*/
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POKE32(0xfe7001c0, 0x002016d1)
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POKE32(0xfe7001c8, 0x9d222200)
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POKE32(0xfe7001d0, 0x9d220044)
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POKE32(0xfe7001d8, 0x00000000)
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/*st40_emi_regs.EMI_BANK4_EMICONFIGDATA0-3*/
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POKE32(0xfe700200, 0x002016d1)
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POKE32(0xfe700208, 0x9d222200)
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POKE32(0xfe700210, 0x9d220044)
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POKE32(0xfe700218, 0x00000000)
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/*st40_emi_regs.EMI_GENCFG*/
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POKE32(0xfe700028, 0x00000010)
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/*st40_lmigp_regs.LMI_MIM_0-1*/
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POKE32(0xfe901008, 0x0b30017b)
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POKE32(0xfe90100c, 0x000000b0)
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/*st40_lmigp_regs.LMI_STR_0-1*/
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POKE32(0xfe901018, 0xcf35b424)
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POKE32(0xfe90101c, 0x00242ed8)
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/*st40_lmigp_regs.LMI_SDRA0_0-1*/
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POKE32(0xfe901030, 0x1c001a20)
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POKE32(0xfe901038, 0x1c001a20)
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DELAY(200000)
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/*st40_lmigp_regs.LMI_SCR_0*/
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020023)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020022)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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/*st40_lmigp_regs.LMI_SDMR0_0*/
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POKE32(0xfe901048, 0x00010000)
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/*st40_lmigp_regs.LMI_SDMR0_0*/
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POKE32(0xfe901048, 0x00018000)
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/*st40_lmigp_regs.LMI_SDMR0_0*/
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POKE32(0xfe901048, 0x00008006)
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/*st40_lmigp_regs.LMI_SDMR0_0*/
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POKE32(0xfe901048, 0x00004363)
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/*st40_lmigp_regs.LMI_SCR_0*/
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020022)
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POKE32(0xfe901010, 0x00020024)
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POKE32(0xfe901010, 0x00020024)
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/*st40_lmigp_regs.LMI_SDMR0_0*/
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POKE32(0xfe901048, 0x00004263)
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/*st40_lmigp_regs.LMI_MIM_0*/
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POKE32(0xfe901008, 0x0b30037b)
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POKE32(0xfe901008, 0x0b30037b)
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/*st40_lmigp_regs.LMI_SCR_0*/
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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POKE32(0xfe901010, 0x00020021)
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/*st40_lmigp_regs.LMI_GCC_0*/
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POKE32(0xfe901028, 0x00000000)
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/*Info: correcting interco reset setup*/
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POKE32(0xfe20d200, 0x00000005)
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POKE32(0xfe20d204, 0x00000004)
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POKE32(0xfe20d208, 0x00000003)
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POKE32(0xfe20d20c, 0x00000002)
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POKE32(0xfe20d210, 0x00000001)
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POKE32(0xfe20d214, 0x00000001)
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POKE32(0xfe20d218, 0x00000001)
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POKE32(0xfe20d21c, 0x00000001)
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POKE32(0xfe20d220, 0x00000001)
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POKE32(0xfe2410fc, 0x00000005)
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POKE32(0xfe20a0ec, 0x00000002)
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POKE32(0xfe20a0f0, 0x00000005)
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POKE32(0xfe20a0f4, 0x00000003)
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POKE32(0xfe20a0f8, 0x00000003)
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POKE32(0xfe20a1ec, 0x00000002)
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POKE32(0xfe20a1f0, 0x00000005)
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POKE32(0xfe20a1f4, 0x00000003)
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POKE32(0xfe20a1f8, 0x00000003)
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POKE32(0xfe20a1fc, 0x00000000)
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POKE32(0xfe20a2ec, 0x00000002)
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POKE32(0xfe20a2f0, 0x00000005)
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POKE32(0xfe20a2f4, 0x00000003)
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POKE32(0xfe20a2f8, 0x00000003)
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POKE32(0xfe20a2fc, 0x00000000)
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POKE32(0xfe20a3ec, 0x00000002)
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POKE32(0xfe20a3f0, 0x00000005)
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POKE32(0xfe20a3f4, 0x00000003)
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POKE32(0xfe20a3f8, 0x00000003)
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POKE32(0xfe20a3fc, 0x00000000)
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POKE32(0xfe20aefc, 0x00000005)
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POKE32(0xfe540034, 0x00000003)
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POKE32(0xfe540038, 0x00000000)
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POKE32(0xfe540110, 0x00010303)
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POKE32(0xfe540114, 0x00000000)
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POKE32(0xfe540030, 0x00000005)
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POKE32(0xfe54010c, 0x00000005)
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POKE32(0xfe540600, 0x00000006)
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POKE32(0xfe540604, 0x00000005)
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POKE32(0xfe540608, 0x00000004)
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POKE32(0xfe54060c, 0x00000003)
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POKE32(0xfe540610, 0x00000002)
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POKE32(0xfe540614, 0x00000001)
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POKE32(0xfe540618, 0x00000000)
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POKE32(0xfe540680, 0x00000001)
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POKE32(0xfe540684, 0x00000000)
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POKE32(0xfe20bb04, 0x00000005)
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POKE32(0xfe20bb08, 0x00000003)
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POKE32(0xfe20bb10, 0x00000002)
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POKE32(0xfe20bb24, 0x00000005)
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POKE32(0xfe20bb28, 0x00000003)
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POKE32(0xfe20bb2c, 0x00000000)
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POKE32(0xfe20bb30, 0x00000002)
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POKE32(0xfe20bb44, 0x00000005)
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POKE32(0xfe20bb48, 0x00000003)
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POKE32(0xfe20bb4c, 0x00000000)
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POKE32(0xfe20bb50, 0x00000002)
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|
POKE32(0xfe20bb84, 0x00000005)
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|
POKE32(0xfe20bb88, 0x00000003)
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|
POKE32(0xfe20bb8c, 0x00000000)
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|
POKE32(0xfe20bb90, 0x00000002)
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POKE32(0xfe20a0fc, 0x00000000)
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|
POKE32(0xfe20bb0c, 0x00000000)
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|
POKE32(0xfe231010, 0x00000008)
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|
POKE32(0xfe231080, 0x00000221)
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POKE32(0xfe261010, 0x00000008)
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|
POKE32(0xfe261080, 0x00000221)
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|
POKE32(0xfd101024, 0x0003c000)
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|
POKE32(0xfd101824, 0x0003c000)
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POKE32(0xfd104d24, 0x0003c000)
|
|
POKE32(0xfd102024, 0x0003c000)
|
|
/* PEEK(0xfe001180) (used target peek value 0x00000b35) */
|
|
POKE32(0xfe001180, 0x00000b05)
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POKE32(0xfe1fff04, 0x00254608)
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|
POKE32(0xfeafff04, 0x00254608)
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|
/* PEEK(0xfe00111c) (used target peek value 0x08081508) */
|
|
POKE32(0xfe00111c, 0x08091508)
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POKE32(0xfd117000, 0x0025c608)
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|
POKE32(0xfd111000, 0x00201004)
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|
/* PEEK(0xfe001180) (used target peek value 0x00000b05) */
|
|
POKE32(0xfe001180, 0x00000b01)
|
|
POKE32(0xfe401744, 0x0025c005)
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|
|
|
|
|
/*st40_ccn_regs.CCN_CCR*/
|
|
POKE32(0xff00001c, 0x8000090d)
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|
|
|
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|
/*stx7105_sysconf_regs.SYSCONF_CFG09*/
|
|
POKE32(0xfe001124, 0x08000a8c)
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|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG05*/
|
|
POKE32(0xfe001114, 0x04000040)
|
|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG26*/
|
|
POKE32(0xfe001168, 0xfe804001)
|
|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG27*/
|
|
POKE32(0xfe00116c, 0x00001fd1)
|
|
POKE32(0xfe00116c, 0x00001fd0)
|
|
|
|
/*stx7105: booted audio companion*/
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG09*/
|
|
POKE32(0xfe001124, 0x08000a8c)
|
|
|
|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG05*/
|
|
POKE32(0xfe001114, 0x04000040)
|
|
|
|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG28*/
|
|
POKE32(0xfe001170, 0xfe604001)
|
|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG29*/
|
|
POKE32(0xfe001174, 0x00001fcd)
|
|
|
|
|
|
/*stx7105_sysconf_regs.SYSCONF_CFG29*/
|
|
POKE32(0xfe001174, 0x00001fcc)
|
|
|
|
/* stx7105: booted video companion*/
|
|
/* TCK frequency set to 12500000 Hz*/
|
|
/* tapmux complete_connect(): single core setup*/
|
|
/* sdk7105 initialization complete*/
|