diff --git a/CMakeLists.txt b/CMakeLists.txt
index be969e2..66c1419 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -79,6 +79,8 @@ include(component_lists_MIMXRT1052)
include(component_serial_manager_uart_MIMXRT1052)
+include(driver_semc_MIMXRT1052)
+
include(driver_lpuart_MIMXRT1052)
include(device_MIMXRT1052_startup_MIMXRT1052)
diff --git a/board/board.h b/board/board.h
index 6f77eea..ff6ed48 100644
--- a/board/board.h
+++ b/board/board.h
@@ -30,7 +30,7 @@
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
-#define BOARD_DEBUG_UART_BAUDRATE (115200U)
+#define BOARD_DEBUG_UART_BAUDRATE (921600)
#endif /* BOARD_DEBUG_UART_BAUDRATE */
/*! @brief The USER_LED used for board */
diff --git a/board/clock_config.c b/board/clock_config.c
index 32b6f48..1d5f98f 100644
--- a/board/clock_config.c
+++ b/board/clock_config.c
@@ -84,7 +84,7 @@ outputs:
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
-- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 150 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
@@ -97,7 +97,7 @@ settings:
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
-- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.SEMC_PODF.scale, value: '4', locked: true}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
@@ -231,7 +231,7 @@ void BOARD_BootClockRUN(void)
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
- CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 3);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
diff --git a/board/clock_config.c.bak b/board/clock_config.c.bak
index 349dc09..32b6f48 100644
--- a/board/clock_config.c.bak
+++ b/board/clock_config.c.bak
@@ -1,9 +1,3 @@
-/*
- * Copyright 2017-2020 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
/*
* How to setup clock using clock driver functions:
*
@@ -25,7 +19,7 @@ product: Clocks v7.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
-processor_version: 0.7.9
+processor_version: 9.0.0
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@@ -252,7 +246,7 @@ void BOARD_BootClockRUN(void)
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */
- CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
diff --git a/board/clock_config.h b/board/clock_config.h
index daf5873..f5396a2 100644
--- a/board/clock_config.h
+++ b/board/clock_config.h
@@ -72,7 +72,7 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
diff --git a/board/clock_config.h.bak b/board/clock_config.h.bak
index d03437b..daf5873 100644
--- a/board/clock_config.h.bak
+++ b/board/clock_config.h.bak
@@ -1,9 +1,3 @@
-/*
- * Copyright 2017-2020 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
diff --git a/board/peripherals.c b/board/peripherals.c
index 96eb1d5..0a58a6a 100644
--- a/board/peripherals.c
+++ b/board/peripherals.c
@@ -55,7 +55,7 @@ instance:
- lpuartConfig:
- clockSource: 'LpuartClock'
- lpuartSrcClkFreq: 'BOARD_BootClockRUN'
- - baudRate_Bps: '115200'
+ - baudRate_Bps: '921600'
- parityMode: 'kLPUART_ParityDisabled'
- dataBitsCount: 'kLPUART_EightDataBits'
- isMsb: 'false'
@@ -70,11 +70,10 @@ instance:
- rxIdleConfig: 'kLPUART_IdleCharacter1'
- enableTx: 'true'
- enableRx: 'true'
- - quick_selection: 'QuickSelection1'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
const lpuart_config_t LPUART1_config = {
- .baudRate_Bps = 115200UL,
+ .baudRate_Bps = 921600UL,
.parityMode = kLPUART_ParityDisabled,
.dataBitsCount = kLPUART_EightDataBits,
.isMsb = false,
@@ -95,6 +94,130 @@ static void LPUART1_init(void) {
LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
}
+/***********************************************************************************************************************
+ * SEMC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'SEMC'
+- type: 'semc'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'semc_84a769c198c91c527e11dcec2f5b4b81'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'SEMC'
+- config_sets:
+ - fsl_semc:
+ - enableDCD: 'false'
+ - clockConfig:
+ - clockSource: 'kSEMC_ClkSrcPeri'
+ - clockSourceFreq: 'BOARD_BootClockRUN'
+ - semc_config_t:
+ - dqsMode: 'kSEMC_Loopbackdqspad'
+ - cmdTimeoutCycles: '0'
+ - busTimeoutCycles: '0'
+ - queueWeight:
+ - queueaEnable: 'false'
+ - queueaWeight:
+ - structORvalue: 'structure'
+ - queueaConfig:
+ - qos: '0'
+ - aging: '0'
+ - slaveHitSwith: '0'
+ - slaveHitNoswitch: '0'
+ - queuebEnable: 'false'
+ - queuebWeight:
+ - structORvalue: 'structure'
+ - queuebConfig:
+ - qos: '0'
+ - aging: '0'
+ - slaveHitSwith: '0'
+ - weightPagehit: '0'
+ - bankRotation: '0'
+ - semc_sdram_config_t:
+ - csxPinMux: 'kSEMC_MUXCSX0'
+ - semcSdramCs: 'kSEMC_SDRAM_CS0'
+ - address: '0x80000000'
+ - memsize_input: '32MB'
+ - portSize: 'kSEMC_PortSize16Bit'
+ - burstLen: 'kSEMC_Sdram_BurstLen1'
+ - columnAddrBitNum: 'kSEMC_SdramColunm_9bit'
+ - casLatency: 'kSEMC_LatencyThree'
+ - tPrecharge2Act_Ns: '18'
+ - tAct2ReadWrite_Ns: '18'
+ - tRefreshRecovery_Ns: '127'
+ - tWriteRecovery_Ns: '12'
+ - tCkeOff_Ns: '42'
+ - tAct2Prechage_Ns: '42'
+ - tSelfRefRecovery_Ns: '67'
+ - tRefresh2Refresh_Ns: '60'
+ - tAct2Act_Ns: '60'
+ - tPrescalePeriod_Ns: '160'
+ - tIdleTimeout_Ns: '0'
+ - refreshPeriod_nsPerRow: '64'
+ - refreshUrgThreshold: '64'
+ - refreshBurstLen: '1'
+ - sdramArray: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+semc_config_t SEMC_config = {
+ .dqsMode = kSEMC_Loopbackdqspad,
+ .cmdTimeoutCycles = 0U,
+ .busTimeoutCycles = 0U,
+ .queueWeight = {
+ .queueaEnable = false,
+ .queueaWeight = {
+ .queueaConfig = {
+ .qos = 0UL,
+ .aging = 0UL,
+ .slaveHitSwith = 0UL,
+ .slaveHitNoswitch = 0UL
+ },
+ },
+ .queuebEnable = false,
+ .queuebWeight = {
+ .queuebConfig = {
+ .qos = 0UL,
+ .aging = 0UL,
+ .slaveHitSwith = 0UL,
+ .weightPagehit = 0UL,
+ .bankRotation = 0UL
+ },
+ }
+ }
+};
+semc_sdram_config_t SEMC_sdram_struct = {
+ .csxPinMux = kSEMC_MUXCSX0,
+ .address = 0x80000000UL,
+ .memsize_kbytes = 32768,
+ .portSize = kSEMC_PortSize16Bit,
+ .burstLen = kSEMC_Sdram_BurstLen1,
+ .columnAddrBitNum = kSEMC_SdramColunm_9bit,
+ .casLatency = kSEMC_LatencyThree,
+ .tPrecharge2Act_Ns = 18U,
+ .tAct2ReadWrite_Ns = 18U,
+ .tRefreshRecovery_Ns = 127U,
+ .tWriteRecovery_Ns = 12U,
+ .tCkeOff_Ns = 42U,
+ .tAct2Prechage_Ns = 42U,
+ .tSelfRefRecovery_Ns = 67U,
+ .tRefresh2Refresh_Ns = 60U,
+ .tAct2Act_Ns = 60U,
+ .tPrescalePeriod_Ns = 160UL,
+ .tIdleTimeout_Ns = 0UL,
+ .refreshPeriod_nsPerRow = 64UL,
+ .refreshUrgThreshold = 64UL,
+ .refreshBurstLen = 1U,
+};
+
+static void SEMC_init(void) {
+ /* Initialize SEMC peripheral. */
+ SEMC_Init(SEMC_PERIPHERAL, &SEMC_config);
+ /* Initialize SEMC SDRAM. */
+ SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
+}
+
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
@@ -102,6 +225,7 @@ void BOARD_InitPeripherals(void)
{
/* Initialize components */
LPUART1_init();
+ SEMC_init();
}
/***********************************************************************************************************************
diff --git a/board/peripherals.c.bak b/board/peripherals.c.bak
index 49aa105..acc6d2d 100644
--- a/board/peripherals.c.bak
+++ b/board/peripherals.c.bak
@@ -34,11 +34,199 @@ component:
**********************************************************************************************************************/
#include "peripherals.h"
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * LPUART1 initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'LPUART1'
+- type: 'lpuart'
+- mode: 'polling'
+- custom_name_enabled: 'false'
+- type_id: 'lpuart_54a65a580e3462acdbacefd5299e0cac'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'LPUART1'
+- config_sets:
+ - lpuartConfig_t:
+ - lpuartConfig:
+ - clockSource: 'LpuartClock'
+ - lpuartSrcClkFreq: 'BOARD_BootClockRUN'
+ - baudRate_Bps: '115200'
+ - parityMode: 'kLPUART_ParityDisabled'
+ - dataBitsCount: 'kLPUART_EightDataBits'
+ - isMsb: 'false'
+ - stopBitCount: 'kLPUART_OneStopBit'
+ - txFifoWatermark: '0'
+ - rxFifoWatermark: '1'
+ - enableRxRTS: 'false'
+ - enableTxCTS: 'false'
+ - txCtsSource: 'kLPUART_CtsSourcePin'
+ - txCtsConfig: 'kLPUART_CtsSampleAtStart'
+ - rxIdleType: 'kLPUART_IdleTypeStartBit'
+ - rxIdleConfig: 'kLPUART_IdleCharacter1'
+ - enableTx: 'true'
+ - enableRx: 'true'
+ - quick_selection: 'QuickSelection1'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const lpuart_config_t LPUART1_config = {
+ .baudRate_Bps = 115200UL,
+ .parityMode = kLPUART_ParityDisabled,
+ .dataBitsCount = kLPUART_EightDataBits,
+ .isMsb = false,
+ .stopBitCount = kLPUART_OneStopBit,
+ .txFifoWatermark = 0U,
+ .rxFifoWatermark = 1U,
+ .enableRxRTS = false,
+ .enableTxCTS = false,
+ .txCtsSource = kLPUART_CtsSourcePin,
+ .txCtsConfig = kLPUART_CtsSampleAtStart,
+ .rxIdleType = kLPUART_IdleTypeStartBit,
+ .rxIdleConfig = kLPUART_IdleCharacter1,
+ .enableTx = true,
+ .enableRx = true
+};
+
+static void LPUART1_init(void) {
+ LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
+}
+
+/***********************************************************************************************************************
+ * SEMC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'SEMC'
+- type: 'semc'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'semc_84a769c198c91c527e11dcec2f5b4b81'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'SEMC'
+- config_sets:
+ - fsl_semc:
+ - enableDCD: 'false'
+ - clockConfig:
+ - clockSource: 'kSEMC_ClkSrcPeri'
+ - clockSourceFreq: 'BOARD_BootClockRUN'
+ - semc_config_t:
+ - dqsMode: 'kSEMC_Loopbackdqspad'
+ - cmdTimeoutCycles: '0'
+ - busTimeoutCycles: '0'
+ - queueWeight:
+ - queueaEnable: 'false'
+ - queueaWeight:
+ - structORvalue: 'structure'
+ - queueaConfig:
+ - qos: '0'
+ - aging: '0'
+ - slaveHitSwith: '0'
+ - slaveHitNoswitch: '0'
+ - queuebEnable: 'false'
+ - queuebWeight:
+ - structORvalue: 'structure'
+ - queuebConfig:
+ - qos: '0'
+ - aging: '0'
+ - slaveHitSwith: '0'
+ - weightPagehit: '0'
+ - bankRotation: '0'
+ - semc_sdram_config_t:
+ - csxPinMux: 'kSEMC_MUXCSX0'
+ - semcSdramCs: 'kSEMC_SDRAM_CS0'
+ - address: '0x80000000'
+ - memsize_input: '32MB'
+ - portSize: 'kSEMC_PortSize16Bit'
+ - burstLen: 'kSEMC_Sdram_BurstLen1'
+ - columnAddrBitNum: 'kSEMC_SdramColunm_9bit'
+ - casLatency: 'kSEMC_LatencyThree'
+ - tPrecharge2Act_Ns: '18'
+ - tAct2ReadWrite_Ns: '18'
+ - tRefreshRecovery_Ns: '127'
+ - tWriteRecovery_Ns: '12'
+ - tCkeOff_Ns: '42'
+ - tAct2Prechage_Ns: '42'
+ - tSelfRefRecovery_Ns: '67'
+ - tRefresh2Refresh_Ns: '60'
+ - tAct2Act_Ns: '60'
+ - tPrescalePeriod_Ns: '160'
+ - tIdleTimeout_Ns: '0'
+ - refreshPeriod_nsPerRow: '64'
+ - refreshUrgThreshold: '64'
+ - refreshBurstLen: '1'
+ - sdramArray: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+semc_config_t SEMC_config = {
+ .dqsMode = kSEMC_Loopbackdqspad,
+ .cmdTimeoutCycles = 0U,
+ .busTimeoutCycles = 0U,
+ .queueWeight = {
+ .queueaEnable = false,
+ .queueaWeight = {
+ .queueaConfig = {
+ .qos = 0UL,
+ .aging = 0UL,
+ .slaveHitSwith = 0UL,
+ .slaveHitNoswitch = 0UL
+ },
+ },
+ .queuebEnable = false,
+ .queuebWeight = {
+ .queuebConfig = {
+ .qos = 0UL,
+ .aging = 0UL,
+ .slaveHitSwith = 0UL,
+ .weightPagehit = 0UL,
+ .bankRotation = 0UL
+ },
+ }
+ }
+};
+semc_sdram_config_t SEMC_sdram_struct = {
+ .csxPinMux = kSEMC_MUXCSX0,
+ .address = 0x80000000UL,
+ .memsize_kbytes = 32768,
+ .portSize = kSEMC_PortSize16Bit,
+ .burstLen = kSEMC_Sdram_BurstLen1,
+ .columnAddrBitNum = kSEMC_SdramColunm_9bit,
+ .casLatency = kSEMC_LatencyThree,
+ .tPrecharge2Act_Ns = 18U,
+ .tAct2ReadWrite_Ns = 18U,
+ .tRefreshRecovery_Ns = 127U,
+ .tWriteRecovery_Ns = 12U,
+ .tCkeOff_Ns = 42U,
+ .tAct2Prechage_Ns = 42U,
+ .tSelfRefRecovery_Ns = 67U,
+ .tRefresh2Refresh_Ns = 60U,
+ .tAct2Act_Ns = 60U,
+ .tPrescalePeriod_Ns = 160UL,
+ .tIdleTimeout_Ns = 0UL,
+ .refreshPeriod_nsPerRow = 64UL,
+ .refreshUrgThreshold = 64UL,
+ .refreshBurstLen = 1U,
+};
+
+static void SEMC_init(void) {
+ /* Initialize SEMC peripheral. */
+ SEMC_Init(SEMC_PERIPHERAL, &SEMC_config);
+ /* Initialize SEMC SDRAM. */
+ SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
+}
+
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void)
{
+ /* Initialize components */
+ LPUART1_init();
+ SEMC_init();
}
/***********************************************************************************************************************
diff --git a/board/peripherals.h b/board/peripherals.h
index d7248c0..78fd912 100644
--- a/board/peripherals.h
+++ b/board/peripherals.h
@@ -12,6 +12,7 @@
#include "fsl_common.h"
#include "fsl_lpuart.h"
#include "fsl_clock.h"
+#include "fsl_semc.h"
#if defined(__cplusplus)
extern "C" {
@@ -25,11 +26,16 @@ extern "C" {
#define LPUART1_PERIPHERAL LPUART1
/* Definition of the clock source frequency */
#define LPUART1_CLOCK_SOURCE 80000000UL
+/* BOARD_InitPeripherals defines for SEMC */
+/* Definition of peripheral ID. */
+#define SEMC_PERIPHERAL SEMC
/***********************************************************************************************************************
* Global variables
**********************************************************************************************************************/
extern const lpuart_config_t LPUART1_config;
+extern semc_config_t SEMC_config;
+extern semc_sdram_config_t SEMC_sdram_struct;
/***********************************************************************************************************************
* Initialization functions
diff --git a/board/peripherals.h.bak b/board/peripherals.h.bak
index fe99cdc..d7248c0 100644
--- a/board/peripherals.h.bak
+++ b/board/peripherals.h.bak
@@ -6,10 +6,31 @@
#ifndef _PERIPHERALS_H_
#define _PERIPHERALS_H_
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+#include "fsl_lpuart.h"
+#include "fsl_clock.h"
+
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals functional group */
+/* Definition of peripheral ID */
+#define LPUART1_PERIPHERAL LPUART1
+/* Definition of the clock source frequency */
+#define LPUART1_CLOCK_SOURCE 80000000UL
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+extern const lpuart_config_t LPUART1_config;
+
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
diff --git a/board/pin_mux.c b/board/pin_mux.c
index 4c5d481..258a1b8 100644
--- a/board/pin_mux.c
+++ b/board/pin_mux.c
@@ -38,6 +38,47 @@ BOARD_InitPins:
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+ - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
+ - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
+ - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
+ - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
+ - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
+ - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
+ - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
+ - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
+ - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
+ - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
+ - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
+ - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
+ - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
+ - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
+ - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
+ - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
+ - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
+ - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
+ - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
+ - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
+ - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+ - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+ - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+ - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+ - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+ - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+ - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+ - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+ - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
+ - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
+ - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
+ - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
+ - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
+ - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
+ - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
+ - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
+ - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+ - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
+ - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
+ - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
+ - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@@ -52,6 +93,47 @@ void BOARD_InitPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
diff --git a/board/pin_mux.c.bak b/board/pin_mux.c.bak
index ec00842..4c5d481 100644
--- a/board/pin_mux.c.bak
+++ b/board/pin_mux.c.bak
@@ -1,10 +1,3 @@
-/*
- * Copyright 2017-2020 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@@ -13,11 +6,12 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
-product: Pins v7.0
+product: Pins v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
-processor_version: 6.0.0
+processor_version: 9.0.0
+board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@@ -54,34 +48,12 @@ BOARD_InitPins:
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
- CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
- IOMUXC_SetPinMux(
- IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
- 0U); /* Software Input On Field: Input Path is determined by functionality */
- IOMUXC_SetPinMux(
- IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
- 0U); /* Software Input On Field: Input Path is determined by functionality */
- IOMUXC_SetPinConfig(
- IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
- 0x10B0U); /* Slew Rate Field: Slow Slew Rate
- Drive Strength Field: R0/6
- Speed Field: medium(100MHz)
- Open Drain Enable Field: Open Drain Disabled
- Pull / Keep Enable Field: Pull/Keeper Enabled
- Pull / Keep Select Field: Keeper
- Pull Up / Down Config. Field: 100K Ohm Pull Down
- Hyst. Enable Field: Hysteresis Disabled */
- IOMUXC_SetPinConfig(
- IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
- 0x10B0U); /* Slew Rate Field: Slow Slew Rate
- Drive Strength Field: R0/6
- Speed Field: medium(100MHz)
- Open Drain Enable Field: Open Drain Disabled
- Pull / Keep Enable Field: Pull/Keeper Enabled
- Pull / Keep Select Field: Keeper
- Pull Up / Down Config. Field: 100K Ohm Pull Down
- Hyst. Enable Field: Hysteresis Disabled */
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
/***********************************************************************************************************************
diff --git a/board/pin_mux.h b/board/pin_mux.h
index 18e01ad..c581434 100644
--- a/board/pin_mux.h
+++ b/board/pin_mux.h
@@ -47,6 +47,246 @@ void BOARD_InitBootPins(void);
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
+/* GPIO_EMC_09 (coord C2), SEMC_A0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
+
+/* GPIO_EMC_10 (coord G1), SEMC_A1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_EMC_11 (coord G3), SEMC_A2 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
+
+/* GPIO_EMC_12 (coord H1), SEMC_A3 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
+
+/* GPIO_EMC_13 (coord A6), SEMC_A4 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
+
+/* GPIO_EMC_14 (coord B6), SEMC_A5 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
+
+/* GPIO_EMC_15 (coord B1), SEMC_A6 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
+
+/* GPIO_EMC_16 (coord A5), SEMC_A7 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
+
+/* GPIO_EMC_17 (coord A4), SEMC_A8 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
+
+/* GPIO_EMC_18 (coord B2), SEMC_A9 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
+
+/* GPIO_EMC_23 (coord G2), SEMC_A10 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
+
+/* GPIO_EMC_19 (coord B4), SEMC_A11 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
+
+/* GPIO_EMC_20 (coord A3), SEMC_A12 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
+
+/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
+
+/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_EMC_24 (coord D3), SEMC_CAS */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
+
+/* GPIO_EMC_27 (coord A2), SEMC_CKE */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
+
+/* GPIO_EMC_26 (coord B3), SEMC_CLK */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
+
+/* GPIO_EMC_41 (coord C7), ENET_MDIO */
+/* Routed pin properties */
+#define BOARD_INITPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */
+#define BOARD_INITPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */
+
+/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
+#define BOARD_INITPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
+
+/* GPIO_EMC_00 (coord E3), SEMC_D0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
+
+/* GPIO_EMC_01 (coord F3), SEMC_D1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_EMC_02 (coord F4), SEMC_D2 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
+
+/* GPIO_EMC_03 (coord G4), SEMC_D3 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
+
+/* GPIO_EMC_04 (coord F2), SEMC_D4 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
+
+/* GPIO_EMC_05 (coord G5), SEMC_D5 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
+
+/* GPIO_EMC_06 (coord H5), SEMC_D6 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
+
+/* GPIO_EMC_07 (coord H4), SEMC_D7 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
+
+/* GPIO_EMC_30 (coord C6), SEMC_D8 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
+
+/* GPIO_EMC_31 (coord C5), SEMC_D9 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
+
+/* GPIO_EMC_32 (coord D5), SEMC_D10 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
+
+/* GPIO_EMC_33 (coord C4), SEMC_D11 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
+
+/* GPIO_EMC_34 (coord D4), SEMC_D12 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
+
+/* GPIO_EMC_35 (coord E5), SEMC_D13 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
+
+/* GPIO_EMC_36 (coord C3), SEMC_D14 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
+
+/* GPIO_EMC_37 (coord E4), SEMC_D15 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
+
+/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
+#define BOARD_INITPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
+
+/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
+#define BOARD_INITPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_EMC_25 (coord D2), SEMC_RAS */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
+
+/* GPIO_EMC_40 (coord A7), ENET_MDC */
+/* Routed pin properties */
+#define BOARD_INITPINS_ENET_MDC_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_ENET_MDC_SIGNAL semc_rdy /*!< Signal name */
+
+/* GPIO_EMC_28 (coord D1), SEMC_WE */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
+
/*!
* @brief Configures pin routing and optionally pin electrical features.
diff --git a/board/pin_mux.h.bak b/board/pin_mux.h.bak
index 83e03a8..18e01ad 100644
--- a/board/pin_mux.h.bak
+++ b/board/pin_mux.h.bak
@@ -1,10 +1,3 @@
-/*
- * Copyright 2017-2020 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@@ -44,6 +37,16 @@ extern "C" {
*/
void BOARD_InitBootPins(void);
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
+
/*!
* @brief Configures pin routing and optionally pin electrical features.
diff --git a/build.sh b/build.sh
new file mode 100644
index 0000000..f135e85
--- /dev/null
+++ b/build.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [[ -z "${ENV}" ]]; then
+ export ENV=debug
+fi
+
+rm build/${ENV} -rf && mkdir -p build/${ENV} && cd build/${ENV}
+
+cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" \
+ -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=${ENV} \
+ ../.. && make $@
+
diff --git a/build_all.sh b/build_all.sh
index 16be00e..f5d837c 100644
--- a/build_all.sh
+++ b/build_all.sh
@@ -1,9 +1,5 @@
#!/bin/sh
-if [ ! -d "build" ]; then mkdir build; fi
-
-cd build
-
TARGETS=(
"debug"
"release"
@@ -13,15 +9,8 @@ TARGETS=(
"flexspi_nor_release"
)
+bash clean.sh
+
for TARGET in "${TARGETS[@]}" ; do
- if [ -d "${TARGET}" ]; then rm -rf ${TARGET}; fi
- mkdir ${TARGET} && cd ${TARGET}
- if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
- if [ -f "Makefile" ];then rm -f Makefile; fi
- if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
- if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
- cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=${TARGET} ../.. && make -j1
- RET=$?
- if [ ! 0 -eq ${RET} ]; then exit ${RET}; fi
- cd ..
+ ENV=${TARGET} bash build.sh $@
done
diff --git a/build_debug.sh b/build_debug.sh
deleted file mode 100644
index 5461271..0000000
--- a/build_debug.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
-if [ -f "Makefile" ];then rm -f Makefile; fi
-if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
-if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
-cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
-make -j 2>&1 | tee build_log.txt
diff --git a/build_flexspi_nor_debug.sh b/build_flexspi_nor_debug.sh
deleted file mode 100644
index f5d64f2..0000000
--- a/build_flexspi_nor_debug.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
-if [ -f "Makefile" ];then rm -f Makefile; fi
-if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
-if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
-cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
-make -j 2>&1 | tee build_log.txt
diff --git a/build_flexspi_nor_release.sh b/build_flexspi_nor_release.sh
deleted file mode 100644
index 5e278c4..0000000
--- a/build_flexspi_nor_release.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
-if [ -f "Makefile" ];then rm -f Makefile; fi
-if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
-if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
-cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
-make -j 2>&1 | tee build_log.txt
diff --git a/build_release.sh b/build_release.sh
deleted file mode 100644
index bde3ccc..0000000
--- a/build_release.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
-if [ -f "Makefile" ];then rm -f Makefile; fi
-if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
-if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
-cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
-make -j 2>&1 | tee build_log.txt
diff --git a/build_sdram_debug.sh b/build_sdram_debug.sh
deleted file mode 100644
index a397837..0000000
--- a/build_sdram_debug.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
-if [ -f "Makefile" ];then rm -f Makefile; fi
-if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
-if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
-cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_debug .
-make -j 2>&1 | tee build_log.txt
diff --git a/build_sdram_release.sh b/build_sdram_release.sh
deleted file mode 100644
index c55149e..0000000
--- a/build_sdram_release.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
-if [ -f "Makefile" ];then rm -f Makefile; fi
-if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
-if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
-cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_release .
-make -j 2>&1 | tee build_log.txt
diff --git a/clean.sh b/clean.sh
index 673bd97..9e64c10 100644
--- a/clean.sh
+++ b/clean.sh
@@ -1,3 +1,3 @@
#!/bin/sh
-rm -rf debug release sdram_debug sdram_release flexspi_nor_debug flexspi_nor_release CMakeFiles
-rm -rf Makefile cmake_install.cmake CMakeCache.txt
+
+rm build -rf
\ No newline at end of file
diff --git a/drivers/driver_semc_MIMXRT1052.cmake b/drivers/driver_semc_MIMXRT1052.cmake
new file mode 100644
index 0000000..681013a
--- /dev/null
+++ b/drivers/driver_semc_MIMXRT1052.cmake
@@ -0,0 +1,17 @@
+if(NOT DRIVER_SEMC_MIMXRT1052_INCLUDED)
+
+ set(DRIVER_SEMC_MIMXRT1052_INCLUDED true CACHE BOOL "driver_semc component is included.")
+
+ target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_semc.c
+ )
+
+
+ target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/.
+ )
+
+
+ include(driver_common_MIMXRT1052)
+
+endif()
diff --git a/drivers/fsl_semc.c b/drivers/fsl_semc.c
new file mode 100644
index 0000000..4b43101
--- /dev/null
+++ b/drivers/fsl_semc.c
@@ -0,0 +1,1347 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_semc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.semc"
+#endif
+
+/*! @brief Define macros for SEMC driver. */
+#define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U)
+#define SEMC_IPCOMMANDMAGICKEY (0xA55A)
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
+#define SEMC_IOCR_PINMUXBITWIDTH (0x4UL)
+#else
+#define SEMC_IOCR_PINMUXBITWIDTH (0x3UL)
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+#define SEMC_IOCR_NAND_CE (4UL)
+#define SEMC_IOCR_NOR_CE (5UL)
+#define SEMC_IOCR_NOR_CE_A8 (2UL)
+#define SEMC_IOCR_PSRAM_CE (6UL)
+#define SEMC_IOCR_PSRAM_CE_A8 (3UL)
+#define SEMC_IOCR_DBI_CSX (7UL)
+#define SEMC_IOCR_DBI_CSX_A8 (4UL)
+#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U)
+#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX (28U)
+#define SEMC_BMCR0_TYPICAL_WQOS (5U)
+#define SEMC_BMCR0_TYPICAL_WAGE (8U)
+#define SEMC_BMCR0_TYPICAL_WSH (0x40U)
+#define SEMC_BMCR0_TYPICAL_WRWS (0x10U)
+#define SEMC_BMCR1_TYPICAL_WQOS (5U)
+#define SEMC_BMCR1_TYPICAL_WAGE (8U)
+#define SEMC_BMCR1_TYPICAL_WPH (0x60U)
+#define SEMC_BMCR1_TYPICAL_WBR (0x40U)
+#define SEMC_BMCR1_TYPICAL_WRWS (0x24U)
+#define SEMC_STARTADDRESS (0x80000000UL)
+#define SEMC_ENDADDRESS (0xDFFFFFFFUL)
+#define SEMC_BR_MEMSIZE_MIN (4U)
+#define SEMC_BR_MEMSIZE_OFFSET (2U)
+#define SEMC_BR_MEMSIZE_MAX (4UL * 1024UL * 1024UL)
+#define SEMC_SDRAM_MODESETCAL_OFFSET (4U)
+#define SEMC_BR_REG_NUM (9U)
+#define SEMC_BYTE_NUMBIT (8U)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for SEMC module.
+ *
+ * @param base SEMC peripheral base address
+ */
+static uint32_t SEMC_GetInstance(SEMC_Type *base);
+
+/*!
+ * @brief Covert the input memory size to internal register set value.
+ *
+ * @param base SEMC peripheral base address
+ * @param size_kbytes SEMC memory size in unit of kbytes.
+ * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F.
+ * @return Execution status.
+ */
+static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted);
+
+/*!
+ * @brief Covert the external timing nanosecond to internal clock cycle.
+ *
+ * @param time_ns SEMC external time interval in unit of nanosecond.
+ * @param clkSrc_Hz SEMC clock source frequency.
+ * @return The changed internal clock cycle.
+ */
+static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz);
+
+/*!
+ * @brief Configure IP command.
+ *
+ * @param base SEMC peripheral base address.
+ * @param size_bytes SEMC IP command data size.
+ * @return Execution status.
+ */
+static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes);
+
+/*!
+ * @brief Check if the IP command has finished.
+ *
+ * @param base SEMC peripheral base address.
+ * @return Execution status.
+ */
+static status_t SEMC_IsIPCommandDone(SEMC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to SEMC clocks for each instance. */
+static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS;
+#if (defined(SEMC_EXSC_CLOCKS))
+static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS;
+#endif /* SEMC_EXSC_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to SEMC bases for each instance. */
+static SEMC_Type *const s_semcBases[] = SEMC_BASE_PTRS;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SEMC_GetInstance(SEMC_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_semcBases); instance++)
+ {
+ if (s_semcBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_semcBases));
+
+ return instance;
+}
+
+static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted)
+{
+ assert(sizeConverted != NULL);
+ uint32_t memsize;
+ status_t status = kStatus_Success;
+
+ if ((size_kbytes < SEMC_BR_MEMSIZE_MIN) || (size_kbytes > SEMC_BR_MEMSIZE_MAX))
+ {
+ status = kStatus_SEMC_InvalidMemorySize;
+ }
+ else
+ {
+ *sizeConverted = 0U;
+ memsize = size_kbytes / 8U;
+ while (memsize != 0x00U)
+ {
+ memsize >>= 1U;
+ (*sizeConverted)++;
+ }
+ }
+
+ return status;
+}
+
+static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz)
+{
+ assert(clkSrc_Hz != 0x00U);
+
+ uint8_t clockCycles = 0;
+ uint32_t tClk_ps;
+
+ clkSrc_Hz /= 1000000U;
+ /* Using ps for high resolution */
+ tClk_ps = 1000000U / clkSrc_Hz;
+
+ while (tClk_ps * clockCycles < time_ns * 1000U)
+ {
+ clockCycles++;
+ }
+
+ return (clockCycles == 0x00U) ? clockCycles : (clockCycles - 0x01U);
+}
+
+static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes)
+{
+ status_t status = kStatus_Success;
+
+ if ((size_bytes > SEMC_IPCOMMANDDATASIZEBYTEMAX) || (size_bytes == 0x00U))
+ {
+ status = kStatus_SEMC_InvalidIpcmdDataSize;
+ }
+ else
+ {
+ /* Set data size. */
+ /* Note: It is better to set data size as the device data port width when transferring
+ * device command data. But for device memory data transfer, it can be set freely.
+ * Note: If the data size is greater than data port width, for example, datsz = 4, data port = 16bit,
+ * then the 4-byte data transfer will be split into two 2-byte transfers, the slave address
+ * will be switched automatically according to connected device type*/
+ base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes);
+ /* Clear data size. */
+ base->IPCR2 = 0;
+ /* Set data size. */
+ if (size_bytes < 4U)
+ {
+ base->IPCR2 |= SEMC_IPCR2_BM3_MASK;
+ }
+ if (size_bytes < 3U)
+ {
+ base->IPCR2 |= SEMC_IPCR2_BM2_MASK;
+ }
+ if (size_bytes < 2U)
+ {
+ base->IPCR2 |= SEMC_IPCR2_BM1_MASK;
+ }
+ }
+
+ return status;
+}
+
+static status_t SEMC_IsIPCommandDone(SEMC_Type *base)
+{
+ status_t status = kStatus_Success;
+
+ /* Poll status bit till command is done*/
+ while ((base->INTR & (uint32_t)SEMC_INTR_IPCMDDONE_MASK) == 0x00U)
+ {
+ };
+
+ /* Clear status bit */
+ base->INTR |= SEMC_INTR_IPCMDDONE_MASK;
+
+ /* Check error status */
+ if ((base->INTR & (uint32_t)SEMC_INTR_IPCMDERR_MASK) != 0x00U)
+ {
+ base->INTR |= SEMC_INTR_IPCMDERR_MASK;
+ status = kStatus_SEMC_IpCommandExecutionError;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Gets the SEMC default basic configuration structure.
+ *
+ * The purpose of this API is to get the default SEMC
+ * configure structure for SEMC_Init(). User may use the initialized
+ * structure unchanged in SEMC_Init(), or modify some fields of the
+ * structure before calling SEMC_Init().
+ * Example:
+ code
+ semc_config_t config;
+ SEMC_GetDefaultConfig(&config);
+ endcode
+ * param config The SEMC configuration structure pointer.
+ */
+void SEMC_GetDefaultConfig(semc_config_t *config)
+{
+ assert(config != NULL);
+
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0, sizeof(*config));
+
+ config->queueWeight.queueaEnable = true;
+ semc_queuea_weight_struct_t *queueaWeight = &(config->queueWeight.queueaWeight.queueaConfig);
+ config->queueWeight.queuebEnable = true;
+ semc_queueb_weight_struct_t *queuebWeight = &(config->queueWeight.queuebWeight.queuebConfig);
+
+ /* Get default settings. */
+ config->dqsMode = kSEMC_Loopbackinternal;
+ config->cmdTimeoutCycles = 0xFF;
+ config->busTimeoutCycles = 0x1F;
+
+ queueaWeight->qos = SEMC_BMCR0_TYPICAL_WQOS;
+ queueaWeight->aging = SEMC_BMCR0_TYPICAL_WAGE;
+ queueaWeight->slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH;
+ queueaWeight->slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS;
+ queuebWeight->qos = SEMC_BMCR1_TYPICAL_WQOS;
+ queuebWeight->aging = SEMC_BMCR1_TYPICAL_WAGE;
+ queuebWeight->slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS;
+ queuebWeight->weightPagehit = SEMC_BMCR1_TYPICAL_WPH;
+ queuebWeight->bankRotation = SEMC_BMCR1_TYPICAL_WBR;
+}
+
+/*!
+ * brief Initializes SEMC.
+ * This function ungates the SEMC clock and initializes SEMC.
+ * This function must be called before calling any other SEMC driver functions.
+ *
+ * param base SEMC peripheral base address.
+ * param configure The SEMC configuration structure pointer.
+ */
+void SEMC_Init(SEMC_Type *base, semc_config_t *configure)
+{
+ assert(configure != NULL);
+
+ uint8_t index = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Un-gate sdram controller clock. */
+ CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]);
+#if (defined(SEMC_EXSC_CLOCKS))
+ CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]);
+#endif /* SEMC_EXSC_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ /* Initialize all BR to zero due to the default base address set. */
+ for (index = 0; index < SEMC_BR_REG_NUM; index++)
+ {
+ base->BR[index] = 0;
+ }
+
+ /* Software reset for SEMC internal logical . */
+ base->MCR = SEMC_MCR_SWRST_MASK;
+ while ((base->MCR & (uint32_t)SEMC_MCR_SWRST_MASK) != 0x00U)
+ {
+ }
+
+ /* Configure, disable module first. */
+ base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_BTO(configure->busTimeoutCycles) |
+ SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode);
+
+ if (configure->queueWeight.queueaEnable == true)
+ {
+ /* Configure Queue A for AXI bus access to SDRAM, NAND, NOR, SRAM and DBI slaves.*/
+ base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight.queueaValue);
+ }
+ else
+ {
+ base->BMCR0 = 0x00U;
+ }
+
+ if (configure->queueWeight.queuebEnable == true)
+ {
+ /* Configure Queue B for AXI bus access to SDRAM slave. */
+ base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight.queuebValue);
+ }
+ else
+ {
+ base->BMCR1 = 0x00U;
+ }
+
+ /* Enable SEMC. */
+ base->MCR &= ~SEMC_MCR_MDIS_MASK;
+}
+
+/*!
+ * brief Deinitializes the SEMC module and gates the clock.
+ * This function gates the SEMC clock. As a result, the SEMC
+ * module doesn't work after calling this function.
+ *
+ * param base SEMC peripheral base address.
+ */
+void SEMC_Deinit(SEMC_Type *base)
+{
+ /* Disable module. Check there is no pending command before disable module. */
+ while ((base->STS0 & (uint32_t)SEMC_STS0_IDLE_MASK) == 0x00U)
+ {
+ ;
+ }
+
+ base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable SDRAM clock. */
+ CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]);
+#if (defined(SEMC_EXSC_CLOCKS))
+ CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]);
+#endif /* SEMC_EXSC_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Configures SDRAM controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param cs The chip selection.
+ * param config The sdram configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz)
+{
+ assert(config != NULL);
+ assert(clkSrc_Hz > 0x00U);
+ assert(config->refreshBurstLen > 0x00U);
+
+ uint8_t memsize;
+ status_t result = kStatus_Success;
+ uint16_t prescale = (uint16_t)(config->tPrescalePeriod_Ns / 16U / (1000000000U / clkSrc_Hz));
+ uint32_t refresh;
+ uint32_t urgentRef;
+ uint32_t idle;
+ uint32_t mode;
+ uint32_t timing;
+
+ if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS))
+ {
+ return kStatus_SEMC_InvalidBaseAddress;
+ }
+
+ if (config->csxPinMux == kSEMC_MUXA8)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+
+ if (prescale > 256U)
+ {
+ return kStatus_SEMC_InvalidTimerSetting;
+ }
+
+ refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns;
+ urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns;
+ idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns;
+
+ uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->csxPinMux));
+
+ /* Base control. */
+ result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+
+ base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+
+#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT)
+ if (kSEMC_SdramColunm_8bit == config->columnAddrBitNum)
+ {
+ base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) |
+ SEMC_SDRAMCR0_COL8(true) | SEMC_SDRAMCR0_CL(config->casLatency);
+ }
+ else
+#endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */
+ {
+ base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) |
+ SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency);
+ }
+
+ /* IOMUX setting. */
+ if (cs != kSEMC_SDRAM_CS0)
+ {
+ base->IOCR = iocReg | ((uint32_t)cs << (uint32_t)config->csxPinMux);
+ }
+
+ base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK;
+
+#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
+ uint32_t tempDelayChain = base->DCCR;
+
+ tempDelayChain &= ~(SEMC_DCCR_SDRAMVAL_MASK | SEMC_DCCR_SDRAMEN_MASK);
+ /* Configure delay chain. */
+ base->DCCR = tempDelayChain | SEMC_DCCR_SDRAMVAL((uint32_t)config->delayChain - 0x01U) | SEMC_DCCR_SDRAMEN_MASK;
+#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
+
+ timing = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz));
+ /* SDRAMCR1 timing setting. */
+ base->SDRAMCR1 = timing;
+
+ timing = SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR2_REF2REF(SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz));
+ timing |= SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | SEMC_SDRAMCR2_ITO(idle);
+ /* SDRAMCR2 timing setting. */
+ base->SDRAMCR2 = timing;
+
+ /* SDRAMCR3 timing setting. */
+ base->SDRAMCR3 = SEMC_SDRAMCR3_REBL((uint32_t)config->refreshBurstLen - 1UL) |
+ /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */
+ SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh - 1UL) | SEMC_SDRAMCR3_UT(urgentRef);
+
+ SEMC->IPCR1 = 0x2U;
+ SEMC->IPCR2 = 0U;
+
+ result =
+ SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, (uint32_t)kSEMC_SDRAMCM_Prechargeall, 0, NULL);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ result =
+ SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, (uint32_t)kSEMC_SDRAMCM_AutoRefresh, 0, NULL);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ result =
+ SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, (uint32_t)kSEMC_SDRAMCM_AutoRefresh, 0, NULL);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ /* Mode setting value. */
+ mode = (uint32_t)config->burstLen | (((uint32_t)config->casLatency) << SEMC_SDRAM_MODESETCAL_OFFSET);
+ result =
+ SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, (uint32_t)kSEMC_SDRAMCM_Modeset, mode, NULL);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ /* Enables refresh */
+ base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Configures NAND controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The nand configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)
+{
+ assert(config != NULL);
+ assert(config->timingConfig != NULL);
+
+ uint8_t memsize;
+ status_t result;
+ uint32_t timing;
+
+ if ((config->axiAddress < SEMC_STARTADDRESS) || (config->axiAddress > SEMC_ENDADDRESS))
+ {
+ return kStatus_SEMC_InvalidBaseAddress;
+ }
+
+ if (config->cePinMux == kSEMC_MUXRDY)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+
+ /* Disable SEMC module during configuring control registers. */
+ base->MCR |= SEMC_MCR_MDIS_MASK;
+
+ uint32_t iocReg =
+ base->IOCR & (~((SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->cePinMux) | SEMC_IOCR_MUX_RDY_MASK));
+
+ /* Base control. */
+ if (config->rdyactivePolarity == kSEMC_RdyActivehigh)
+ {
+ base->MCR |= SEMC_MCR_WPOL1_MASK;
+ }
+ else
+ {
+ base->MCR &= ~SEMC_MCR_WPOL1_MASK;
+ }
+ result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+
+ result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+
+ /* IOMUX setting. */
+ if ((uint32_t)config->cePinMux != 0x00U)
+ {
+ base->IOCR = iocReg | (SEMC_IOCR_NAND_CE << (uint32_t)config->cePinMux);
+ }
+ else
+ {
+ base->IOCR = iocReg | (1UL << (uint32_t)config->cePinMux);
+ }
+
+ base->NANDCR0 = SEMC_NANDCR0_PS(config->portSize) | SEMC_NANDCR0_BL(config->burstLen) |
+ SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum);
+
+ timing = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz));
+ /* NANDCR1 timing setting. */
+ base->NANDCR1 = timing;
+
+ timing = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz));
+ timing |= SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz));
+
+ /* NANDCR2 timing setting. */
+ base->NANDCR2 = timing;
+
+ /* NANDCR3 timing setting. */
+ base->NANDCR3 = (uint32_t)config->arrayAddrOption;
+
+ /* Enables SEMC module after configuring control registers completely. */
+ base->MCR &= ~SEMC_MCR_MDIS_MASK;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Configures NOR controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The nor configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)
+{
+ assert(config != NULL);
+
+ uint8_t memsize;
+ status_t result;
+ uint32_t timing;
+
+ if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS))
+ {
+ return kStatus_SEMC_InvalidBaseAddress;
+ }
+
+ uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->cePinMux));
+ uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
+ (SEMC_IOCR_NOR_CE - 1U) :
+ ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE);
+
+ /* IOMUX setting. */
+ base->IOCR = iocReg | (muxCe << (uint32_t)config->cePinMux);
+ /* Address bit setting. */
+ if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE)
+ {
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1U))
+ {
+ /* Address bit 24 (A24) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX0_MASK;
+ if (config->cePinMux == kSEMC_MUXCSX0)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2U))
+ {
+ /* Address bit 25 (A25) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX1_MASK;
+ if (config->cePinMux == kSEMC_MUXCSX1)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3U))
+ {
+ /* Address bit 26 (A26) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX2_MASK;
+ if (config->cePinMux == kSEMC_MUXCSX2)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4U))
+ {
+ if (config->addr27 == kSEMC_NORA27_MUXCSX3)
+ {
+ /* Address bit 27 (A27) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX3_MASK;
+ }
+ else if (config->addr27 == kSEMC_NORA27_MUXRDY)
+ {
+ base->IOCR |= SEMC_IOCR_MUX_RDY_MASK;
+ }
+ else
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ if (config->cePinMux == kSEMC_MUXCSX3)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX)
+ {
+ return kStatus_SEMC_InvalidAddressPortWidth;
+ }
+ }
+
+ /* Base control. */
+ if (config->rdyactivePolarity == kSEMC_RdyActivehigh)
+ {
+ base->MCR |= SEMC_MCR_WPOL0_MASK;
+ }
+ else
+ {
+ base->MCR &= ~SEMC_MCR_WPOL0_MASK;
+ }
+ result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+ base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) |
+ SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) |
+ SEMC_NORCR0_COL(config->columnAddrBitNum);
+
+#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
+ uint32_t tempDelayChain = base->DCCR;
+
+ tempDelayChain &= ~(SEMC_DCCR_NORVAL_MASK | SEMC_DCCR_NOREN_MASK);
+ /* Configure delay chain. */
+ base->DCCR = tempDelayChain | SEMC_DCCR_NORVAL((uint32_t)config->delayChain - 0x01U) | SEMC_DCCR_NOREN_MASK;
+#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
+
+ timing = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));
+
+ /* NORCR1 timing setting. */
+ base->NORCR1 = timing;
+
+ timing = SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
+ timing |= SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz));
+#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME */
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
+ timing |= SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz));
+#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME */
+ timing |= SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz));
+ timing |= SEMC_NORCR2_AWDH((uint32_t)SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 0x01UL);
+ timing |= SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD((uint32_t)config->readCycle - 0x01UL);
+
+ /* NORCR2 timing setting. */
+ base->NORCR2 = timing;
+
+ return SEMC_ConfigureIPCommand(base, ((uint8_t)config->portSize + 1U));
+}
+
+/*!
+ * brief Configures SRAM controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The sram configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz)
+{
+ return SEMC_ConfigureSRAMWithChipSelection(base, kSEMC_SRAM_CS0, config, clkSrc_Hz);
+}
+
+/*!
+ * brief Configures SRAM controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param cs The chip selection.
+ * param config The sram configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
+ semc_sram_cs_t cs,
+ semc_sram_config_t *config,
+ uint32_t clkSrc_Hz)
+{
+ assert(config != NULL);
+
+ uint32_t tempBRVal;
+ uint32_t timing;
+ uint8_t memsize;
+ status_t result = kStatus_Success;
+
+ if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS))
+ {
+ return kStatus_SEMC_InvalidBaseAddress;
+ }
+
+ uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->cePinMux));
+
+ uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
+ (SEMC_IOCR_PSRAM_CE - 1U) :
+ ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE);
+
+ /* IOMUX setting. */
+ base->IOCR = iocReg | (muxCe << (uint32_t)config->cePinMux);
+ /* Address bit setting. */
+ if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE)
+ {
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1U))
+ {
+ /* Address bit 24 (A24) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX0_MASK;
+ if (config->cePinMux == kSEMC_MUXCSX0)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2U))
+ {
+ /* Address bit 25 (A25) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX1_MASK;
+ if (config->cePinMux == kSEMC_MUXCSX1)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3U))
+ {
+ /* Address bit 26 (A26) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX2_MASK;
+ if (config->cePinMux == kSEMC_MUXCSX2)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth >= (SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4U))
+ {
+ if (config->addr27 == kSEMC_NORA27_MUXCSX3)
+ {
+ /* Address bit 27 (A27) */
+ base->IOCR &= ~(uint32_t)SEMC_IOCR_MUX_CSX3_MASK;
+ }
+ else if (config->addr27 == kSEMC_NORA27_MUXRDY)
+ {
+ base->IOCR |= SEMC_IOCR_MUX_RDY_MASK;
+ }
+ else
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+
+ if (config->cePinMux == kSEMC_MUXCSX3)
+ {
+ return kStatus_SEMC_InvalidSwPinmuxSelection;
+ }
+ }
+ if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX)
+ {
+ return kStatus_SEMC_InvalidAddressPortWidth;
+ }
+ }
+ /* Base control. */
+ result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+
+ tempBRVal = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+
+ uint32_t tempCtrlVal;
+
+ switch (cs)
+ {
+ case kSEMC_SRAM_CS0:
+ base->BR[6] = tempBRVal;
+ break;
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
+ case kSEMC_SRAM_CS1:
+ base->BR9 = tempBRVal;
+ break;
+ case kSEMC_SRAM_CS2:
+ base->BR10 = tempBRVal;
+ break;
+ case kSEMC_SRAM_CS3:
+ base->BR11 = tempBRVal;
+ break;
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+ default:
+ assert(NULL);
+ break;
+ }
+
+ /* PSRAM0 SRAMCRx timing setting. */
+ if (kSEMC_SRAM_CS0 == cs)
+ {
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
+ /* Ready/wait(WAITEN and WAITSP) feature is only for async mode. */
+ if (kSEMC_AsyncMode == config->syncMode)
+ {
+ tempCtrlVal = SEMC_SRAMCR0_PS(config->portSize) |
+#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
+ SEMC_SRAMCR4_SYNCEN(config->syncMode) |
+#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
+#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK)
+ SEMC_SRAMCR0_WAITEN(config->waitEnable) |
+#endif /* SEMC_SRAMCR0_WAITEN_MASK */
+#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK)
+ SEMC_SRAMCR0_WAITSP(config->waitSample) |
+#endif /* SEMC_SRAMCR0_WAITSP_MASK */
+ SEMC_SRAMCR0_BL(config->burstLen) | SEMC_SRAMCR0_AM(config->addrMode) |
+ SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
+#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
+ SEMC_SRAMCR4_ADVH(config->advLevelCtrl) |
+#endif /* SEMC_SRAMCR4_ADVH_MASK */
+ SEMC_SRAMCR0_COL_MASK;
+ }
+ else
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+ {
+ tempCtrlVal = SEMC_SRAMCR0_PS(config->portSize) |
+#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
+ SEMC_SRAMCR4_SYNCEN(config->syncMode) |
+#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
+ SEMC_SRAMCR0_BL(config->burstLen) | SEMC_SRAMCR0_AM(config->addrMode) |
+ SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
+#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
+ SEMC_SRAMCR4_ADVH(config->advLevelCtrl) |
+#endif /* SEMC_SRAMCR4_ADVH_MASK */
+ SEMC_SRAMCR0_COL_MASK;
+ }
+
+ base->SRAMCR0 = tempCtrlVal;
+ }
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
+ /* PSRAM1~PSRAM3 SRAMCRx timing setting. */
+ else
+ {
+ /* Ready/wait(WAITEN and WAITSP) feature is only for async mode. */
+ if (kSEMC_AsyncMode == config->syncMode)
+ {
+ tempCtrlVal = SEMC_SRAMCR4_PS(config->portSize) | SEMC_SRAMCR4_SYNCEN(config->syncMode) |
+ SEMC_SRAMCR4_WAITEN(config->waitEnable) | SEMC_SRAMCR4_WAITSP(config->waitSample) |
+ SEMC_SRAMCR4_BL(config->burstLen) | SEMC_SRAMCR4_AM(config->addrMode) |
+ SEMC_SRAMCR4_ADVP(config->advActivePolarity) | SEMC_SRAMCR4_ADVH(config->advLevelCtrl) |
+ SEMC_SRAMCR4_COL_MASK;
+ }
+ else
+ {
+ tempCtrlVal = SEMC_SRAMCR4_PS(config->portSize) | SEMC_SRAMCR4_SYNCEN(config->syncMode) |
+ SEMC_SRAMCR4_BL(config->burstLen) | SEMC_SRAMCR4_AM(config->addrMode) |
+ SEMC_SRAMCR4_ADVP(config->advActivePolarity) | SEMC_SRAMCR4_ADVH(config->advLevelCtrl) |
+ SEMC_SRAMCR4_COL_MASK;
+ }
+
+ base->SRAMCR4 = tempCtrlVal;
+ }
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+
+#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
+ uint32_t tempDelayChain = base->DCCR;
+
+ /* Configure delay chain. */
+ switch (cs)
+ {
+ case kSEMC_SRAM_CS0:
+ tempDelayChain &= ~(SEMC_DCCR_SRAM0VAL_MASK | SEMC_DCCR_SRAM0EN_MASK);
+ base->DCCR =
+ tempDelayChain | SEMC_DCCR_SRAM0VAL((uint32_t)config->delayChain - 0x01U) | SEMC_DCCR_SRAM0EN_MASK;
+ break;
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
+ case kSEMC_SRAM_CS1:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kSEMC_SRAM_CS2:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kSEMC_SRAM_CS3:
+ tempDelayChain &= ~(SEMC_DCCR_SRAMXVAL_MASK | SEMC_DCCR_SRAMXEN_MASK);
+ base->DCCR =
+ tempDelayChain | SEMC_DCCR_SRAMXVAL((uint32_t)config->delayChain - 0x01U) | SEMC_DCCR_SRAMXEN_MASK;
+ break;
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+ default:
+ assert(NULL);
+ break;
+ }
+#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
+
+ if (kSEMC_SRAM_CS0 == cs)
+ {
+ timing = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));
+
+ /* SRAMCR1 timing setting. */
+ base->SRAMCR1 = timing;
+
+ timing = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR2_WDH((uint32_t)SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz) + 1UL);
+ timing |= SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD((uint32_t)config->readCycle - 1UL);
+ timing |= SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));
+#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
+ timing |= SEMC_SRAMCR2_RDH((uint32_t)SEMC_ConvertTiming(config->readHoldTime_Ns, clkSrc_Hz) + 0x01U);
+#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
+
+ /* SRAMCR2 timing setting. */
+ base->SRAMCR2 = timing;
+ }
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
+ else
+ {
+ timing = SEMC_SRAMCR5_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR5_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));
+
+ /* SRAMCR5 timing setting. */
+ base->SRAMCR5 = timing;
+
+ timing = SEMC_SRAMCR6_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR6_WDH((uint32_t)SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz) + 1UL);
+ timing |= SEMC_SRAMCR6_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR6_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz));
+ timing |= SEMC_SRAMCR6_LC(config->latencyCount) | SEMC_SRAMCR2_RD((uint32_t)config->readCycle - 1UL);
+ timing |= SEMC_SRAMCR6_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));
+#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
+ timing |= SEMC_SRAMCR6_RDH((uint32_t)SEMC_ConvertTiming(config->readHoldTime_Ns, clkSrc_Hz) + 0x01U);
+#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
+
+ /* SRAMCR6 timing setting. */
+ base->SRAMCR6 = timing;
+ }
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+
+ return result;
+}
+
+/*!
+ * brief Configures DBI controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The dbi configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz)
+{
+ assert(config != NULL);
+
+ uint8_t memsize;
+ status_t result;
+ uint32_t timing;
+
+ if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS))
+ {
+ return kStatus_SEMC_InvalidBaseAddress;
+ }
+
+ uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->csxPinMux));
+ uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ?
+ (SEMC_IOCR_DBI_CSX - 1U) :
+ ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX);
+
+ /* IOMUX setting. */
+ base->IOCR = iocReg | (muxCsx << (uint32_t)config->csxPinMux);
+ /* Base control. */
+ result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+
+ /* DBICR0 timing setting. */
+ base->DBICR0 =
+ SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum);
+
+ timing = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz));
+ timing |= SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz));
+ timing |= SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz));
+ timing |= SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz));
+ timing |= SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz));
+ timing |= SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz));
+
+ /* DBICR1 timing setting. */
+ base->DBICR1 = timing;
+ return SEMC_ConfigureIPCommand(base, ((uint8_t)config->portSize + 1U));
+}
+
+/*!
+ * brief SEMC IP command access.
+ *
+ * param base SEMC peripheral base address.
+ * param type SEMC memory type. refer to "semc_mem_type_t"
+ * param address SEMC device address.
+ * param command SEMC IP command.
+ * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
+ * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
+ * For SRAM device, take refer to "semc_ipcmd_sram_t".
+ * For SDRAM device, take refer to "semc_ipcmd_sdram_t".
+ * param write Data for write access.
+ * param read Data pointer for read data out.
+ */
+status_t SEMC_SendIPCommand(
+ SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
+{
+ uint32_t cmdMode;
+ bool readCmd = false;
+ bool writeCmd = false;
+ status_t result;
+
+ /* Clear status bit */
+ base->INTR |= SEMC_INTR_IPCMDDONE_MASK;
+ /* Set address. */
+ base->IPCR0 = address;
+
+ /* Check command mode. */
+ cmdMode = (uint32_t)command & 0x0FU;
+ switch (type)
+ {
+ case kSEMC_MemType_NAND:
+ readCmd = (cmdMode == (uint32_t)kSEMC_NANDCM_CommandAddressRead) ||
+ (cmdMode == (uint32_t)kSEMC_NANDCM_CommandRead) || (cmdMode == (uint32_t)kSEMC_NANDCM_Read);
+ writeCmd = (cmdMode == (uint32_t)kSEMC_NANDCM_CommandAddressWrite) ||
+ (cmdMode == (uint32_t)kSEMC_NANDCM_CommandWrite) || (cmdMode == (uint32_t)kSEMC_NANDCM_Write);
+ break;
+ case kSEMC_MemType_NOR:
+ case kSEMC_MemType_8080:
+ readCmd = (cmdMode == (uint32_t)kSEMC_NORDBICM_Read);
+ writeCmd = (cmdMode == (uint32_t)kSEMC_NORDBICM_Write);
+ break;
+ case kSEMC_MemType_SRAM:
+ readCmd = (cmdMode == (uint32_t)kSEMC_SRAMCM_ArrayRead) || (cmdMode == (uint32_t)kSEMC_SRAMCM_RegRead);
+ writeCmd = (cmdMode == (uint32_t)kSEMC_SRAMCM_ArrayWrite) || (cmdMode == (uint32_t)kSEMC_SRAMCM_RegWrite);
+ break;
+ case kSEMC_MemType_SDRAM:
+ readCmd = (cmdMode == (uint32_t)kSEMC_SDRAMCM_Read);
+ writeCmd = (cmdMode == (uint32_t)kSEMC_SDRAMCM_Write) || (cmdMode == (uint32_t)kSEMC_SDRAMCM_Modeset);
+ break;
+ default:
+ assert(false);
+ break;
+ }
+
+ if (writeCmd)
+ {
+ /* Set data. */
+ base->IPTXDAT = write;
+ }
+
+ /* Set command code. */
+ base->IPCMD = command | SEMC_IPCMD_KEY(SEMC_IPCOMMANDMAGICKEY);
+ /* Wait for command done. */
+ result = SEMC_IsIPCommandDone(base);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+
+ if (readCmd)
+ {
+ /* Get the read data */
+ *read = base->IPRXDAT;
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief SEMC NAND device memory write through IP command.
+ *
+ * param base SEMC peripheral base address.
+ * param address SEMC NAND device address.
+ * param data Data for write access.
+ * param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
+{
+ assert(data != NULL);
+
+ status_t result = kStatus_Success;
+ uint16_t ipCmd;
+ uint32_t tempData = 0;
+
+ /* Write command built */
+ ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Write);
+ while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX)
+ {
+ /* Configure IP command data size. */
+ (void)SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX);
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, *(uint32_t *)(void *)data, NULL);
+ if (result != kStatus_Success)
+ {
+ break;
+ }
+
+ data += SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ }
+
+ if ((result == kStatus_Success) && (size_bytes != 0x00U))
+ {
+ (void)SEMC_ConfigureIPCommand(base, (uint8_t)size_bytes);
+
+ while (size_bytes != 0x00U)
+ {
+ size_bytes--;
+ tempData <<= SEMC_BYTE_NUMBIT;
+ tempData |= data[size_bytes];
+ }
+
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL);
+ }
+
+ return result;
+}
+
+/*!
+ * brief SEMC NAND device memory read through IP command.
+ *
+ * param base SEMC peripheral base address.
+ * param address SEMC NAND device address.
+ * param data Data pointer for data read out.
+ * param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
+{
+ assert(data != NULL);
+
+ status_t result = kStatus_Success;
+ uint16_t ipCmd;
+ uint32_t tempData = 0;
+
+ /* Configure IP command data size. */
+ (void)SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX);
+ /* Read command built */
+ ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Read);
+
+ while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX)
+ {
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, (uint32_t *)(void *)data);
+ if (result != kStatus_Success)
+ {
+ break;
+ }
+
+ data += SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ }
+
+ if ((result == kStatus_Success) && (size_bytes != 0x00U))
+ {
+ (void)SEMC_ConfigureIPCommand(base, (uint8_t)size_bytes);
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, &tempData);
+
+ while (size_bytes != 0x00U)
+ {
+ size_bytes--;
+ *(data + size_bytes) = (uint8_t)((tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU);
+ }
+ }
+
+ return result;
+}
+
+/*!
+ * brief SEMC NOR device memory read through IP command.
+ *
+ * param base SEMC peripheral base address.
+ * param address SEMC NOR device address.
+ * param data Data pointer for data read out.
+ * param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
+{
+ assert(data != NULL);
+
+ uint32_t tempData = 0;
+ status_t result = kStatus_Success;
+ uint8_t dataSize = (uint8_t)base->NORCR0 & SEMC_NORCR0_PS_MASK;
+
+ /* Configure IP command data size. */
+ (void)SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX);
+
+ while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX)
+ {
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, (uint32_t)kSEMC_NORDBICM_Read, 0,
+ (uint32_t *)(void *)data);
+ if (result != kStatus_Success)
+ {
+ break;
+ }
+
+ data += SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ }
+
+ if ((result == kStatus_Success) && (size_bytes != 0x00U))
+ {
+ (void)SEMC_ConfigureIPCommand(base, (uint8_t)size_bytes);
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, (uint16_t)kSEMC_NORDBICM_Read, 0, &tempData);
+ while (size_bytes != 0x00U)
+ {
+ size_bytes--;
+ *(data + size_bytes) = (uint8_t)((tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU);
+ }
+ }
+
+ (void)SEMC_ConfigureIPCommand(base, dataSize);
+ return result;
+}
+
+/*!
+ * brief SEMC NOR device memory write through IP command.
+ *
+ * param base SEMC peripheral base address.
+ * param address SEMC NOR device address.
+ * param data Data for write access.
+ * param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
+{
+ assert(data != NULL);
+
+ uint32_t tempData = 0;
+ status_t result = kStatus_Success;
+ uint8_t dataSize = (uint8_t)base->NORCR0 & SEMC_NORCR0_PS_MASK;
+
+ /* Write command built */
+ while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX)
+ {
+ /* Configure IP command data size. */
+ (void)SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX);
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, (uint16_t)kSEMC_NORDBICM_Write,
+ *(uint32_t *)(void *)data, NULL);
+ if (result != kStatus_Success)
+ {
+ break;
+ }
+ size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ data += SEMC_IPCOMMANDDATASIZEBYTEMAX;
+ }
+
+ if ((result == kStatus_Success) && (size_bytes != 0x00U))
+ {
+ (void)SEMC_ConfigureIPCommand(base, (uint8_t)size_bytes);
+
+ while (size_bytes != 0x00U)
+ {
+ tempData |= ((uint32_t) * (data + size_bytes - 1U) << ((size_bytes - 1U) * SEMC_BYTE_NUMBIT));
+ size_bytes--;
+ }
+
+ result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, (uint16_t)kSEMC_NORDBICM_Write, tempData, NULL);
+ }
+ (void)SEMC_ConfigureIPCommand(base, dataSize);
+
+ return result;
+}
diff --git a/drivers/fsl_semc.h b/drivers/fsl_semc.h
new file mode 100644
index 0000000..d445c9f
--- /dev/null
+++ b/drivers/fsl_semc.h
@@ -0,0 +1,912 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_SEMC_H_
+#define _FSL_SEMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup semc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SEMC driver version 2.3.1. */
+#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+/*@}*/
+
+/*! @brief SEMC status, _semc_status. */
+enum
+{
+ kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */
+ kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */
+ kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */
+ kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */
+ kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */
+ kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */
+ kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */
+ kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */
+ kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */
+ /*! Invalid column address bit width. */
+ kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
+ kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */
+ kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */
+};
+
+/*! @brief SEMC memory device type. */
+typedef enum _semc_mem_type
+{
+ kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
+ kSEMC_MemType_SRAM, /*!< SRAM */
+ kSEMC_MemType_NOR, /*!< NOR */
+ kSEMC_MemType_NAND, /*!< NAND */
+ kSEMC_MemType_8080 /*!< 8080. */
+} semc_mem_type_t;
+
+/*! @brief SEMC WAIT/RDY polarity. */
+typedef enum _semc_waitready_polarity
+{
+ kSEMC_LowActive = 0, /*!< Low active. */
+ kSEMC_HighActive, /*!< High active. */
+} semc_waitready_polarity_t;
+
+/*! @brief SEMC SDRAM Chip selection . */
+typedef enum _semc_sdram_cs
+{
+ kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
+ kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
+ kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
+ kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
+} semc_sdram_cs_t;
+
+/*! @brief SEMC SRAM Chip selection . */
+typedef enum _semc_sram_cs
+{
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U)
+ kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
+ kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */
+ kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */
+ kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */
+#else
+ kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
+} semc_sram_cs_t;
+
+/*! @brief SEMC NAND device type. */
+typedef enum _semc_nand_access_type
+{
+ kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */
+ kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */
+} semc_nand_access_type_t;
+
+/*! @brief SEMC interrupts . */
+typedef enum _semc_interrupt_enable
+{
+ kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
+ kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
+ kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
+ kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
+} semc_interrupt_enable_t;
+
+/*! @brief SEMC IP command data size in bytes. */
+typedef enum _semc_ipcmd_datasize
+{
+ kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
+ kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
+ kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
+ kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
+} semc_ipcmd_datasize_t;
+
+/*! @brief SEMC auto-refresh timing. */
+typedef enum _semc_refresh_time
+{
+ kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
+ kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
+ kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
+} semc_refresh_time_t;
+
+/*! @brief CAS latency */
+typedef enum _semc_caslatency
+{
+ kSEMC_LatencyOne = 1, /*!< Latency 1. */
+ kSEMC_LatencyTwo, /*!< Latency 2. */
+ kSEMC_LatencyThree, /*!< Latency 3. */
+} semc_caslatency_t;
+
+/*! @brief SEMC sdram column address bit number. */
+typedef enum _semc_sdram_column_bit_num
+{
+ kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
+ kSEMC_SdramColunm_11bit, /*!< 11 bit. */
+ kSEMC_SdramColunm_10bit, /*!< 10 bit. */
+ kSEMC_SdramColunm_9bit, /*!< 9 bit. */
+#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT)
+ kSEMC_SdramColunm_8bit, /*!< 8 bit. */
+#endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */
+} semc_sdram_column_bit_num_t;
+
+/*! @brief SEMC sdram burst length. */
+typedef enum _semc_sdram_burst_len
+{
+/*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during
+ long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */
+#if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U)
+ kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
+#else
+ kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
+ kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
+ kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
+ kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
+#endif /* FSL_FEATURE_SEMC_ERRATA_050577 */
+} sem_sdram_burst_len_t;
+
+/*! @brief SEMC nand column address bit number. */
+typedef enum _semc_nand_column_bit_num
+{
+ kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
+ kSEMC_NandColum_15bit, /*!< 15 bit. */
+ kSEMC_NandColum_14bit, /*!< 14 bit. */
+ kSEMC_NandColum_13bit, /*!< 13 bit. */
+ kSEMC_NandColum_12bit, /*!< 12 bit. */
+ kSEMC_NandColum_11bit, /*!< 11 bit. */
+ kSEMC_NandColum_10bit, /*!< 10 bit. */
+ kSEMC_NandColum_9bit, /*!< 9 bit. */
+} semc_nand_column_bit_num_t;
+
+/*! @brief SEMC nand burst length. */
+typedef enum _semc_nand_burst_len
+{
+ kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
+ kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
+ kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
+ kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
+ kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
+ kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
+ kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
+} sem_nand_burst_len_t;
+
+/*! @brief SEMC nor/sram column address bit number. */
+typedef enum _semc_norsram_column_bit_num
+{
+ kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
+ kSEMC_NorColum_11bit, /*!< 11 bit. */
+ kSEMC_NorColum_10bit, /*!< 10 bit. */
+ kSEMC_NorColum_9bit, /*!< 9 bit. */
+ kSEMC_NorColum_8bit, /*!< 8 bit. */
+ kSEMC_NorColum_7bit, /*!< 7 bit. */
+ kSEMC_NorColum_6bit, /*!< 6 bit. */
+ kSEMC_NorColum_5bit, /*!< 5 bit. */
+ kSEMC_NorColum_4bit, /*!< 4 bit. */
+ kSEMC_NorColum_3bit, /*!< 3 bit. */
+ kSEMC_NorColum_2bit /*!< 2 bit. */
+} semc_norsram_column_bit_num_t;
+
+/*! @brief SEMC nor/sram burst length. */
+typedef enum _semc_norsram_burst_len
+{
+ kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
+ kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
+ kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
+ kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
+ kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
+ kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
+ kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
+} sem_norsram_burst_len_t;
+
+/*! @brief SEMC dbi column address bit number. */
+typedef enum _semc_dbi_column_bit_num
+{
+ kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
+ kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
+ kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
+ kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
+ kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
+ kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
+ kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
+ kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
+ kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
+ kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
+ kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
+} semc_dbi_column_bit_num_t;
+
+/*! @brief SEMC dbi burst length. */
+typedef enum _semc_dbi_burst_len
+{
+ kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
+ kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
+ kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
+ kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
+ kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
+ kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
+ kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
+} sem_dbi_burst_len_t;
+
+/*! @brief SEMC IOMUXC. */
+typedef enum _semc_iomux_pin
+{
+ kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
+ kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
+ kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
+ kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
+ kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
+ kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
+} semc_iomux_pin;
+
+/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
+typedef enum _semc_iomux_nora27_pin
+{
+ kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
+ kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
+ kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
+} semc_iomux_nora27_pin;
+
+/*! @brief SEMC port size. */
+typedef enum _semc_port_size
+{
+ kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
+ kSEMC_PortSize16Bit, /*!< 16-Bit port size. */
+#if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U)
+ kSEMC_PortSize32Bit /*!< 32-Bit port size. */
+#endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */
+} smec_port_size_t;
+
+/*! @brief SEMC address mode. */
+typedef enum _semc_addr_mode
+{
+ kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
+ kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
+ kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
+} semc_addr_mode_t;
+
+/*! @brief SEMC DQS read strobe mode. */
+typedef enum _semc_dqs_mode
+{
+ kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
+ kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
+} semc_dqs_mode_t;
+
+/*! @brief SEMC ADV signal active polarity. */
+typedef enum _semc_adv_polarity
+{
+ kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
+ kSEMC_AdvActiveHigh, /*!< Adv active high. */
+} semc_adv_polarity_t;
+
+/*! @brief SEMC sync mode. */
+typedef enum _semc_sync_mode
+{
+ kSEMC_AsyncMode = 0, /*!< Async mode. */
+ kSEMC_SyncMode, /*!< Sync mode. */
+} semc_sync_mode_t;
+
+/*! @brief SEMC ADV signal level control. */
+typedef enum _semc_adv_level_control
+{
+ kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */
+ kSEMC_AdvLow, /*!< Adv is low during address hold state. */
+} semc_adv_level_control_t;
+
+/*! @brief SEMC RDY signal active polarity. */
+typedef enum _semc_rdy_polarity
+{
+ kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
+ kSEMC_RdyActivehigh, /*!< Adv active low. */
+} semc_rdy_polarity_t;
+
+/*! @brief SEMC IP command for NAND: address mode. */
+typedef enum _semc_ipcmd_nand_addrmode
+{
+ kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
+ kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
+ kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
+ kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
+ kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
+ kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
+} semc_ipcmd_nand_addrmode_t;
+
+/*! @brief SEMC IP command for NAND: command mode. */
+typedef enum _semc_ipcmd_nand_cmdmode
+{
+ kSEMC_NANDCM_Command = 0x2U, /*!< command. */
+ kSEMC_NANDCM_CommandHold, /*!< Command hold. */
+ kSEMC_NANDCM_CommandAddress, /*!< Command address. */
+ kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
+ kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
+ kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
+ kSEMC_NANDCM_CommandRead, /*!< Command read. */
+ kSEMC_NANDCM_CommandWrite, /*!< Command write. */
+ kSEMC_NANDCM_Read, /*!< Read. */
+ kSEMC_NANDCM_Write /*!< Write. */
+} semc_ipcmd_nand_cmdmode_t;
+
+/*! @brief SEMC NAND address option. */
+typedef enum _semc_nand_address_option
+{
+ kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
+ kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
+ kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
+ kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
+ kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
+ kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
+} semc_nand_address_option_t;
+
+/*! @brief SEMC IP command for NOR. */
+typedef enum _semc_ipcmd_nor_dbi
+{
+ kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
+ kSEMC_NORDBICM_Write /*!< NOR write. */
+} semc_ipcmd_nor_dbi_t;
+
+/*! @brief SEMC IP command for SRAM. */
+typedef enum _semc_ipcmd_sram
+{
+ kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
+ kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
+ kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
+ kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
+} semc_ipcmd_sram_t;
+
+/*! @brief SEMC IP command for SDARM. */
+typedef enum _semc_ipcmd_sdram
+{
+ kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
+ kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
+ kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
+ kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
+ kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
+ kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
+ kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
+ kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
+} semc_ipcmd_sdram_t;
+
+/*! @brief SEMC SDRAM configuration structure.
+ *
+ * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
+ * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
+ * Take refer to BR0~BR3 register in RM for details.
+ * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
+ * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
+ * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
+ * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
+ * similar to prescalePeriod_N16Cycle.
+ *
+ */
+typedef struct _semc_sdram_config
+{
+ semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
+ uint32_t address; /*!< The base address. */
+ uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
+ smec_port_size_t portSize; /*!< Port size. */
+ sem_sdram_burst_len_t burstLen; /*!< Burst length. */
+ semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
+ semc_caslatency_t casLatency; /*!< CAS latency. */
+ uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
+ uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
+ uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
+ uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
+ uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
+ uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
+ uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
+ uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
+ uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
+ uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
+ uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
+ uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
+ uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
+ uint8_t refreshBurstLen; /*!< Refresh burst length. */
+#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
+ uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
+ read data. */
+#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
+} semc_sdram_config_t;
+
+/*! @brief SEMC NAND device timing configuration structure. */
+typedef struct _semc_nand_timing_config
+{
+ uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
+ uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
+ uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
+ uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
+ uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
+ uint8_t tReLow_Ns; /*!< RE low time: tRP. */
+ uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
+ uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
+ uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
+ uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
+ uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
+ uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
+ uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
+} semc_nand_timing_config_t;
+
+/*! @brief SEMC NAND configuration structure. */
+typedef struct _semc_nand_config
+{
+ semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
+ uint32_t axiAddress; /*!< The base address for AXI nand. */
+ uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
+ uint32_t ipgAddress; /*!< The base address for IPG nand . */
+ uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
+ semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
+ bool edoModeEnabled; /*!< EDO mode enabled. */
+ semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
+ semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
+ sem_nand_burst_len_t burstLen; /*!< Burst length. */
+ smec_port_size_t portSize; /*!< Port size. */
+ semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
+} semc_nand_config_t;
+
+/*! @brief SEMC NOR configuration structure. */
+typedef struct _semc_nor_config
+{
+ semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
+ semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
+ uint32_t address; /*!< The base address. */
+ uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
+ uint8_t addrPortWidth; /*!< The address port width. */
+ semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
+ semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
+ semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
+ semc_addr_mode_t addrMode; /*!< Address mode. */
+ sem_norsram_burst_len_t burstLen; /*!< Burst length. */
+ smec_port_size_t portSize; /*!< Port size. */
+ uint8_t tCeSetup_Ns; /*!< The CE setup time. */
+ uint8_t tCeHold_Ns; /*!< The CE hold time. */
+ uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
+ uint8_t tAddrSetup_Ns; /*!< The address setup time. */
+ uint8_t tAddrHold_Ns; /*!< The address hold time. */
+ uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
+ uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
+ uint8_t tReLow_Ns; /*!< RE low time for async mode. */
+ uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
+ uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
+ uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
+ uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
+#endif
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
+ uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
+#endif
+ uint8_t latencyCount; /*!< Latency count for sync mode. */
+ uint8_t readCycle; /*!< Read cycle time for sync mode. */
+#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
+ uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
+ read data. */
+#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
+} semc_nor_config_t;
+
+/*! @brief SEMC SRAM configuration structure. */
+typedef struct _semc_sram_config
+{
+ semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
+ semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
+ uint32_t address; /*!< The base address. */
+ uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
+ uint8_t addrPortWidth; /*!< The address port width. */
+ semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
+ semc_addr_mode_t addrMode; /*!< Address mode. */
+ sem_norsram_burst_len_t burstLen; /*!< Burst length. */
+ smec_port_size_t portSize; /*!< Port size. */
+#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
+ semc_sync_mode_t syncMode; /*!< Sync mode. */
+#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
+#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK)
+ bool waitEnable; /*!< Wait enable. */
+#endif /* SEMC_SRAMCR0_WAITEN_MASK */
+#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK)
+ uint8_t waitSample; /*!< Wait sample. */
+#endif /* SEMC_SRAMCR0_WAITSP_MASK */
+#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
+ semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */
+#endif /* SEMC_SRAMCR4_ADVH_MASK */
+ uint8_t tCeSetup_Ns; /*!< The CE setup time. */
+ uint8_t tCeHold_Ns; /*!< The CE hold time. */
+ uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
+#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
+ uint8_t readHoldTime_Ns; /*!< read hold time. */
+#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
+ uint8_t tAddrSetup_Ns; /*!< The address setup time. */
+ uint8_t tAddrHold_Ns; /*!< The address hold time. */
+ uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
+ uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
+ uint8_t tReLow_Ns; /*!< RE low time for async mode. */
+ uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
+ uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
+ uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
+ uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
+ uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
+ uint8_t latencyCount; /*!< Latency count for sync mode. */
+ uint8_t readCycle; /*!< Read cycle time for sync mode. */
+#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
+ uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
+ read data. */
+#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
+} semc_sram_config_t;
+
+/*! @brief SEMC DBI configuration structure. */
+typedef struct _semc_dbi_config
+{
+ semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
+ uint32_t address; /*!< The base address. */
+ uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
+ semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
+ sem_dbi_burst_len_t burstLen; /*!< Burst length. */
+ smec_port_size_t portSize; /*!< Port size. */
+ uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
+ uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
+ uint8_t tWexLow_Ns; /*!< WEX low time. */
+ uint8_t tWexHigh_Ns; /*!< WEX high time. */
+ uint8_t tRdxLow_Ns; /*!< RDX low time. */
+ uint8_t tRdxHigh_Ns; /*!< RDX high time. */
+ uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
+} semc_dbi_config_t;
+
+/*! @brief SEMC AXI queue a weight setting structure. */
+typedef struct _semc_queuea_weight_struct
+{
+ uint32_t qos : 4; /*!< weight of qos for queue 0 . */
+ uint32_t aging : 4; /*!< weight of aging for queue 0.*/
+ uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
+ uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
+} semc_queuea_weight_struct_t;
+
+/*! @brief SEMC AXI queue a weight setting union. */
+typedef union _semc_queuea_weight
+{
+ semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
+ uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
+} semc_queuea_weight_t;
+
+/*! @brief SEMC AXI queue b weight setting structure. */
+typedef struct _semc_queueb_weight_struct
+{
+ uint32_t qos : 4; /*!< weight of qos for queue 1. */
+ uint32_t aging : 4; /*!< weight of aging for queue 1.*/
+ uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
+ uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
+ uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
+} semc_queueb_weight_struct_t;
+
+/*! @brief SEMC AXI queue b weight setting union. */
+typedef union _semc_queueb_weight
+{
+ semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
+ uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
+} semc_queueb_weight_t;
+
+/*! @brief SEMC AXI queue weight setting. */
+typedef struct _semc_axi_queueweight
+{
+ bool queueaEnable; /*!< Enable queue a. */
+ semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
+ bool queuebEnable; /*!< Enable queue b. */
+ semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
+} semc_axi_queueweight_t;
+
+/*!
+ * @brief SEMC configuration structure.
+ *
+ * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
+ * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
+ * cmdTimeoutCycles: is used for command execution timeout cycles. it's
+ * similar to the busTimeoutCycles.
+ */
+typedef struct _semc_config_t
+{
+ semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
+ uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
+ uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
+ semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
+} semc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name SEMC Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Gets the SEMC default basic configuration structure.
+ *
+ * The purpose of this API is to get the default SEMC
+ * configure structure for SEMC_Init(). User may use the initialized
+ * structure unchanged in SEMC_Init(), or modify some fields of the
+ * structure before calling SEMC_Init().
+ * Example:
+ @code
+ semc_config_t config;
+ SEMC_GetDefaultConfig(&config);
+ @endcode
+ * @param config The SEMC configuration structure pointer.
+ */
+void SEMC_GetDefaultConfig(semc_config_t *config);
+
+/*!
+ * @brief Initializes SEMC.
+ * This function ungates the SEMC clock and initializes SEMC.
+ * This function must be called before calling any other SEMC driver functions.
+ *
+ * @param base SEMC peripheral base address.
+ * @param configure The SEMC configuration structure pointer.
+ */
+void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
+
+/*!
+ * @brief Deinitializes the SEMC module and gates the clock.
+ *
+ * This function gates the SEMC clock. As a result, the SEMC module doesn't work after
+ * calling this function, for some IDE, calling this API may cause the next downloading
+ * operation failed. so, please call this API cautiously. Additional, users can
+ * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
+ * operation in drivers.
+ *
+ * @param base SEMC peripheral base address.
+ */
+void SEMC_Deinit(SEMC_Type *base);
+
+/* @} */
+
+/*!
+ * @name SEMC Configuration Operation For Each Memory Type
+ * @{
+ */
+
+/*!
+ * @brief Configures SDRAM controller in SEMC.
+ *
+ * @param base SEMC peripheral base address.
+ * @param cs The chip selection.
+ * @param config The sdram configuration.
+ * @param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
+
+/*!
+ * @brief Configures NAND controller in SEMC.
+ *
+ * @param base SEMC peripheral base address.
+ * @param config The nand configuration.
+ * @param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
+
+/*!
+ * @brief Configures NOR controller in SEMC.
+ *
+ * @param base SEMC peripheral base address.
+ * @param config The nor configuration.
+ * @param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
+
+/*!
+ * @brief Configures SRAM controller in SEMC.
+ *
+ * @param base SEMC peripheral base address.
+ * @param cs The chip selection.
+ * @param config The sram configuration.
+ * @param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
+ semc_sram_cs_t cs,
+ semc_sram_config_t *config,
+ uint32_t clkSrc_Hz);
+
+/*!
+ * @brief Configures SRAM controller in SEMC.
+ * @deprecated Do not use this function. It has been superceded by @ref SEMC_ConfigureSRAMWithChipSelection.
+ * @param base SEMC peripheral base address.
+ * @param config The sram configuration.
+ * @param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
+
+/*!
+ * @brief Configures DBI controller in SEMC.
+ *
+ * @param base SEMC peripheral base address.
+ * @param config The dbi configuration.
+ * @param clkSrc_Hz The SEMC clock frequency.
+ */
+status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
+
+/* @} */
+
+/*!
+ * @name SEMC Interrupt Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the SEMC interrupt.
+ *
+ * This function enables the SEMC interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
+ * For example, to enable the IP command done and error interrupt, do the following.
+ * @code
+ * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
+ * @endcode
+ *
+ * @param base SEMC peripheral base address.
+ * @param mask SEMC interrupts to enable. This is a logical OR of the
+ * enumeration :: semc_interrupt_enable_t.
+ */
+static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
+{
+ base->INTEN |= mask;
+}
+
+/*!
+ * @brief Disables the SEMC interrupt.
+ *
+ * This function disables the SEMC interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
+ * For example, to disable the IP command done and error interrupt, do the following.
+ * @code
+ * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
+ * @endcode
+ *
+ * @param base SEMC peripheral base address.
+ * @param mask SEMC interrupts to disable. This is a logical OR of the
+ * enumeration :: semc_interrupt_enable_t.
+ */
+static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
+{
+ base->INTEN &= ~mask;
+}
+
+/*!
+ * @brief Gets the SEMC status.
+ *
+ * This function gets the SEMC interrupts event status.
+ * User can use the a logical OR of enumeration member as a mask.
+ * See @ref semc_interrupt_enable_t.
+ *
+ * @param base SEMC peripheral base address.
+ * @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
+ */
+static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
+{
+ return (base->INTR != 0x00U) ? true : false;
+}
+
+/*!
+ * @brief Clears the SEMC status flag state.
+ *
+ * The following status register flags can be cleared SEMC interrupt status.
+ *
+ * @param base SEMC base pointer
+ * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
+ */
+static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
+{
+ base->INTR |= mask;
+}
+
+/* @} */
+
+/*!
+ * @name SEMC Memory Access Operation
+ * @{
+ */
+
+/*!
+ * @brief Check if SEMC is in idle.
+ *
+ * @param base SEMC peripheral base address.
+ * @return True SEMC is in idle, false is not in idle.
+ */
+static inline bool SEMC_IsInIdle(SEMC_Type *base)
+{
+ return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false;
+}
+
+/*!
+ * @brief SEMC IP command access.
+ *
+ * @param base SEMC peripheral base address.
+ * @param type SEMC memory type. refer to "semc_mem_type_t"
+ * @param address SEMC device address.
+ * @param command SEMC IP command.
+ * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
+ * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
+ * For SRAM device, take refer to "semc_ipcmd_sram_t".
+ * For SDRAM device, take refer to "semc_ipcmd_sdram_t".
+ * @param write Data for write access.
+ * @param read Data pointer for read data out.
+ */
+status_t SEMC_SendIPCommand(
+ SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
+
+/*!
+ * @brief Build SEMC IP command for NAND.
+ *
+ * This function build SEMC NAND IP command. The command is build of user command code,
+ * SEMC address mode and SEMC command mode.
+ *
+ * @param userCommand NAND device normal command.
+ * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
+ * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
+ */
+static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
+ semc_ipcmd_nand_addrmode_t addrMode,
+ semc_ipcmd_nand_cmdmode_t cmdMode)
+{
+ return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU);
+}
+
+/*!
+ * @brief Check if the NAND device is ready.
+ *
+ * @param base SEMC peripheral base address.
+ * @return True NAND is ready, false NAND is not ready.
+ */
+static inline bool SEMC_IsNandReady(SEMC_Type *base)
+{
+ return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false;
+}
+
+/*!
+ * @brief SEMC NAND device memory write through IP command.
+ *
+ * @param base SEMC peripheral base address.
+ * @param address SEMC NAND device address.
+ * @param data Data for write access.
+ * @param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
+
+/*!
+ * @brief SEMC NAND device memory read through IP command.
+ *
+ * @param base SEMC peripheral base address.
+ * @param address SEMC NAND device address.
+ * @param data Data pointer for data read out.
+ * @param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
+
+/*!
+ * @brief SEMC NOR device memory write through IP command.
+ *
+ * @param base SEMC peripheral base address.
+ * @param address SEMC NOR device address.
+ * @param data Data for write access.
+ * @param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
+
+/*!
+ * @brief SEMC NOR device memory read through IP command.
+ *
+ * @param base SEMC peripheral base address.
+ * @param address SEMC NOR device address.
+ * @param data Data pointer for data read out.
+ * @param size_bytes Data length.
+ */
+status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SEMC_H_*/
diff --git a/imxrt1050.cfg b/imxrt1050.cfg
new file mode 100644
index 0000000..33c0388
--- /dev/null
+++ b/imxrt1050.cfg
@@ -0,0 +1,36 @@
+# NXP i.MX RT1050 family (Arm Cortex-M7 @ 600 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imxrt1050
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPU_SWD_TAPID] } {
+ set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+ set _CPU_SWD_TAPID 0x0bd11477
+}
+
+if { [using_jtag] } {
+ set _CPU_TAPID 0
+} else {
+ set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+
+set _TARGETNAME $_CHIPNAME
+dap create $_TARGETNAME.dap -chain-position $_TARGETNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_TARGETNAME.dap
+
+if { ![using_hla] } {
+ cortex_m reset_config sysresetreq
+}
+
+gdb_breakpoint_override hard
+
+adapter speed 8000
diff --git a/rt1050_freertos_hello.mex b/rt1050_freertos_hello.mex
index 4a24c52..1c40f86 100644
--- a/rt1050_freertos_hello.mex
+++ b/rt1050_freertos_hello.mex
@@ -39,6 +39,11 @@
true
+
+
+ true
+
+
true
@@ -77,6 +82,47 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -181,7 +227,7 @@
-
+
@@ -195,7 +241,7 @@
-
+
@@ -390,6 +436,16 @@
2.2.8
+
+
+ true
+
+
+
+
+ 2.3.0
+
+
@@ -421,11 +477,11 @@
-
+
-
+
@@ -443,6 +499,68 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/source/freertos_hello.c b/source/freertos_hello.c
index da654ba..bec362b 100644
--- a/source/freertos_hello.c
+++ b/source/freertos_hello.c
@@ -17,6 +17,7 @@
#include "fsl_debug_console.h"
#include "pin_mux.h"
#include "clock_config.h"
+#include "peripherals.h"
#include "board.h"
/*******************************************************************************
@@ -42,6 +43,7 @@ int main(void)
BOARD_ConfigMPU();
BOARD_InitBootPins();
BOARD_InitBootClocks();
+ BOARD_InitBootPeripherals();
BOARD_InitDebugConsole();
if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) !=
pdPASS)
@@ -63,6 +65,6 @@ static void hello_task(void *pvParameters)
for (;;)
{
PRINTF("Hello world.\r\n");
- vTaskSuspend(NULL);
+ vTaskDelay(pdMS_TO_TICKS(400));
}
}