commit 137f26ee72b744e44d603a9c726075d46795a603 Author: imi415 Date: Thu Feb 4 01:44:12 2021 +0800 Initial commit diff --git a/CMSIS/CMSIS_Include_common_MIMXRT1052.cmake b/CMSIS/CMSIS_Include_common_MIMXRT1052.cmake new file mode 100644 index 0000000..77a3b75 --- /dev/null +++ b/CMSIS/CMSIS_Include_common_MIMXRT1052.cmake @@ -0,0 +1,10 @@ +if(NOT CMSIS_INCLUDE_COMMON_MIMXRT1052_INCLUDED) + +set(CMSIS_INCLUDE_COMMON_MIMXRT1052_INCLUDED true CACHE BOOL "CMSIS_Include_common component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + +endif() diff --git a/CMSIS/CMSIS_Include_core_cm7_MIMXRT1052.cmake b/CMSIS/CMSIS_Include_core_cm7_MIMXRT1052.cmake new file mode 100644 index 0000000..553b29b --- /dev/null +++ b/CMSIS/CMSIS_Include_core_cm7_MIMXRT1052.cmake @@ -0,0 +1,14 @@ +if(NOT CMSIS_INCLUDE_CORE_CM7_MIMXRT1052_INCLUDED) + +set(CMSIS_INCLUDE_CORE_CM7_MIMXRT1052_INCLUDED true CACHE BOOL "CMSIS_Include_core_cm7 component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + +include(CMSIS_Include_common_MIMXRT1052) + +include(CMSIS_Include_dsp_MIMXRT1052) + +endif() diff --git a/CMSIS/CMSIS_Include_dsp_MIMXRT1052.cmake b/CMSIS/CMSIS_Include_dsp_MIMXRT1052.cmake new file mode 100644 index 0000000..49c9a7b --- /dev/null +++ b/CMSIS/CMSIS_Include_dsp_MIMXRT1052.cmake @@ -0,0 +1,10 @@ +if(NOT CMSIS_INCLUDE_DSP_MIMXRT1052_INCLUDED) + +set(CMSIS_INCLUDE_DSP_MIMXRT1052_INCLUDED true CACHE BOOL "CMSIS_Include_dsp component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + +endif() diff --git a/CMSIS/arm_common_tables.h b/CMSIS/arm_common_tables.h new file mode 100644 index 0000000..6a4337f --- /dev/null +++ b/CMSIS/arm_common_tables.h @@ -0,0 +1,378 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/CMSIS/arm_const_structs.h b/CMSIS/arm_const_structs.h new file mode 100644 index 0000000..80a3e8b --- /dev/null +++ b/CMSIS/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/CMSIS/arm_math.h b/CMSIS/arm_math.h new file mode 100644 index 0000000..eb37f82 --- /dev/null +++ b/CMSIS/arm_math.h @@ -0,0 +1,7361 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.6.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if !defined ( _MSC_VER ) +#include "cmsis_compiler.h" +#else +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __ALIGNED(x) __declspec(align(x)) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + +#include "string.h" +#include "math.h" +#include "float.h" + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(__ARM_NEON) +#include +#endif + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + + memcpy (&val, pQ15, 4); + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 += 2; + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 -= 2; + + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ15, &val, 4); + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (pQ15, &val, 4); +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ7, &val, 4); + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +#if defined(ARM_MATH_NEON) + +static inline float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +static inline int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +static inline int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + + + void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/CMSIS/cmsis_armcc.h b/CMSIS/cmsis_armcc.h new file mode 100644 index 0000000..59f173a --- /dev/null +++ b/CMSIS/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/CMSIS/cmsis_armclang.h b/CMSIS/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/CMSIS/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/CMSIS/cmsis_armclang_ltm.h b/CMSIS/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/CMSIS/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/CMSIS/cmsis_compiler.h b/CMSIS/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/CMSIS/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/CMSIS/cmsis_gcc.h b/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/CMSIS/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/CMSIS/cmsis_iccarm.h b/CMSIS/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/CMSIS/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/CMSIS/cmsis_version.h b/CMSIS/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/CMSIS/core_cm7.h b/CMSIS/core_cm7.h new file mode 100644 index 0000000..d1b2f2c --- /dev/null +++ b/CMSIS/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS/mpu_armv7.h b/CMSIS/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/CMSIS/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..505be10 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,127 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.1.1) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(rt1050_freertos_hello) + +set(MCUX_SDK_PROJECT_NAME rt1050_rt1050_freertos_hello.elf) + +include(${ProjDirPath}/.//flags.cmake) + +include(${ProjDirPath}/.//config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/board/board.c" +"${ProjDirPath}/board/board.h" +"${ProjDirPath}/board/clock_config.c" +"${ProjDirPath}/board/clock_config.h" +"${ProjDirPath}/board/dcd.c" +"${ProjDirPath}/board/dcd.h" +"${ProjDirPath}/board/pin_mux.c" +"${ProjDirPath}/board/pin_mux.h" +"${ProjDirPath}/board/peripherals.c" +"${ProjDirPath}/board/peripherals.h" +"${ProjDirPath}/source/FreeRTOSConfig.h" +"${ProjDirPath}/source/freertos_hello.c" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${ProjDirPath}/board +${ProjDirPath}/source +) + +set(CMAKE_MODULE_PATH +${ProjDirPath}/./ +${ProjDirPath}/CMSIS +${ProjDirPath}/component/lists +${ProjDirPath}/component/serial_manager +${ProjDirPath}/component/uart +${ProjDirPath}/device +${ProjDirPath}/drivers +${ProjDirPath}/freertos +${ProjDirPath}/startup +${ProjDirPath}/utilities +${ProjDirPath}/xip +) + +# include modules +include(driver_clock_MIMXRT1052) + +include(middleware_freertos-kernel_heap_4_MIMXRT1052) + +include(driver_common_MIMXRT1052) + +include(device_MIMXRT1052_CMSIS_MIMXRT1052) + +include(utility_debug_console_MIMXRT1052) + +include(component_lpuart_adapter_MIMXRT1052) + +include(component_serial_manager_MIMXRT1052) + +include(component_lists_MIMXRT1052) + +include(component_serial_manager_uart_MIMXRT1052) + +include(driver_lpuart_MIMXRT1052) + +include(device_MIMXRT1052_startup_MIMXRT1052) + +include(driver_iomuxc_MIMXRT1052) + +include(utility_assert_MIMXRT1052) + +include(driver_igpio_MIMXRT1052) + +include(driver_xip_device_MIMXRT1052) + +include(driver_xip_board_MIMXRT1052) + +include(middleware_freertos-kernel_MIMXRT1052) + +include(middleware_freertos-kernel_extension_MIMXRT1052) + +include(utilities_misc_utilities_MIMXRT1052) + +include(CMSIS_Include_core_cm7_MIMXRT1052) + +include(CMSIS_Include_common_MIMXRT1052) + +include(CMSIS_Include_dsp_MIMXRT1052) + +include(device_MIMXRT1052_system_MIMXRT1052) + + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + + diff --git a/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld b/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld new file mode 100644 index 0000000..58ccb84 --- /dev/null +++ b/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld @@ -0,0 +1,258 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.0, 2018-09-21 +** Build: b200110 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_data2); + __NCACHE_REGION_SIZE = 0; + + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld b/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld new file mode 100644 index 0000000..2198cf0 --- /dev/null +++ b/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.0, 2018-09-21 +** Build: b200110 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_data2); + __NCACHE_REGION_SIZE = 0; + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + __VECTOR_RAM = ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld b/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld new file mode 100644 index 0000000..bc362a4 --- /dev/null +++ b/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld @@ -0,0 +1,228 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.0, 2018-09-21 +** Build: b200110 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81E00000 - HEAP_SIZE; +NCACHE_HEAP_SIZE = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01E00000 : 0x01E00000 - HEAP_SIZE + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00200000 - HEAP_SIZE : 0x00200000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + m_heap (RW) : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_ncache); + __NCACHE_REGION_SIZE = LENGTH(m_ncache) + NCACHE_HEAP_SIZE; + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + __VECTOR_RAM = ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/armgcc.cmake b/armgcc.cmake new file mode 100644 index 0000000..284a7db --- /dev/null +++ b/armgcc.cmake @@ -0,0 +1,56 @@ +# TOOLCHAIN EXTENSION +IF(WIN32) + SET(TOOLCHAIN_EXT ".exe") +ELSE() + SET(TOOLCHAIN_EXT "") +ENDIF() + +# EXECUTABLE EXTENSION +SET (CMAKE_EXECUTABLE_SUFFIX ".elf") + +# TOOLCHAIN_DIR AND NANO LIBRARY +SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR}) +STRING(REGEX REPLACE "\\\\" "/" TOOLCHAIN_DIR "${TOOLCHAIN_DIR}") + +IF(NOT TOOLCHAIN_DIR) + MESSAGE(FATAL_ERROR "***Please set ARMGCC_DIR in envionment variables***") +ENDIF() + +MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR}) + +# TARGET_TRIPLET +SET(TARGET_TRIPLET "arm-none-eabi") + +SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin) +SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include) +SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib) + +SET(CMAKE_SYSTEM_NAME Generic) +SET(CMAKE_SYSTEM_PROCESSOR arm) + +SET(CMAKE_C_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT}) +SET(CMAKE_CXX_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-g++${TOOLCHAIN_EXT}) +SET(CMAKE_ASM_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT}) + +set(CMAKE_C_COMPILER_FORCED TRUE) +set(CMAKE_CXX_COMPILER_FORCED TRUE) + +SET(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objcopy CACHE INTERNAL "objcopy tool") +SET(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objdump CACHE INTERNAL "objdump tool") + +SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "c compiler flags debug") +SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "cxx compiler flags debug") +SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG} -g" CACHE INTERNAL "asm compiler flags debug") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG}" CACHE INTERNAL "linker flags debug") + +SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -O3 " CACHE INTERNAL "c compiler flags release") +SET(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 " CACHE INTERNAL "cxx compiler flags release") +SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}" CACHE INTERNAL "asm compiler flags release") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "${CMAKE_EXE_LINKER_FLAGS_RELEASE}" CACHE INTERNAL "linker flags release") + +SET(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_DIR}/${TARGET_TRIPLET} ${EXTRA_FIND_PATH}) +SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE}) diff --git a/board/board.c b/board/board.c new file mode 100644 index 0000000..0f4335c --- /dev/null +++ b/board/board.c @@ -0,0 +1,381 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#include "fsl_iomuxc.h" +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get debug console frequency. */ +uint32_t BOARD_DebugConsoleSrcFreq(void) +{ + uint32_t freq; + + /* To make it simple, we assume default PLL and divider settings, and the only variable + from application is use PLL3 source or OSC source */ + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + + return freq; +} + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq(); + + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} + +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) +{ + lpi2c_master_config_t lpi2cConfig = {0}; + + /* + * lpi2cConfig.debugEnable = false; + * lpi2cConfig.ignoreAck = false; + * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; + * lpi2cConfig.baudRate_Hz = 100000U; + * lpi2cConfig.busIdleTimeout_ns = 0; + * lpi2cConfig.pinLowTimeout_ns = 0; + * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; + * lpi2cConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&lpi2cConfig); + LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); +} + +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Read; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + status_t status; + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = NULL; + xfer.dataSize = 0; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + + if (kStatus_Success == status) + { + xfer.subaddressSize = 0; + xfer.direction = kLPI2C_Read; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + } + + return status; +} + +void BOARD_Accel_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ); +} + +status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff) +{ + uint8_t data = (uint8_t)txBuff; + + return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1); +} + +status_t BOARD_Accel_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize); +} + +void BOARD_Codec_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); +} + +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); +} + +void BOARD_Camera_I2C_Init(void) +{ + CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER); + BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ); +} + +status_t BOARD_Camera_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Camera_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize); +} + +status_t BOARD_Camera_I2C_SendSCCB( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Camera_I2C_ReceiveSCCB( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize); +} +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? + 0 : + ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; +#endif + volatile uint32_t i = 0; + + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) + { + SCB_DisableDCache(); + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + * + */ + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif + + /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + while ((size >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + + /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} diff --git a/board/board.h b/board/board.h new file mode 100644 index 0000000..6f77eea --- /dev/null +++ b/board/board.h @@ -0,0 +1,215 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "IMXRT1050-EVKB" + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#define BOARD_DEBUG_UART_INSTANCE 1U + +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() + +#define BOARD_UART_IRQ LPUART1_IRQn +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE (115200U) +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON (0U) +#define LOGIC_LED_OFF (1U) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO GPIO1 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN (9U) +#endif + +#define USER_LED_INIT(output) \ + GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ + BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ +#define USER_LED_ON() \ + GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ +#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); + /* Disable pfd offset. */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK; +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable pfd offset. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK; + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Tx clock source. */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + diff --git a/board/clock_config.c.bak b/board/clock_config.c.bak new file mode 100644 index 0000000..349dc09 --- /dev/null +++ b/board/clock_config.c.bak @@ -0,0 +1,496 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v7.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 0.7.9 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); + /* Disable pfd offset. */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK; +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable pfd offset. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK; + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Tx clock source. */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + diff --git a/board/clock_config.h b/board/clock_config.h new file mode 100644 index 0000000..daf5873 --- /dev/null +++ b/board/clock_config.h @@ -0,0 +1,116 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/board/clock_config.h.bak b/board/clock_config.h.bak new file mode 100644 index 0000000..d03437b --- /dev/null +++ b/board/clock_config.h.bak @@ -0,0 +1,122 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/board/dcd.c b/board/dcd.c new file mode 100644 index 0000000..adfea80 --- /dev/null +++ b/board/dcd.c @@ -0,0 +1,308 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 9.0.0 +board: IMXRT1050-EVKB +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 + }; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/board/dcd.c.bak b/board/dcd.c.bak new file mode 100644 index 0000000..c3b2132 --- /dev/null +++ b/board/dcd.c.bak @@ -0,0 +1,315 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: IMXRT1050-EVKB +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 + }; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/board/dcd.h b/board/dcd.h new file mode 100644 index 0000000..3d8b7cd --- /dev/null +++ b/board/dcd.h @@ -0,0 +1,25 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/board/dcd.h.bak b/board/dcd.h.bak new file mode 100644 index 0000000..185b0ec --- /dev/null +++ b/board/dcd.h.bak @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/board/peripherals.c b/board/peripherals.c new file mode 100644 index 0000000..96eb1d5 --- /dev/null +++ b/board/peripherals.c @@ -0,0 +1,113 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v9.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 9.0.0 +board: IMXRT1050-EVKB +functionalGroups: +- name: BOARD_InitPeripherals + UUID: c02f2a7b-0e89-43b6-9488-2b4f58340ab8 + called_from_default_init: true + selectedCore: core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * LPUART1 initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'LPUART1' +- type: 'lpuart' +- mode: 'polling' +- custom_name_enabled: 'false' +- type_id: 'lpuart_54a65a580e3462acdbacefd5299e0cac' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'LPUART1' +- config_sets: + - lpuartConfig_t: + - lpuartConfig: + - clockSource: 'LpuartClock' + - lpuartSrcClkFreq: 'BOARD_BootClockRUN' + - baudRate_Bps: '115200' + - parityMode: 'kLPUART_ParityDisabled' + - dataBitsCount: 'kLPUART_EightDataBits' + - isMsb: 'false' + - stopBitCount: 'kLPUART_OneStopBit' + - txFifoWatermark: '0' + - rxFifoWatermark: '1' + - enableRxRTS: 'false' + - enableTxCTS: 'false' + - txCtsSource: 'kLPUART_CtsSourcePin' + - txCtsConfig: 'kLPUART_CtsSampleAtStart' + - rxIdleType: 'kLPUART_IdleTypeStartBit' + - rxIdleConfig: 'kLPUART_IdleCharacter1' + - enableTx: 'true' + - enableRx: 'true' + - quick_selection: 'QuickSelection1' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const lpuart_config_t LPUART1_config = { + .baudRate_Bps = 115200UL, + .parityMode = kLPUART_ParityDisabled, + .dataBitsCount = kLPUART_EightDataBits, + .isMsb = false, + .stopBitCount = kLPUART_OneStopBit, + .txFifoWatermark = 0U, + .rxFifoWatermark = 1U, + .enableRxRTS = false, + .enableTxCTS = false, + .txCtsSource = kLPUART_CtsSourcePin, + .txCtsConfig = kLPUART_CtsSampleAtStart, + .rxIdleType = kLPUART_IdleTypeStartBit, + .rxIdleConfig = kLPUART_IdleCharacter1, + .enableTx = true, + .enableRx = true +}; + +static void LPUART1_init(void) { + LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ + /* Initialize components */ + LPUART1_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/board/peripherals.c.bak b/board/peripherals.c.bak new file mode 100644 index 0000000..49aa105 --- /dev/null +++ b/board/peripherals.c.bak @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v9.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 9.0.0 +board: IMXRT1050-EVKB +functionalGroups: +- name: BOARD_InitPeripherals + UUID: c02f2a7b-0e89-43b6-9488-2b4f58340ab8 + called_from_default_init: true + selectedCore: core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/board/peripherals.h b/board/peripherals.h new file mode 100644 index 0000000..d7248c0 --- /dev/null +++ b/board/peripherals.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_lpuart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals functional group */ +/* Definition of peripheral ID */ +#define LPUART1_PERIPHERAL LPUART1 +/* Definition of the clock source frequency */ +#define LPUART1_CLOCK_SOURCE 80000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const lpuart_config_t LPUART1_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/board/peripherals.h.bak b/board/peripherals.h.bak new file mode 100644 index 0000000..fe99cdc --- /dev/null +++ b/board/peripherals.h.bak @@ -0,0 +1,28 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/board/pin_mux.c b/board/pin_mux.c new file mode 100644 index 0000000..4c5d481 --- /dev/null +++ b/board/pin_mux.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 9.0.0 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/board/pin_mux.c.bak b/board/pin_mux.c.bak new file mode 100644 index 0000000..ec00842 --- /dev/null +++ b/board/pin_mux.c.bak @@ -0,0 +1,89 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v7.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 6.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/board/pin_mux.h b/board/pin_mux.h new file mode 100644 index 0000000..18e01ad --- /dev/null +++ b/board/pin_mux.h @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/board/pin_mux.h.bak b/board/pin_mux.h.bak new file mode 100644 index 0000000..83e03a8 --- /dev/null +++ b/board/pin_mux.h.bak @@ -0,0 +1,65 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/build_all.bat b/build_all.bat new file mode 100644 index 0000000..2df2e4e --- /dev/null +++ b/build_all.bat @@ -0,0 +1,43 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F 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-f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_release . +make -j 2>&1 | tee build_log.txt diff --git a/clean.bat b/clean.bat new file mode 100644 index 0000000..0dcc6eb --- /dev/null +++ b/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release sdram_debug sdram_release flexspi_nor_debug flexspi_nor_release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/clean.sh b/clean.sh new file mode 100644 index 0000000..673bd97 --- /dev/null +++ b/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release sdram_debug sdram_release flexspi_nor_debug flexspi_nor_release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/component/lists/component_lists_MIMXRT1052.cmake b/component/lists/component_lists_MIMXRT1052.cmake new file mode 100644 index 0000000..893a0e6 --- /dev/null +++ b/component/lists/component_lists_MIMXRT1052.cmake @@ -0,0 +1,17 @@ +if(NOT COMPONENT_LISTS_MIMXRT1052_INCLUDED) + +set(COMPONENT_LISTS_MIMXRT1052_INCLUDED true CACHE BOOL "component_lists component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_component_generic_list.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(driver_common_MIMXRT1052) + +endif() diff --git a/component/lists/fsl_component_generic_list.c b/component/lists/fsl_component_generic_list.c new file mode 100644 index 0000000..6184631 --- /dev/null +++ b/component/lists/fsl_component_generic_list.c @@ -0,0 +1,493 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_component_generic_list.h" + +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define LIST_ENTER_CRITICAL() \ + OSA_SR_ALLOC(); \ + OSA_ENTER_CRITICAL() +#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define LIST_ENTER_CRITICAL() +#define LIST_EXIT_CRITICAL() +#endif +#else +#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif + +static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; +#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U)) + list_element_handle_t element = list->head; +#endif + if ((list->max != 0U) && (list->max == list->size)) + { + listStatus = kLIST_Full; /*List is full*/ + } +#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U)) + else + { + while (element != NULL) /*Scan list*/ + { + /* Determine if element is duplicated */ + if (element == newElement) + { + listStatus = kLIST_DuplicateError; + break; + } + element = element->next; + } + } +#endif + return listStatus; +} + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* + * \brief Initialises the list descriptor. + * + * \param[in] list - LIST_ handle to init. + * max - Maximum number of elements in list. 0 for unlimited. + * + * \return void. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +void LIST_Init(list_handle_t list, uint32_t max) +{ + list->head = NULL; + list->tail = NULL; + list->max = (uint16_t)max; + list->size = 0; +} + +/*! ********************************************************************************* + * \brief Gets the list that contains the given element. + * + * \param[in] element - Handle of the element. + * + * \return NULL if element is orphan. + * Handle of the list the element is inserted into. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_handle_t LIST_GetList(list_element_handle_t element) +{ + return element->list; +} + +/*! ********************************************************************************* + * \brief Links element to the tail of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) +{ + LIST_ENTER_CRITICAL(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, element); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + if (list->size == 0U) + { + list->head = element; + } + else + { + list->tail->next = element; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + element->prev = list->tail; +#endif + element->list = list; + element->next = NULL; + list->tail = element; + list->size++; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links element to the head of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) +{ + LIST_ENTER_CRITICAL(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, element); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + /* Links element to the head of the list */ + if (list->size == 0U) + { + list->tail = element; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + list->head->prev = element; + } + element->prev = NULL; +#endif + element->list = list; + element->next = list->head; + list->head = element; + list->size++; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Unlinks element from the head of the list. + * + * \param[in] list - ID of list to remove from. + * + * \return NULL if list is empty. + * ID of removed element(pointer) if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_RemoveHead(list_handle_t list) +{ + list_element_handle_t element; + + LIST_ENTER_CRITICAL(); + + if ((NULL == list) || (list->size == 0U)) + { + element = NULL; /*LIST_ is empty*/ + } + else + { + element = list->head; + list->size--; + if (list->size == 0U) + { + list->tail = NULL; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + element->next->prev = NULL; + } +#endif + element->list = NULL; + list->head = element->next; /*Is NULL if element is head*/ + } + + LIST_EXIT_CRITICAL(); + return element; +} + +/*! ********************************************************************************* + * \brief Gets head element ID. + * + * \param[in] list - ID of list. + * + * \return NULL if list is empty. + * ID of head element if list is not empty. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetHead(list_handle_t list) +{ + return list->head; +} + +/*! ********************************************************************************* + * \brief Gets next element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is tail. + * ID of next element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetNext(list_element_handle_t element) +{ + return element->next; +} + +/*! ********************************************************************************* + * \brief Gets previous element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is head. + * ID of previous element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element) +{ +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + return NULL; +#else + return element->prev; +#endif +} + +/*! ********************************************************************************* + * \brief Unlinks an element from its list. + * + * \param[in] element - ID of the element to remove. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Ok if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_RemoveElement(list_element_handle_t element) +{ + list_status_t listStatus = kLIST_Ok; + LIST_ENTER_CRITICAL(); + + if (element->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = element->list->head; + while (NULL != element_list) + { + if (element->list->head == element) + { + element->list->head = element_list->next; + break; + } + if (element_list->next == element) + { + element_list->next = element->next; + break; + } + element_list = element_list->next; + } +#else + if (element->prev == NULL) /*Element is head or solo*/ + { + element->list->head = element->next; /*is null if solo*/ + } + if (element->next == NULL) /*Element is tail or solo*/ + { + element->list->tail = element->prev; /*is null if solo*/ + } + if (element->prev != NULL) /*Element is not head*/ + { + element->prev->next = element->next; + } + if (element->next != NULL) /*Element is not tail*/ + { + element->next->prev = element->prev; + } +#endif + element->list->size--; + element->list = NULL; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links an element in the previous position relative to a given member + * of a list. + * + * \param[in] element - ID of a member of a list. + * newElement - new element to insert before the given member. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + LIST_ENTER_CRITICAL(); + + if (element->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { + listStatus = LIST_Error_Check(element->list, newElement); + if (listStatus == kLIST_Ok) + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = element->list->head; + while (NULL != element_list) + { + if ((element_list->next == element) || (element_list == element)) + { + if (element_list == element) + { + element->list->head = newElement; + } + else + { + element_list->next = newElement; + } + newElement->list = element->list; + newElement->next = element; + element->list->size++; + break; + } + element_list = element_list->next; + } + +#else + if (element->prev == NULL) /*Element is list head*/ + { + element->list->head = newElement; + } + else + { + element->prev->next = newElement; + } + newElement->list = element->list; + element->list->size++; + newElement->next = element; + newElement->prev = element->prev; + element->prev = newElement; +#endif + } + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Gets the current size of a list. + * + * \param[in] list - ID of the list. + * + * \return Current size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetSize(list_handle_t list) +{ + return list->size; +} + +/*! ********************************************************************************* + * \brief Gets the number of free places in the list. + * + * \param[in] list - ID of the list. + * + * \return Available size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetAvailableSize(list_handle_t list) +{ + return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/ +} diff --git a/component/lists/fsl_component_generic_list.h b/component/lists/fsl_component_generic_list.h new file mode 100644 index 0000000..ccdc219 --- /dev/null +++ b/component/lists/fsl_component_generic_list.h @@ -0,0 +1,201 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _GENERIC_LIST_H_ +#define _GENERIC_LIST_H_ + +#include "fsl_common.h" +/*! + * @addtogroup GenericList + * @{ + */ + +/********************************************************************************** +* Include +***********************************************************************************/ + +/********************************************************************************** +* Public macro definitions +***********************************************************************************/ +/*! @brief Definition to determine whether use list light. */ +#ifndef GENERIC_LIST_LIGHT +#define GENERIC_LIST_LIGHT (1) +#endif + +/*! @brief Definition to determine whether enable list duplicated checking. */ +#ifndef GENERIC_LIST_DUPLICATED_CHECKING +#define GENERIC_LIST_DUPLICATED_CHECKING (0) +#endif + +/********************************************************************************** +* Public type definitions +***********************************************************************************/ +/*! @brief The list status */ +typedef enum _list_status +{ + kLIST_Ok = kStatus_Success, /*!< Success */ + kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ + kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ + kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ + kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ + kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */ +} list_status_t; + +/*! @brief The list structure*/ +typedef struct list_label +{ + struct list_element_tag *head; /*!< list head */ + struct list_element_tag *tail; /*!< list tail */ + uint16_t size; /*!< list size */ + uint16_t max; /*!< list max number of elements */ +} list_label_t, *list_handle_t; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#else +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_element_tag *prev; /*!< previous list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#endif +/********************************************************************************** +* Public prototypes +***********************************************************************************/ +/********************************************************************************** + * API + **********************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +/*! + * @brief Initialize the list. + * + * This function initialize the list. + * + * @param list - List handle to initialize. + * @param max - Maximum number of elements in list. 0 for unlimited. + */ +void LIST_Init(list_handle_t list, uint32_t max); + +/*! + * @brief Gets the list that contains the given element. + * + * + * @param element - Handle of the element. + * @retval NULL if element is orphan, Handle of the list the element is inserted into. + */ +list_handle_t LIST_GetList(list_element_handle_t element); + +/*! + * @brief Links element to the head of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Links element to the tail of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Unlinks element from the head of the list. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_RemoveHead(list_handle_t list); + +/*! + * @brief Gets head element handle. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetHead(list_handle_t list); + +/*! + * @brief Gets next element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetNext(list_element_handle_t element); + +/*! + * @brief Gets previous element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element); + +/*! + * @brief Unlinks an element from its list. + * + * @param element - Handle of the element. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_RemoveElement(list_element_handle_t element); + +/*! + * @brief Links an element in the previous position relative to a given member of a list. + * + * @param element - Handle of the element. + * @param newElement - New element to insert before the given member. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement); + +/*! + * @brief Gets the current size of a list. + * + * @param list - Handle of the list. + * + * @retval Current size of the list. + */ +uint32_t LIST_GetSize(list_handle_t list); + +/*! + * @brief Gets the number of free places in the list. + * + * @param list - Handle of the list. + * + * @retval Available size of the list. + */ +uint32_t LIST_GetAvailableSize(list_handle_t list); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /*_GENERIC_LIST_H_*/ diff --git a/component/serial_manager/component_serial_manager_MIMXRT1052.cmake b/component/serial_manager/component_serial_manager_MIMXRT1052.cmake new file mode 100644 index 0000000..e771527 --- /dev/null +++ b/component/serial_manager/component_serial_manager_MIMXRT1052.cmake @@ -0,0 +1,40 @@ +if(NOT COMPONENT_SERIAL_MANAGER_MIMXRT1052_INCLUDED) + +set(COMPONENT_SERIAL_MANAGER_MIMXRT1052_INCLUDED true CACHE BOOL "component_serial_manager component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_component_serial_manager.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +#OR Logic component +if(CONFIG_USE_component_serial_manager_uart_MIMXRT1052) +include(component_serial_manager_uart_MIMXRT1052) +endif() +if(CONFIG_USE_component_serial_manager_usb_cdc_MIMXRT1052) +include(component_serial_manager_usb_cdc_MIMXRT1052) +endif() +if(CONFIG_USE_component_serial_manager_virtual_MIMXRT1052) +include(component_serial_manager_virtual_MIMXRT1052) +endif() +if(CONFIG_USE_component_serial_manager_swo_MIMXRT1052) +include(component_serial_manager_swo_MIMXRT1052) +endif() +if(CONFIG_USE_component_serial_manager_rpmsg_MIMXRT1052) +include(component_serial_manager_rpmsg_MIMXRT1052) +endif() +if(NOT (CONFIG_USE_component_serial_manager_uart_MIMXRT1052 OR CONFIG_USE_component_serial_manager_usb_cdc_MIMXRT1052 OR CONFIG_USE_component_serial_manager_virtual_MIMXRT1052 OR CONFIG_USE_component_serial_manager_swo_MIMXRT1052 OR CONFIG_USE_component_serial_manager_rpmsg_MIMXRT1052)) +message(WARNING "Since component_serial_manager_uart_MIMXRT1052/component_serial_manager_usb_cdc_MIMXRT1052/component_serial_manager_virtual_MIMXRT1052/component_serial_manager_swo_MIMXRT1052/component_serial_manager_rpmsg_MIMXRT1052 is not included at first or config in config.cmake file, use component_serial_manager_uart_MIMXRT1052 by default.") +include(component_serial_manager_uart_MIMXRT1052) +endif() + +include(driver_common_MIMXRT1052) + +include(component_lists_MIMXRT1052) + +endif() diff --git a/component/serial_manager/component_serial_manager_uart_MIMXRT1052.cmake b/component/serial_manager/component_serial_manager_uart_MIMXRT1052.cmake new file mode 100644 index 0000000..0fcde66 --- /dev/null +++ b/component/serial_manager/component_serial_manager_uart_MIMXRT1052.cmake @@ -0,0 +1,28 @@ +if(NOT COMPONENT_SERIAL_MANAGER_UART_MIMXRT1052_INCLUDED) + +set(COMPONENT_SERIAL_MANAGER_UART_MIMXRT1052_INCLUDED true CACHE BOOL "component_serial_manager_uart component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_component_serial_port_uart.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +#OR Logic component +if(CONFIG_USE_driver_lpuart_MIMXRT1052) +include(driver_lpuart_MIMXRT1052) +endif() +if(NOT (CONFIG_USE_driver_lpuart_MIMXRT1052)) +message(WARNING "Since driver_lpuart_MIMXRT1052 is not included at first or config in config.cmake file, use driver_uart_MIMXRT1052 by default.") +include(driver_uart_MIMXRT1052) +endif() + +include(component_lpuart_adapter_MIMXRT1052) + +include(component_serial_manager_MIMXRT1052) + +endif() diff --git a/component/serial_manager/fsl_component_serial_manager.c b/component/serial_manager/fsl_component_serial_manager.c new file mode 100644 index 0000000..5d5bd40 --- /dev/null +++ b/component/serial_manager/fsl_component_serial_manager.c @@ -0,0 +1,1722 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "fsl_component_serial_manager.h" +#include "fsl_component_serial_port_internal.h" +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#include "fsl_component_generic_list.h" + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#else +#include "fsl_os_abstraction.h" +#endif + +#endif + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define SERIAL_EVENT_DATA_RECEIVED (1U << 0) +#define SERIAL_EVENT_DATA_SENT (1U << 1) +#define SERIAL_EVENT_DATA_START_SEND (1U << 2) +#define SERIAL_EVENT_DATA_RX_NOTIFY (1U << 3) + +#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U +#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +typedef enum _serial_manager_transmission_mode +{ + kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/ + kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/ +} serial_manager_transmission_mode_t; + +/* TX transfer structure */ +typedef struct _serial_manager_transfer +{ + uint8_t *buffer; + volatile uint32_t length; + volatile uint32_t soFar; + serial_manager_transmission_mode_t mode; + serial_manager_status_t status; +} serial_manager_transfer_t; +#endif + +/* write handle structure */ +typedef struct _serial_manager_send_handle +{ + struct _serial_manager_handle *serialManagerHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_element_t link; /*!< list element of the link */ + serial_manager_transfer_t transfer; + serial_manager_callback_t callback; + void *callbackParam; + uint32_t tag; +#endif +} serial_manager_write_handle_t; +typedef struct _serial_manager_send_block_handle +{ + struct _serial_manager_handle *serialManagerHandle; + +} serial_manager_write_block_handle_t; + +typedef serial_manager_write_handle_t serial_manager_read_handle_t; +typedef serial_manager_write_block_handle_t serial_manager_read_block_handle_t; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/* receive state structure */ +typedef struct _serial_manager_read_ring_buffer +{ + uint8_t *ringBuffer; + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; +} serial_manager_read_ring_buffer_t; + +typedef struct _serial_manager_block_handle +{ + serial_manager_type_t handleType; + serial_port_type_t type; + serial_manager_read_handle_t *volatile openedReadHandleHead; + volatile uint32_t openedWriteHandleCount; + union + { + uint32_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_BLOCK_HANDLE_SIZE]; +#endif + }; + +} serial_manager_block_handle_t; +#endif + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/* The serial manager handle structure */ +typedef struct _serial_manager_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_type_t handleType; +#endif + serial_port_type_t type; + serial_manager_read_handle_t *volatile openedReadHandleHead; + volatile uint32_t openedWriteHandleCount; + union + { + uint32_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_VIRTUAL_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + uint8_t rpmsgHandleBuffer[SERIAL_PORT_RPMSG_HANDLE_SIZE]; +#endif + }; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_read_ring_buffer_t ringBuffer; +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + common_task_message_t commontaskMsg; +#else + OSA_EVENT_HANDLE_DEFINE(event); /*!< Event instance */ + OSA_TASK_HANDLE_DEFINE(taskId); /*!< Task handle */ +#endif + +#endif + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_label_t runningWriteHandleHead; /*!< The queue of running write handle */ + list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */ +#endif + +} serial_manager_handle_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_Task(void *param); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + +#else + /* + * \brief Defines the serial manager task's stack + */ +static OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false); +#endif + +#endif + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node) +{ + (void)LIST_AddTail(queue, &node->link); +} + +static void SerialManager_RemoveHead(list_label_t *queue) +{ + (void)LIST_RemoveHead(queue); +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + serial_manager_write_handle_t *writeHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); + + if (writeHandle != NULL) + { + writeHandle = (serial_manager_write_handle_t *)((uint32_t)writeHandle - 4U); + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + status = Serial_PortVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + status = Serial_RpmsgWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif + default: + status = kStatus_SerialManager_Error; + break; + } + } + return status; +} +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) +static serial_manager_status_t SerialManager_StartBlockWriting(serial_manager_handle_t *handle, + serial_manager_write_handle_t *writeHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == handle->type) /* Serial port UART */ + { + status = Serial_UartWriteBlocking(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == handle->type) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == handle->type) /* Serial port SWO */ + { + status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == handle->type) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == handle->type) /* Serial port RPMSG */ + { + status = Serial_RpmsgWriteBlocking(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} + +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (NULL != readHandle) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + if ((kSerialPort_Uart == handle->type) && + (kSerialManager_Blocking == handle->handleType)) /* Serial port UART */ + { + status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (handle->type == kSerialPort_UsbCdc) + { + status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (handle->type == kSerialPort_Virtual) + { + status = Serial_PortVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if 0 +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (handle->type == kSerialPort_Rpmsg) + { + status = Serial_RpmsgRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#endif + } + return status; +} + +#else /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle, + serial_manager_write_handle_t *writeHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == handle->type) /* Serial port UART */ + { + status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == handle->type) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == handle->type) /* Serial port SWO */ + { + status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == handle->type) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == handle->type) /* Serial port Rpmsg */ + { + status = Serial_RpmsgWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == handle->type) /* Serial port UART */ + { + status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == handle->type) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == handle->type) /* Serial port SWO */ + { + status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == handle->type) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == handle->type) /* Serial port UsbCdcVirtual */ + { + status = Serial_RpmsgRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} +#endif /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_IsrFunction(serial_manager_handle_t *handle) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + Serial_PortVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + EnableGlobalIRQ(regPrimask); +} + +static void SerialManager_Task(void *param) +{ + serial_manager_handle_t *handle = (serial_manager_handle_t *)param; + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_read_handle_t *serialReadHandle; + uint32_t primask; + serial_manager_callback_message_t msg; +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) + uint32_t ringBufferLength; +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + + if (NULL != handle) + { +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + osa_event_flags_t ev = 0; + + do + { + if (KOSA_StatusSuccess == + OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, 0U, osaWaitForever_c, &ev)) + { +#endif +#endif +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev & SERIAL_EVENT_DATA_START_SEND)) +#endif + +#endif + { + (void)SerialManager_StartWriting(handle); + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev & SERIAL_EVENT_DATA_SENT)) +#endif + +#endif + { + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); + while (NULL != serialWriteHandle) + { + serialWriteHandle = (serial_manager_write_handle_t *)((uint32_t)serialWriteHandle - 4U); + SerialManager_RemoveHead(&handle->completedWriteHandleHead); + msg.buffer = serialWriteHandle->transfer.buffer; + msg.length = serialWriteHandle->transfer.soFar; + serialWriteHandle->transfer.buffer = NULL; + if (NULL != serialWriteHandle->callback) + { + serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg, + serialWriteHandle->transfer.status); + } + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); + } + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev & SERIAL_EVENT_DATA_RECEIVED)) +#endif + +#endif + { + primask = DisableGlobalIRQ(); + serialReadHandle = handle->openedReadHandleHead; + EnableGlobalIRQ(primask); + + if (NULL != serialReadHandle) + { + if (NULL != serialReadHandle->transfer.buffer) + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + msg.buffer = serialReadHandle->transfer.buffer; + msg.length = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + if (NULL != serialReadHandle->callback) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &msg, + serialReadHandle->transfer.status); + } + } + } + } + } + +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev & SERIAL_EVENT_DATA_RX_NOTIFY)) +#endif + { + ringBufferLength = + handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize; + /* Notify there are data in ringbuffer */ + if (0U != ringBufferLength) + { + msg.buffer = NULL; + msg.length = ringBufferLength; + if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback)) + { + handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, &msg, + kStatus_SerialManager_Notify); + } + } + } +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + } + } while (0U != gUseRtos_c); +#endif + +#endif + } +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_TxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *handle; + serial_manager_write_handle_t *writeHandle; + + assert(callbackParam); + assert(message); + + handle = (serial_manager_handle_t *)callbackParam; + + writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); + + if (NULL != writeHandle) + { + writeHandle = (serial_manager_write_handle_t *)((uint32_t)writeHandle - 4U); + SerialManager_RemoveHead(&handle->runningWriteHandleHead); + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_START_SEND); +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + (void)SerialManager_StartWriting(handle); +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + + writeHandle->transfer.soFar = message->length; + writeHandle->transfer.status = status; + if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode) + { + SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + handle->commontaskMsg.callback = SerialManager_Task; + handle->commontaskMsg.callbackParam = handle; + COMMON_TASK_post_message(&handle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT); +#endif + +#else + SerialManager_Task(handle); +#endif + } + else + { + writeHandle->transfer.buffer = NULL; + } + } +} + +void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); +void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *handle; + uint32_t ringBufferLength; + uint32_t primask; + + assert(callbackParam); + assert(message); + + handle = (serial_manager_handle_t *)callbackParam; + + status = kStatus_SerialManager_Notify; + + for (uint32_t i = 0; i < message->length; i++) + { + handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i]; + if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringHead = 0U; + } + if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail) + { + status = kStatus_SerialManager_RingBufferOverflow; + handle->ringBuffer.ringTail++; + if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringTail = 0U; + } + } + } + + ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize; + + primask = DisableGlobalIRQ(); + if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->transfer.buffer)) + { + if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) + { + uint32_t remainLength = + handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar; + for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++) + { + handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] = + handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; + handle->ringBuffer.ringTail++; + handle->openedReadHandleHead->transfer.soFar++; + if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringTail = 0U; + } + } + ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength); + } + + if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) + { + } + else + { + if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode) + { + handle->openedReadHandleHead->transfer.buffer = NULL; + } + else + { + handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + handle->commontaskMsg.callback = SerialManager_Task; + handle->commontaskMsg.callbackParam = handle; + COMMON_TASK_post_message(&handle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED); +#endif + +#else + SerialManager_Task(handle); +#endif + } + } + } + + if (0U != ringBufferLength) + { +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RX_NOTIFY); + (void)status; /* Fix "set but never used" warning. */ +#else /* !SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + message->buffer = NULL; + message->length = ringBufferLength; + if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback)) + { + handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status); + } +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + } + + ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength; + + if (NULL != handle->openedReadHandleHead) + { + (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength); + } + EnableGlobalIRQ(primask); +} + +/* + * This function is used for perdiodic check if the transfer is complete, and will be called in blocking transfer at + * non-blocking mode. The predic unit is ms and default value is define by SERIAL_MANAGER_TIME_DELAY_DEFAULT_VALUE. The + * function SerialManager_TimeDelay() is a weak function, so it could be re-implemented by upper layer. + */ +__WEAK_FUNC void SerialManager_TimeDelay(uint32_t ms); +__WEAK_FUNC void SerialManager_TimeDelay(uint32_t ms) +{ +#if defined(OSA_USED) + OSA_TimeDelay(ms); +#endif +} + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *handle; + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + /* Do nothing. */ +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + serial_manager_status_t status = kStatus_SerialManager_Success; +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + + uint32_t primask; + uint8_t isEmpty = 0U; + + assert(writeHandle); + assert(buffer); + assert(length); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + handle = serialWriteHandle->serialManagerHandle; + assert(handle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + if ((handle->handleType == kSerialManager_Blocking) || (kSerialManager_TransmissionBlocking == mode)) + { + return SerialManager_StartBlockWriting(handle, serialWriteHandle, buffer, length); + } +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE*/ + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback))); + + primask = DisableGlobalIRQ(); + if (NULL != serialWriteHandle->transfer.buffer) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialWriteHandle->transfer.buffer = buffer; + serialWriteHandle->transfer.length = length; + serialWriteHandle->transfer.soFar = 0U; + serialWriteHandle->transfer.mode = mode; + + if (NULL == LIST_GetHead(&handle->runningWriteHandleHead)) + { + isEmpty = 1U; + } + SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle); + EnableGlobalIRQ(primask); + + if (0U != isEmpty) + { +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_START_SEND); +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + status = SerialManager_StartWriting(handle); + if ((serial_manager_status_t)kStatus_SerialManager_Success != status) + { +#if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) + if (status == kStatus_SerialManager_NotConnected) + { + SerialManager_RemoveHead(&handle->runningWriteHandleHead); + serialWriteHandle->transfer.buffer = 0U; + serialWriteHandle->transfer.length = 0U; + } +#endif /* USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1 */ + return status; + } +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar) + { +#if defined(__GIC_PRIO_BITS) + if (0x13 == (__get_CPSR() & CPSR_M_Msk)) +#else + if (0U != __get_IPSR()) +#endif + { + SerialManager_IsrFunction(handle); + } + else + { + SerialManager_TimeDelay(SERIAL_MANAGER_TIME_DELAY_DEFAULT_VALUE); + } + } + } + return kStatus_SerialManager_Success; +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode, + uint32_t *receivedLength) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *handle; + uint32_t dataLength; + uint32_t primask; + + assert(readHandle); + assert(buffer); + assert(length); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + handle = serialReadHandle->serialManagerHandle; + assert(handle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + if (handle->handleType == kSerialManager_Blocking) + /* if ((handle->handleType == kSerialManager_Blocking) || (kSerialManager_TransmissionBlocking == mode)) */ + { + return SerialManager_StartReading(handle, serialReadHandle, buffer, length); + } +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE*/ + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback))); + + primask = DisableGlobalIRQ(); + if (NULL != serialReadHandle->transfer.buffer) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialReadHandle->transfer.buffer = buffer; + serialReadHandle->transfer.length = length; + serialReadHandle->transfer.soFar = 0U; + serialReadHandle->transfer.mode = mode; + + dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + dataLength = dataLength % handle->ringBuffer.ringBufferSize; + + for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length); + serialReadHandle->transfer.soFar++) + { + buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; + handle->ringBuffer.ringTail++; + if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringTail = 0U; + } + } + + dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + dataLength = dataLength % handle->ringBuffer.ringBufferSize; + dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength; + + (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength); + + if (NULL != receivedLength) + { + *receivedLength = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + } + else + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + if (kSerialManager_TransmissionNonBlocking == mode) + { + if (NULL != serialReadHandle->callback) + { + serial_manager_callback_message_t msg; + msg.buffer = buffer; + msg.length = serialReadHandle->transfer.soFar; + serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success); + } + } + } + else + { + EnableGlobalIRQ(primask); + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar) + { + } + } + } + + return kStatus_SerialManager_Success; +} + +#else + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *handle; + + assert(writeHandle); + assert(buffer); + assert(length); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + handle = serialWriteHandle->serialManagerHandle; + + assert(handle); + + return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length); +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *handle; + + assert(readHandle); + assert(buffer); + assert(length); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + handle = serialReadHandle->serialManagerHandle; + + assert(handle); + + return SerialManager_StartReading(handle, serialReadHandle, buffer, length); +} +#endif + +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *config) +{ + serial_manager_handle_t *handle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(config); + + assert(serialHandle); + assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t)); + + handle = (serial_manager_handle_t *)serialHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + if (config->blockType == kSerialManager_Blocking) + { + (void)memset(handle, 0, SERIAL_MANAGER_BLOCK_HANDLE_SIZE); + } + else +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ + { + assert(config->ringBuffer); + assert(config->ringBufferSize); + (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE); + } + handle->handleType = config->blockType; +#else + (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE); +#endif + handle->type = config->type; + + switch (config->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + if (config->blockType == kSerialManager_Blocking) + { + return status; + } +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + (void)Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + + (void)Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + status = Serial_PortVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + status = Serial_RpmsgInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), (void *)config); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_RpmsgInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_RpmsgInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } + } +#endif + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + + COMMON_TASK_init(); + +#else + if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, 1U)) + { + return kStatus_SerialManager_Error; + } + + if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle)) + { + return kStatus_SerialManager_Error; + } +#endif + +#endif + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + handle->ringBuffer.ringBuffer = config->ringBuffer; + handle->ringBuffer.ringBufferSize = config->ringBufferSize; +#endif + return status; +} + +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) +{ + serial_manager_handle_t *handle; + uint32_t primask; + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + + assert(serialHandle); + + handle = (serial_manager_handle_t *)serialHandle; + + primask = DisableGlobalIRQ(); + if ((NULL != handle->openedReadHandleHead) || (0U != handle->openedWriteHandleCount)) + { + serialManagerStatus = kStatus_SerialManager_Busy; /*Serial Manager Busy*/ + } + else + { + switch (handle->type) /*serial port type*/ + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + (void)Serial_PortVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + (void)Serial_RpmsgDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + (void)OSA_EventDestroy((osa_event_handle_t)handle->event); + (void)OSA_TaskDestroy((osa_task_handle_t)handle->taskId); +#endif + +#endif + +#endif + } + + EnableGlobalIRQ(primask); + return serialManagerStatus; +} + +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *handle; + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + + assert(serialHandle); + assert(writeHandle); + assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t)); + + handle = (serial_manager_handle_t *)serialHandle; + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + primask = DisableGlobalIRQ(); + handle->openedWriteHandleCount++; + EnableGlobalIRQ(primask); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (handle->handleType == kSerialManager_Blocking) + { + serialWriteHandle->serialManagerHandle = handle; + return kStatus_SerialManager_Success; + } + else +#endif + { + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); + } + + serialWriteHandle->serialManagerHandle = handle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG; +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *handle; + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + + assert(writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; + + assert(handle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelWriting(writeHandle); +#endif + primask = DisableGlobalIRQ(); + if (handle->openedWriteHandleCount > 0U) + { + handle->openedWriteHandleCount--; + } + EnableGlobalIRQ(primask); + + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle) +{ + serial_manager_handle_t *handle; + serial_manager_read_handle_t *serialReadHandle; /* read handle structure */ + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + uint32_t primask; + + assert(serialHandle); + assert(readHandle); + assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t)); + + handle = (serial_manager_handle_t *)serialHandle; + serialReadHandle = (serial_manager_read_handle_t *)readHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (handle->handleType == kSerialManager_Blocking) + { + serialReadHandle->serialManagerHandle = handle; + return kStatus_SerialManager_Success; + } +#endif + primask = DisableGlobalIRQ(); + if (handle->openedReadHandleHead != NULL) + { + serialManagerStatus = kStatus_SerialManager_Busy; + } + else + { + handle->openedReadHandleHead = serialReadHandle; + + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); + + serialReadHandle->serialManagerHandle = handle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialReadHandle->tag = SERIAL_MANAGER_READ_TAG; +#endif + } + EnableGlobalIRQ(primask); + return serialManagerStatus; +} + +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle) +{ + serial_manager_handle_t *handle; + serial_manager_read_handle_t *serialReadHandle; + uint32_t primask; + + assert(readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; + + assert((NULL != handle) && (handle->openedReadHandleHead == serialReadHandle)); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelReading(readHandle); +#endif + + primask = DisableGlobalIRQ(); + handle->openedReadHandleHead = NULL; + EnableGlobalIRQ(primask); + + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking); +#else + return SerialManager_Write(writeHandle, buffer, length); +#endif +} + +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL); +#else + return SerialManager_Read(readHandle, buffer, length); +#endif +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length) +{ + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking); +} + +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL); +} + +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle) +{ + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + uint8_t isNotUsed = 0U; + uint8_t isNotNeed2Cancel = 0U; + + assert(writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(serialWriteHandle->serialManagerHandle); + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + if ((NULL != serialWriteHandle->transfer.buffer) && + (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + if (serialWriteHandle != + (serial_manager_write_handle_t *)((uint32_t)LIST_GetHead( + &serialWriteHandle->serialManagerHandle->runningWriteHandleHead) - + 4U)) + { + if (kLIST_Ok == LIST_RemoveElement(&serialWriteHandle->link)) + { + isNotUsed = 1U; + } + else + { + isNotNeed2Cancel = 1U; + } + } + EnableGlobalIRQ(primask); + + if (0U == isNotNeed2Cancel) + { + if (0U != isNotUsed) + { + serialWriteHandle->transfer.soFar = 0; + serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled; + + SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task; + serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = + serialWriteHandle->serialManagerHandle; + COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, + SERIAL_EVENT_DATA_SENT); +#endif + +#else + SerialManager_Task(serialWriteHandle->serialManagerHandle); +#endif + } + else + { + switch (serialWriteHandle->serialManagerHandle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + (void)Serial_PortVirtualCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + } + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + (void)OSA_EventSet((osa_event_handle_t)&serialWriteHandle->serialManagerHandle->event, + SERIAL_EVENT_DATA_START_SEND); +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle); +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + } + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_callback_message_t msg; + uint8_t *buffer; + uint32_t primask; + + assert(readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + if ((NULL != serialReadHandle->transfer.buffer) && + (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + buffer = serialReadHandle->transfer.buffer; + serialReadHandle->transfer.buffer = NULL; + serialReadHandle->transfer.length = 0; + msg.buffer = buffer; + msg.length = serialReadHandle->transfer.soFar; + EnableGlobalIRQ(primask); + + if (NULL != buffer) + { + if (NULL != serialReadHandle->callback) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength) +{ + assert(receivedLength); + + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength); +} + +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_write_handle_t *serialWriteHandle; + + assert(writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + serialWriteHandle->callbackParam = callbackParam; + serialWriteHandle->callback = callback; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_read_handle_t *serialReadHandle; + + assert(readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + serialReadHandle->callbackParam = callbackParam; + serialReadHandle->callback = callback; + + return kStatus_SerialManager_Success; +} +#endif + +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle) +{ + serial_manager_handle_t *handle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(serialHandle); + + handle = (serial_manager_handle_t *)serialHandle; + + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartEnterLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Rpmsg: + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + return status; +} + +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle) +{ + serial_manager_handle_t *handle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(serialHandle); + + handle = (serial_manager_handle_t *)serialHandle; + + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartExitLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Rpmsg: + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + return status; +} diff --git a/component/serial_manager/fsl_component_serial_manager.h b/component/serial_manager/fsl_component_serial_manager.h new file mode 100644 index 0000000..914ddd9 --- /dev/null +++ b/component/serial_manager/fsl_component_serial_manager.h @@ -0,0 +1,735 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_MANAGER_H__ +#define __SERIAL_MANAGER_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup Serial_Manager + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) +#endif +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U) +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/*! @brief Enable or disable serial manager dual(block and non-block) mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#else +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#ifndef SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE +#define SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE (1U) +#endif +#endif +#endif +#ifndef SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE +#define SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE (0U) +#endif +#endif + +/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_UART +#define SERIAL_PORT_TYPE_UART (0U) +#endif + +/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_USBCDC +#define SERIAL_PORT_TYPE_USBCDC (0U) +#endif + +/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SWO +#define SERIAL_PORT_TYPE_SWO (0U) +#endif + +/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_VIRTUAL +#define SERIAL_PORT_TYPE_VIRTUAL (0U) +#endif + +/*! @brief Enable or disable rPMSG port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_RPMSG +#define SERIAL_PORT_TYPE_RPMSG (0U) +#endif + +/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_TX +#define SERIAL_MANAGER_TASK_HANDLE_TX (0U) +#endif +#if (defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX > 0U)) +#ifndef OSA_USED +#error When SERIAL_MANAGER_TASK_HANDLE_TX=1, OSA_USED must be set. +#endif +#endif + +/*! @brief Set the default delay time in ms used by SerialManager_TimeDelay(). */ +#ifndef SERIAL_MANAGER_TIME_DELAY_DEFAULT_VALUE +#define SERIAL_MANAGER_TIME_DELAY_DEFAULT_VALUE (1U) +#endif + +/*! @brief Enable or disable SerialManager_Task() handle RX data available notify */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY +#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY (0U) +#endif +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) +#ifndef OSA_USED +#error When SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY=1, OSA_USED must be set. +#endif +#endif + +/*! @brief Set serial manager write handle size */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U) +#else +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U) +#endif + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#include "fsl_component_serial_port_uart.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) +#include "fsl_component_serial_port_rpmsg.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "fsl_component_serial_port_usb.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +#include "fsl_component_serial_port_swo.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "fsl_component_serial_port_virtual.h" +#endif + +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + +#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + +#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + +#if (SERIAL_PORT_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_VIRTUAL_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + +#if (SERIAL_PORT_RPMSG_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_RPMSG_HANDLE_SIZE + +#endif + +#endif + +/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */ +#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U))) +#else +#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_VIRTUAL should not be cleared at same time. +#endif + +/*! @brief Definition of serial manager handle size. */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U) +#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U) +#else +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#endif + +/*! + * @brief Defines the serial manager handle + * + * This macro is used to define a 4 byte aligned serial manager handle. + * Then use "(serial_handle_t)name" to get the serial manager handle. + * + * The macro should be global and could be optional. You could also define serial manager handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle); + * @endcode + * + * @param name The name string of the serial manager handle. + */ +#define SERIAL_MANAGER_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +/*! + * @brief Defines the serial manager write handle + * + * This macro is used to define a 4 byte aligned serial manager write handle. + * Then use "(serial_write_handle_t)name" to get the serial manager write handle. + * + * The macro should be global and could be optional. You could also define serial manager write handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle); + * @endcode + * + * @param name The name string of the serial manager write handle. + */ +#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +/*! + * @brief Defines the serial manager read handle + * + * This macro is used to define a 4 byte aligned serial manager read handle. + * Then use "(serial_read_handle_t)name" to get the serial manager read handle. + * + * The macro should be global and could be optional. You could also define serial manager read handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle); + * @endcode + * + * @param name The name string of the serial manager read handle. + */ +#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#if defined(OSA_USED) +#include "fsl_component_common_task.h" +#endif +/*! @brief Macro to determine whether use common task. */ +#ifndef SERIAL_MANAGER_USE_COMMON_TASK +#define SERIAL_MANAGER_USE_COMMON_TASK (0U) +#if (defined(COMMON_TASK_ENABLE) && (COMMON_TASK_ENABLE == 0U)) +#undef SERIAL_MANAGER_USE_COMMON_TASK +#define SERIAL_MANAGER_USE_COMMON_TASK (0U) +#endif +#endif + +/*! @brief Macro to set serial manager task priority. */ +#ifndef SERIAL_MANAGER_TASK_PRIORITY +#define SERIAL_MANAGER_TASK_PRIORITY (2U) +#endif + +/*! @brief Macro to set serial manager task stack size. */ +#ifndef SERIAL_MANAGER_TASK_STACK_SIZE +#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U) +#endif + +/*! @brief The handle of the serial manager module */ +typedef void *serial_handle_t; + +/*! @brief The write handle of the serial manager module */ +typedef void *serial_write_handle_t; + +/*! @brief The read handle of the serial manager module */ +typedef void *serial_read_handle_t; + +/*! @brief serial port type*/ +typedef enum _serial_port_type +{ + kSerialPort_Uart = 1U, /*!< Serial port UART */ + kSerialPort_UsbCdc, /*!< Serial port USB CDC */ + kSerialPort_Swo, /*!< Serial port SWO */ + kSerialPort_Virtual, /*!< Serial port Virtual */ + kSerialPort_Rpmsg, /*!< Serial port RPMSG */ +} serial_port_type_t; + +/*! @brief serial manager type*/ +typedef enum _serial_manager_type +{ + kSerialManager_NonBlocking = 0x0U, /*!< None blocking handle*/ + kSerialManager_Blocking = 0x8F41U, /*!< Blocking handle*/ +} serial_manager_type_t; +/*! @brief serial manager config structure*/ +typedef struct _serial_manager_config +{ +#if defined(SERIAL_MANAGER_NON_BLOCKING_MODE) + uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. + Besides, the memory space cannot be free during the lifetime of the serial + manager module. */ + uint32_t ringBufferSize; /*!< The size of the ring buffer */ +#endif + serial_port_type_t type; /*!< Serial port type */ + serial_manager_type_t blockType; /*!< Serial manager port type */ + void *portConfig; /*!< Serial port configuration */ +} serial_manager_config_t; + +/*! @brief serial manager error code*/ +typedef enum _serial_manager_status +{ + kStatus_SerialManager_Success = kStatus_Success, /*!< Success */ + kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */ + kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */ + kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */ + kStatus_SerialManager_Canceled = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */ + kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */ + kStatus_SerialManager_RingBufferOverflow = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */ + kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7), /*!< The host is not connected */ +} serial_manager_status_t; + +/*! @brief Callback message structure */ +typedef struct _serial_manager_callback_message +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ +} serial_manager_callback_message_t; + +/*! @brief callback function */ +typedef void (*serial_manager_callback_t)(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure. + * + * This function configures the Serial Manager module with user-defined settings. + * The user can configure the configuration structure. + * The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE + * allocated by the caller. + * The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB + * CDC and swo. + * Please refer to #serial_port_type_t for serial port setting. + * These three types can be set by using #serial_manager_config_t. + * + * Example below shows how to use this API to configure the Serial Manager. + * For UART, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_uart_config_t uartConfig; + * config.type = kSerialPort_Uart; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * uartConfig.instance = 0; + * uartConfig.clockRate = 24000000; + * uartConfig.baudRate = 115200; + * uartConfig.parityMode = kSerialManager_UartParityDisabled; + * uartConfig.stopBitCount = kSerialManager_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * uartConfig.enableRxRTS = 0; + * uartConfig.enableTxCTS = 0; + * config.portConfig = &uartConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode + * For USB CDC, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_usb_cdc_config_t usbCdcConfig; + * config.type = kSerialPort_UsbCdc; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0; + * config.portConfig = &usbCdcConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode + * + * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle); + * or + * uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param config Pointer to user-defined configuration structure. + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed. + */ +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *config); + +/*! + * @brief De-initializes the serial manager module instance. + * + * This function de-initializes the serial manager module instance. If the opened writing or + * reading handle is not closed, the function will return kStatus_SerialManager_Busy. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed. + * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed. + */ +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle); + +/*! + * @brief Opens a writing handle for the serial manager module. + * + * This function Opens a writing handle for the serial manager module. If the serial manager needs to + * be used in different tasks, the task should open a dedicated write handle for itself by calling + * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing + * handle at the same time, multiple writing handles need to be opened when the multiple transmission + * is needed for a task. + * + * @param serialHandle The serial manager module handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param writeHandle The serial manager module writing handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle); + * or + * uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_HandleConflict The writing handle was opened. + * @retval kStatus_SerialManager_Success The writing handle is opened. + * + * Example below shows how to use this API to write data. + * For task 1, + * @code + * static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1); + * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n"; + * SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1); + * SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1, + * Task1_SerialManagerTxCallback, + * s_serialWriteHandle1); + * SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1, + * s_nonBlockingWelcome1, + * sizeof(s_nonBlockingWelcome1) - 1U); + * @endcode + * For task 2, + * @code + * static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2); + * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n"; + * SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2); + * SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2, + * Task2_SerialManagerTxCallback, + * s_serialWriteHandle2); + * SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2, + * s_nonBlockingWelcome2, + * sizeof(s_nonBlockingWelcome2) - 1U); + * @endcode + */ +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle); + +/*! + * @brief Closes a writing handle for the serial manager module. + * + * This function Closes a writing handle for the serial manager module. + * + * @param writeHandle The serial manager module writing handle pointer. + * @retval kStatus_SerialManager_Success The writing handle is closed. + */ +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle); + +/*! + * @brief Opens a reading handle for the serial manager module. + * + * This function Opens a reading handle for the serial manager module. The reading handle can not be + * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when + * the previous reading handle is not closed. And there can only be one buffer for receiving for the + * reading handle at the same time. + * + * @param serialHandle The serial manager module handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param readHandle The serial manager module reading handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle); + * or + * uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The reading handle is opened. + * @retval kStatus_SerialManager_Busy Previous reading handle is not closed. + * + * Example below shows how to use this API to read data. + * @code + * static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle); + * SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle); + * static uint8_t s_nonBlockingBuffer[64]; + * SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle, + * APP_SerialManagerRxCallback, + * s_serialReadHandle); + * SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle, + * s_nonBlockingBuffer, + * sizeof(s_nonBlockingBuffer)); + * @endcode + */ +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle); + +/*! + * @brief Closes a reading for the serial manager module. + * + * This function Closes a reading for the serial manager module. + * + * @param readHandle The serial manager module reading handle pointer. + * @retval kStatus_SerialManager_Success The reading handle is closed. + */ +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle); + +/*! + * @brief Transmits data with the blocking mode. + * + * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking + * cannot be used at the same time. + * And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the blocking mode. + * + * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking + * cannot be used at the same time. + * And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief Transmits data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be sent. + * When all data is sent, the module notifies the upper layer through a TX callback function and passes + * the status parameter @ref kStatus_SerialManager_Success. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking + * cannot be used at the same time. And, the TX callback is mandatory before the function could be used. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be received. + * When all data is received, the module driver notifies the upper layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking + * cannot be used at the same time. And, the RX callback is mandatory before the function could be used. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Tries to read data. + * + * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be + * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length. + * After the data is copied, the actual data length is passed by the parameter length. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @param receivedLength Length received from the ring buffer directly. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength); + +/*! + * @brief Cancels unfinished send transmission. + * + * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer + * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of + * the function #SerialManager_WriteBlocking. + * + * @param writeHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the sending. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle); + +/*! + * @brief Cancels unfinished receive transmission. + * + * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper + * layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of + * the function #SerialManager_ReadBlocking. + * + * @param readHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the receiving. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle); + +/*! + * @brief Installs a TX callback and callback parameter. + * + * This function is used to install the TX callback and callback parameter for the serial manager module. + * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param writeHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam); + +/*! + * @brief Installs a RX callback and callback parameter. + * + * This function is used to install the RX callback and callback parameter for the serial manager module. + * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param readHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam); + +#endif + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle); + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* __SERIAL_MANAGER_H__ */ diff --git a/component/serial_manager/fsl_component_serial_port_internal.h b/component/serial_manager/fsl_component_serial_port_internal.h new file mode 100644 index 0000000..ed0401d --- /dev/null +++ b/component/serial_manager/fsl_component_serial_port_internal.h @@ -0,0 +1,130 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_INTERNAL_H__ +#define __SERIAL_PORT_INTERNAL_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif +#else +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UartIsrFunction(serial_handle_t serialHandle); +#endif +serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) +serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +#endif +serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) +serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_SwoIsrFunction(serial_handle_t serialHandle); +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) +serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __SERIAL_PORT_INTERNAL_H__ */ diff --git a/component/serial_manager/fsl_component_serial_port_uart.c b/component/serial_manager/fsl_component_serial_port_uart.c new file mode 100644 index 0000000..f791e03 --- /dev/null +++ b/component/serial_manager/fsl_component_serial_port_uart.c @@ -0,0 +1,460 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_component_serial_manager.h" +#include "fsl_component_serial_port_internal.h" + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#include "fsl_adapter_uart.h" + +#include "fsl_component_serial_port_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U +#define SERIAL_MANAGER_BLOCK_OFFSET (12U) +typedef struct _serial_uart_send_state +{ + uint8_t *buffer; + uint32_t length; + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; +} serial_uart_send_state_t; + +typedef struct _serial_uart_recv_state +{ + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; + volatile uint8_t rxEnable; + uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH]; +} serial_uart_recv_state_t; +typedef struct _serial_uart_block_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); +} serial_uart_block_state_t; +#endif + +typedef struct _serial_uart_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_uart_send_state_t tx; + serial_uart_recv_state_t rx; +#endif +} serial_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static serial_manager_status_t Serial_UartEnableReceiving(serial_uart_state_t *serialUartHandle) +{ +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + if (1U == serialUartHandle->rx.rxEnable) + { + serialUartHandle->rx.busy = 1U; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = &serialUartHandle->rx.readBuffer[0]; + transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); + if (kStatus_HAL_UartSuccess != + HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if (kStatus_HAL_UartSuccess != + HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) +#endif + { + serialUartHandle->rx.busy = 0U; + return kStatus_SerialManager_Error; + } + } + return kStatus_SerialManager_Success; +} + +/* UART user callback */ +static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t msg; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + + assert(userData); + serialUartHandle = (serial_uart_state_t *)userData; + + if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status) + { + if ((NULL != serialUartHandle->rx.callback)) + { + msg.buffer = &serialUartHandle->rx.readBuffer[0]; + msg.length = sizeof(serialUartHandle->rx.readBuffer); + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success); + } +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = &serialUartHandle->rx.readBuffer[0]; + transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); + serialUartHandle->rx.busy = 0U; + if (kStatus_HAL_UartSuccess == + HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if ((hal_uart_status_t)kStatus_HAL_UartSuccess == + HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) +#endif + { + serialUartHandle->rx.busy = 1U; + } + } + else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status) + { + if (0U != serialUartHandle->tx.busy) + { + serialUartHandle->tx.busy = 0U; + if ((NULL != serialUartHandle->tx.callback)) + { + msg.buffer = serialUartHandle->tx.buffer; + msg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success); + } + } + } + else + { + } +} +#endif + +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig) +{ + serial_uart_state_t *serialUartHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_port_uart_config_t *uartConfig = (serial_port_uart_config_t *)serialConfig; +#endif + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +#if 0 /* Not used below! */ + hal_uart_transfer_t transfer; +#endif +#endif +#endif + + assert(serialConfig); + assert(serialHandle); + assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t)); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + serialManagerStatus = (serial_manager_status_t)HAL_UartInit( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig); + assert(kStatus_SerialManager_Success == serialManagerStatus); + (void)serialManagerStatus; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + serial_manager_type_t type = *(serial_manager_type_t *)((uint32_t)serialHandle - SERIAL_MANAGER_BLOCK_OFFSET); + if (type == kSerialManager_Blocking) + { + return serialManagerStatus; + } +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ + serialUartHandle->rx.rxEnable = uartConfig->enableRx; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + + (void)HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartCallback, serialUartHandle); +#else + (void)HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), Serial_UartCallback, + serialUartHandle); +#endif +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialManagerStatus = Serial_UartEnableReceiving(serialUartHandle); +#endif + + return serialManagerStatus; +} + +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif +#endif + (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->tx.busy = 0U; + serialUartHandle->rx.busy = 0U; +#endif + + return kStatus_SerialManager_Success; +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + hal_uart_status_t uartstatus; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) + serial_manager_type_t type = *(serial_manager_type_t *)((uint32_t)serialHandle - SERIAL_MANAGER_BLOCK_OFFSET); + if (type == kSerialManager_Blocking) + { + return (serial_manager_status_t)HAL_UartSendBlocking( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); + } +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ + if (0U != serialUartHandle->tx.busy) + { + return kStatus_SerialManager_Busy; + } + serialUartHandle->tx.busy = 1U; + + serialUartHandle->tx.buffer = buffer; + serialUartHandle->tx.length = length; + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = buffer; + transfer.dataSize = length; + uartstatus = + HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer); +#else + + uartstatus = HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +#endif + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} +serial_manager_status_t Serial_UartWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + buffer, length); +} +#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U)) +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartReceiveBlocking( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +} +#endif /* SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE */ +#else + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + buffer, length); +} + +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartReceiveBlocking( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +} + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t msg; + uint32_t primask; + uint8_t isBusy = 0U; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + primask = DisableGlobalIRQ(); + isBusy = serialUartHandle->tx.busy; + serialUartHandle->tx.busy = 0U; + EnableGlobalIRQ(primask); + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif + if (0U != isBusy) + { + if ((NULL != serialUartHandle->tx.callback)) + { + msg.buffer = serialUartHandle->tx.buffer; + msg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->tx.callback = callback; + serialUartHandle->tx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->rx.callback = callback; + serialUartHandle->rx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +void Serial_UartIsrFunction(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +} +#endif + +serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_status_t status = kStatus_SerialManager_Success; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_type_t type = + *(serial_manager_type_t *)(void *)((uint8_t *)serialHandle - SERIAL_MANAGER_BLOCK_OFFSET); + if (type != kSerialManager_Blocking) + { + status = Serial_UartEnableReceiving(serialUartHandle); + } +#endif + + return status; +} + +#endif diff --git a/component/serial_manager/fsl_component_serial_port_uart.h b/component/serial_manager/fsl_component_serial_port_uart.h new file mode 100644 index 0000000..0b8e35e --- /dev/null +++ b/component/serial_manager/fsl_component_serial_port_uart.h @@ -0,0 +1,80 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_UART_H__ +#define __SERIAL_PORT_UART_H__ + +#include "fsl_adapter_uart.h" + +/*! + * @addtogroup serial_port_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief serial port uart handle size*/ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE) +#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE) +#else +#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE) +#endif + +#ifndef SERIAL_USE_CONFIGURE_STRUCTURE +#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */ +#endif + +/*! @brief serial port uart parity mode*/ +typedef enum _serial_port_uart_parity_mode +{ + kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */ + kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */ +} serial_port_uart_parity_mode_t; + +/*! @brief serial port uart stop bit count*/ +typedef enum _serial_port_uart_stop_bit_count +{ + kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */ + kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */ +} serial_port_uart_stop_bit_count_t; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/*! @brief serial port uart block mode*/ +typedef enum _serial_port_uart_block_mode +{ + kSerialManager_UartNonBlockMode = 0x0U, /*!< Uart NonBlock Mode */ + kSerialManager_UartBlockMode = 0x1U, /*!< Uart Block Mode */ +} serial_port_uart_block_mode_t; +#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */ + +typedef struct _serial_port_uart_config +{ + uint32_t clockRate; /*!< clock rate */ + uint32_t baudRate; /*!< baud rate */ + serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_port_uart_block_mode_t mode; /*!< serial port uart block mode */ +#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */ +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif +} serial_port_uart_config_t; +/*! @} */ +#endif /* __SERIAL_PORT_UART_H__ */ diff --git a/component/uart/component_lpuart_adapter_MIMXRT1052.cmake b/component/uart/component_lpuart_adapter_MIMXRT1052.cmake new file mode 100644 index 0000000..149b7d7 --- /dev/null +++ b/component/uart/component_lpuart_adapter_MIMXRT1052.cmake @@ -0,0 +1,19 @@ +if(NOT COMPONENT_LPUART_ADAPTER_MIMXRT1052_INCLUDED) + +set(COMPONENT_LPUART_ADAPTER_MIMXRT1052_INCLUDED true CACHE BOOL "component_lpuart_adapter component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_adapter_lpuart.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(driver_common_MIMXRT1052) + +include(driver_lpuart_MIMXRT1052) + +endif() diff --git a/component/uart/fsl_adapter_lpuart.c b/component/uart/fsl_adapter_lpuart.c new file mode 100644 index 0000000..50cbd84 --- /dev/null +++ b/component/uart/fsl_adapter_lpuart.c @@ -0,0 +1,1205 @@ +/* + * Copyright 2018, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +#include "fsl_adapter_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#ifndef HAL_UART_ADAPTER_LOWPOWER_RESTORE +#define HAL_UART_ADAPTER_LOWPOWER_RESTORE (1) +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_receive_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_send_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_send_state_t; +#endif +/*! @brief uart state structure. */ +typedef struct _hal_uart_state +{ + uint8_t instance; +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + hal_uart_block_mode_t mode; + hal_uart_transfer_callback_t callback; + void *callbackParam; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + lpuart_handle_t hardwareHandle; +#endif + hal_uart_receive_state_t rx; + hal_uart_send_state_t tx; +#endif +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) + uint32_t reg_BAUD; + uint32_t reg_CTRL; + uint32_t reg_WATER; + uint32_t reg_MODIR; +#else + hal_uart_config_t config; +#endif +#endif +} hal_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static LPUART_Type *const s_LpuartAdapterBase[] = LPUART_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) +static const clock_ip_name_t s_LpuartAdapterClock[] = LPUART_CLOCKS; +#endif /* HAL_UART_ADAPTER_LOWPOWER_RESTORE */ +#endif /* HAL_UART_ADAPTER_LOWPOWER */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +static const IRQn_Type s_LpuartRxIRQ[] = LPUART_RX_IRQS; +static const IRQn_Type s_LpuartTxIRQ[] = LPUART_TX_IRQS; +#else +static const IRQn_Type s_LpuartIRQ[] = LPUART_RX_TX_IRQS; +#endif +#endif + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static hal_uart_state_t *s_UartState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)]; +#endif + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus = kStatus_HAL_UartError; + switch (status) + { + case (int32_t)kStatus_Success: + uartStatus = kStatus_HAL_UartSuccess; + break; + case (int32_t)kStatus_LPUART_TxBusy: + uartStatus = kStatus_HAL_UartTxBusy; + break; + case (int32_t)kStatus_LPUART_RxBusy: + uartStatus = kStatus_HAL_UartRxBusy; + break; + case (int32_t)kStatus_LPUART_TxIdle: + uartStatus = kStatus_HAL_UartTxIdle; + break; + case (int32_t)kStatus_LPUART_RxIdle: + uartStatus = kStatus_HAL_UartRxIdle; + break; + case (int32_t)kStatus_LPUART_BaudrateNotSupport: + uartStatus = kStatus_HAL_UartBaudrateNotSupport; + break; + case (int32_t)kStatus_LPUART_NoiseError: + case (int32_t)kStatus_LPUART_FramingError: + case (int32_t)kStatus_LPUART_ParityError: + uartStatus = kStatus_HAL_UartProtocolError; + break; + default: + /*MISRA rule 16.4*/ + break; + } + return uartStatus; +} +#else +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus; + if ((int32_t)kStatus_Success == status) + { + uartStatus = kStatus_HAL_UartSuccess; /* Successfully */ + } + else + { + uartStatus = kStatus_HAL_UartError; /* Error occurs on HAL uart */ + } + return uartStatus; +} +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static void HAL_UartCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + assert(callbackParam); + + uartHandle = (hal_uart_state_t *)callbackParam; + + assert(uartHandle->mode != kHAL_UartBlockMode); + + if (kStatus_HAL_UartProtocolError == uartStatus) + { + if (0U != uartHandle->hardwareHandle.rxDataSize) + { + uartStatus = kStatus_HAL_UartError; + } + } + + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); + } +} + +#else + +static void HAL_UartInterruptHandle(uint8_t instance) +{ + hal_uart_state_t *uartHandle = s_UartState[instance]; + uint32_t status; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t count; +#endif + + assert(uartHandle); + + status = LPUART_GetStatusFlags(s_LpuartAdapterBase[instance]); + +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + s_LpuartAdapterBase[instance]->STAT = + ((s_LpuartAdapterBase[instance]->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + } +#endif + + /* Receive data register full */ + if (((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & + (uint32_t)kLPUART_RxDataRegFullInterruptEnable))) +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + || ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != + (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable))) +#endif + ) + { + if (NULL != uartHandle->rx.buffer) + { +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_RXCOUNT_MASK) >> + LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1u; +#endif + while (0u != count) + { + count--; +#endif + uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = LPUART_ReadByte(s_LpuartAdapterBase[instance]); + if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) + { + LPUART_DisableInterrupts( + s_LpuartAdapterBase[instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + | (uint32_t)kLPUART_IdleLineInterruptEnable +#endif + ); + uartHandle->rx.buffer = NULL; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + count = 0u; +#endif + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); + } + } +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + } +#endif + } +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != + (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable))) + { + s_LpuartAdapterBase[instance]->STAT |= ((uint32_t)kLPUART_IdleLineFlag); + } +#endif + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != (LPUART_STAT_TDRE_MASK & status)) && (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & + (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable))) + { + if (NULL != uartHandle->tx.buffer) + { +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + /* Get the size that transmit buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[instance]) - + (uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_TXCOUNT_MASK) >> + LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1u; +#endif + while (0u != count) + { + count--; +#endif + LPUART_WriteByte(s_LpuartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); + if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) + { + LPUART_DisableInterrupts(s_LpuartAdapterBase[instance], + (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + uartHandle->tx.buffer = NULL; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + count = 0u; +#endif + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); + } + } +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + } +#endif + } + } + +#if !(defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], status); +#endif +} +#endif + +#endif + +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config) +{ + hal_uart_state_t *uartHandle; + lpuart_config_t lpuartConfig; + status_t status; + hal_uart_status_t uartStatus = kStatus_HAL_UartSuccess; + assert(handle); + assert(config); + assert(config->instance < (sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *))); + assert(s_LpuartAdapterBase[config->instance]); + assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t)); + + LPUART_GetDefaultConfig(&lpuartConfig); + lpuartConfig.baudRate_Bps = config->baudRate_Bps; + lpuartConfig.parityMode = (lpuart_parity_mode_t)config->parityMode; + lpuartConfig.stopBitCount = (lpuart_stop_bit_count_t)config->stopBitCount; + lpuartConfig.enableRx = (bool)config->enableRx; + lpuartConfig.enableTx = (bool)config->enableTx; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + if (config->txFifoWatermark > 0U) + { + lpuartConfig.txFifoWatermark = + MIN(config->txFifoWatermark, FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[config->instance])) - 1U; + } + if (config->rxFifoWatermark > 0U) + { + lpuartConfig.rxFifoWatermark = + MIN(config->rxFifoWatermark, FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[config->instance])) - 1U; + } +#endif +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + lpuartConfig.enableRxRTS = (bool)config->enableRxRTS; + lpuartConfig.enableTxCTS = (bool)config->enableTxCTS; +#endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */ + status = LPUART_Init(s_LpuartAdapterBase[config->instance], (void *)&lpuartConfig, config->srcClock_Hz); + + if ((int32_t)kStatus_Success != status) + { + uartStatus = HAL_UartGetStatus(status); /*Get current uart status*/ + } + else + { + uartHandle = (hal_uart_state_t *)handle; + uartHandle->instance = config->instance; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + uartHandle->mode = config->mode; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + LPUART_TransferCreateHandle(s_LpuartAdapterBase[config->instance], &uartHandle->hardwareHandle, + (lpuart_transfer_callback_t)HAL_UartCallback, handle); +#else + s_UartState[uartHandle->instance] = uartHandle; +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif + +#endif +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) + uartHandle->reg_BAUD = s_LpuartAdapterBase[uartHandle->instance]->BAUD; + uartHandle->reg_CTRL = s_LpuartAdapterBase[uartHandle->instance]->CTRL; + uartHandle->reg_WATER = s_LpuartAdapterBase[uartHandle->instance]->WATER; + uartHandle->reg_MODIR = s_LpuartAdapterBase[uartHandle->instance]->MODIR; +#else + memcpy(&uartHandle->config, config, sizeof(hal_uart_config_t)); +#endif +#endif + } + + return uartStatus; +} + +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + + LPUART_Deinit(s_LpuartAdapterBase[uartHandle->instance]); /*LPUART Deinitialization*/ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + s_UartState[uartHandle->instance] = NULL; +#endif + +#endif + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + + status = LPUART_ReadBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + + (void)LPUART_WriteBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle) +{ + assert(handle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle) +{ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + hal_uart_state_t *uartHandle; + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; +#if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable lpuart clock */ + CLOCK_EnableClock(s_LpuartAdapterClock[uartHandle->instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + s_LpuartAdapterBase[uartHandle->instance]->BAUD = uartHandle->reg_BAUD; + s_LpuartAdapterBase[uartHandle->instance]->WATER = uartHandle->reg_WATER; + s_LpuartAdapterBase[uartHandle->instance]->MODIR = uartHandle->reg_MODIR; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Enable tx/rx FIFO */ + s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + /* Flush FIFO */ + s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif /* FSL_FEATURE_LPUART_HAS_FIFO */ + s_LpuartAdapterBase[uartHandle->instance]->CTRL = uartHandle->reg_CTRL; +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif + if (uartHandle->mode == kHAL_UartNonBlockMode) + { + s_LpuartAdapterBase[uartHandle->instance]->CTRL |= LPUART_CTRL_RIE_MASK; + HAL_UartIsrFunction(uartHandle); + } + +#endif +#else + HAL_UartInit(handle, &uartHandle->config); +#endif +#endif + return kStatus_HAL_UartSuccess; +} + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + assert(uartHandle->mode != kHAL_UartBlockMode); + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + status = LPUART_TransferReceiveNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (lpuart_transfer_t *)(void *)transfer, NULL); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + status = LPUART_TransferSendNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (lpuart_transfer_t *)(void *)transfer); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + status = + LPUART_TransferGetReceiveCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + status = LPUART_TransferGetSendCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + LPUART_TransferAbortReceive(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + LPUART_TransferAbortSend(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +#else + +/* None transactional API with non-blocking mode. */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + if (NULL != uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } + + uartHandle->rx.bufferLength = length; + uartHandle->rx.bufferSofar = 0; + uartHandle->rx.buffer = data; + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + | (uint32_t)kLPUART_IdleLineInterruptEnable +#endif + ); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + if (NULL != uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } + uartHandle->tx.bufferLength = length; + uartHandle->tx.bufferSofar = 0; + uartHandle->tx.buffer = data; + LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(reCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + if (NULL != uartHandle->rx.buffer) + { + *reCount = uartHandle->rx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(seCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + if (NULL != uartHandle->tx.buffer) + { + *seCount = uartHandle->tx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + if (NULL != uartHandle->rx.buffer) + { + LPUART_DisableInterrupts( + s_LpuartAdapterBase[uartHandle->instance], + (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + uartHandle->rx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + assert(uartHandle->mode != kHAL_UartBlockMode); + if (NULL != uartHandle->tx.buffer) + { + LPUART_DisableInterrupts(s_LpuartAdapterBase[uartHandle->instance], + (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + uartHandle->tx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +#endif + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + DisableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif + LPUART_TransferHandleIRQ(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +} + +#else + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + DisableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif + HAL_UartInterruptHandle(uartHandle->instance); +#if 0 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); + NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); +#else + NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_LpuartIRQ[uartHandle->instance]); +#endif +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_IRQHandler(void) +{ + if ((s_UartState[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL))) + { + HAL_UartInterruptHandle(0); + } + } + if ((s_UartState[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL))) + { + HAL_UartInterruptHandle(1); + } + } + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_LPUART1_TX_IRQHandler(void) +{ + if ((s_UartState[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) + { + HAL_UartInterruptHandle(0); + } + } + if ((s_UartState[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) + { + HAL_UartInterruptHandle(1); + } + } + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_LPUART1_IRQHandler(void); +void LPUART0_LPUART1_IRQHandler(void) +{ + uint32_t orMask; + uint32_t rdrfMask; + uint32_t rieMask; + uint32_t tdreMask; + uint32_t tieMask; + if (NULL != (s_UartState[0])) + { + orMask = LPUART_STAT_OR_MASK & LPUART0->STAT; + rdrfMask = LPUART_STAT_RDRF_MASK & LPUART0->STAT; + rieMask = LPUART_CTRL_RIE_MASK & LPUART0->CTRL; + tdreMask = LPUART0->STAT & LPUART_STAT_TDRE_MASK; + tieMask = LPUART0->CTRL & LPUART_CTRL_TIE_MASK; + if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask)) + { + HAL_UartInterruptHandle(0); + } + } + if (NULL != (s_UartState[1])) + { + orMask = LPUART_STAT_OR_MASK & LPUART1->STAT; + rdrfMask = LPUART_STAT_RDRF_MASK & LPUART1->STAT; + rieMask = LPUART_CTRL_RIE_MASK & LPUART1->CTRL; + tdreMask = LPUART1->STAT & LPUART_STAT_TDRE_MASK; + tieMask = LPUART1->CTRL & LPUART_CTRL_TIE_MASK; + if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask)) + { + HAL_UartInterruptHandle(1); + } + } + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_IRQHandler(void); +void LPUART0_IRQHandler(void) +{ + HAL_UartInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +void LPUART1_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART1_IRQHandler(void); +void LPUART1_IRQHandler(void) +{ + HAL_UartInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +void LPUART2_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART2_IRQHandler(void); +void LPUART2_IRQHandler(void) +{ + HAL_UartInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +void LPUART3_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART3_IRQHandler(void); +void LPUART3_IRQHandler(void) +{ + HAL_UartInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(4); + SDK_ISR_EXIT_BARRIER; +} +void LPUART4_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(4); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART4_IRQHandler(void); +void LPUART4_IRQHandler(void) +{ + HAL_UartInterruptHandle(4); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(5); + SDK_ISR_EXIT_BARRIER; +} +void LPUART5_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(5); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART5_IRQHandler(void); +void LPUART5_IRQHandler(void) +{ + HAL_UartInterruptHandle(5); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(6); + SDK_ISR_EXIT_BARRIER; +} +void LPUART6_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(6); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART6_IRQHandler(void); +void LPUART6_IRQHandler(void) +{ + HAL_UartInterruptHandle(6); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(7); + SDK_ISR_EXIT_BARRIER; +} +void LPUART7_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(7); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART7_IRQHandler(void); +void LPUART7_IRQHandler(void) +{ + HAL_UartInterruptHandle(7); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_IRQHandler(void) +{ + HAL_UartInterruptHandle(8); + SDK_ISR_EXIT_BARRIER; +} +void LPUART8_RX_IRQHandler(void) +{ + HAL_UartInterruptHandle(8); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART8_IRQHandler(void); +void LPUART8_IRQHandler(void) +{ + HAL_UartInterruptHandle(8); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_IRQHandler(void); +void M4_0_LPUART_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(CM4_0__LPUART)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_IRQHandler(void); +void M4_1_LPUART_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(CM4_1__LPUART)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_IRQHandler(void); +void M4_LPUART_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(CM4__LPUART)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART0)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART1)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART2)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART3)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART4)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_IRQHandler(void); +void ADMA_UART0_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART0)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_IRQHandler(void); +void ADMA_UART1_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART1)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_IRQHandler(void); +void ADMA_UART2_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART2)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_IRQHandler(void); +void ADMA_UART3_INT_IRQHandler(void) +{ + HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART3)); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#endif + +#endif diff --git a/component/uart/fsl_adapter_uart.h b/component/uart/fsl_adapter_uart.h new file mode 100644 index 0000000..f97c00e --- /dev/null +++ b/component/uart/fsl_adapter_uart.h @@ -0,0 +1,558 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_UART_ADAPTER_H__ +#define __HAL_UART_ADAPTER_H__ + +#include "fsl_common.h" +#if defined(FSL_RTOS_FREE_RTOS) +#include "FreeRTOS.h" +#endif + +/*! + * @addtogroup UART_Adapter + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define UART_ADAPTER_NON_BLOCKING_MODE (1U) +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define UART_ADAPTER_NON_BLOCKING_MODE (0U) +#else +#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE +#endif +#endif + +#if defined(__GIC_PRIO_BITS) +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (25U) +#endif +#else +#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#endif +#else +/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. + * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum + * priority is 3 (2^2 - 1). So, the default value is 3. + */ +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (3U) +#endif +#endif +#endif + +#ifndef HAL_UART_ADAPTER_LOWPOWER +#define HAL_UART_ADAPTER_LOWPOWER (0U) +#endif /* HAL_UART_ADAPTER_LOWPOWER */ + +#ifndef HAL_UART_ADAPTER_FIFO +#define HAL_UART_ADAPTER_FIFO (0U) +#endif /* HAL_UART_ADAPTER_FIFO */ + +/*! @brief Definition of uart adapter handle size. */ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U) +#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U) +#else +#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U) +#endif + +/*! + * @brief Defines the uart handle + * + * This macro is used to define a 4 byte aligned uart handle. + * Then use "(hal_uart_handle_t)name" to get the uart handle. + * + * The macro should be global and could be optional. You could also define uart handle by yourself. + * + * This is an example, + * @code + * UART_HANDLE_DEFINE(uartHandle); + * @endcode + * + * @param name The name string of the uart handle. + */ +#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */ +#ifndef HAL_UART_TRANSFER_MODE +#define HAL_UART_TRANSFER_MODE (0U) +#endif + +/*! @brief The handle of uart adapter. */ +typedef void *hal_uart_handle_t; + +/*! @brief UART status */ +typedef enum _hal_uart_status +{ + kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */ + kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */ + kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */ + kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */ + kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */ + kStatus_HAL_UartBaudrateNotSupport = + MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */ + kStatus_HAL_UartProtocolError = MAKE_STATUS( + kStatusGroup_HAL_UART, + 6), /*!< Error occurs for Noise, Framing, Parity, etc. + For transactional transfer, The up layer needs to abort the transfer and then starts again */ + kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */ +} hal_uart_status_t; + +/*! @brief UART parity mode. */ +typedef enum _hal_uart_parity_mode +{ + kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */ + kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */ +} hal_uart_parity_mode_t; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! @brief UART Block Mode. */ +typedef enum _hal_uart_block_mode +{ + kHAL_UartNonBlockMode = 0x0U, /*!< Uart NonBlock Mode */ + kHAL_UartBlockMode = 0x1U, /*!< Uart Block Mode */ +} hal_uart_block_mode_t; +#endif /* UART_ADAPTER_NON_BLOCKING_MODE */ + +/*! @brief UART stop bit count. */ +typedef enum _hal_uart_stop_bit_count +{ + kHAL_UartOneStopBit = 0U, /*!< One stop bit */ + kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */ +} hal_uart_stop_bit_count_t; + +/*! @brief UART configuration structure. */ +typedef struct _hal_uart_config +{ + uint32_t srcClock_Hz; /*!< Source clock */ + uint32_t baudRate_Bps; /*!< Baud rate */ + hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the + SOC corresponding RM. + Invalid instance value will cause initialization failure. */ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + hal_uart_block_mode_t mode; /*!< Uart block mode */ +#endif /* UART_ADAPTER_NON_BLOCKING_MODE */ +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif +} hal_uart_config_t; + +/*! @brief UART transfer callback function. */ +typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam); + +/*! @brief UART transfer structure. */ +typedef struct _hal_uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} hal_uart_transfer_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with the UART handle and the user configuration structure. + * + * This function configures the UART module with user-defined settings. The user can configure the configuration + * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by + * the caller. Example below shows how to use this API to configure the UART. + * @code + * UART_HANDLE_DEFINE(g_UartHandle); + * hal_uart_config_t config; + * config.srcClock_Hz = 48000000; + * config.baudRate_Bps = 115200U; + * config.parityMode = kHAL_UartParityDisabled; + * config.stopBitCount = kHAL_UartOneStopBit; + * config.enableRx = 1; + * config.enableTx = 1; + * config.enableRxRTS = 0; + * config.enableTxCTS = 0; + * config.instance = 0; + * HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config); + * @endcode + * + * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #UART_HANDLE_DEFINE(handle); + * or + * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param config Pointer to user-defined configuration structure. + * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_HAL_UartSuccess UART initialization succeed + */ +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess UART de-initialization succeed + */ +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle); + +/*! @}*/ + +/*! + * @name Blocking bus Operations + * @{ + */ + +/*! + * @brief Reads RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the RX register. + * + * @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_HAL_UartError An error occurred while receiving data. + * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data. + * @retval kStatus_HAL_UartSuccess Successfully received all data. + */ +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully sent all data. + */ +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length); + +/*! @}*/ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +/*! + * @name Transactional + * @note The transactional API and the functional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When any status of the UART changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART driver. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure, see #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure. See #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#else + +/*! + * @name Functional API with non-blocking mode. + * @note The functional API and the transactional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART adapter. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART adapter notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#endif +#endif + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess Successful operation. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess Successful operation. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle); + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param handle UART handle pointer. + */ +void HAL_UartIsrFunction(hal_uart_handle_t handle); +#endif + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* __HAL_UART_ADAPTER_H__ */ diff --git a/config.cmake b/config.cmake new file mode 100644 index 0000000..aa67b5b --- /dev/null +++ b/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMXRT1052 true) +set(CONFIG_USE_driver_lpuart_MIMXRT1052 true) diff --git a/device/MIMXRT1052.h b/device/MIMXRT1052.h new file mode 100644 index 0000000..5b5dd36 --- /dev/null +++ b/device/MIMXRT1052.h @@ -0,0 +1,46337 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.3, 2019-04-29 +** Build: b201019 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMXRT1052 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. +** - rev. 1.3 (2019-04-29) +** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052.h + * @version 1.3 + * @date 2019-04-29 + * @brief CMSIS Peripheral Access Layer for MIMXRT1052 + * + * CMSIS Peripheral Access Layer for MIMXRT1052 + */ + +#ifndef _MIMXRT1052_H_ +#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0003U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ + DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ + DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ + DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ + DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ + DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ + DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ + DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ + DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ + DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ + DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ + DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ + DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ + DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ + DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ + DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ + DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ + CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ + CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ + CORE_IRQn = 19, /**< CorePlatform exception IRQ */ + LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ + LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ + LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ + LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ + LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ + LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ + LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ + LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ + LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ + LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ + LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ + LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ + LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ + LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ + LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ + LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ + CAN1_IRQn = 36, /**< CAN1 interrupt */ + CAN2_IRQn = 37, /**< CAN2 interrupt */ + FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ + KPP_IRQn = 39, /**< Keypad nterrupt */ + TSC_DIG_IRQn = 40, /**< TSC interrupt */ + GPR_IRQ_IRQn = 41, /**< GPR interrupt */ + LCDIF_IRQn = 42, /**< LCDIF interrupt */ + CSI_IRQn = 43, /**< CSI interrupt */ + PXP_IRQn = 44, /**< PXP interrupt */ + WDOG2_IRQn = 45, /**< WDOG2 interrupt */ + SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */ + SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */ + SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ + CSU_IRQn = 49, /**< CSU interrupt */ + DCP_IRQn = 50, /**< DCP_IRQ interrupt */ + DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */ + Reserved68_IRQn = 52, /**< Reserved interrupt */ + TRNG_IRQn = 53, /**< TRNG interrupt */ + SJC_IRQn = 54, /**< SJC interrupt */ + BEE_IRQn = 55, /**< BEE interrupt */ + SAI1_IRQn = 56, /**< SAI1 interrupt */ + SAI2_IRQn = 57, /**< SAI1 interrupt */ + SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ + SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ + SPDIF_IRQn = 60, /**< SPDIF interrupt */ + PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */ + TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */ + USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ + USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ + ADC1_IRQn = 67, /**< ADC1 interrupt */ + ADC2_IRQn = 68, /**< ADC2 interrupt */ + DCDC_IRQn = 69, /**< DCDC interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Reserved87_IRQn = 71, /**< Reserved interrupt */ + GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ + GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ + GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ + GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ + FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ + FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */ + WDOG1_IRQn = 92, /**< WDOG1 interrupt */ + RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ + EWM_IRQn = 94, /**< EWM interrupt */ + CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ + CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ + GPC_IRQn = 97, /**< GPC interrupt */ + SRC_IRQn = 98, /**< SRC interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + GPT1_IRQn = 100, /**< GPT1 interrupt */ + GPT2_IRQn = 101, /**< GPT2 interrupt */ + PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ + PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ + PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ + PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ + PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ + SEMC_IRQn = 109, /**< Reserved interrupt */ + USDHC1_IRQn = 110, /**< USDHC1 interrupt */ + USDHC2_IRQn = 111, /**< USDHC2 interrupt */ + USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ + ENET_IRQn = 114, /**< ENET interrupt */ + ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ + XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ + XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ + ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ + ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ + ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ + ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ + PIT_IRQn = 122, /**< PIT interrupt */ + ACMP1_IRQn = 123, /**< ACMP interrupt */ + ACMP2_IRQn = 124, /**< ACMP interrupt */ + ACMP3_IRQn = 125, /**< ACMP interrupt */ + ACMP4_IRQn = 126, /**< ACMP interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + ENC1_IRQn = 129, /**< ENC1 interrupt */ + ENC2_IRQn = 130, /**< ENC2 interrupt */ + ENC3_IRQn = 131, /**< ENC3 interrupt */ + ENC4_IRQn = 132, /**< ENC4 interrupt */ + TMR1_IRQn = 133, /**< TMR1 interrupt */ + TMR2_IRQn = 134, /**< TMR2 interrupt */ + TMR3_IRQn = 135, /**< TMR3 interrupt */ + TMR4_IRQn = 136, /**< TMR4 interrupt */ + PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ + PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ + PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ + PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ + PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */ + PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */ + PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */ + PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */ + PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */ + PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */ + PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */ + PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ + PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ + PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ + PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M7 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ +#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ +#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm7.h" /* Core Peripheral Access Layer */ +#include "system_MIMXRT1052.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ + kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ + kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ + kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ + kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ + kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ + kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ + kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ + kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ + kDmaRequestMuxCSI = 12|0x100U, /**< CSI */ + kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ + kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ + kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ + kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ + kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ + kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ + kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ + kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ + kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ + kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ + kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ + kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ + kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ + kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ + kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ + kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ + kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ + kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ + kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ + kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ + kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ + kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ + kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */ + kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */ + kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */ + kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */ + kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */ + kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ + kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ + kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ + kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ + kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ + kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ + kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ + kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ + kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ + kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ + kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ + kDmaRequestMuxPxp = 75|0x100U, /**< PXP */ + kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */ + kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ + kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ + kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ + kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ + kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ + kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ + kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ + kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ + kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ + kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ + kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ + kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ + kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ + kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ + kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ + kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ + kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ + kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ + kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ + kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ + kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ + kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */ + kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */ + kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */ + kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */ + kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */ + kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ + kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ + kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ + kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ + kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ + kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ +} dma_request_source_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +typedef enum _xbar_input_signal +{ + kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ + kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ + kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ + kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ + kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ + kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ + kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ + kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ + kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ + kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ + kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ + kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ + kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ + kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ + kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ + kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ + kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ + kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ + kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ + kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ + kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ + kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ + kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ + kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ + kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ + kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ + kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */ + kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */ + kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */ + kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */ + kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */ + kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */ + kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ + kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ + kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ + kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ + kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ + kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ + kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ + kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ + kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ + kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ + kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ + kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ + kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ + kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ + kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ + kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ + kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ + kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ + kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ + kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ + kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ + kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ + kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ + kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ + kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ + kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ + kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ + kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ + kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ + kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ + kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ + kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ + kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */ + kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */ + kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */ + kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */ + kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */ + kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */ + kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */ + kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */ + kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */ + kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */ + kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */ + kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */ + kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */ + kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */ + kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */ + kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */ + kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ + kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ + kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ + kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ + kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ + kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ + kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ + kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ + kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ + kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */ + kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */ + kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */ + kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */ + kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */ + kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */ + kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */ + kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */ + kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */ + kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */ + kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ + kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ + kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ + kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ + kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ + kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ + kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ + kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ + kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ + kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ + kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ + kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ + kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ + kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ + kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ + kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ + kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ + kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ + kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ + kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ + kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ + kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ + kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ + kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ + kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ + kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ + kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ + kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ + kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ + kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ + kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ + kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ + kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ + kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ + kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ + kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ + kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ + kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ + kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */ + kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */ + kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */ + kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */ + kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */ + kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */ + kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */ + kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */ + kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ + kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ + kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */ + kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */ + kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */ + kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */ + kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */ + kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */ + kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */ + kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */ + kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */ + kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */ + kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ + kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ + kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ + kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ + kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ + kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ + kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ + kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ + kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ + kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ + kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ + kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ + kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ + kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ + kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ + kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ + kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ + kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ + kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ + kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ + kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ + kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ + kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ + kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ + kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ + kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ + kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ + kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ + kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ + kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ + kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ + kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ + kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ + kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ + kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ + kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ + kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ + kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ + kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */ + kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */ + kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */ + kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */ + kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */ + kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */ + kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */ + kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ + kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ + kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ + kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ + kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ + kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ + kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ + kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ + kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ + kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ + kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ + kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ + kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ + kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ + kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ + kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ + kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ + kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ + kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ + kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ + kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ + kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ + kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ + kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ + kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */ + kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */ + kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ + kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ + kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ + kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ + kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ + kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ + kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ + kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ + kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ + kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ + kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ + kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ + kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ + kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ + kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ + kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ + kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ + kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ + kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ + kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ + kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ + kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ + kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ + kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ + kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */ + kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */ + kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */ + kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */ + kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */ + kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */ + kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */ + kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */ + kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */ + kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */ + kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */ + kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */ + kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */ + kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */ + kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */ + kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */ + kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */ + kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */ + kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */ + kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */ + kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */ + kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */ + kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */ + kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */ + kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */ + kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */ + kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */ + kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */ + kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */ + kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */ + kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */ + kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */ + kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */ + kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */ + kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */ + kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */ + kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */ + kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ + kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ + kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ + kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ + kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ + kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ + kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ + kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ + kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */ + kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */ + kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */ + kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */ + kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */ + kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */ + kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */ + kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */ + kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */ + kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */ + kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */ + kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */ + kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */ + kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */ + kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */ + kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */ + kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ + kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ + kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ + kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ + kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ + kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ + kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ + kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */ + kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */ + kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */ + kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */ + kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */ + kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */ + kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */ + kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */ + kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */ + kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */ + kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */ + kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */ + kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */ + kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */ + kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */ + kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */ + kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */ + kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */ + kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */ + kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */ + kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */ + kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */ + kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */ + kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */ + kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */ + kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */ + kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */ + kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */ + kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ + __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ + __IO uint32_t GC; /**< General control register, offset: 0x48 */ + __IO uint32_t GS; /**< General status register, offset: 0x4C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +/*! @{ */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b10000..External channel selection from ADC_ETC + * 0b11000..Reserved. + * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + * 0b11010..Reserved. + * 0b11011..Reserved. + * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. + */ +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +/*! AIEN - Conversion Complete Interrupt Enable/Disable Control + * 0b1..Conversion complete interrupt enabled + * 0b0..Conversion complete interrupt disabled + */ +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (8U) + +/*! @name HS - Status register for HW triggers */ +/*! @{ */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +/*! COCO0 - Conversion Complete Flag + */ +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ + +/*! @name R - Data result register for HW triggers */ +/*! @{ */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +/*! CDATA - Data (result of an ADC conversion) + */ +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ + +/* The count of ADC_R */ +#define ADC_R_COUNT (8U) + +/*! @name CFG - Configuration register */ +/*! @{ */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..IPG clock + * 0b01..IPG clock divided by 2 + * 0b10..Reserved + * 0b11..Asynchronous clock (ADACK) + */ +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +/*! MODE - Conversion Mode Selection + * 0b00..8-bit conversion + * 0b01..10-bit conversion + * 0b10..12-bit conversion + * 0b11..Reserved + */ +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +/*! ADLSMP - Long Sample Time Configuration + * 0b0..Short sample mode. + * 0b1..Long sample mode. + */ +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..Input clock + * 0b01..Input clock / 2 + * 0b10..Input clock / 4 + * 0b11..Input clock / 8 + */ +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..ADC hard block not in low power mode. + * 0b1..ADC hard block in low power mode. + */ +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +/*! ADSTS + * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + */ +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +/*! ADHSC - High Speed Configuration + * 0b0..Normal conversion selected. + * 0b1..High speed conversion selected. + */ +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Selects VREFH/VREFL as reference voltage. + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected + * 0b1..Hardware trigger selected + */ +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +/*! AVGS - Hardware Average select + * 0b00..4 samples averaged + * 0b01..8 samples averaged + * 0b10..16 samples averaged + * 0b11..32 samples averaged + */ +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +/*! OVWREN - Data Overwrite Enable + * 0b1..Enable the overwriting. + * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + */ +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ + +/*! @name GC - General control register */ +/*! @{ */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +/*! ADACKEN - Asynchronous clock output enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC + */ +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled (default) + * 0b1..DMA enabled + */ +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + */ +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" + * functionality based on the values placed in the ADC_CV register. + * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" + * functionality based on the values placed in the ADC_CV registers. + */ +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled + * 0b1..Compare function enabled + */ +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +/*! AVGE - Hardware average enable + * 0b0..Hardware average function disabled + * 0b1..Hardware average function enabled + */ +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + */ +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +/*! CAL - Calibration + */ +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ + +/*! @name GS - General status register */ +/*! @{ */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +/*! AWKST - Asynchronous wakeup interrupt status + * 0b1..Asynchronous wake up interrupt occurred in stop mode. + * 0b0..No asynchronous interrupt. + */ +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ + +/*! @name CV - Compare value register */ +/*! @{ */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +/*! CV1 - Compare Value 1 + */ +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +/*! CV2 - Compare Value 2 + */ +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ + +/*! @name OFS - Offset correction value register */ +/*! @{ */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +/*! OFS - Offset value + */ +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +/*! SIGN - Sign bit + * 0b0..The offset value is added with the raw result + * 0b1..The offset value is subtracted from the raw converted value + */ +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ + +/*! @name CAL - Calibration value register */ +/*! @{ */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +/*! CAL_CODE - Calibration Result Value + */ +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400C4000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400C8000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer + * @{ + */ + +/** ADC_ETC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ + __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ + __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ + __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ + } TRIG[8]; +} ADC_ETC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks + * @{ + */ + +/*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ +#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) +#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) +#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) +#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) +#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) +#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) +#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) +#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) +#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) +#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) +#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ + +/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ + +/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ + +/*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ + +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CTRL */ +#define ADC_ETC_TRIGn_CTRL_COUNT (8U) + +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_COUNTER */ +#define ADC_ETC_TRIGn_COUNTER_COUNT (8U) + +/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ +#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) + +/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ +#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) + +/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ +#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) + +/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ +#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) + +/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_1_0 */ +#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) + +/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_3_2 */ +#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) + +/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_5_4 */ +#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) + +/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_7_6 */ +#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) + + +/*! + * @} + */ /* end of group ADC_ETC_Register_Masks */ + + +/* ADC_ETC - Peripheral instance base addresses */ +/** Peripheral ADC_ETC base address */ +#define ADC_ETC_BASE (0x403B0000u) +/** Peripheral ADC_ETC base pointer */ +#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) +/** Array initializer of ADC_ETC peripheral base addresses */ +#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } +/** Array initializer of ADC_ETC peripheral base pointers */ +#define ADC_ETC_BASE_PTRS { ADC_ETC } +/** Interrupt vectors for the ADC_ETC peripheral type */ +#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } +#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } + +/*! + * @} + */ /* end of group ADC_ETC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +/*! @{ */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x4007C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x4017C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x4027C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Peripheral AIPSTZ4 base address */ +#define AIPSTZ4_BASE (0x4037C000u) +/** Peripheral AIPSTZ4 base pointer */ +#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x403B4000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Peripheral AOI2 base address */ +#define AOI2_BASE (0x403B8000u) +/** Peripheral AOI2 base pointer */ +#define AOI2 ((AOI_Type *)AOI2_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BEE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer + * @{ + */ + +/** BEE - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */ + __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */ + __IO uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */ + __IO uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */ + __IO uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */ + __IO uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */ + __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */ + __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */ + __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */ + __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */ + __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */ + __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */ + __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */ + __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */ + __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */ + __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */ + __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */ +} BEE_Type; + +/* ---------------------------------------------------------------------------- + -- BEE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Register_Masks BEE Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define BEE_CTRL_BEE_ENABLE_MASK (0x1U) +#define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +/*! BEE_ENABLE + * 0b0..Disable BEE + * 0b1..Enable BEE + */ +#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) +#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) +#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) +#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) +#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) +#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) +#define BEE_CTRL_KEY_VALID_MASK (0x10U) +#define BEE_CTRL_KEY_VALID_SHIFT (4U) +#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) +#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) +#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +/*! KEY_REGION_SEL + * 0b0..Load AES key for region0 + * 0b1..Load AES key for region1 + */ +#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) +#define BEE_CTRL_AC_PROT_EN_MASK (0x40U) +#define BEE_CTRL_AC_PROT_EN_SHIFT (6U) +#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) +#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +/*! LITTLE_ENDIAN + * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, + * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to + * Byte0 to Byte15. + * 0b1..The input and output data of AES core is not swapped. + */ +#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) +#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) +#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) +#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +/*! CTRL_AES_MODE_R0 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) +#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +/*! CTRL_AES_MODE_R1 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) +#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) +#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) +#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) +#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) +#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) +#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) +#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) +#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) +#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) +#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) +#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) +#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) +#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) +#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) +#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) +#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) +#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) +#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET0 - Offset region 0 Register */ +/*! @{ */ +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET1 - Offset region 1 Register */ +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) +/*! @} */ + +/*! @name AES_KEY0_W0 - AES Key 0 Register */ +/*! @{ */ +#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) +/*! KEY0 - AES 128 key from software + */ +#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ + +/*! @name AES_KEY0_W1 - AES Key 1 Register */ +/*! @{ */ +#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) +/*! KEY1 - AES 128 key from software + */ +#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ + +/*! @name AES_KEY0_W2 - AES Key 2 Register */ +/*! @{ */ +#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) +/*! KEY2 - AES 128 key from software + */ +#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ + +/*! @name AES_KEY0_W3 - AES Key 3 Register */ +/*! @{ */ +#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) +/*! KEY3 - AES 128 key from software + */ +#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ +#define BEE_STATUS_IRQ_VEC_MASK (0xFFU) +#define BEE_STATUS_IRQ_VEC_SHIFT (0U) +#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) +#define BEE_STATUS_BEE_IDLE_MASK (0x100U) +#define BEE_STATUS_BEE_IDLE_SHIFT (8U) +#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W0 - NONCE00 Register */ +/*! @{ */ +#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) +#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W1 - NONCE01 Register */ +/*! @{ */ +#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) +#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W2 - NONCE02 Register */ +/*! @{ */ +#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) +#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W3 - NONCE03 Register */ +/*! @{ */ +#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) +#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W0 - NONCE10 Register */ +/*! @{ */ +#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) +#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W1 - NONCE11 Register */ +/*! @{ */ +#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) +#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W2 - NONCE12 Register */ +/*! @{ */ +#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) +#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W3 - NONCE13 Register */ +/*! @{ */ +#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) +#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ + +/*! @name REGION1_TOP - Region1 Top Address Register */ +/*! @{ */ +#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) +#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) +/*! REGION1_TOP - Address upper limit of region1 + */ +#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ + +/*! @name REGION1_BOT - Region1 Bottom Address Register */ +/*! @{ */ +#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) +#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) +/*! REGION1_BOT - Address lower limit of region1 + */ +#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BEE_Register_Masks */ + + +/* BEE - Peripheral instance base addresses */ +/** Peripheral BEE base address */ +#define BEE_BASE (0x403EC000u) +/** Peripheral BEE base pointer */ +#define BEE ((BEE_Type *)BEE_BASE) +/** Array initializer of BEE peripheral base addresses */ +#define BEE_BASE_ADDRS { BEE_BASE } +/** Array initializer of BEE peripheral base pointers */ +#define BEE_BASE_PTRS { BEE } + +/*! + * @} + */ /* end of group BEE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[8]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_4[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_5[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +/*! @{ */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM + * 0b00..Format A One full ID (standard or extended) per ID filter Table element. + * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + * 0b11..Format D All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN + * 0b1..Abort enabled + * 0b0..Abort disabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN + * 0b1..Local Priority enabled + * 0b0..Local Priority disabled + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ + * 0b1..Individual Rx masking and queue feature are enabled. + * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS + * 0b1..Self reception disabled + * 0b0..Self reception enabled + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN + * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK + * 0b1..FLEXCAN Self Wake Up feature is enabled + * 0b0..FLEXCAN Self Wake Up feature is disabled + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access + * behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK + * 0b1..FLEXCAN in Freeze Mode, prescaler stopped + * 0b0..FLEXCAN not in Freeze Mode, prescaler running + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST + * 0b1..Reset the registers + * 0b0..No reset request + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK + * 0b1..Wake Up Interrupt is enabled + * 0b0..Wake Up Interrupt is disabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT + * 0b1..Enters Freeze Mode if the FRZ bit is asserted. + * 0b0..No Freeze Mode request. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN + * 0b1..FIFO enabled + * 0b0..FIFO not enabled + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ + * 0b1..Enabled to enter Freeze Mode + * 0b0..Not enabled to enter Freeze Mode + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS + * 0b1..Disable the FLEXCAN module + * 0b0..Enable the FLEXCAN module + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 Register */ +/*! @{ */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM + * 0b1..FLEXCAN module operates in Listen Only Mode + * 0b0..Listen Only Mode is deactivated + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF + * 0b1..Lowest number buffer is transmitted first + * 0b0..Buffer with highest priority is transmitted first + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN + * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 + * preceding samples, a majority rule is used + * 0b0..Just one sample is used to determine the bit value + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK + * 0b1..Rx Warning Interrupt enabled + * 0b0..Rx Warning Interrupt disabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK + * 0b1..Tx Warning Interrupt enabled + * 0b0..Tx Warning Interrupt disabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB + * 0b1..Loop Back enabled + * 0b0..Loop Back disabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK + * 0b1..Error interrupt enabled + * 0b0..Error interrupt disabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK + * 0b1..Bus Off interrupt enabled + * 0b0..Bus Off interrupt disabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free Running Timer Register */ +/*! @{ */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +/*! @{ */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +/*! @{ */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter Register */ +/*! @{ */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 Register */ +/*! @{ */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT + * 0b1..Indicates setting of any Error Bit in the Error and Status Register + * 0b0..No such occurrence + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT + * 0b1..FLEXCAN module entered 'Bus Off' state + * 0b0..No such occurrence + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE + * 0b1..CAN bus is now IDLE + * 0b0..No such occurrence + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN + * 0b1..Rx_Err_Counter >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN + * 0b1..TX_Err_Counter >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR + * 0b1..A Stuffing Error occurred since last read of this register. + * 0b0..No such occurrence. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR + * 0b1..A Form Error occurred since last read of this register + * 0b0..No such occurrence + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR + * 0b1..A CRC error occurred since last read of this register. + * 0b0..No such occurrence + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR + * 0b1..An ACK error occurred since last read of this register + * 0b0..No such occurrence + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR + * 0b1..At least one bit sent as dominant is received as recessive + * 0b0..No such occurrence + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR + * 0b1..At least one bit sent as recessive is received as dominant + * 0b0..No such occurrence + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT + * 0b1..The Rx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT + * 0b1..The Tx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH + * 0b1..FlexCAN is synchronized to the CAN bus + * 0b0..FlexCAN is not synchronized to the CAN bus + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +/*! @{ */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +/*! BUFHM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @{ */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +/*! BUFLM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +/*! @{ */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +/*! BUFHI + * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception + * 0b00000000000000000000000000000000..No such occurrence + */ +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @{ */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +/*! BUF4TO0I + * 0b00001..Corresponding MB completed transmission/reception + * 0b00000..No such occurrence + */ +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I + * 0b1..MB5 completed transmission/reception or frames available in the FIFO + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I + * 0b1..MB6 completed transmission/reception or FIFO almost full + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I + * 0b1..MB7 completed transmission/reception or FIFO overflow + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN + * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within + * the incoming frame. Mask bits do apply. + * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS + * 0b1..Remote Request Frame is stored + * 0b0..Remote Response Frame is generated + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP + * 0b1..Matching starts from Mailboxes and continues on Rx FIFO + * 0b0..Matching starts from Rx FIFO and continues on Mailboxes + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ + * 0b1..Enable unrestricted write access to FlexCAN memory + * 0b0..Keep the write access restricted in some regions of FlexCAN memory + */ +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 Register */ +/*! @{ */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS + * 0b1..Contents of IMB and LPTM are valid + * 0b0..Contents of IMB and LPTM are invalid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - CRC Register */ +/*! @{ */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +/*! @{ */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +/*! CFSM - CAN Finite State Machine + */ +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +/*! CBN - CAN Bit Number + */ +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +/*! RMP - Rx Matching Pointer + */ +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +/*! TAP - Tx Arbitration Pointer + */ +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +/*! @{ */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. + */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. + */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. + */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. + */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Reserved + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +/*! @{ */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. + */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. + */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 7 of Rx/Tx frame. + */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 6 of Rx/Tx frame. + */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 5 of Rx/Tx frame. + */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 4 of Rx/Tx frame. + */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x401D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x401D4000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_3[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_4[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +/*! @{ */ +#define CCM_CCR_OSCNT_MASK (0xFFU) +#define CCM_CCR_OSCNT_SHIFT (0U) +/*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as + * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. + * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from + * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for + * the dpll_ip to use and only then the gate in dpll_ip can be opened. + */ +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +/*! COSC_EN + * 0b0..disable on chip oscillator + * 0b1..enable on chip oscillator + */ +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock periods delay + */ +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +/*! RBC_EN + * 0b1..REG_BYPASS_COUNTER enabled. + * 0b0..REG_BYPASS_COUNTER disabled + */ +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ + +/*! @name CSR - CCM Status Register */ +/*! @{ */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +/*! REF_EN_B + * 0b0..value of CCM_REF_EN_B is '0' + * 0b1..value of CCM_REF_EN_B is '1' + */ +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_CAMP2_READY_MASK (0x8U) +#define CCM_CSR_CAMP2_READY_SHIFT (3U) +/*! CAMP2_READY + * 0b0..CAMP2 is not ready. + * 0b1..CAMP2 is ready. + */ +#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +/*! COSC_READY + * 0b0..on board oscillator is not ready. + * 0b1..on board oscillator is ready. + */ +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ + +/*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +/*! PLL3_SW_CLK_SEL + * 0b0..pll3_main_clk + * 0b1..pll3 bypass clock + */ +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ + +/*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +/*! ARM_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ +#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) +#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +/*! SEMC_CLK_SEL + * 0b0..Periph_clk output will be used as SEMC clock root + * 0b1..SEMC alternative clock will be used as SEMC clock root + */ +#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +/*! SEMC_ALT_CLK_SEL + * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock + * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock + */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +/*! IPG_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +/*! AHB_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) +#define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +/*! SEMC_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +/*! PERIPH_CLK_SEL + * 0b0..derive clock from pre_periph_clk_sel + * 0b1..derive clock from periph_clk2_clk_divided + */ +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +/*! PERIPH_CLK2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +/*! LPSPI_CLK_SEL + * 0b00..derive clock from PLL3 PFD1 clk + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL2 + * 0b11..derive clock from PLL2 PFD2 + */ +#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +/*! PERIPH_CLK2_SEL + * 0b00..derive clock from pll3_sw_clk + * 0b01..derive clock from osc_clk (pll1_ref_clk) + * 0b10..derive clock from pll2_bypass_clk + * 0b11..reserved + */ +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +/*! TRACE_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from PLL2 PFD1 + */ +#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +/*! PRE_PERIPH_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from divided PLL1 + */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) +/*! LCDIF_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) +#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +/*! LPSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +/*! PERCLK_PODF - Divider for perclk podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +/*! PERCLK_CLK_SEL + * 0b0..derive clock from ipg clk root + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +/*! SAI1_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +/*! SAI2_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +/*! SAI3_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +/*! USDHC1_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +/*! USDHC2_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +/*! FLEXSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +/*! FLEXSPI_CLK_SEL + * 0b00..derive clock from semc_clk_root_pre + * 0b01..derive clock from pll3_sw_clk + * 0b10..derive clock from PLL2 PFD2 + * 0b11..derive clock from PLL3 PFD0 + */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +/*! CAN_CLK_PODF - Divider for CAN clock podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +/*! CAN_CLK_SEL + * 0b00..derive clock from pll3_sw_clk divided clock (60M) + * 0b01..derive clock from osc_clk (24M) + * 0b10..derive clock from pll3_sw_clk divided clock (80M) + * 0b11..Disable FlexCAN clock + */ +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) +/*! FLEXIO2_CLK_SEL + * 0b00..derive clock from PLL4 divided clock + * 0b01..derive clock from PLL3 PFD2 clock + * 0b10..derive clock from PLL5 clock + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +/*! UART_CLK_PODF - Divider for uart clock podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +/*! UART_CLK_SEL + * 0b0..derive clock from pll3_80m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +/*! USDHC1_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +/*! USDHC2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +/*! TRACE_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ + +/*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +/*! SAI1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) +/*! FLEXIO2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +/*! SAI3_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) +/*! FLEXIO2_CLK_PODF - Divider for flexio2 clock. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ + +/*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +/*! SAI2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) +/*! FLEXIO1_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) +/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) +/*! FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +/*! SPDIF0_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +/*! @{ */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) +/*! LCDIF_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) +/*! LCDIF_PRE_CLK_SEL + * 0b000..derive clock from PLL2 + * 0b001..derive clock from PLL3 PFD3 + * 0b010..derive clock from PLL5 + * 0b011..derive clock from PLL2 PFD0 + * 0b100..derive clock from PLL2 PFD1 + * 0b101..derive clock from PLL3 PFD1 + */ +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +/*! LPI2C_CLK_SEL + * 0b0..derive clock from pll3_60m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is + * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used + * to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +/*! CSI_CLK_SEL + * 0b00..derive clock from osc_clk (24M) + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from pll3_120M + * 0b11..derive clock from PLL3 PFD1 + */ +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +/*! CSI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ +#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +/*! SEMC_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the semc_podf will be applied. + */ +#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +/*! AHB_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + */ +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +/*! PERIPH2_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the + * previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +/*! PERIPH_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the + * previous value of select, and after the handshake periph_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +/*! ARM_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the arm_podf will be applied. + */ +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ + +/*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +/*! LPM + * 0b00..Remain in run mode + * 0b01..Transfer to wait mode + * 0b10..Transfer to stop mode + * 0b11..Reserved + */ +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +/*! ARM_CLK_DIS_ON_LPM + * 0b0..ARM clock enabled on wait mode. + * 0b1..ARM clock disabled on wait mode. . + */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +/*! SBYOS + * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain + * asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be + * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will + * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will + * continue with the exit from the STOP mode process. + */ +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +/*! DIS_REF_OSC + * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + */ +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +/*! STBY_COUNT + * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +/*! COSC_PWRDOWN + * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) +#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) +#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +/*! MASK_CORE0_WFI + * 0b0..WFI of core0 is not masked + * 0b1..WFI of core0 is masked + */ +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +/*! MASK_SCU_IDLE + * 0b1..SCU IDLE is masked + * 0b0..SCU IDLE is not masked + */ +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +/*! MASK_L2CC_IDLE + * 0b1..L2CC IDLE is masked + * 0b0..L2CC IDLE is not masked + */ +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ + +/*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +/*! LRF_PLL + * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs + */ +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +/*! COSC_READY + * 0b0..interrupt is not generated due to on board oscillator ready + * 0b1..interrupt generated due to on board oscillator ready + */ +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +/*! SEMC_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of semc_podf + * 0b1..interrupt generated due to frequency change of semc_podf + */ +#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! PERIPH2_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel + * 0b1..interrupt generated due to frequency change of periph2_clk_sel + */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +/*! AHB_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of ahb_podf + * 0b1..interrupt generated due to frequency change of ahb_podf + */ +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! PERIPH_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to update of periph_clk_sel. + * 0b1..interrupt generated due to update of periph_clk_sel. + */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of arm_podf + * 0b1..interrupt generated due to frequency change of arm_podf + */ +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +/*! MASK_LRF_PLL + * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created + * 0b1..mask interrupt due to lrf of PLLs + */ +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +/*! MASK_COSC_READY + * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created + * 0b1..mask interrupt due to on board oscillator ready + */ +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +/*! MASK_SEMC_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of semc_podf + */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! MASK_PERIPH2_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph2_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +/*! MASK_AHB_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of ahb_podf + */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! MASK_PERIPH_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of arm_podf + */ +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +/*! CLKO1_SEL + * 0b0000..USB1 PLL clock (divided by 2) + * 0b0001..SYS PLL clock (divided by 2) + * 0b0011..VIDEO PLL clock (divided by 2) + * 0b0101..semc_clk_root + * 0b0110..Reserved + * 0b1010..lcdif_pix_clk_root + * 0b1011..ahb_clk_root + * 0b1100..ipg_clk_root + * 0b1101..perclk_root + * 0b1110..ckil_sync_clk_root + * 0b1111..pll4_main_clk + */ +#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +/*! CLKO1_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +/*! CLKO1_EN + * 0b0..CCM_CLKO1 disabled. + * 0b1..CCM_CLKO1 enabled. + */ +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +/*! CLK_OUT_SEL + * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock + * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock + */ +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +/*! CLKO2_SEL + * 0b00011..usdhc1_clk_root + * 0b00101..wrck_clk_root + * 0b00110..lpi2c_clk_root + * 0b01011..csi_clk_root + * 0b01110..osc_clk + * 0b10001..usdhc2_clk_root + * 0b10010..sai1_clk_root + * 0b10011..sai2_clk_root + * 0b10100..sai3_clk_root + * 0b10111..can_clk_root + * 0b11011..flexspi_clk_root + * 0b11100..uart_clk_root + * 0b11101..spdif0_clk_root + * 0b11111..Reserved + */ +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +/*! CLKO2_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +/*! CLKO2_EN + * 0b0..CCM_CLKO2 disabled. + * 0b1..CCM_CLKO2 enabled. + */ +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ + +/*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +/*! PMIC_DELAY_SCALER + * 0b0..clock is not divided + * 0b1..clock is divided /8 + */ +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +/*! EFUSE_PROG_SUPPLY_GATE + * 0b0..fuse programing supply voltage is gated off to the efuse module + * 0b1..allow fuse programing. + */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +/*! SYS_MEM_DS_CTRL + * 0b00..Disable memory DS mode always + * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode + */ +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +/*! FPL - Fast PLL enable. + * 0b0..Engage PLL enable default way. + * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + */ +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +/*! INT_MEM_CLK_LPM + * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode + * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low + * Power Modes (WAIT and STOP without power gating) + */ +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ + +/*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +/*! MOD_EN_OV_GPT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +/*! MOD_EN_OV_PIT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +/*! MOD_EN_USDHC + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) +#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +/*! MOD_EN_OV_TRNG + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +/*! MOD_EN_OV_CAN2_CPI + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +/*! MOD_EN_OV_CAN1_CPI + * 0b0..don't overide module enable signal + * 0b1..overide module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x400FC000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +/*! ENABLE - Enable bit + * 0b0..Spread spectrum modulation disabled + * 0b1..Soread spectrum modulation enabled + */ +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x400D8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CM7_MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CM7_MCM_Peripheral_Access_Layer CM7_MCM Peripheral Access Layer + * @{ + */ + +/** CM7_MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */ +} CM7_MCM_Type; + +/* ---------------------------------------------------------------------------- + -- CM7_MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CM7_MCM_Register_Masks CM7_MCM Register Masks + * @{ + */ + +/*! @name ISCR - Interrupt Status and Control Register */ +/*! @{ */ +#define CM7_MCM_ISCR_WABS_MASK (0x20U) +#define CM7_MCM_ISCR_WABS_SHIFT (5U) +/*! WABS - Write Abort on Slave + * 0b0..No abort + * 0b1..Abort + */ +#define CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK) +#define CM7_MCM_ISCR_WABSO_MASK (0x40U) +#define CM7_MCM_ISCR_WABSO_SHIFT (6U) +/*! WABSO - Write Abort on Slave Overrun + * 0b0..No write abort overrun + * 0b1..Write abort overrun occurred + */ +#define CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK) +#define CM7_MCM_ISCR_FIOC_MASK (0x100U) +#define CM7_MCM_ISCR_FIOC_SHIFT (8U) +/*! FIOC - FPU Invalid Operation interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured + */ +#define CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK) +#define CM7_MCM_ISCR_FDZC_MASK (0x200U) +#define CM7_MCM_ISCR_FDZC_SHIFT (9U) +/*! FDZC - FPU Divide-by-Zero Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured + */ +#define CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK) +#define CM7_MCM_ISCR_FOFC_MASK (0x400U) +#define CM7_MCM_ISCR_FOFC_SHIFT (10U) +/*! FOFC - FPU Overflow interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occured + */ +#define CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK) +#define CM7_MCM_ISCR_FUFC_MASK (0x800U) +#define CM7_MCM_ISCR_FUFC_SHIFT (11U) +/*! FUFC - FPU Underflow Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured + */ +#define CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK) +#define CM7_MCM_ISCR_FIXC_MASK (0x1000U) +#define CM7_MCM_ISCR_FIXC_SHIFT (12U) +/*! FIXC - FPU Inexact Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured + */ +#define CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK) +#define CM7_MCM_ISCR_FIDC_MASK (0x8000U) +#define CM7_MCM_ISCR_FIDC_SHIFT (15U) +/*! FIDC - FPU Input Denormal Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured + */ +#define CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK) +#define CM7_MCM_ISCR_WABE_MASK (0x200000U) +#define CM7_MCM_ISCR_WABE_SHIFT (21U) +/*! WABE - TCM Write Abort Interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK) +#define CM7_MCM_ISCR_FIOCE_MASK (0x1000000U) +#define CM7_MCM_ISCR_FIOCE_SHIFT (24U) +/*! FIOCE - FPU Invalid Operation Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK) +#define CM7_MCM_ISCR_FDZCE_MASK (0x2000000U) +#define CM7_MCM_ISCR_FDZCE_SHIFT (25U) +/*! FDZCE - FPU Divide-by-Zero Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK) +#define CM7_MCM_ISCR_FOFCE_MASK (0x4000000U) +#define CM7_MCM_ISCR_FOFCE_SHIFT (26U) +/*! FOFCE - FPU Overflow Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK) +#define CM7_MCM_ISCR_FUFCE_MASK (0x8000000U) +#define CM7_MCM_ISCR_FUFCE_SHIFT (27U) +/*! FUFCE - FPU Underflow Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK) +#define CM7_MCM_ISCR_FIXCE_MASK (0x10000000U) +#define CM7_MCM_ISCR_FIXCE_SHIFT (28U) +/*! FIXCE - FPU Inexact Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK) +#define CM7_MCM_ISCR_FIDCE_MASK (0x80000000U) +#define CM7_MCM_ISCR_FIDCE_SHIFT (31U) +/*! FIDCE - FPU Input Denormal Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CM7_MCM_Register_Masks */ + + +/* CM7_MCM - Peripheral instance base addresses */ +/** Peripheral CM7_MCM base address */ +#define CM7_MCM_BASE (0xE0080000u) +/** Peripheral CM7_MCM base pointer */ +#define CM7_MCM ((CM7_MCM_Type *)CM7_MCM_BASE) +/** Array initializer of CM7_MCM peripheral base addresses */ +#define CM7_MCM_BASE_ADDRS { CM7_MCM_BASE } +/** Array initializer of CM7_MCM peripheral base pointers */ +#define CM7_MCM_BASE_PTRS { CM7_MCM } + +/*! + * @} + */ /* end of group CM7_MCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + * 0b001..One sample must agree. The comparator output is simply sampled. + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. + */ +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ + +/*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. + */ +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +/*! OPE - Comparator Output Pin Enable + * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the + * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this + * bit has no effect. + */ +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +/*! COS - Comparator Output Select + * 0b0..Set the filtered comparator output (CMPO) to equal COUT. + * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. + */ +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +/*! INV - Comparator INVERT + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. + */ +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +/*! PMODE - Power Mode Select + * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + */ +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. + */ +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. + */ +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ + +/*! @name FPR - CMP Filter Period Register */ +/*! @{ */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +/*! FILT_PER - Filter Sample Period + */ +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ + +/*! @name SCR - CMP Status and Control Register */ +/*! @{ */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +/*! COUT - Analog Comparator Output + */ +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Falling-edge on COUT has not been detected. + * 0b1..Falling-edge on COUT has occurred. + */ +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Rising-edge on COUT has not been detected. + * 0b1..Rising-edge on COUT has occurred. + */ +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +/*! DMAEN - DMA Enable Control + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. + */ +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ + +/*! @name DACCR - DAC Control Register */ +/*! @{ */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +/*! VOSEL - DAC Output Voltage Select + */ +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..Vin1 is selected as resistor ladder network supply reference. + * 0b1..Vin2 is selected as resistor ladder network supply reference. + */ +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. + */ +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ + +/*! @name MUXCR - MUX Control Register */ +/*! @{ */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +/*! MSEL - Minus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +/*! PSEL - Plus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40094000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x40094008u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Peripheral CMP3 base address */ +#define CMP3_BASE (0x40094010u) +/** Peripheral CMP3 base pointer */ +#define CMP3 ((CMP_Type *)CMP3_BASE) +/** Peripheral CMP4 base address */ +#define CMP4_BASE (0x40094018u) +/** Peripheral CMP4 base pointer */ +#define CMP4 ((CMP_Type *)CMP4_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +/*! @{ */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +/*! PIXEL_BIT + * 0b0..8-bit data for each pixel + * 0b1..10-bit data for each pixel + */ +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +/*! REDGE + * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK + * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK + */ +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +/*! INV_PCLK + * 0b0..CSI_PIXCLK is directly applied to internal circuitry + * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry + */ +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +/*! INV_DATA + * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry + * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry + */ +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +/*! GCLK_MODE + * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + */ +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +/*! PACK_DIR + * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For + * stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For + * stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + */ +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +/*! FCC + * 0b0..Asynchronous FIFO clear is selected. + * 0b1..Synchronous FIFO clear is selected. + */ +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +/*! CCIR_EN + * 0b0..Traditional interface is selected. Timing interface logic is used to latch data. + * 0b1..CCIR656 interface is selected. + */ +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +/*! HSYNC_POL + * 0b0..HSYNC is active low + * 0b1..HSYNC is active high + */ +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +/*! SOF_INTEN + * 0b0..SOF interrupt disable + * 0b1..SOF interrupt enable + */ +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +/*! SOF_POL + * 0b0..SOF interrupt is generated on SOF falling edge + * 0b1..SOF interrupt is generated on SOF rising edge + */ +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +/*! RXFF_INTEN + * 0b0..RxFIFO full interrupt disable + * 0b1..RxFIFO full interrupt enable + */ +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +/*! FB1_DMA_DONE_INTEN + * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable + */ +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +/*! FB2_DMA_DONE_INTEN + * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable + */ +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +/*! STATFF_INTEN + * 0b0..STATFIFO full interrupt disable + * 0b1..STATFIFO full interrupt enable + */ +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +/*! SFF_DMA_DONE_INTEN + * 0b0..STATFIFO DMA Transfer Done interrupt disable + * 0b1..STATFIFO DMA Transfer Done interrupt enable + */ +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +/*! RF_OR_INTEN + * 0b0..RxFIFO overrun interrupt is disabled + * 0b1..RxFIFO overrun interrupt is enabled + */ +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +/*! SF_OR_INTEN + * 0b0..STATFIFO overrun interrupt is disabled + * 0b1..STATFIFO overrun interrupt is enabled + */ +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +/*! COF_INT_EN + * 0b0..COF interrupt is disabled + * 0b1..COF interrupt is enabled + */ +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U) +#define CSI_CSICR1_CCIR_MODE_SHIFT (27U) +/*! CCIR_MODE + * 0b0..Progressive mode is selected + * 0b1..Interlace mode is selected + */ +#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +/*! PrP_IF_EN + * 0b0..CSI to PrP bus is disabled + * 0b1..CSI to PrP bus is enabled + */ +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +/*! EOF_INT_EN + * 0b0..EOF interrupt is disabled. + * 0b1..EOF interrupt is generated when RX count value is reached. + */ +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +/*! EXT_VSYNC + * 0b0..Internal VSYNC mode + * 0b1..External VSYNC mode + */ +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +/*! SWAP16_EN + * 0b0..Disable swapping + * 0b1..Enable swapping + */ +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) +/*! @} */ + +/*! @name CSICR2 - CSI Control Register 2 */ +/*! @{ */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +/*! LVRM + * 0b000..512 x 384 + * 0b001..448 x 336 + * 0b010..384 x 288 + * 0b011..384 x 256 + * 0b100..320 x 240 + * 0b101..288 x 216 + * 0b110..400 x 300 + */ +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +/*! BTS + * 0b00..GR + * 0b01..RG + * 0b10..BG + * 0b11..GB + */ +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +/*! SCE + * 0b0..Skip count disable + * 0b1..Skip count enable + */ +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +/*! AFS + * 0b00..Abs Diff on consecutive green pixels + * 0b01..Abs Diff on every third green pixels + * 0b1x..Abs Diff on every four green pixels + */ +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +/*! DRM + * 0b0..Stats grid of 8 x 6 + * 0b1..Stats grid of 8 x 12 + */ +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +/*! DMA_BURST_TYPE_SFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 + */ +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +/*! DMA_BURST_TYPE_RFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 + */ +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +/*! @} */ + +/*! @name CSICR3 - CSI Control Register 3 */ +/*! @{ */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +/*! ECC_AUTO_EN + * 0b0..Auto Error correction is disabled. + * 0b1..Auto Error correction is enabled. + */ +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +/*! ECC_INT_EN + * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + * 0b1..Interrupt is generated when error is detected. + */ +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +/*! ZERO_PACK_EN + * 0b0..Zero packing disabled + * 0b1..Zero packing enabled + */ +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +/*! TWO_8BIT_SENSOR + * 0b0..Only one sensor is connected. + * 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected. + */ +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +/*! RxFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..16 Double words + * 0b011..24 Double words + * 0b100..32 Double words + * 0b101..48 Double words + * 0b110..64 Double words + * 0b111..96 Double words + */ +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +/*! HRESP_ERR_EN + * 0b0..Disable hresponse error interrupt + * 0b1..Enable hresponse error interrupt + */ +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +/*! STATFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..12 Double words + * 0b011..16 Double words + * 0b100..24 Double words + * 0b101..32 Double words + * 0b110..48 Double words + * 0b111..64 Double words + */ +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +/*! DMA_REQ_EN_SFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request + */ +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +/*! DMA_REQ_EN_RFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request + */ +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +/*! DMA_REFLASH_SFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller + */ +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +/*! DMA_REFLASH_RFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller + */ +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +/*! FRMCNT_RST + * 0b0..Do not reset + * 0b1..Reset frame counter immediately + */ +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) +/*! @} */ + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +/*! @{ */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) +/*! @} */ + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +/*! @{ */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) +/*! @} */ + +/*! @name CSIRXCNT - CSI RX Count Register */ +/*! @{ */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) +/*! @} */ + +/*! @name CSISR - CSI Status Register */ +/*! @{ */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +/*! DRDY + * 0b0..No data (word) is ready + * 0b1..At least 1 datum (word) is ready in RXFIFO. + */ +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +/*! ECC_INT + * 0b0..No error detected + * 0b1..Error is detected in CCIR coding + */ +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +/*! HRESP_ERR_INT + * 0b0..No hresponse error. + * 0b1..Hresponse error is detected. + */ +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +/*! COF_INT + * 0b0..Video field has no change. + * 0b1..Change of video field is detected. + */ +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +/*! F1_INT + * 0b0..Field 1 of video is not detected. + * 0b1..Field 1 of video is about to start. + */ +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +/*! F2_INT + * 0b0..Field 2 of video is not detected + * 0b1..Field 2 of video is about to start + */ +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +/*! SOF_INT + * 0b0..SOF is not detected. + * 0b1..SOF is detected. + */ +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +/*! EOF_INT + * 0b0..EOF is not detected. + * 0b1..EOF is detected. + */ +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +/*! RxFF_INT + * 0b0..RxFIFO is not full. + * 0b1..RxFIFO is full. + */ +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +/*! DMA_TSF_DONE_FB1 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +/*! DMA_TSF_DONE_FB2 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +/*! STATFF_INT + * 0b0..STATFIFO is not full. + * 0b1..STATFIFO is full. + */ +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +/*! DMA_TSF_DONE_SFF + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +/*! RF_OR_INT + * 0b0..RXFIFO has not overflowed. + * 0b1..RXFIFO has overflowed. + */ +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +/*! SF_OR_INT + * 0b0..STATFIFO has not overflowed. + * 0b1..STATFIFO has overflowed. + */ +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) +/*! @} */ + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +/*! @{ */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/*! @} */ + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +/*! @{ */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/*! @} */ + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @{ */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) +/*! @} */ + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +/*! @{ */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +/*! @} */ + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +/*! @{ */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) +/*! @} */ + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +/*! @{ */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) +/*! @} */ + +/*! @name CSICR18 - CSI Control Register 18 */ +/*! @{ */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +/*! DEINTERLACE_EN + * 0b0..Deinterlace disabled + * 0b1..Deinterlace enabled + */ +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +/*! BASEADDR_SWITCH_SEL + * 0b0..Switching base address at the edge of the vsync + * 0b1..Switching base address at the edge of the first data of each frame + */ +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +/*! FIELD0_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +/*! DMA_FIELD1_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +/*! LAST_DMA_REQ_SEL + * 0b0..fifo_full_level + * 0b1..hburst_length + */ +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +/*! RGB888A_FORMAT_SEL + * 0b0..{8'h0, data[23:0]} + * 0b1..{data[23:0], 8'h0} + */ +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +/*! MASK_OPTION + * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b01..Writing to memory when CSI_ENABLE is 1. + * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + */ +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) +/*! @} */ + +/*! @name CSICR19 - CSI Control Register 19 */ +/*! @{ */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x402BC000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer + * @{ + */ + +/** CSU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[384]; + __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ + uint8_t RESERVED_2[316]; + __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ +} CSU_Type; + +/* ---------------------------------------------------------------------------- + -- CSU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Register_Masks CSU Register Masks + * @{ + */ + +/*! @name CSL - Config security level register */ +/*! @{ */ +#define CSU_CSL_SUR_S2_MASK (0x1U) +#define CSU_CSL_SUR_S2_SHIFT (0U) +/*! SUR_S2 + * 0b0..The secure user read access is disabled for the second slave. + * 0b1..The secure user read access is enabled for the second slave. + */ +#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) +#define CSU_CSL_SSR_S2_MASK (0x2U) +#define CSU_CSL_SSR_S2_SHIFT (1U) +/*! SSR_S2 + * 0b0..The secure supervisor read access is disabled for the second slave. + * 0b1..The secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) +#define CSU_CSL_NUR_S2_MASK (0x4U) +#define CSU_CSL_NUR_S2_SHIFT (2U) +/*! NUR_S2 + * 0b0..The non-secure user read access is disabled for the second slave. + * 0b1..The non-secure user read access is enabled for the second slave. + */ +#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) +#define CSU_CSL_NSR_S2_MASK (0x8U) +#define CSU_CSL_NSR_S2_SHIFT (3U) +/*! NSR_S2 + * 0b0..The non-secure supervisor read access is disabled for the second slave. + * 0b1..The non-secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) +#define CSU_CSL_SUW_S2_MASK (0x10U) +#define CSU_CSL_SUW_S2_SHIFT (4U) +/*! SUW_S2 + * 0b0..The secure user write access is disabled for the second slave. + * 0b1..The secure user write access is enabled for the second slave. + */ +#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) +#define CSU_CSL_SSW_S2_MASK (0x20U) +#define CSU_CSL_SSW_S2_SHIFT (5U) +/*! SSW_S2 + * 0b0..The secure supervisor write access is disabled for the second slave. + * 0b1..The secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) +#define CSU_CSL_NUW_S2_MASK (0x40U) +#define CSU_CSL_NUW_S2_SHIFT (6U) +/*! NUW_S2 + * 0b0..The non-secure user write access is disabled for the second slave. + * 0b1..The non-secure user write access is enabled for the second slave. + */ +#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) +#define CSU_CSL_NSW_S2_MASK (0x80U) +#define CSU_CSL_NSW_S2_SHIFT (7U) +/*! NSW_S2 + * 0b0..The non-secure supervisor write access is disabled for the second slave. + * 0b1..The non-secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) +#define CSU_CSL_LOCK_S2_MASK (0x100U) +#define CSU_CSL_LOCK_S2_SHIFT (8U) +/*! LOCK_S2 + * 0b0..Not locked. Bits 7-0 can be written by the software. + * 0b1..Bits 7-0 are locked and cannot be written by the software + */ +#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) +#define CSU_CSL_SUR_S1_MASK (0x10000U) +#define CSU_CSL_SUR_S1_SHIFT (16U) +/*! SUR_S1 + * 0b0..The secure user read access is disabled for the first slave. + * 0b1..The secure user read access is enabled for the first slave. + */ +#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) +#define CSU_CSL_SSR_S1_MASK (0x20000U) +#define CSU_CSL_SSR_S1_SHIFT (17U) +/*! SSR_S1 + * 0b0..The secure supervisor read access is disabled for the first slave. + * 0b1..The secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) +#define CSU_CSL_NUR_S1_MASK (0x40000U) +#define CSU_CSL_NUR_S1_SHIFT (18U) +/*! NUR_S1 + * 0b0..The non-secure user read access is disabled for the first slave. + * 0b1..The non-secure user read access is enabled for the first slave. + */ +#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) +#define CSU_CSL_NSR_S1_MASK (0x80000U) +#define CSU_CSL_NSR_S1_SHIFT (19U) +/*! NSR_S1 + * 0b0..The non-secure supervisor read access is disabled for the first slave. + * 0b1..The non-secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) +#define CSU_CSL_SUW_S1_MASK (0x100000U) +#define CSU_CSL_SUW_S1_SHIFT (20U) +/*! SUW_S1 + * 0b0..The secure user write access is disabled for the first slave. + * 0b1..The secure user write access is enabled for the first slave. + */ +#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) +#define CSU_CSL_SSW_S1_MASK (0x200000U) +#define CSU_CSL_SSW_S1_SHIFT (21U) +/*! SSW_S1 + * 0b0..The secure supervisor write access is disabled for the first slave. + * 0b1..The secure supervisor write access is enabled for the first slave. + */ +#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) +#define CSU_CSL_NUW_S1_MASK (0x400000U) +#define CSU_CSL_NUW_S1_SHIFT (22U) +/*! NUW_S1 + * 0b0..The non-secure user write access is disabled for the first slave. + * 0b1..The non-secure user write access is enabled for the first slave. + */ +#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) +#define CSU_CSL_NSW_S1_MASK (0x800000U) +#define CSU_CSL_NSW_S1_SHIFT (23U) +/*! NSW_S1 + * 0b0..The non-secure supervisor write access is disabled for the first slave. + * 0b1..The non-secure supervisor write access is enabled for the first slave + */ +#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) +#define CSU_CSL_LOCK_S1_MASK (0x1000000U) +#define CSU_CSL_LOCK_S1_SHIFT (24U) +/*! LOCK_S1 + * 0b0..Not locked. The bits 16-23 can be written by the software. + * 0b1..The bits 16-23 are locked and can't be written by the software. + */ +#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ + +/* The count of CSU_CSL */ +#define CSU_CSL_COUNT (32U) + +/*! @name HP0 - HP0 register */ +/*! @{ */ +#define CSU_HP0_HP_DMA_MASK (0x4U) +#define CSU_HP0_HP_DMA_SHIFT (2U) +/*! HP_DMA + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) +#define CSU_HP0_L_DMA_MASK (0x8U) +#define CSU_HP0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) +#define CSU_HP0_HP_LCDIF_MASK (0x10U) +#define CSU_HP0_HP_LCDIF_SHIFT (4U) +/*! HP_LCDIF + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) +#define CSU_HP0_L_LCDIF_MASK (0x20U) +#define CSU_HP0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) +#define CSU_HP0_HP_CSI_MASK (0x40U) +#define CSU_HP0_HP_CSI_SHIFT (6U) +/*! HP_CSI + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) +#define CSU_HP0_L_CSI_MASK (0x80U) +#define CSU_HP0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) +#define CSU_HP0_HP_PXP_MASK (0x100U) +#define CSU_HP0_HP_PXP_SHIFT (8U) +/*! HP_PXP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) +#define CSU_HP0_L_PXP_MASK (0x200U) +#define CSU_HP0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) +#define CSU_HP0_HP_DCP_MASK (0x400U) +#define CSU_HP0_HP_DCP_SHIFT (10U) +/*! HP_DCP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) +#define CSU_HP0_L_DCP_MASK (0x800U) +#define CSU_HP0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. + */ +#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) +#define CSU_HP0_HP_ENET_MASK (0x4000U) +#define CSU_HP0_HP_ENET_SHIFT (14U) +/*! HP_ENET + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) +#define CSU_HP0_L_ENET_MASK (0x8000U) +#define CSU_HP0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) +#define CSU_HP0_HP_USDHC1_MASK (0x10000U) +#define CSU_HP0_HP_USDHC1_SHIFT (16U) +/*! HP_USDHC1 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) +#define CSU_HP0_L_USDHC1_MASK (0x20000U) +#define CSU_HP0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) +#define CSU_HP0_HP_USDHC2_MASK (0x40000U) +#define CSU_HP0_HP_USDHC2_SHIFT (18U) +/*! HP_USDHC2 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) +#define CSU_HP0_L_USDHC2_MASK (0x80000U) +#define CSU_HP0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) +#define CSU_HP0_HP_TPSMP_MASK (0x100000U) +#define CSU_HP0_HP_TPSMP_SHIFT (20U) +/*! HP_TPSMP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) +#define CSU_HP0_L_TPSMP_MASK (0x200000U) +#define CSU_HP0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) +#define CSU_HP0_HP_USB_MASK (0x400000U) +#define CSU_HP0_HP_USB_SHIFT (22U) +/*! HP_USB + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) +#define CSU_HP0_L_USB_MASK (0x800000U) +#define CSU_HP0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ + +/*! @name SA - Secure access register */ +/*! @{ */ +#define CSU_SA_NSA_DMA_MASK (0x4U) +#define CSU_SA_NSA_DMA_SHIFT (2U) +/*! NSA_DMA - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) +#define CSU_SA_L_DMA_MASK (0x8U) +#define CSU_SA_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) +#define CSU_SA_NSA_LCDIF_MASK (0x10U) +#define CSU_SA_NSA_LCDIF_SHIFT (4U) +/*! NSA_LCDIF - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) +#define CSU_SA_L_LCDIF_MASK (0x20U) +#define CSU_SA_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) +#define CSU_SA_NSA_CSI_MASK (0x40U) +#define CSU_SA_NSA_CSI_SHIFT (6U) +/*! NSA_CSI - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) +#define CSU_SA_L_CSI_MASK (0x80U) +#define CSU_SA_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) +#define CSU_SA_NSA_PXP_MASK (0x100U) +#define CSU_SA_NSA_PXP_SHIFT (8U) +/*! NSA_PXP - Non-Secure Access Policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) +#define CSU_SA_L_PXP_MASK (0x200U) +#define CSU_SA_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) +#define CSU_SA_NSA_DCP_MASK (0x400U) +#define CSU_SA_NSA_DCP_SHIFT (10U) +/*! NSA_DCP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) +#define CSU_SA_L_DCP_MASK (0x800U) +#define CSU_SA_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) +#define CSU_SA_NSA_ENET_MASK (0x4000U) +#define CSU_SA_NSA_ENET_SHIFT (14U) +/*! NSA_ENET - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) +#define CSU_SA_L_ENET_MASK (0x8000U) +#define CSU_SA_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) +#define CSU_SA_NSA_USDHC1_MASK (0x10000U) +#define CSU_SA_NSA_USDHC1_SHIFT (16U) +/*! NSA_USDHC1 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) +#define CSU_SA_L_USDHC1_MASK (0x20000U) +#define CSU_SA_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) +#define CSU_SA_NSA_USDHC2_MASK (0x40000U) +#define CSU_SA_NSA_USDHC2_SHIFT (18U) +/*! NSA_USDHC2 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) +#define CSU_SA_L_USDHC2_MASK (0x80000U) +#define CSU_SA_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) +#define CSU_SA_NSA_TPSMP_MASK (0x100000U) +#define CSU_SA_NSA_TPSMP_SHIFT (20U) +/*! NSA_TPSMP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) +#define CSU_SA_L_TPSMP_MASK (0x200000U) +#define CSU_SA_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) +#define CSU_SA_NSA_USB_MASK (0x400000U) +#define CSU_SA_NSA_USB_SHIFT (22U) +/*! NSA_USB - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) +#define CSU_SA_L_USB_MASK (0x800000U) +#define CSU_SA_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ + +/*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ +#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) +#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +/*! HPC_DMA + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) +#define CSU_HPCONTROL0_L_DMA_MASK (0x8U) +#define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) +#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) +#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +/*! HPC_LCDIF + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) +#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) +#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) +#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) +#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +/*! HPC_CSI + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) +#define CSU_HPCONTROL0_L_CSI_MASK (0x80U) +#define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) +#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) +#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +/*! HPC_PXP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) +#define CSU_HPCONTROL0_L_PXP_MASK (0x200U) +#define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) +#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) +#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +/*! HPC_DCP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) +#define CSU_HPCONTROL0_L_DCP_MASK (0x800U) +#define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) +#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) +#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +/*! HPC_ENET + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) +#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) +#define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) +#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) +#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +/*! HPC_USDHC1 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) +#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) +#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) +#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) +#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +/*! HPC_USDHC2 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) +#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) +#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) +#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) +#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +/*! HPC_TPSMP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) +#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) +#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) +#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) +#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +/*! HPC_USB + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) +#define CSU_HPCONTROL0_L_USB_MASK (0x800000U) +#define CSU_HPCONTROL0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSU_Register_Masks */ + + +/* CSU - Peripheral instance base addresses */ +/** Peripheral CSU base address */ +#define CSU_BASE (0x400DC000u) +/** Peripheral CSU base pointer */ +#define CSU ((CSU_Type *)CSU_BASE) +/** Array initializer of CSU peripheral base addresses */ +#define CSU_BASE_ADDRS { CSU_BASE } +/** Array initializer of CSU peripheral base pointers */ +#define CSU_BASE_PTRS { CSU } + +/*! + * @} + */ /* end of group CSU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ + __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ + __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ + __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name REG0 - DCDC Register 0 */ +/*! @{ */ +#define DCDC_REG0_PWD_ZCD_MASK (0x1U) +#define DCDC_REG0_PWD_ZCD_SHIFT (0U) +#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) +#define DCDC_REG0_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_SEL_CLK_SHIFT (2U) +#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) +#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) +#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) +#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) +#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) +#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) +#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) +#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) +#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) +#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) +#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) +#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) +#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) +#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) +#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) +#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) +#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) +#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) +#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) +#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) +#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) +#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) +#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) +#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) +#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) +#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) +#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) +#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) +#define DCDC_REG0_STS_DC_OK_SHIFT (31U) +#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ + +/*! @name REG1 - DCDC Register 1 */ +/*! @{ */ +#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) +#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) +#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) +#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) +#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) +#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) +#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) +#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) +#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) +#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) +#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) +#define DCDC_REG1_VBG_TRIM_SHIFT (24U) +#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ + +/*! @name REG2 - DCDC Register 2 */ +/*! @{ */ +#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) +#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) +#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) +#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) +#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) +#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) +#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) +#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) +#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) +#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) +#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) +#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) +#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) +#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) +#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ + +/*! @name REG3 - DCDC Register 3 */ +/*! @{ */ +#define DCDC_REG3_TRG_MASK (0x1FU) +#define DCDC_REG3_TRG_SHIFT (0U) +#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) +#define DCDC_REG3_TARGET_LP_MASK (0x700U) +#define DCDC_REG3_TARGET_LP_SHIFT (8U) +#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) +#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) +#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) +#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) +#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) +#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) +#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK) +#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) +#define DCDC_REG3_DISABLE_STEP_SHIFT (30U) +#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCDC_Register_Masks */ + + +/* DCDC - Peripheral instance base addresses */ +/** Peripheral DCDC base address */ +#define DCDC_BASE (0x40080000u) +/** Peripheral DCDC base pointer */ +#define DCDC ((DCDC_Type *)DCDC_BASE) +/** Array initializer of DCDC peripheral base addresses */ +#define DCDC_BASE_ADDRS { DCDC_BASE } +/** Array initializer of DCDC peripheral base pointers */ +#define DCDC_BASE_PTRS { DCDC } +/** Interrupt vectors for the DCDC peripheral type */ +#define DCDC_IRQS { DCDC_IRQn } + +/*! + * @} + */ /* end of group DCDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< DCP control register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< DCP control register 0, offset: 0xC */ + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< DCP status register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< DCP status register, offset: 0x1C */ + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + __IO uint32_t CHANNELCTRL_SET; /**< DCP channel control register, offset: 0x24 */ + __IO uint32_t CHANNELCTRL_CLR; /**< DCP channel control register, offset: 0x28 */ + __IO uint32_t CHANNELCTRL_TOG; /**< DCP channel control register, offset: 0x2C */ + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_11[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + __IO uint32_t CH0STAT_SET; /**< DCP channel 0 status register, offset: 0x124 */ + __IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128 */ + __IO uint32_t CH0STAT_TOG; /**< DCP channel 0 status register, offset: 0x12C */ + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + __IO uint32_t CH0OPTS_SET; /**< DCP channel 0 options register, offset: 0x134 */ + __IO uint32_t CH0OPTS_CLR; /**< DCP channel 0 options register, offset: 0x138 */ + __IO uint32_t CH0OPTS_TOG; /**< DCP channel 0 options register, offset: 0x13C */ + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + __IO uint32_t CH1STAT_SET; /**< DCP channel 1 status register, offset: 0x164 */ + __IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168 */ + __IO uint32_t CH1STAT_TOG; /**< DCP channel 1 status register, offset: 0x16C */ + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + __IO uint32_t CH1OPTS_SET; /**< DCP channel 1 options register, offset: 0x174 */ + __IO uint32_t CH1OPTS_CLR; /**< DCP channel 1 options register, offset: 0x178 */ + __IO uint32_t CH1OPTS_TOG; /**< DCP channel 1 options register, offset: 0x17C */ + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + __IO uint32_t CH2STAT_SET; /**< DCP channel 2 status register, offset: 0x1A4 */ + __IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8 */ + __IO uint32_t CH2STAT_TOG; /**< DCP channel 2 status register, offset: 0x1AC */ + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + __IO uint32_t CH2OPTS_SET; /**< DCP channel 2 options register, offset: 0x1B4 */ + __IO uint32_t CH2OPTS_CLR; /**< DCP channel 2 options register, offset: 0x1B8 */ + __IO uint32_t CH2OPTS_TOG; /**< DCP channel 2 options register, offset: 0x1BC */ + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + __IO uint32_t CH3STAT_SET; /**< DCP channel 3 status register, offset: 0x1E4 */ + __IO uint32_t CH3STAT_CLR; /**< DCP channel 3 status register, offset: 0x1E8 */ + __IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC */ + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + __IO uint32_t CH3OPTS_SET; /**< DCP channel 3 options register, offset: 0x1F4 */ + __IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F8 */ + __IO uint32_t CH3OPTS_TOG; /**< DCP channel 3 options register, offset: 0x1FC */ + uint8_t RESERVED_20[512]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_21[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_22[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_23[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK) +#define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_SET_CLKGATE_SHIFT (30U) +#define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK) +#define DCP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SET_SFTRST_SHIFT (31U) +#define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK) +#define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK) +#define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_CLR_SFTRST_SHIFT (31U) +#define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK) +#define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK) +#define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_TOG_SFTRST_SHIFT (31U) +#define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - DCP status register */ +/*! @{ */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name STAT_SET - DCP status register */ +/*! @{ */ +#define DCP_STAT_SET_IRQ_MASK (0xFU) +#define DCP_STAT_SET_IRQ_SHIFT (0U) +#define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK) +#define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK) +#define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK) +#define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK) +#define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name STAT_CLR - DCP status register */ +/*! @{ */ +#define DCP_STAT_CLR_IRQ_MASK (0xFU) +#define DCP_STAT_CLR_IRQ_SHIFT (0U) +#define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK) +#define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK) +#define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK) +#define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK) +#define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name STAT_TOG - DCP status register */ +/*! @{ */ +#define DCP_STAT_TOG_IRQ_MASK (0xFU) +#define DCP_STAT_TOG_IRQ_SHIFT (0U) +#define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK) +#define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK) +#define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK) +#define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK) +#define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ + +/*! @name CHANNELCTRL_SET - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK) +/*! @} */ + +/*! @name CHANNELCTRL_CLR - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CHANNELCTRL_TOG - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ + +/*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +/*! CIPHER_ALGORITHMS + * 0b0000000000000001..AES128 + */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +/*! HASH_ALGORITHMS + * 0b0000000000000001..SHA1 + * 0b0000000000000010..CRC32 + * 0b0000000000000100..SHA256 + */ +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ + +/*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ + +/*! @name KEY - DCP key index */ +/*! @{ */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ + +/*! @name KEYDATA - DCP key data */ +/*! @{ */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ + +/*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ + +/*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +/*! CIPHER_ENCRYPT + * 0b1..ENCRYPT + * 0b0..DECRYPT + */ +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +/*! HASH_OUTPUT + * 0b0..INPUT + * 0b1..OUTPUT + */ +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ + +/*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +/*! CIPHER_SELECT + * 0b0000..AES128 + */ +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +/*! CIPHER_MODE + * 0b0000..ECB + * 0b0001..CBC + */ +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +/*! KEY_SELECT + * 0b00000000..KEY0 + * 0b00000001..KEY1 + * 0b00000010..KEY2 + * 0b00000011..KEY3 + * 0b11111110..UNIQUE_KEY + * 0b11111111..OTP_KEY + */ +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +/*! HASH_SELECT + * 0b0000..SHA1 + * 0b0001..CRC32 + * 0b0010..SHA256 + */ +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ + +/*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ + +/*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ + +/*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ + +/*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ + +/*! @name CH0STAT_SET - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK) +#define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK) +#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK) +#define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_SET_TAG_SHIFT (24U) +#define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH0STAT_CLR - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK) +#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH0STAT_TOG - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK) +#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH0OPTS_SET - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH0OPTS_CLR - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH0OPTS_TOG - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ + +/*! @name CH1STAT_SET - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK) +#define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK) +#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK) +#define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_SET_TAG_SHIFT (24U) +#define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH1STAT_CLR - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK) +#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH1STAT_TOG - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK) +#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH1OPTS_SET - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH1OPTS_CLR - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH1OPTS_TOG - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ + +/*! @name CH2STAT_SET - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK) +#define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK) +#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK) +#define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_SET_TAG_SHIFT (24U) +#define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH2STAT_CLR - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK) +#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH2STAT_TOG - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK) +#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH2OPTS_SET - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH2OPTS_CLR - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH2OPTS_TOG - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ + +/*! @name CH3STAT_SET - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK) +#define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK) +#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK) +#define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_SET_TAG_SHIFT (24U) +#define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH3STAT_CLR - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK) +#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH3STAT_TOG - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK) +#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH3OPTS_SET - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH3OPTS_CLR - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH3OPTS_TOG - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +/*! INDEX + * 0b00000001..CONTROL + * 0b00010000..OTPKEY0 + * 0b00010001..OTPKEY1 + * 0b00010010..OTPKEY2 + * 0b00010011..OTPKEY3 + */ +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ + +/*! @name DBGDATA - DCP debug data register */ +/*! @{ */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ + +/*! @name PAGETABLE - DCP page table register */ +/*! @{ */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ + +/*! @name VERSION - DCP version register */ +/*! @{ */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x402FC000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ + __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ + __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ + __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ + __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ + __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ + __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ + __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ + __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ + __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ + __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ + __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ + __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ + __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ + __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ + __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ + uint8_t RESERVED_7[3808]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to + * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_ERGA_MASK (0x8U) +#define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration is used for selection among the groups. + * 0b1..Round robin arbitration is used for selection among the groups. + */ +#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated + * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel + * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the + * next minor loop. + */ +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES + * field. The individual enable fields allow the minor loop offset to be applied to the source address, the + * destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_GRP0PRI_MASK (0x100U) +#define DMA_CR_GRP0PRI_SHIFT (8U) +/*! GRP0PRI - Channel Group 0 Priority + */ +#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) +#define DMA_CR_GRP1PRI_MASK (0x400U) +#define DMA_CR_GRP1PRI_SHIFT (10U) +/*! GRP1PRI - Channel Group 1 Priority + */ +#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and + * force the minor loop to finish. The cancel takes effect after the last write of the current read/write + * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX + * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an + * optional error interrupt. + */ +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The + * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after + * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) +#define DMA_CR_ACTIVE_MASK (0x80000000U) +#define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ +#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Error Status Register */ +/*! @{ */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. + * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, + * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0x1F00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number + */ +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel + * priorities within a group are not unique. + */ +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_GPE_MASK (0x8000U) +#define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error + * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ +#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +/*! VLD - VLD + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ + +/*! @name ERQ - Enable Request Register */ +/*! @{ */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) +#define DMA_ERQ_ERQ16_MASK (0x10000U) +#define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) +#define DMA_ERQ_ERQ17_MASK (0x20000U) +#define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) +#define DMA_ERQ_ERQ18_MASK (0x40000U) +#define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) +#define DMA_ERQ_ERQ19_MASK (0x80000U) +#define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) +#define DMA_ERQ_ERQ20_MASK (0x100000U) +#define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) +#define DMA_ERQ_ERQ21_MASK (0x200000U) +#define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) +#define DMA_ERQ_ERQ22_MASK (0x400000U) +#define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) +#define DMA_ERQ_ERQ23_MASK (0x800000U) +#define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) +#define DMA_ERQ_ERQ24_MASK (0x1000000U) +#define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) +#define DMA_ERQ_ERQ25_MASK (0x2000000U) +#define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) +#define DMA_ERQ_ERQ26_MASK (0x4000000U) +#define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) +#define DMA_ERQ_ERQ27_MASK (0x8000000U) +#define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) +#define DMA_ERQ_ERQ28_MASK (0x10000000U) +#define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) +#define DMA_ERQ_ERQ29_MASK (0x20000000U) +#define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) +#define DMA_ERQ_ERQ30_MASK (0x40000000U) +#define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) +#define DMA_ERQ_ERQ31_MASK (0x80000000U) +#define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ + +/*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) +#define DMA_EEI_EEI16_MASK (0x10000U) +#define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) +#define DMA_EEI_EEI17_MASK (0x20000U) +#define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) +#define DMA_EEI_EEI18_MASK (0x40000U) +#define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) +#define DMA_EEI_EEI19_MASK (0x80000U) +#define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) +#define DMA_EEI_EEI20_MASK (0x100000U) +#define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) +#define DMA_EEI_EEI21_MASK (0x200000U) +#define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) +#define DMA_EEI_EEI22_MASK (0x400000U) +#define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) +#define DMA_EEI_EEI23_MASK (0x800000U) +#define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) +#define DMA_EEI_EEI24_MASK (0x1000000U) +#define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) +#define DMA_EEI_EEI25_MASK (0x2000000U) +#define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) +#define DMA_EEI_EEI26_MASK (0x4000000U) +#define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) +#define DMA_EEI_EEI27_MASK (0x8000000U) +#define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) +#define DMA_EEI_EEI28_MASK (0x10000000U) +#define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) +#define DMA_EEI_EEI29_MASK (0x20000000U) +#define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) +#define DMA_EEI_EEI30_MASK (0x40000000U) +#define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) +#define DMA_EEI_EEI31_MASK (0x80000000U) +#define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_CEEI_CEEI_MASK (0x1FU) +#define DMA_CEEI_CEEI_SHIFT (0U) +/*! CEEI - Clear Enable Error Interrupt + */ +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ + +/*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_SEEI_SEEI_MASK (0x1FU) +#define DMA_SEEI_SEEI_SHIFT (0U) +/*! SEEI - Set Enable Error Interrupt + */ +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ + +/*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ +#define DMA_CERQ_CERQ_MASK (0x1FU) +#define DMA_CERQ_CERQ_SHIFT (0U) +/*! CERQ - Clear Enable Request + */ +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ + +/*! @name SERQ - Set Enable Request Register */ +/*! @{ */ +#define DMA_SERQ_SERQ_MASK (0x1FU) +#define DMA_SERQ_SERQ_SHIFT (0U) +/*! SERQ - Set Enable Request + */ +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ + +/*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ +#define DMA_CDNE_CDNE_MASK (0x1FU) +#define DMA_CDNE_CDNE_SHIFT (0U) +/*! CDNE - Clear DONE Bit + */ +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ + +/*! @name SSRT - Set START Bit Register */ +/*! @{ */ +#define DMA_SSRT_SSRT_MASK (0x1FU) +#define DMA_SSRT_SSRT_SHIFT (0U) +/*! SSRT - Set START Bit + */ +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ + +/*! @name CERR - Clear Error Register */ +/*! @{ */ +#define DMA_CERR_CERR_MASK (0x1FU) +#define DMA_CERR_CERR_SHIFT (0U) +/*! CERR - Clear Error Indicator + */ +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ + +/*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ +#define DMA_CINT_CINT_MASK (0x1FU) +#define DMA_CINT_CINT_SHIFT (0U) +/*! CINT - Clear Interrupt Request + */ +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ + +/*! @name INT - Interrupt Request Register */ +/*! @{ */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) +#define DMA_INT_INT16_MASK (0x10000U) +#define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) +#define DMA_INT_INT17_MASK (0x20000U) +#define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) +#define DMA_INT_INT18_MASK (0x40000U) +#define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) +#define DMA_INT_INT19_MASK (0x80000U) +#define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) +#define DMA_INT_INT20_MASK (0x100000U) +#define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) +#define DMA_INT_INT21_MASK (0x200000U) +#define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) +#define DMA_INT_INT22_MASK (0x400000U) +#define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) +#define DMA_INT_INT23_MASK (0x800000U) +#define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) +#define DMA_INT_INT24_MASK (0x1000000U) +#define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) +#define DMA_INT_INT25_MASK (0x2000000U) +#define DMA_INT_INT25_SHIFT (25U) +/*! INT25 - Interrupt Request 25 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) +#define DMA_INT_INT26_MASK (0x4000000U) +#define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) +#define DMA_INT_INT27_MASK (0x8000000U) +#define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) +#define DMA_INT_INT28_MASK (0x10000000U) +#define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) +#define DMA_INT_INT29_MASK (0x20000000U) +#define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) +#define DMA_INT_INT30_MASK (0x40000000U) +#define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) +#define DMA_INT_INT31_MASK (0x80000000U) +#define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ + +/*! @name ERR - Error Register */ +/*! @{ */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) +#define DMA_ERR_ERR16_MASK (0x10000U) +#define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) +#define DMA_ERR_ERR17_MASK (0x20000U) +#define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) +#define DMA_ERR_ERR18_MASK (0x40000U) +#define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) +#define DMA_ERR_ERR19_MASK (0x80000U) +#define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) +#define DMA_ERR_ERR20_MASK (0x100000U) +#define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) +#define DMA_ERR_ERR21_MASK (0x200000U) +#define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) +#define DMA_ERR_ERR22_MASK (0x400000U) +#define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) +#define DMA_ERR_ERR23_MASK (0x800000U) +#define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) +#define DMA_ERR_ERR24_MASK (0x1000000U) +#define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) +#define DMA_ERR_ERR25_MASK (0x2000000U) +#define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) +#define DMA_ERR_ERR26_MASK (0x4000000U) +#define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) +#define DMA_ERR_ERR27_MASK (0x8000000U) +#define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) +#define DMA_ERR_ERR28_MASK (0x10000000U) +#define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) +#define DMA_ERR_ERR29_MASK (0x20000000U) +#define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) +#define DMA_ERR_ERR30_MASK (0x40000000U) +#define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) +#define DMA_ERR_ERR31_MASK (0x80000000U) +#define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ + +/*! @name HRS - Hardware Request Status Register */ +/*! @{ */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) +#define DMA_HRS_HRS16_MASK (0x10000U) +#define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ +#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) +#define DMA_HRS_HRS17_MASK (0x20000U) +#define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ +#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) +#define DMA_HRS_HRS18_MASK (0x40000U) +#define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ +#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) +#define DMA_HRS_HRS19_MASK (0x80000U) +#define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present + */ +#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) +#define DMA_HRS_HRS20_MASK (0x100000U) +#define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present + */ +#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) +#define DMA_HRS_HRS21_MASK (0x200000U) +#define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present + */ +#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) +#define DMA_HRS_HRS22_MASK (0x400000U) +#define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present + */ +#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) +#define DMA_HRS_HRS23_MASK (0x800000U) +#define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present + */ +#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) +#define DMA_HRS_HRS24_MASK (0x1000000U) +#define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present + */ +#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) +#define DMA_HRS_HRS25_MASK (0x2000000U) +#define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ +#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) +#define DMA_HRS_HRS26_MASK (0x4000000U) +#define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ +#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) +#define DMA_HRS_HRS27_MASK (0x8000000U) +#define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ +#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) +#define DMA_HRS_HRS28_MASK (0x10000000U) +#define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ +#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) +#define DMA_HRS_HRS29_MASK (0x20000000U) +#define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ +#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) +#define DMA_HRS_HRS30_MASK (0x40000000U) +#define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ +#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) +#define DMA_HRS_HRS31_MASK (0x80000000U) +#define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ +#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ + +/*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0. + * 0b1..Enable asynchronous DMA request for channel 0. + */ +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1. + */ +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2. + * 0b1..Enable asynchronous DMA request for channel 2. + */ +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3. + * 0b1..Enable asynchronous DMA request for channel 3. + */ +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 + * 0b0..Disable asynchronous DMA request for channel 4. + * 0b1..Enable asynchronous DMA request for channel 4. + */ +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 + * 0b0..Disable asynchronous DMA request for channel 5. + * 0b1..Enable asynchronous DMA request for channel 5. + */ +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 + * 0b0..Disable asynchronous DMA request for channel 6. + * 0b1..Enable asynchronous DMA request for channel 6. + */ +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 + * 0b0..Disable asynchronous DMA request for channel 7. + * 0b1..Enable asynchronous DMA request for channel 7. + */ +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 + * 0b0..Disable asynchronous DMA request for channel 8. + * 0b1..Enable asynchronous DMA request for channel 8. + */ +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 + * 0b0..Disable asynchronous DMA request for channel 9. + * 0b1..Enable asynchronous DMA request for channel 9. + */ +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 + * 0b0..Disable asynchronous DMA request for channel 10. + * 0b1..Enable asynchronous DMA request for channel 10. + */ +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 + * 0b0..Disable asynchronous DMA request for channel 11. + * 0b1..Enable asynchronous DMA request for channel 11. + */ +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 + * 0b0..Disable asynchronous DMA request for channel 12. + * 0b1..Enable asynchronous DMA request for channel 12. + */ +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 + * 0b0..Disable asynchronous DMA request for channel 13. + * 0b1..Enable asynchronous DMA request for channel 13. + */ +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 + * 0b0..Disable asynchronous DMA request for channel 14. + * 0b1..Enable asynchronous DMA request for channel 14. + */ +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 + * 0b0..Disable asynchronous DMA request for channel 15. + * 0b1..Enable asynchronous DMA request for channel 15. + */ +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) +#define DMA_EARS_EDREQ_16_MASK (0x10000U) +#define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ +#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) +#define DMA_EARS_EDREQ_17_MASK (0x20000U) +#define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ +#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) +#define DMA_EARS_EDREQ_18_MASK (0x40000U) +#define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ +#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) +#define DMA_EARS_EDREQ_19_MASK (0x80000U) +#define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ +#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) +#define DMA_EARS_EDREQ_20_MASK (0x100000U) +#define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ +#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) +#define DMA_EARS_EDREQ_21_MASK (0x200000U) +#define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ +#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) +#define DMA_EARS_EDREQ_22_MASK (0x400000U) +#define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ +#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) +#define DMA_EARS_EDREQ_23_MASK (0x800000U) +#define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ +#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) +#define DMA_EARS_EDREQ_24_MASK (0x1000000U) +#define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ +#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) +#define DMA_EARS_EDREQ_25_MASK (0x2000000U) +#define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ +#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) +#define DMA_EARS_EDREQ_26_MASK (0x4000000U) +#define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ +#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) +#define DMA_EARS_EDREQ_27_MASK (0x8000000U) +#define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ +#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) +#define DMA_EARS_EDREQ_28_MASK (0x10000000U) +#define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ +#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) +#define DMA_EARS_EDREQ_29_MASK (0x20000000U) +#define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ +#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) +#define DMA_EARS_EDREQ_30_MASK (0x40000000U) +#define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ +#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) +#define DMA_EARS_EDREQ_31_MASK (0x80000000U) +#define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ +#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ + +/*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI19_CHPRI_MASK (0xFU) +#define DMA_DCHPRI19_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) +#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) +#define DMA_DCHPRI19_DPA_MASK (0x40U) +#define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) +#define DMA_DCHPRI19_ECP_MASK (0x80U) +#define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI18_CHPRI_MASK (0xFU) +#define DMA_DCHPRI18_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) +#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) +#define DMA_DCHPRI18_DPA_MASK (0x40U) +#define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) +#define DMA_DCHPRI18_ECP_MASK (0x80U) +#define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI17_CHPRI_MASK (0xFU) +#define DMA_DCHPRI17_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) +#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) +#define DMA_DCHPRI17_DPA_MASK (0x40U) +#define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) +#define DMA_DCHPRI17_ECP_MASK (0x80U) +#define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI16_CHPRI_MASK (0xFU) +#define DMA_DCHPRI16_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) +#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) +#define DMA_DCHPRI16_DPA_MASK (0x40U) +#define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) +#define DMA_DCHPRI16_ECP_MASK (0x80U) +#define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI23_CHPRI_MASK (0xFU) +#define DMA_DCHPRI23_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) +#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) +#define DMA_DCHPRI23_DPA_MASK (0x40U) +#define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) +#define DMA_DCHPRI23_ECP_MASK (0x80U) +#define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI22_CHPRI_MASK (0xFU) +#define DMA_DCHPRI22_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) +#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) +#define DMA_DCHPRI22_DPA_MASK (0x40U) +#define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) +#define DMA_DCHPRI22_ECP_MASK (0x80U) +#define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI21_CHPRI_MASK (0xFU) +#define DMA_DCHPRI21_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) +#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) +#define DMA_DCHPRI21_DPA_MASK (0x40U) +#define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) +#define DMA_DCHPRI21_ECP_MASK (0x80U) +#define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI20_CHPRI_MASK (0xFU) +#define DMA_DCHPRI20_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) +#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) +#define DMA_DCHPRI20_DPA_MASK (0x40U) +#define DMA_DCHPRI20_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) +#define DMA_DCHPRI20_ECP_MASK (0x80U) +#define DMA_DCHPRI20_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI27_CHPRI_MASK (0xFU) +#define DMA_DCHPRI27_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) +#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) +#define DMA_DCHPRI27_DPA_MASK (0x40U) +#define DMA_DCHPRI27_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) +#define DMA_DCHPRI27_ECP_MASK (0x80U) +#define DMA_DCHPRI27_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI26_CHPRI_MASK (0xFU) +#define DMA_DCHPRI26_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) +#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) +#define DMA_DCHPRI26_DPA_MASK (0x40U) +#define DMA_DCHPRI26_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) +#define DMA_DCHPRI26_ECP_MASK (0x80U) +#define DMA_DCHPRI26_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI25_CHPRI_MASK (0xFU) +#define DMA_DCHPRI25_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) +#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) +#define DMA_DCHPRI25_DPA_MASK (0x40U) +#define DMA_DCHPRI25_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) +#define DMA_DCHPRI25_ECP_MASK (0x80U) +#define DMA_DCHPRI25_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI24_CHPRI_MASK (0xFU) +#define DMA_DCHPRI24_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) +#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) +#define DMA_DCHPRI24_DPA_MASK (0x40U) +#define DMA_DCHPRI24_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) +#define DMA_DCHPRI24_ECP_MASK (0x80U) +#define DMA_DCHPRI24_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI31_CHPRI_MASK (0xFU) +#define DMA_DCHPRI31_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) +#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) +#define DMA_DCHPRI31_DPA_MASK (0x40U) +#define DMA_DCHPRI31_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) +#define DMA_DCHPRI31_ECP_MASK (0x80U) +#define DMA_DCHPRI31_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI30_CHPRI_MASK (0xFU) +#define DMA_DCHPRI30_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) +#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) +#define DMA_DCHPRI30_DPA_MASK (0x40U) +#define DMA_DCHPRI30_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) +#define DMA_DCHPRI30_ECP_MASK (0x80U) +#define DMA_DCHPRI30_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI29_CHPRI_MASK (0xFU) +#define DMA_DCHPRI29_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) +#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) +#define DMA_DCHPRI29_DPA_MASK (0x40U) +#define DMA_DCHPRI29_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) +#define DMA_DCHPRI29_ECP_MASK (0x80U) +#define DMA_DCHPRI29_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI28_CHPRI_MASK (0xFU) +#define DMA_DCHPRI28_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) +#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) +#define DMA_DCHPRI28_DPA_MASK (0x40U) +#define DMA_DCHPRI28_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) +#define DMA_DCHPRI28_ECP_MASK (0x80U) +#define DMA_DCHPRI28_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ + +/*! @name SADDR - TCD Source Address */ +/*! @{ */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address + */ +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (32U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source address signed offset + */ +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (32U) + +/*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination data transfer size + */ +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo + */ +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF + * calculation is performed on the original register value. Setting this field provides the ability + * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the + * queue should start at a 0-modulo-size address and the SMOD field should be set to the + * appropriate value for the queue, freezing the desired number of upper address bits. The value + * programmed into this field specifies the number of lower address bits allowed to change. For a + * circular queue application, the SOFF is typically set to the transfer size to implement + * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + */ +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (32U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +/*! NBYTES - Minor Byte Transfer Count + */ +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (32U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Minor Byte Transfer Count + */ +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (32U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Minor Byte Transfer Count + */ +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the + * source or destination address to form the next-state value after the minor loop completes. + */ +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (32U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +/*! SLAST - Last Source Address Adjustment + */ +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (32U) + +/*! @name DADDR - TCD Destination Address */ +/*! @{ */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address + */ +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (32U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset + */ +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (32U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count + */ +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (32U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count + */ +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number + */ +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (32U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +/*! DLASTSGA - DLASTSGA + */ +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (32U) + +/*! @name CSR - TCD Control and Status */ +/*! @{ */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer + * to the next TCD to be loaded into this channel after the major loop completes its execution. + */ +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +/*! ACTIVE - Channel Active + */ +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +/*! DONE - Channel Done + */ +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number + */ +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls. + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W. + * 0b11..eDMA engine stalls for 8 cycles after each R/W. + */ +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (32U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count + */ +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (32U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting major iteration count + */ +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number + */ +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (32U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x400E8000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } +#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +/*! SOURCE - DMA Channel Source (Slot Number) + */ +#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) +#define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled + */ +#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) +#define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the + * specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + */ +#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) +#define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled + */ +#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (32U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x400EC000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer + * @{ + */ + +/** ENC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ + __IO uint16_t TST; /**< Test Register, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ +} ENC_Type; + +/* ---------------------------------------------------------------------------- + -- ENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Register_Masks ENC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define ENC_CTRL_CMPIE_MASK (0x1U) +#define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Compare interrupt is disabled + * 0b1..Compare interrupt is enabled + */ +#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) +#define ENC_CTRL_CMPIRQ_MASK (0x2U) +#define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL_WDE_MASK (0x4U) +#define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Watchdog timer is disabled + * 0b1..Watchdog timer is enabled + */ +#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) +#define ENC_CTRL_DIE_MASK (0x8U) +#define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Watchdog timer interrupt is disabled + * 0b1..Watchdog timer interrupt is enabled + */ +#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) +#define ENC_CTRL_DIRQ_MASK (0x10U) +#define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) +#define ENC_CTRL_XNE_MASK (0x20U) +#define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive transition edge of INDEX pulse + * 0b1..Use negative transition edge of INDEX pulse + */ +#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) +#define ENC_CTRL_XIP_MASK (0x40U) +#define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..INDEX pulse initializes the position counter + */ +#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) +#define ENC_CTRL_XIE_MASK (0x80U) +#define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..INDEX pulse interrupt is disabled + * 0b1..INDEX pulse interrupt is enabled + */ +#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) +#define ENC_CTRL_XIRQ_MASK (0x100U) +#define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..INDEX pulse interrupt has occurred + */ +#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) +#define ENC_CTRL_PH1_MASK (0x200U) +#define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The + * PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If + * CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, + * PHASEB = 1, then count up + */ +#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) +#define ENC_CTRL_REV_MASK (0x400U) +#define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ +#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) +#define ENC_CTRL_SWIP_MASK (0x800U) +#define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) +#define ENC_CTRL_HNE_MASK (0x1000U) +#define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) +#define ENC_CTRL_HIP_MASK (0x2000U) +#define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) +#define ENC_CTRL_HIE_MASK (0x4000U) +#define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable HOME interrupts + * 0b1..Enable HOME interrupts + */ +#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) +#define ENC_CTRL_HIRQ_MASK (0x8000U) +#define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No interrupt + * 0b1..HOME signal transition interrupt request + */ +#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ +#define ENC_FILT_FILT_PER_MASK (0xFFU) +#define ENC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period + */ +#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) +#define ENC_FILT_FILT_CNT_MASK (0x700U) +#define ENC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count + */ +#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ +#define ENC_WTR_WDOG_MASK (0xFFFFU) +#define ENC_WTR_WDOG_SHIFT (0U) +#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ +#define ENC_POSD_POSD_MASK (0xFFFFU) +#define ENC_POSD_POSD_SHIFT (0U) +#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ +#define ENC_POSDH_POSDH_MASK (0xFFFFU) +#define ENC_POSDH_POSDH_SHIFT (0U) +#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ +#define ENC_REV_REV_MASK (0xFFFFU) +#define ENC_REV_REV_SHIFT (0U) +#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ +#define ENC_REVH_REVH_MASK (0xFFFFU) +#define ENC_REVH_REVH_SHIFT (0U) +#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ +#define ENC_UPOS_POS_MASK (0xFFFFU) +#define ENC_UPOS_POS_SHIFT (0U) +#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ +#define ENC_LPOS_POS_MASK (0xFFFFU) +#define ENC_LPOS_POS_SHIFT (0U) +#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ +#define ENC_UPOSH_POSH_MASK (0xFFFFU) +#define ENC_UPOSH_POSH_SHIFT (0U) +#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ +#define ENC_LPOSH_POSH_MASK (0xFFFFU) +#define ENC_LPOSH_POSH_SHIFT (0U) +#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ +#define ENC_UINIT_INIT_MASK (0xFFFFU) +#define ENC_UINIT_INIT_SHIFT (0U) +#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ +#define ENC_LINIT_INIT_MASK (0xFFFFU) +#define ENC_LINIT_INIT_SHIFT (0U) +#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ +#define ENC_IMR_HOME_MASK (0x1U) +#define ENC_IMR_HOME_SHIFT (0U) +#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) +#define ENC_IMR_INDEX_MASK (0x2U) +#define ENC_IMR_INDEX_SHIFT (1U) +#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) +#define ENC_IMR_PHB_MASK (0x4U) +#define ENC_IMR_PHB_SHIFT (2U) +#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) +#define ENC_IMR_PHA_MASK (0x8U) +#define ENC_IMR_PHA_SHIFT (3U) +#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) +#define ENC_IMR_FHOM_MASK (0x10U) +#define ENC_IMR_FHOM_SHIFT (4U) +#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) +#define ENC_IMR_FIND_MASK (0x20U) +#define ENC_IMR_FIND_SHIFT (5U) +#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) +#define ENC_IMR_FPHB_MASK (0x40U) +#define ENC_IMR_FPHB_SHIFT (6U) +#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) +#define ENC_IMR_FPHA_MASK (0x80U) +#define ENC_IMR_FPHA_SHIFT (7U) +#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ +#define ENC_TST_TEST_COUNT_MASK (0xFFU) +#define ENC_TST_TEST_COUNT_SHIFT (0U) +#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) +#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) +#define ENC_TST_TEST_PERIOD_SHIFT (8U) +#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) +#define ENC_TST_QDN_MASK (0x2000U) +#define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Leaves quadrature decoder signal in a positive direction + * 0b1..Generates a negative quadrature decoder signal + */ +#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) +#define ENC_TST_TCE_MASK (0x4000U) +#define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Test count is not enabled + * 0b1..Test count is enabled + */ +#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) +#define ENC_TST_TEN_MASK (0x8000U) +#define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Test module is not enabled + * 0b1..Test module is enabled + */ +#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define ENC_CTRL2_UPDHLD_MASK (0x1U) +#define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on rising edge of TRIGGER + * 0b1..Enable updates of hold registers on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) +#define ENC_CTRL2_UPDPOS_MASK (0x2U) +#define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) +#define ENC_CTRL2_MOD_MASK (0x4U) +#define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ +#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) +#define ENC_CTRL2_DIR_MASK (0x8U) +#define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ +#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) +#define ENC_CTRL2_RUIE_MASK (0x10U) +#define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Roll-under interrupt is disabled + * 0b1..Roll-under interrupt is enabled + */ +#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) +#define ENC_CTRL2_RUIRQ_MASK (0x20U) +#define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) +#define ENC_CTRL2_ROIE_MASK (0x40U) +#define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Roll-over interrupt is disabled + * 0b1..Roll-over interrupt is enabled + */ +#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) +#define ENC_CTRL2_ROIRQ_MASK (0x80U) +#define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) +#define ENC_CTRL2_REVMOD_MASK (0x100U) +#define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + */ +#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) +#define ENC_CTRL2_OUTCTL_MASK (0x200U) +#define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + */ +#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) +#define ENC_CTRL2_SABIE_MASK (0x400U) +#define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. + * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled. + */ +#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) +#define ENC_CTRL2_SABIRQ_MASK (0x800U) +#define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred. + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred. + */ +#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ +#define ENC_UMOD_MOD_MASK (0xFFFFU) +#define ENC_UMOD_MOD_SHIFT (0U) +#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ +#define ENC_LMOD_MOD_MASK (0xFFFFU) +#define ENC_LMOD_MOD_SHIFT (0U) +#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ +#define ENC_UCOMP_COMP_MASK (0xFFFFU) +#define ENC_UCOMP_COMP_SHIFT (0U) +#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ +#define ENC_LCOMP_COMP_MASK (0xFFFFU) +#define ENC_LCOMP_COMP_SHIFT (0U) +#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ENC_Register_Masks */ + + +/* ENC - Peripheral instance base addresses */ +/** Peripheral ENC1 base address */ +#define ENC1_BASE (0x403C8000u) +/** Peripheral ENC1 base pointer */ +#define ENC1 ((ENC_Type *)ENC1_BASE) +/** Peripheral ENC2 base address */ +#define ENC2_BASE (0x403CC000u) +/** Peripheral ENC2 base pointer */ +#define ENC2 ((ENC_Type *)ENC2_BASE) +/** Peripheral ENC3 base address */ +#define ENC3_BASE (0x403D0000u) +/** Peripheral ENC3 base pointer */ +#define ENC3 ((ENC_Type *)ENC3_BASE) +/** Peripheral ENC4 base address */ +#define ENC4_BASE (0x403D4000u) +/** Peripheral ENC4 base pointer */ +#define ENC4 ((ENC_Type *)ENC4_BASE) +/** Array initializer of ENC peripheral base addresses */ +#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE } +/** Array initializer of ENC peripheral base pointers */ +#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 } +/** Interrupt vectors for the ENC peripheral type */ +#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } + +/*! + * @} + */ /* end of group ENC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - Timestamp Timer + */ +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - Transmit Timestamp Available + */ +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +/*! WAKEUP - Node Wakeup Request Indication + */ +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +/*! PLR - Payload Receive Error + */ +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +/*! UN - Transmit FIFO Underrun + */ +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +/*! RL - Collision Retry Limit + */ +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +/*! LC - Late Collision + */ +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +/*! EBERR - Ethernet Bus Error + */ +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +/*! MII - MII Interrupt. + */ +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +/*! RXB - Receive Buffer Interrupt + */ +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +/*! RXF - Receive Frame Interrupt + */ +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +/*! TXB - Transmit Buffer Interrupt + */ +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +/*! TXF - Transmit Frame Interrupt + */ +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +/*! GRA - Graceful Stop Complete + */ +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +/*! BABT - Babbling Transmit Error + */ +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +/*! BABR - Babbling Receive Error + */ +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - TS_TIMER Interrupt Mask + */ +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - TS_AVAIL Interrupt Mask + */ +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +/*! WAKEUP - WAKEUP Interrupt Mask + */ +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +/*! PLR - PLR Interrupt Mask + */ +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +/*! UN - UN Interrupt Mask + */ +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +/*! RL - RL Interrupt Mask + */ +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +/*! LC - LC Interrupt Mask + */ +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +/*! EBERR - EBERR Interrupt Mask + */ +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +/*! MII - MII Interrupt Mask + */ +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +/*! RXB - RXB Interrupt Mask + */ +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +/*! RXF - RXF Interrupt Mask + */ +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active + */ +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active + */ +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +/*! RESET - Ethernet MAC Reset + */ +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +/*! DATA - Management Frame Data + */ +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +/*! TA - Turn Around + */ +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +/*! RA - Register Address + */ +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +/*! PA - PHY Address + */ +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +/*! OP - Operation Code + */ +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +/*! ST - Start Of Frame Delimiter + */ +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +/*! MII_SPEED - MII Speed + */ +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +/*! BC_REJ - Broadcast Frame Reject + */ +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +/*! FCE - Flow Control Enable + */ +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s operation. + * 0b1..10-Mbit/s operation. + */ +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +/*! MAX_FL - Maximum Frame Length + */ +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +/*! GRS - Graceful Receive Stopped + */ +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +/*! GTS - Graceful Transmit Stop + */ +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +/*! FDEN - Full-Duplex Enable + */ +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +/*! RFC_PAUSE - Receive Frame Control Pause + */ +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +/*! PADDR1 - Pause Address + */ +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +/*! TYPE - Type Field In PAUSE Frames + */ +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +/*! PAUSE_DUR - Pause Duration + */ +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +/*! OPCODE - Opcode Field In PAUSE Frames + */ +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold + */ +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold + */ +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold + */ +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold + */ +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b011111..1984 bytes written. + */ +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold + */ +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold + */ +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold + */ +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold + */ +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold + */ +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold + */ +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold + */ +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold + */ +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +/*! IPG - Transmit Inter-Packet Gap + */ +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +/*! TRUNC_FL - Frame Truncation Length + */ +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the + * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This + * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is + * extended to a 16-byte header. + */ +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must + * be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the + * frame. The checksum field must be cleared. The other frames are not modified. + */ +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no + * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in + * store and forward mode (RSFL cleared). + */ +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame + * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL + * cleared). + */ +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +/*! TXPKTS - Packet count + */ +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Broadcast packets + */ +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Multicast packets + */ +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +/*! TXPKTS - Packets with CRC/align error + */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC + */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC + */ +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of packets less than 64 bytes with bad CRC + */ +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC + */ +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit collisions + */ +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 64-byte transmit packets + */ +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 65- to 127-byte transmit packets + */ +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 128- to 255-byte transmit packets + */ +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 256- to 511-byte transmit packets + */ +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 512- to 1023-byte transmit packets + */ +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 1024- to 2047-byte transmit packets + */ +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than 2048 bytes + */ +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +/*! TXOCTS - Number of transmit octets + */ +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted OK + */ +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with one collision + */ +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with multiple collisions + */ +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with deferral delay + */ +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with late collision + */ +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with excessive collisions + */ +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with transmit FIFO underrun + */ +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with carrier sense error + */ +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames transmitted + */ +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + */ +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +/*! COUNT - Number of packets received + */ +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive broadcast packets + */ +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive multicast packets + */ +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with CRC or align error + */ +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and good CRC + */ +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and good CRC + */ +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC + */ +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC + */ +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +/*! COUNT - Number of 64-byte receive packets + */ +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +/*! COUNT - Number of 65- to 127-byte recieve packets + */ +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +/*! COUNT - Number of 128- to 255-byte recieve packets + */ +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +/*! COUNT - Number of 256- to 511-byte recieve packets + */ +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +/*! COUNT - Number of 512- to 1023-byte recieve packets + */ +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +/*! COUNT - Number of 1024- to 2047-byte recieve packets + */ +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +/*! COUNT - Number of greater-than-2048-byte recieve packets + */ +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +/*! COUNT - Number of receive octets + */ +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +/*! COUNT - Frame count + */ +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received OK + */ +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with CRC error + */ +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with alignment error + */ +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Receive FIFO overflow count + */ +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames received + */ +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of octets for frames received without error + */ +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared + * when the offset event is reached, so no further event occurs until the field is set again. The timer + * offset value must be set before setting this field. + */ +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when + * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before + * setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +/*! RESTART - Reset Timer + */ +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except + * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +/*! COR - Correction Counter Wrap-Around Value + */ +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + */ +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +/*! INC_CORR - Correction Increment Value + */ +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + */ +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +/*! TPWC - Timer PulseWidth Control + * 0b00000..Pulse width is one 1588-clock cycle. + * 0b00001..Pulse width is two 1588-clock cycles. + * 0b00010..Pulse width is three 1588-clock cycles. + * 0b00011..Pulse width is four 1588-clock cycles. + * 0b11111..Pulse width is 32 1588-clock cycles. + */ +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +/*! TCC - Timer Capture Compare + */ +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x402D8000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn } +#define ENET_Error_IRQS { ENET_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +/*! EWMEN - EWM enable. + */ +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +/*! ASSIN - EWM_in's Assertion State Select. + */ +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +/*! INEN - Input Enable. + */ +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +/*! INTEN - Interrupt Enable. + */ +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service Register */ +/*! @{ */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +/*! SERVICE - SERVICE + */ +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low Register */ +/*! @{ */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +/*! COMPAREL - COMPAREL + */ +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High Register */ +/*! @{ */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +/*! COMPAREH - COMPAREH + */ +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +/*! CLKSEL - CLKSEL + */ +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +/*! CLK_DIV - CLK_DIV + */ +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x400B4000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_5[240]; + __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_12[368]; + __IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_14[112]; + __IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number + */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number + */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number + */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number + */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FlexIO Control Register */ +/*! @{ */ +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State Register */ +/*! @{ */ +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input + */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flags + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flags + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable + */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable + */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable + */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable + */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer + */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select + */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select + */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (4U) + +/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width + */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (4U) + +/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer + */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (4U) + +/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer + */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (4U) + +/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer + */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (4U) + +/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer + */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (4U) + +/*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b00..Timer Disabled. + * 0b01..Dual 8-bit counters baud mode. + * 0b10..Dual 8-bit counters PWM high mode. + * 0b11..Single 16-bit counter mode. + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select + */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select + */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (4U) + +/*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer reset + * 0b01..Timer output is logic zero when enabled and is not affected by timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (4U) + +/*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value + */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (4U) + +/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer + */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (4U) + +/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer + */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (4U) + +/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer + */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (4U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x401AC000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Peripheral FLEXIO2 base address */ +#define FLEXIO2_BASE (0x401B0000u) +/** Peripheral FLEXIO2 base pointer */ +#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer + * @{ + */ + +/** FLEXRAM - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ + __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ +} FLEXRAM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks + * @{ + */ + +/*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable + * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable + * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) +/*! FORCE_CLK_ON - Force RAM Clock Always On + */ +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +/*! ITCM_ERR_STATUS - ITCM Access Error Status + * 0b0..ITCM access error does not happen + * 0b1..ITCM access error happens. + */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +/*! DTCM_ERR_STATUS - DTCM Access Error Status + * 0b0..DTCM access error does not happen + * 0b1..DTCM access error happens. + */ +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +/*! OCRAM_ERR_STATUS - OCRAM Access Error Status + * 0b0..OCRAM access error does not happen + * 0b1..OCRAM access error happens. + */ +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) +/*! @} */ + +/*! @name INT_STAT_EN - Interrupt Status Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXRAM_Register_Masks */ + + +/* FLEXRAM - Peripheral instance base addresses */ +/** Peripheral FLEXRAM base address */ +#define FLEXRAM_BASE (0x400B0000u) +/** Peripheral FLEXRAM base pointer */ +#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) +/** Array initializer of FLEXRAM peripheral base addresses */ +#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } +/** Array initializer of FLEXRAM peripheral base pointers */ +#define FLEXRAM_BASE_PTRS { FLEXRAM } +/** Interrupt vectors for the FLEXRAM peripheral type */ +#define FLEXRAM_IRQS { FLEXRAM_IRQn } + +/*! + * @} + */ /* end of group FLEXRAM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[48]; + __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + uint8_t RESERVED_4[4]; + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_6[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +/*! SWRESET - Software Reset + */ +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + */ +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..Reserved + * 0b11..Flash provided Read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. + * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + */ +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. + * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + */ +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, + * external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is + * enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +/*! IPGRANTWAIT - Time out wait cycle for IP command grant. + */ +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. + */ +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned + * automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or + * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP + * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is + * written with 0x1. This bit will be auto-cleared immediately. + */ +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash + * A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, + * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be + * ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). + * In this case, port B flash access is not available. After change the value of this feild, + * MCR0[SWRESET] should be set. + * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. + */ +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. + */ +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat + * of AHB write access, refer for more details about AHB bufferable write. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus + * ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is + * granted by arbitrator and will not wait for AHB command finished. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +/*! PREFETCHEN - AHB Read Prefetch Enable. + */ +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB + * burst required to meet the alignment requirement. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. + */ +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. + */ +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. + */ +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. + */ +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +/*! SCKSTOPBYRDEN - SCK is stopped during command sequence because Async RX FIFO full interrupt enable. + */ +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +/*! SCKSTOPBYWREN - SCK is stopped during command sequence because Async TX FIFO empty interrupt enable. + */ +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + */ +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. + */ +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Register */ +/*! @{ */ +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also + * generated when there is IPCMDGE or IPCMDERR interrupt generated. + */ +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. + */ +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. + */ +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for + * IP command, this command will be ignored and not executed at all. + */ +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for + * AHB command, this command will be ignored and not executed at all. + */ +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +/*! IPRXWA - IP RX FIFO watermark available interrupt. + */ +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +/*! IPTXWE - IP TX FIFO watermark empty interrupt. + */ +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +/*! SCKSTOPBYRD - SCK is stopped during command sequence because Async RX FIFO full interrupt. + */ +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +/*! SCKSTOPBYWR - SCK is stopped during command sequence because Async TX FIFO empty interrupt. + */ +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + */ +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +/*! SEQTIMEOUT - Sequence execution timeout interrupt. + */ +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +/*! KEY - The Key to lock or unlock LUT. + */ +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control Register */ +/*! @{ */ +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +/*! LOCK - Lock LUT + */ +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +/*! UNLOCK - Unlock LUT + */ +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +/*! BUFSZ - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + */ +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + */ +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + */ +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) + +/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +/*! FLSHSZ - Flash Size in KByte. + */ +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +/*! TCSS - Serial Flash CS setup time. + */ +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +/*! TCSH - Serial Flash CS Hold time. + */ +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +/*! WA - Word Addressable. + */ +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +/*! CAS - Column Address Size. + */ +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection + * deassertion and flash device Chip selection assertion. If external flash has a limitation on + * the interval between command sequences, this field should be set accordingly. If there is no + * limitation, set this field with value 0x0. + */ +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. + */ +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. + */ +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +/*! AWRSEQID - Sequence Index for AHB Write triggered Command. + */ +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. + */ +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. + * Refer Programmable Sequence Engine for details. + */ +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for + * memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for + * memory device on port B, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +/*! SFAR - Serial Flash Address for IP command. + */ +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. + */ +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +/*! ISEQID - Sequence Index in LUT for IP command. + */ +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. + */ +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +/*! IPAREN - Parallel mode Enabled for IP command. + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command Register */ +/*! @{ */ +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +/*! TRG - Setting this bit will trigger an IP Command. + */ +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. + */ +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. + */ +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. + */ +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. + */ +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +/*! DLLEN - DLL calibration enable. + */ +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the + * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset + * action is edge triggered, so software need to clear this bit after set this bit (no delay + * limitation). + */ +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock). + */ +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +/*! OVRDEN - Slave clock delay line delay cell number selection override enable. + */ +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +/*! OVRDVAL - Slave clock delay line delay cell number selection override value. + */ +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status Register 0 */ +/*! @{ */ +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command + * sequence executing on FlexSPI interface. + */ +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command + * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state + * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So + * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. + */ +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted + * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ + +/*! @name STS1 - Status Register 1 */ +/*! @{ */ +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field + * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + */ +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be + * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be + * cleared when INTR[IPCMDERR] is write-1-clear(w1c). + */ +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be + * cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status Register 2 */ +/*! @{ */ +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +/*! ASLVLOCK - Flash A sample clock slave delay line locked. + */ +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +/*! AREFLOCK - Flash A sample clock reference delay line locked. + */ +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . + */ +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. + */ +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +/*! BSLVLOCK - Flash B sample clock slave delay line locked. + */ +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +/*! BREFLOCK - Flash B sample clock reference delay line locked. + */ +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. + */ +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. + */ +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. + */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +/*! BUFID - AHB RX BUF ID for suspended command sequence. + */ +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +/*! DATLFT - Left Data size for suspended command sequence (in byte). + */ +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill level of IP RX FIFO. + */ +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. + */ +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill level of IP TX FIFO. + */ +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. + */ +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +/*! RXDATA - RX Data + */ +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +/*! TXDATA - TX Data + */ +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +/*! OPERAND0 - OPERAND0 + */ +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +/*! NUM_PADS0 - NUM_PADS0 + */ +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +/*! OPCODE0 - OPCODE + */ +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +/*! OPERAND1 - OPERAND1 + */ +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +/*! NUM_PADS1 - NUM_PADS1 + */ +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +/*! OPCODE1 - OPCODE1 + */ +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI base address */ +#define FLEXSPI_BASE (0x402A8000u) +/** Peripheral FLEXSPI base pointer */ +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI_IRQn } +/* FlexSPI AMBA address. */ +#define FlexSPI_AMBA_BASE (0x60000000U) +/* FlexSPI ASFM address. */ +#define FlexSPI_ASFM_BASE (0x00000000U) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI_ARDF_BASE (0x7FC00000U) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI_ATDF_BASE (0x7F800000U) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */ + __I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +/*! @{ */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +/*! MEGA_PDN_REQ + * 0b0..No Request + * 0b1..Request power down sequence + */ +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +/*! MEGA_PUP_REQ + * 0b0..No Request + * 0b1..Request power up sequence + */ +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) +#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +/*! PDRAM0_PGE + * 0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down. + * 0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down. + */ +#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + +/*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ +#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) +#define GPC_IMR5_IMR5_SHIFT (0U) +#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ + +/*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ +#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR5_ISR4_SHIFT (0U) +#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x400F4000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +/*! DR - DR + */ +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +/*! GDIR - GDIR + */ +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +/*! PSR - PSR + */ +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 - ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 - ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 - ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 - ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 - ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 - ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 - ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 - ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 - ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 - ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 - ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 - ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 - ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 - ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 - ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 - ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 - ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 - ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 - ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 - ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 - ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 - ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 - ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 - ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 - ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 - ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 - ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 - ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 - ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 - ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 - ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 - ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +/*! IMR - IMR + */ +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +/*! ISR - ISR + */ +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +/*! GPIO_EDGE_SEL - GPIO_EDGE_SEL + */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +/*! DR_SET - DR_SET + */ +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +/*! DR_CLEAR - DR_CLEAR + */ +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +/*! DR_TOGGLE - DR_TOGGLE + */ +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x401B8000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x401BC000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x401C0000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x401C4000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x400C0000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +/*! @{ */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ + +/*! @name PR - GPT Prescaler Register */ +/*! @{ */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ + +/*! @name SR - GPT Status Register */ +/*! @{ */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ + +/*! @name IR - GPT Interrupt Register */ +/*! @{ */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +/*! @{ */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x401EC000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x401F0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ + __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[16]; + __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ + __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Datalines + */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size + */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size + */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide + */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable + */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_TCR3_CFR_MASK (0xF000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset + */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame size + */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data Register + */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (4U) + +/*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer + */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer + */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (4U) + +/*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide + */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable + */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_RCR3_CFR_MASK (0xF000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset + */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - SAI Receive Data Register */ +/*! @{ */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data Register + */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (4U) + +/*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer + */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer + */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (4U) + +/*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x40384000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x40388000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x4038C000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc + * 0b001..Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 + * 0b010..Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2 + * 0b011..Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1 + * 0b100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1 + * 0b101..Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_EMC_00 + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) + +/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b0..Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3 + * 0b1..Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0 + */ +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (154U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x401F8000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ + __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ + __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ + uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ + __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ + __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ + uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ + __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ + __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ + __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ + __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ + __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ + __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ + __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ + __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ + __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +/*! SAI1_MCLK1_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +/*! SAI1_MCLK2_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +/*! SAI1_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +/*! SAI2_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +/*! SAI3_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +/*! GINT + * 0b0..Global interrupt request is not asserted. + * 0b1..Global interrupt request is asserted. + */ +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +/*! ENET1_CLK_SEL + * 0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + * 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the + * clock for both the external PHY and the internal controller. + */ +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +/*! USB_EXP_MODE + * 0b0..Exposure mode is disabled. + * 0b1..Exposure mode is enabled. + */ +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +/*! ENET1_TX_CLK_DIR + * 0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. + * 0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. + */ +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +/*! SAI1_MCLK_DIR + * 0b0..sai1.MCLK is input signal + * 0b1..sai1.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +/*! SAI2_MCLK_DIR + * 0b0..sai2.MCLK is input signal + * 0b1..sai2.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +/*! SAI3_MCLK_DIR + * 0b0..sai3.MCLK is input signal + * 0b1..sai3.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +/*! EXC_MON + * 0b0..OKAY response + * 0b1..SLVError response + */ +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) +/*! ENET_IPG_CLK_S_EN + * 0b0..ipg_clk_s is gated when there is no IPS access + * 0b1..ipg_clk_s is always on + */ +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +/*! CM7_FORCE_HCLK_EN + * 0b0..AHB clock is not running (gated) + * 0b1..AHB clock is running (enabled) + */ +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ + +/*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +/*! L2_MEM_EN_POWERSAVING + * 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + * 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +/*! L2_MEM_DEEPSLEEP + * 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + * 0b1..force memory into deep sleep mode + */ +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + * 0b00000000..mclk frequency = 1/1 * hmclk frequency + * 0b00000001..mclk frequency = 1/2 * hmclk frequency + * 0b00000010..mclk frequency = 1/3 * hmclk frequency + * 0b00000011..mclk frequency = 1/4 * hmclk frequency + * 0b00000100..mclk frequency = 1/5 * hmclk frequency + * 0b00000101..mclk frequency = 1/6 * hmclk frequency + * 0b00000110..mclk frequency = 1/7 * hmclk frequency + * 0b00000111..mclk frequency = 1/8 * hmclk frequency + * 0b00001000..mclk frequency = 1/9 * hmclk frequency + * 0b00001001..mclk frequency = 1/10 * hmclk frequency + * 0b00001010..mclk frequency = 1/11 * hmclk frequency + * 0b00001011..mclk frequency = 1/12 * hmclk frequency + * 0b00001100..mclk frequency = 1/13 * hmclk frequency + * 0b00001101..mclk frequency = 1/14 * hmclk frequency + * 0b00001110..mclk frequency = 1/15 * hmclk frequency + * 0b00001111..mclk frequency = 1/16 * hmclk frequency + * 0b00010000..mclk frequency = 1/17 * hmclk frequency + * 0b00010001..mclk frequency = 1/18 * hmclk frequency + * 0b00010010..mclk frequency = 1/19 * hmclk frequency + * 0b00010011..mclk frequency = 1/20 * hmclk frequency + * 0b00010100..mclk frequency = 1/21 * hmclk frequency + * 0b00010101..mclk frequency = 1/22 * hmclk frequency + * 0b00010110..mclk frequency = 1/23 * hmclk frequency + * 0b00010111..mclk frequency = 1/24 * hmclk frequency + * 0b00011000..mclk frequency = 1/25 * hmclk frequency + * 0b00011001..mclk frequency = 1/26 * hmclk frequency + * 0b00011010..mclk frequency = 1/27 * hmclk frequency + * 0b00011011..mclk frequency = 1/28 * hmclk frequency + * 0b00011100..mclk frequency = 1/29 * hmclk frequency + * 0b00011101..mclk frequency = 1/30 * hmclk frequency + * 0b00011110..mclk frequency = 1/31 * hmclk frequency + * 0b00011111..mclk frequency = 1/32 * hmclk frequency + * 0b00100000..mclk frequency = 1/33 * hmclk frequency + * 0b00100001..mclk frequency = 1/34 * hmclk frequency + * 0b00100010..mclk frequency = 1/35 * hmclk frequency + * 0b00100011..mclk frequency = 1/36 * hmclk frequency + * 0b00100100..mclk frequency = 1/37 * hmclk frequency + * 0b00100101..mclk frequency = 1/38 * hmclk frequency + * 0b00100110..mclk frequency = 1/39 * hmclk frequency + * 0b00100111..mclk frequency = 1/40 * hmclk frequency + * 0b00101000..mclk frequency = 1/41 * hmclk frequency + * 0b00101001..mclk frequency = 1/42 * hmclk frequency + * 0b00101010..mclk frequency = 1/43 * hmclk frequency + * 0b00101011..mclk frequency = 1/44 * hmclk frequency + * 0b00101100..mclk frequency = 1/45 * hmclk frequency + * 0b00101101..mclk frequency = 1/46 * hmclk frequency + * 0b00101110..mclk frequency = 1/47 * hmclk frequency + * 0b00101111..mclk frequency = 1/48 * hmclk frequency + * 0b00110000..mclk frequency = 1/49 * hmclk frequency + * 0b00110001..mclk frequency = 1/50 * hmclk frequency + * 0b00110010..mclk frequency = 1/51 * hmclk frequency + * 0b00110011..mclk frequency = 1/52 * hmclk frequency + * 0b00110100..mclk frequency = 1/53 * hmclk frequency + * 0b00110101..mclk frequency = 1/54 * hmclk frequency + * 0b00110110..mclk frequency = 1/55 * hmclk frequency + * 0b00110111..mclk frequency = 1/56 * hmclk frequency + * 0b00111000..mclk frequency = 1/57 * hmclk frequency + * 0b00111001..mclk frequency = 1/58 * hmclk frequency + * 0b00111010..mclk frequency = 1/59 * hmclk frequency + * 0b00111011..mclk frequency = 1/60 * hmclk frequency + * 0b00111100..mclk frequency = 1/61 * hmclk frequency + * 0b00111101..mclk frequency = 1/62 * hmclk frequency + * 0b00111110..mclk frequency = 1/63 * hmclk frequency + * 0b00111111..mclk frequency = 1/64 * hmclk frequency + * 0b01000000..mclk frequency = 1/65 * hmclk frequency + * 0b01000001..mclk frequency = 1/66 * hmclk frequency + * 0b01000010..mclk frequency = 1/67 * hmclk frequency + * 0b01000011..mclk frequency = 1/68 * hmclk frequency + * 0b01000100..mclk frequency = 1/69 * hmclk frequency + * 0b01000101..mclk frequency = 1/70 * hmclk frequency + * 0b01000110..mclk frequency = 1/71 * hmclk frequency + * 0b01000111..mclk frequency = 1/72 * hmclk frequency + * 0b01001000..mclk frequency = 1/73 * hmclk frequency + * 0b01001001..mclk frequency = 1/74 * hmclk frequency + * 0b01001010..mclk frequency = 1/75 * hmclk frequency + * 0b01001011..mclk frequency = 1/76 * hmclk frequency + * 0b01001100..mclk frequency = 1/77 * hmclk frequency + * 0b01001101..mclk frequency = 1/78 * hmclk frequency + * 0b01001110..mclk frequency = 1/79 * hmclk frequency + * 0b01001111..mclk frequency = 1/80 * hmclk frequency + * 0b01010000..mclk frequency = 1/81 * hmclk frequency + * 0b01010001..mclk frequency = 1/82 * hmclk frequency + * 0b01010010..mclk frequency = 1/83 * hmclk frequency + * 0b01010011..mclk frequency = 1/84 * hmclk frequency + * 0b01010100..mclk frequency = 1/85 * hmclk frequency + * 0b01010101..mclk frequency = 1/86 * hmclk frequency + * 0b01010110..mclk frequency = 1/87 * hmclk frequency + * 0b01010111..mclk frequency = 1/88 * hmclk frequency + * 0b01011000..mclk frequency = 1/89 * hmclk frequency + * 0b01011001..mclk frequency = 1/90 * hmclk frequency + * 0b01011010..mclk frequency = 1/91 * hmclk frequency + * 0b01011011..mclk frequency = 1/92 * hmclk frequency + * 0b01011100..mclk frequency = 1/93 * hmclk frequency + * 0b01011101..mclk frequency = 1/94 * hmclk frequency + * 0b01011110..mclk frequency = 1/95 * hmclk frequency + * 0b01011111..mclk frequency = 1/96 * hmclk frequency + * 0b01100000..mclk frequency = 1/97 * hmclk frequency + * 0b01100001..mclk frequency = 1/98 * hmclk frequency + * 0b01100010..mclk frequency = 1/99 * hmclk frequency + * 0b01100011..mclk frequency = 1/100 * hmclk frequency + * 0b01100100..mclk frequency = 1/101 * hmclk frequency + * 0b01100101..mclk frequency = 1/102 * hmclk frequency + * 0b01100110..mclk frequency = 1/103 * hmclk frequency + * 0b01100111..mclk frequency = 1/104 * hmclk frequency + * 0b01101000..mclk frequency = 1/105 * hmclk frequency + * 0b01101001..mclk frequency = 1/106 * hmclk frequency + * 0b01101010..mclk frequency = 1/107 * hmclk frequency + * 0b01101011..mclk frequency = 1/108 * hmclk frequency + * 0b01101100..mclk frequency = 1/109 * hmclk frequency + * 0b01101101..mclk frequency = 1/110 * hmclk frequency + * 0b01101110..mclk frequency = 1/111 * hmclk frequency + * 0b01101111..mclk frequency = 1/112 * hmclk frequency + * 0b01110000..mclk frequency = 1/113 * hmclk frequency + * 0b01110001..mclk frequency = 1/114 * hmclk frequency + * 0b01110010..mclk frequency = 1/115 * hmclk frequency + * 0b01110011..mclk frequency = 1/116 * hmclk frequency + * 0b01110100..mclk frequency = 1/117 * hmclk frequency + * 0b01110101..mclk frequency = 1/118 * hmclk frequency + * 0b01110110..mclk frequency = 1/119 * hmclk frequency + * 0b01110111..mclk frequency = 1/120 * hmclk frequency + * 0b01111000..mclk frequency = 1/121 * hmclk frequency + * 0b01111001..mclk frequency = 1/122 * hmclk frequency + * 0b01111010..mclk frequency = 1/123 * hmclk frequency + * 0b01111011..mclk frequency = 1/124 * hmclk frequency + * 0b01111100..mclk frequency = 1/125 * hmclk frequency + * 0b01111101..mclk frequency = 1/126 * hmclk frequency + * 0b01111110..mclk frequency = 1/127 * hmclk frequency + * 0b01111111..mclk frequency = 1/128 * hmclk frequency + * 0b10000000..mclk frequency = 1/129 * hmclk frequency + * 0b10000001..mclk frequency = 1/130 * hmclk frequency + * 0b10000010..mclk frequency = 1/131 * hmclk frequency + * 0b10000011..mclk frequency = 1/132 * hmclk frequency + * 0b10000100..mclk frequency = 1/133 * hmclk frequency + * 0b10000101..mclk frequency = 1/134 * hmclk frequency + * 0b10000110..mclk frequency = 1/135 * hmclk frequency + * 0b10000111..mclk frequency = 1/136 * hmclk frequency + * 0b10001000..mclk frequency = 1/137 * hmclk frequency + * 0b10001001..mclk frequency = 1/138 * hmclk frequency + * 0b10001010..mclk frequency = 1/139 * hmclk frequency + * 0b10001011..mclk frequency = 1/140 * hmclk frequency + * 0b10001100..mclk frequency = 1/141 * hmclk frequency + * 0b10001101..mclk frequency = 1/142 * hmclk frequency + * 0b10001110..mclk frequency = 1/143 * hmclk frequency + * 0b10001111..mclk frequency = 1/144 * hmclk frequency + * 0b10010000..mclk frequency = 1/145 * hmclk frequency + * 0b10010001..mclk frequency = 1/146 * hmclk frequency + * 0b10010010..mclk frequency = 1/147 * hmclk frequency + * 0b10010011..mclk frequency = 1/148 * hmclk frequency + * 0b10010100..mclk frequency = 1/149 * hmclk frequency + * 0b10010101..mclk frequency = 1/150 * hmclk frequency + * 0b10010110..mclk frequency = 1/151 * hmclk frequency + * 0b10010111..mclk frequency = 1/152 * hmclk frequency + * 0b10011000..mclk frequency = 1/153 * hmclk frequency + * 0b10011001..mclk frequency = 1/154 * hmclk frequency + * 0b10011010..mclk frequency = 1/155 * hmclk frequency + * 0b10011011..mclk frequency = 1/156 * hmclk frequency + * 0b10011100..mclk frequency = 1/157 * hmclk frequency + * 0b10011101..mclk frequency = 1/158 * hmclk frequency + * 0b10011110..mclk frequency = 1/159 * hmclk frequency + * 0b10011111..mclk frequency = 1/160 * hmclk frequency + * 0b10100000..mclk frequency = 1/161 * hmclk frequency + * 0b10100001..mclk frequency = 1/162 * hmclk frequency + * 0b10100010..mclk frequency = 1/163 * hmclk frequency + * 0b10100011..mclk frequency = 1/164 * hmclk frequency + * 0b10100100..mclk frequency = 1/165 * hmclk frequency + * 0b10100101..mclk frequency = 1/166 * hmclk frequency + * 0b10100110..mclk frequency = 1/167 * hmclk frequency + * 0b10100111..mclk frequency = 1/168 * hmclk frequency + * 0b10101000..mclk frequency = 1/169 * hmclk frequency + * 0b10101001..mclk frequency = 1/170 * hmclk frequency + * 0b10101010..mclk frequency = 1/171 * hmclk frequency + * 0b10101011..mclk frequency = 1/172 * hmclk frequency + * 0b10101100..mclk frequency = 1/173 * hmclk frequency + * 0b10101101..mclk frequency = 1/174 * hmclk frequency + * 0b10101110..mclk frequency = 1/175 * hmclk frequency + * 0b10101111..mclk frequency = 1/176 * hmclk frequency + * 0b10110000..mclk frequency = 1/177 * hmclk frequency + * 0b10110001..mclk frequency = 1/178 * hmclk frequency + * 0b10110010..mclk frequency = 1/179 * hmclk frequency + * 0b10110011..mclk frequency = 1/180 * hmclk frequency + * 0b10110100..mclk frequency = 1/181 * hmclk frequency + * 0b10110101..mclk frequency = 1/182 * hmclk frequency + * 0b10110110..mclk frequency = 1/183 * hmclk frequency + * 0b10110111..mclk frequency = 1/184 * hmclk frequency + * 0b10111000..mclk frequency = 1/185 * hmclk frequency + * 0b10111001..mclk frequency = 1/186 * hmclk frequency + * 0b10111010..mclk frequency = 1/187 * hmclk frequency + * 0b10111011..mclk frequency = 1/188 * hmclk frequency + * 0b10111100..mclk frequency = 1/189 * hmclk frequency + * 0b10111101..mclk frequency = 1/190 * hmclk frequency + * 0b10111110..mclk frequency = 1/191 * hmclk frequency + * 0b10111111..mclk frequency = 1/192 * hmclk frequency + * 0b11000000..mclk frequency = 1/193 * hmclk frequency + * 0b11000001..mclk frequency = 1/194 * hmclk frequency + * 0b11000010..mclk frequency = 1/195 * hmclk frequency + * 0b11000011..mclk frequency = 1/196 * hmclk frequency + * 0b11000100..mclk frequency = 1/197 * hmclk frequency + * 0b11000101..mclk frequency = 1/198 * hmclk frequency + * 0b11000110..mclk frequency = 1/199 * hmclk frequency + * 0b11000111..mclk frequency = 1/200 * hmclk frequency + * 0b11001000..mclk frequency = 1/201 * hmclk frequency + * 0b11001001..mclk frequency = 1/202 * hmclk frequency + * 0b11001010..mclk frequency = 1/203 * hmclk frequency + * 0b11001011..mclk frequency = 1/204 * hmclk frequency + * 0b11001100..mclk frequency = 1/205 * hmclk frequency + * 0b11001101..mclk frequency = 1/206 * hmclk frequency + * 0b11001110..mclk frequency = 1/207 * hmclk frequency + * 0b11001111..mclk frequency = 1/208 * hmclk frequency + * 0b11010000..mclk frequency = 1/209 * hmclk frequency + * 0b11010001..mclk frequency = 1/210 * hmclk frequency + * 0b11010010..mclk frequency = 1/211 * hmclk frequency + * 0b11010011..mclk frequency = 1/212 * hmclk frequency + * 0b11010100..mclk frequency = 1/213 * hmclk frequency + * 0b11010101..mclk frequency = 1/214 * hmclk frequency + * 0b11010110..mclk frequency = 1/215 * hmclk frequency + * 0b11010111..mclk frequency = 1/216 * hmclk frequency + * 0b11011000..mclk frequency = 1/217 * hmclk frequency + * 0b11011001..mclk frequency = 1/218 * hmclk frequency + * 0b11011010..mclk frequency = 1/219 * hmclk frequency + * 0b11011011..mclk frequency = 1/220 * hmclk frequency + * 0b11011100..mclk frequency = 1/221 * hmclk frequency + * 0b11011101..mclk frequency = 1/222 * hmclk frequency + * 0b11011110..mclk frequency = 1/223 * hmclk frequency + * 0b11011111..mclk frequency = 1/224 * hmclk frequency + * 0b11100000..mclk frequency = 1/225 * hmclk frequency + * 0b11100001..mclk frequency = 1/226 * hmclk frequency + * 0b11100010..mclk frequency = 1/227 * hmclk frequency + * 0b11100011..mclk frequency = 1/228 * hmclk frequency + * 0b11100100..mclk frequency = 1/229 * hmclk frequency + * 0b11100101..mclk frequency = 1/230 * hmclk frequency + * 0b11100110..mclk frequency = 1/231 * hmclk frequency + * 0b11100111..mclk frequency = 1/232 * hmclk frequency + * 0b11101000..mclk frequency = 1/233 * hmclk frequency + * 0b11101001..mclk frequency = 1/234 * hmclk frequency + * 0b11101010..mclk frequency = 1/235 * hmclk frequency + * 0b11101011..mclk frequency = 1/236 * hmclk frequency + * 0b11101100..mclk frequency = 1/237 * hmclk frequency + * 0b11101101..mclk frequency = 1/238 * hmclk frequency + * 0b11101110..mclk frequency = 1/239 * hmclk frequency + * 0b11101111..mclk frequency = 1/240 * hmclk frequency + * 0b11110000..mclk frequency = 1/241 * hmclk frequency + * 0b11110001..mclk frequency = 1/242 * hmclk frequency + * 0b11110010..mclk frequency = 1/243 * hmclk frequency + * 0b11110011..mclk frequency = 1/244 * hmclk frequency + * 0b11110100..mclk frequency = 1/245 * hmclk frequency + * 0b11110101..mclk frequency = 1/246 * hmclk frequency + * 0b11110110..mclk frequency = 1/247 * hmclk frequency + * 0b11110111..mclk frequency = 1/248 * hmclk frequency + * 0b11111000..mclk frequency = 1/249 * hmclk frequency + * 0b11111001..mclk frequency = 1/250 * hmclk frequency + * 0b11111010..mclk frequency = 1/251 * hmclk frequency + * 0b11111011..mclk frequency = 1/252 * hmclk frequency + * 0b11111100..mclk frequency = 1/253 * hmclk frequency + * 0b11111101..mclk frequency = 1/254 * hmclk frequency + * 0b11111110..mclk frequency = 1/255 * hmclk frequency + * 0b11111111..mclk frequency = 1/256 * hmclk frequency + */ +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +/*! MQS_SW_RST + * 0b0..Exit software reset for MQS + * 0b1..Enable software reset for MQS + */ +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +/*! MQS_EN + * 0b0..Disable MQS + * 0b1..Enable MQS + */ +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +/*! MQS_OVERSAMPLE + * 0b0..32 + * 0b1..64 + */ +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +/*! QTIMER1_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) +/*! QTIMER2_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) +/*! QTIMER3_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) +/*! QTIMER4_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +/*! DCP_KEY_SEL + * 0b0..Select [127:0] from snvs/ocotp key as dcp key + * 0b1..Select [255:128] from snvs/ocotp key as dcp key + */ +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +/*! OCRAM_STATUS + * 0b0000..read data pipeline configuration valid + * 0b0001..read data pipeline control bit changed + */ +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +/*! @} */ + +/*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +/*! EDMA_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +/*! CAN1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +/*! CAN2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +/*! TRNG_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) +/*! ENET_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +/*! SAI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +/*! SAI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +/*! SAI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) +/*! SEMC_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +/*! PIT_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +/*! FLEXSPI_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +/*! FLEXIO1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) +/*! FLEXIO2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +/*! EDMA_STOP_ACK + * 0b0..EDMA stop acknowledge is not asserted + * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode). + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +/*! CAN1_STOP_ACK + * 0b0..CAN1 stop acknowledge is not asserted + * 0b1..CAN1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +/*! CAN2_STOP_ACK + * 0b0..CAN2 stop acknowledge is not asserted + * 0b1..CAN2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +/*! TRNG_STOP_ACK + * 0b0..TRNG stop acknowledge is not asserted + * 0b1..TRNG stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) +/*! ENET_STOP_ACK + * 0b0..ENET stop acknowledge is not asserted + * 0b1..ENET stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +/*! SAI1_STOP_ACK + * 0b0..SAI1 stop acknowledge is not asserted + * 0b1..SAI1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +/*! SAI2_STOP_ACK + * 0b0..SAI2 stop acknowledge is not asserted + * 0b1..SAI2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +/*! SAI3_STOP_ACK + * 0b0..SAI3 stop acknowledge is not asserted + * 0b1..SAI3 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) +/*! SEMC_STOP_ACK + * 0b0..SEMC stop acknowledge is not asserted + * 0b1..SEMC stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +/*! PIT_STOP_ACK + * 0b0..PIT stop acknowledge is not asserted + * 0b1..PIT stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +/*! FLEXSPI_STOP_ACK + * 0b0..FLEXSPI stop acknowledge is not asserted + * 0b1..FLEXSPI stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +/*! FLEXIO1_STOP_ACK + * 0b0..FLEXIO1 stop acknowledge is not asserted + * 0b1..FLEXIO1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) +/*! FLEXIO2_STOP_ACK + * 0b0..FLEXIO2 stop acknowledge is not asserted + * 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + */ +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +/*! GPT2_CAPIN1_SEL + * 0b0..source from pad + * 0b1..source from enet1.ipp_do_mac0_timer[3] + */ +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) +/*! ENET_EVENT3IN_SEL + * 0b0..event3 source input from pad + * 0b1..event3 source input from gpt2.ipp_do_cmpout1 + */ +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +/*! VREF_1M_CLK_GPT1 + * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +/*! VREF_1M_CLK_GPT2 + * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ + +/*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +/*! QTIMER1_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +/*! QTIMER1_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +/*! QTIMER1_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +/*! QTIMER1_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) +/*! QTIMER2_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) +/*! QTIMER2_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) +/*! QTIMER2_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) +/*! QTIMER2_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) +/*! QTIMER3_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) +/*! QTIMER3_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) +/*! QTIMER3_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) +/*! QTIMER3_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) +/*! QTIMER4_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) +/*! QTIMER4_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) +/*! QTIMER4_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) +/*! QTIMER4_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +/*! IOMUXC_XBAR_DIR_SEL_4 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +/*! IOMUXC_XBAR_DIR_SEL_5 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +/*! IOMUXC_XBAR_DIR_SEL_6 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +/*! IOMUXC_XBAR_DIR_SEL_7 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +/*! IOMUXC_XBAR_DIR_SEL_8 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +/*! IOMUXC_XBAR_DIR_SEL_9 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +/*! IOMUXC_XBAR_DIR_SEL_10 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +/*! IOMUXC_XBAR_DIR_SEL_11 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +/*! IOMUXC_XBAR_DIR_SEL_12 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +/*! IOMUXC_XBAR_DIR_SEL_13 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +/*! IOMUXC_XBAR_DIR_SEL_14 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +/*! IOMUXC_XBAR_DIR_SEL_15 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +/*! IOMUXC_XBAR_DIR_SEL_16 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +/*! IOMUXC_XBAR_DIR_SEL_17 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +/*! IOMUXC_XBAR_DIR_SEL_18 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +/*! IOMUXC_XBAR_DIR_SEL_19 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ + +/*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +/*! LPI2C1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +/*! LPI2C2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) +/*! LPI2C3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) +/*! LPI2C4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +/*! LPSPI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +/*! LPSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) +/*! LPSPI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) +/*! LPSPI4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +/*! LPUART1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +/*! LPUART2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +/*! LPUART3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +/*! LPUART4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) +/*! LPUART5_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) +/*! LPUART6_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) +/*! LPUART7_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) +/*! LPUART8_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +/*! LPI2C1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +/*! LPI2C2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) +/*! LPI2C3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) +/*! LPI2C4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +/*! LPSPI1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +/*! LPSPI2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) +/*! LPSPI3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) +/*! LPSPI4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +/*! LPUART1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +/*! LPUART2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +/*! LPUART3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +/*! LPUART4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) +/*! LPUART5_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) +/*! LPUART6_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) +/*! LPUART7_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) +/*! LPUART8_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +/*! LPI2C1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +/*! LPI2C1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +/*! LPI2C2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +/*! LPI2C2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) +/*! LPI2C3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) +/*! LPI2C3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) +/*! LPI2C4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) +/*! LPI2C4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +/*! LPSPI1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +/*! LPSPI1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +/*! LPSPI2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +/*! LPSPI2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) +/*! LPSPI3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) +/*! LPSPI3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) +/*! LPSPI4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) +/*! LPSPI4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +/*! LPUART1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +/*! LPUART1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +/*! LPUART2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +/*! LPUART2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +/*! LPUART3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +/*! LPUART3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +/*! LPUART4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +/*! LPUART4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) +/*! LPUART5_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) +/*! LPUART5_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) +/*! LPUART6_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) +/*! LPUART6_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) +/*! LPUART7_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) +/*! LPUART7_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) +/*! LPUART8_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) +/*! LPUART8_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +/*! NIDEN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +/*! DBG_EN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +/*! SEC_ERR_RESP + * 0b0..OKEY response + * 0b1..SLVError (default) + */ +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +/*! DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Select key from Key MUX (SNVS/OTPMK). + * 0b1..Select key from OCOTP (SW_GP2). + */ +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows + * the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +/*! LOCK_NIDEN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +/*! LOCK_DBG_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +/*! LOCK_SEC_ERR_RESP + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +/*! LOCK_OCRAM_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +/*! LOCK_OCRAM_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ + +/*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +/*! M7_APC_AC_R0_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +/*! M7_APC_AC_R1_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +/*! M7_APC_AC_R2_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +/*! M7_APC_AC_R3_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ + +/*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +/*! FLEXIO1_IPG_STOP_MODE + * 0b0..FlexIO1 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +/*! FLEXIO1_IPG_DOZE + * 0b0..FLEXIO1 is not in doze mode + * 0b1..FLEXIO1 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) +/*! FLEXIO2_IPG_STOP_MODE + * 0b0..FlexIO2 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) +/*! FLEXIO2_IPG_DOZE + * 0b0..FLEXIO2 is not in doze mode + * 0b1..FLEXIO2 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) +/*! ACMP_IPG_STOP_MODE + * 0b0..ACMP is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +/*! @} */ + +/*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Cacheable attribute is off for read transactions. + * 0b1..Cacheable attribute is on for read transactions. + */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Cacheable attribute is off for write transactions. + * 0b1..Cacheable attribute is on for write transactions. + */ +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) +#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) +/*! CACHE_ENET + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) +#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) +#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +/*! CACHE_USB + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ + +/*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) +/*! ACMP1_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) +/*! ACMP2_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) +/*! ACMP3_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) +/*! ACMP4_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) +/*! ACMP1_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) +/*! ACMP2_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) +/*! ACMP3_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) +/*! ACMP4_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) +/*! ACMP1_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) +/*! ACMP2_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) +/*! ACMP3_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) +/*! ACMP4_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ + +/*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +/*! INIT_ITCM_EN + * 0b0..ITCM is disabled + * 0b1..ITCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +/*! INIT_DTCM_EN + * 0b0..DTCM is disabled + * 0b1..DTCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +/*! FLEXRAM_BANK_CFG_SEL + * 0b0..use fuse value to config + * 0b1..use FLEXRAM_BANK_CFG to config + */ +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) +/*! @} */ + +/*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) +/*! FLEXRAM_BANK_CFG - FlexRAM bank config value + */ +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ + +/*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ + +/*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ + +/*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ + +/*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ + +/*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ + +/*! @name GPR23 - GPR23 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ + +/*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK) +/*! @} */ + +/*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x400AC000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */ + __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */ + __IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */ + __IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */ + __IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad WAKEUP + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_ON_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_STBY_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x400A8000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ +} IOMUXC_SNVS_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks + * @{ + */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) +/*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear + */ +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */ + + +/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS_GPR base address */ +#define IOMUXC_SNVS_GPR_BASE (0x400A4000u) +/** Peripheral IOMUXC_SNVS_GPR base pointer */ +#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) +/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */ +#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } +/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */ +#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +/*! @{ */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +/*! KRE + * 0b00000000..Row is not included in the keypad key press detect. + * 0b00000001..Row is included in the keypad key press detect. + */ +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +/*! KCO + * 0b00000000..Column strobe output is totem pole drive. + * 0b00000001..Column strobe output is open drain. + */ +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ + +/*! @name KPSR - Keypad Status Register */ +/*! @{ */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +/*! KPKD + * 0b0..No key presses detected + * 0b1..A key has been depressed + */ +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +/*! KPKR + * 0b0..No key release detected + * 0b1..All keys have been released + */ +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +/*! KDSC + * 0b0..No effect + * 0b1..Set bits that clear the keypad depress synchronizer chain + */ +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +/*! KRSS + * 0b0..No effect + * 0b1..Set bits which sets keypad release synchronizer chain + */ +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +/*! KDIE + * 0b0..No interrupt request is generated when KPKD is set. + * 0b1..An interrupt request is generated when KPKD is set. + */ +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +/*! KRIE + * 0b0..No interrupt request is generated when KPKR is set. + * 0b1..An interrupt request is generated when KPKR is set. + */ +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ + +/*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +/*! KRDD + * 0b00000000..ROWn pin configured as an input. + * 0b00000001..ROWn pin configured as an output. + */ +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +/*! KCDD + * 0b00000000..COLn pin is configured as an input. + * 0b00000001..COLn pin is configured as an output. + */ +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ + +/*! @name KPDR - Keypad Data Register */ +/*! @{ */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x401FC000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[28]; + __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_6[220]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_8[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_9[76]; + __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_10[380]; + __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ + __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ + __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */ + __IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */ + __IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */ + __IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */ + __IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */ + __IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */ + __IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */ + __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */ + __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */ + __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */ + uint8_t RESERVED_11[1104]; + struct { /* offset: 0x800, array step: 0x40 */ + __IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */ + uint8_t RESERVED_2[28]; + } PIGEON[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */ + uint8_t RESERVED_12[12]; + __IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */ + uint8_t RESERVED_13[12]; + __IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */ + uint8_t RESERVED_14[12]; + __IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */ + uint8_t RESERVED_15[12]; + __IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in + * each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL1 - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_SET - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_CLR - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_TOG - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL2 - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_SET - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_CLR - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_TOG - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) +/*! @} */ + +/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @{ */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/*! @} */ + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +/*! @{ */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) +/*! @} */ + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +/*! @{ */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @{ */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/*! @} */ + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +/*! @{ */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/*! @} */ + +/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @{ */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) +/*! @} */ + +/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @{ */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/*! @} */ + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +/*! @{ */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) +/*! @} */ + +/*! @name CRC_STAT - CRC Status Register */ +/*! @{ */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) +/*! @} */ + +/*! @name STAT - LCD Interface Status Register */ +/*! @{ */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) +#define LCDIF_STAT_DMA_REQ_SHIFT (30U) +#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) +/*! @} */ + +/*! @name THRES - LCDIF Threshold Register */ +/*! @{ */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEON_0 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_0_EN_MASK (0x1U) +#define LCDIF_PIGEON_0_EN_SHIFT (0U) +#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) +#define LCDIF_PIGEON_0_POL_MASK (0x2U) +#define LCDIF_PIGEON_0_POL_SHIFT (1U) +/*! POL + * 0b0..Normal Signal (Active high) + * 0b1..Inverted signal (Active low) + */ +#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) +#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) +#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) +/*! INC_SEL + * 0b00..pclk + * 0b01..Line start pulse + * 0b10..Frame start pulse + * 0b11..Use another signal as tick event + */ +#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) +#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) +#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) +#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) +/*! MASK_CNT_SEL + * 0b0000..pclk counter within one hscan state + * 0b0001..pclk cycle within one hscan state + * 0b0010..line counter within one vscan state + * 0b0011..line cycle within one vscan state + * 0b0100..frame counter + * 0b0101..frame cycle + * 0b0110..horizontal counter (pclk counter within one line ) + * 0b0111..vertical counter (line counter within one frame) + */ +#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) +#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) +#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) +#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) +#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) +/*! STATE_MASK + * 0b00000001..FRAME SYNC + * 0b00000010..FRAME BEGIN + * 0b00000100..FRAME DATA + * 0b00001000..FRAME END + * 0b00010000..LINE SYNC + * 0b00100000..LINE BEGIN + * 0b01000000..LINE DATA + * 0b10000000..LINE END + */ +#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_0 */ +#define LCDIF_PIGEON_0_COUNT (12U) + +/*! @name PIGEON_1 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) +#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) +/*! SET_CNT + * 0b0000000000000000..Start as active + */ +#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) +#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) +#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) +/*! CLR_CNT + * 0b0000000000000000..Keep active until mask off + */ +#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_1 */ +#define LCDIF_PIGEON_1_COUNT (12U) + +/*! @name PIGEON_2 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) +#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) +/*! SIG_LOGIC + * 0b0000..No logic operation + * 0b0001..sigout = sig_another AND this_sig + * 0b0010..sigout = sig_another OR this_sig + * 0b0011..mask = sig_another AND other_masks + */ +#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) +#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) +#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) +/*! SIG_ANOTHER + * 0b00000..Keep active until mask off + */ +#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) +#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) +#define LCDIF_PIGEON_2_RSVD_SHIFT (9U) +#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_2 */ +#define LCDIF_PIGEON_2_COUNT (12U) + +/*! @name LUT_CTRL - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) +#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) +#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) +/*! @} */ + +/*! @name LUT0_ADDR - Lookup Table Control Register. */ +/*! @{ */ +#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) +#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name LUT0_DATA - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) +#define LCDIF_LUT0_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) +/*! @} */ + +/*! @name LUT1_ADDR - Lookup Table Control Register. */ +/*! @{ */ +#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) +#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name LUT1_DATA - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) +#define LCDIF_LUT1_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x402B8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } +/** Interrupt vectors for the LCDIF peripheral type */ +#define LCDIF_IRQ0_IRQS { LCDIF_IRQn } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + uint8_t RESERVED_6[156]; + __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + uint8_t RESERVED_7[4]; + __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Master only, with standard feature set + * 0b0000000000000011..Master and slave, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Master Transmit FIFO Size + */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Master Receive FIFO Size + */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Master Control Register */ +/*! @{ */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Master Enable + * 0b0..Master logic is disabled + * 0b1..Master logic is enabled + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Master is enabled in Doze mode + * 0b1..Master is disabled in Doze mode + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Master is disabled in debug mode + * 0b1..Master is enabled in debug mode + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Master Status Register */ +/*! @{ */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data is not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..Master has not generated a STOP or Repeated START condition + * 0b1..Master has generated a STOP or Repeated START condition + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Master has not generated a STOP condition + * 0b1..Master has generated a STOP condition + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..Unexpected NACK was not detected + * 0b1..Unexpected NACK was detected + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Master has not lost arbitration + * 0b1..Master has lost arbitration + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Master sending or receiving data without a START condition + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout has not occurred or is disabled + * 0b1..Pin low timeout has occurred + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Master Busy Flag + * 0b0..I2C Master is idle + * 0b1..I2C Master is busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ + +/*! @name MDER - Master DMA Enable Register */ +/*! @{ */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request input is disabled + * 0b1..Host request input is enabled + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ + +/*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic STOP Generation + * 0b0..No effect + * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - IGNACK + * 0b0..LPI2C Master will receive ACK and NACK normally + * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) + * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) + * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..2-pin open drain mode + * 0b001..2-pin output only mode (ultra-fast mode) + * 0b010..2-pin push-pull mode + * 0b011..4-pin push-pull mode + * 0b100..2-pin open drain mode with separate LPI2C slave + * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave + * 0b110..2-pin push-pull mode with separate LPI2C slave + * 0b111..4-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout + */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL + */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA + */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout + */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Master Data Match Register */ +/*! @{ */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value + */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value + */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period + */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period + */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay + */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay + */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period + */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period + */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay + */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay + */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark + */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark + */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count + */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count + */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data + */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate STOP condition + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) START and transmit address in DATA[7:0] + * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Master Receive Data Register */ +/*! @{ */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data + */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Receive FIFO is not empty + * 0b1..Receive FIFO is empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Slave Control Register */ +/*! @{ */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Slave Enable + * 0b0..I2C Slave mode is disabled + * 0b1..I2C Slave mode is enabled + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Slave mode logic is not reset + * 0b1..Slave mode logic is reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable digital filter and output delay counter for slave mode + * 0b1..Enable digital filter and output delay counter for slave mode + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Filter remains enabled in Doze mode + * 0b1..Filter is disabled in Doze mode + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit Data Register is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive Data Register is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Slave Status Register */ +/*! @{ */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Address Status Register is not valid + * 0b1..Address Status Register is valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Transmit ACK/NACK is not required + * 0b1..Transmit ACK/NACK is required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..Slave has not detected a Repeated START condition + * 0b1..Slave has detected a Repeated START condition + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Slave has not detected a STOP condition + * 0b1..Slave has detected a STOP condition + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..Slave has not detected a bit error + * 0b1..Slave has detected a bit error + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..FIFO underflow or overflow was not detected + * 0b1..FIFO underflow or overflow was detected + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..Have not received an ADDR0 matching address + * 0b1..Have received an ADDR0 matching address + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address + * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled + * 0b1..Slave has detected the General Call Address + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..SMBus Alert Response is disabled or not detected + * 0b1..SMBus Alert Response is enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Slave Busy Flag + * 0b0..I2C Slave is idle + * 0b1..I2C Slave is busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - TX Data SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..General Call address is disabled + * 0b1..General Call address is enabled + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disables match on SMBus Alert + * 0b1..Enables match on SMBus Alert + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address + * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid + * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..Slave will end transfer when NACK is detected + * 0b1..Slave will not end transfer when NACK detected + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - High Speed Mode Enable + * 0b0..Disables detection of HS-mode master code + * 0b1..Enables detection of HS-mode master code + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) + * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) + * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time + */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay + */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL + */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA + */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Slave Address Match Register */ +/*! @{ */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value + */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value + */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Slave Address Status Register */ +/*! @{ */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address + */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Received Address (RADDR) is valid + * 0b1..Received Address (RADDR) is not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Write a Transmit ACK for each received word + * 0b1..Write a Transmit NACK for each received word + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data + */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data + */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..The Receive Data Register is not empty + * 0b1..The Receive Data Register is empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start Of Frame + * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition + * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x403F0000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x403F4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x403F8000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base address */ +#define LPI2C4_BASE (0x403FC000u) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< Status Register, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ + uint8_t RESERVED_3[20]; + __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size + */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size + */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number + */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Module is enabled in Doze mode + * 0b1..Module is disabled in Doze mode + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Module is disabled in debug mode + * 0b1..Module is enabled in debug mode + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable Register */ +/*! @{ */ +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..The Peripheral Chip Select pin PCSx is active low + * 0b0001..The Peripheral Chip Select pin PCSx is active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st + * data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., + * [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data + * 0b10..SOUT is used for both input and output data + * 0b11..SOUT is used for input data and SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Config + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are enabled + * 0b1..PCS[3:2] are disabled + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value + */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value + */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration Register */ +/*! @{ */ +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider + */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers + */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay + */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay + */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control Register */ +/*! @{ */ +#define LPSPI_FCR_TXWATER_MASK (0xFU) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark + */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) +#define LPSPI_FCR_RXWATER_MASK (0xF0000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark + */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status Register */ +/*! @{ */ +#define LPSPI_FSR_TXCOUNT_MASK (0x1FU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count + */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) +#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count + */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command Register */ +/*! @{ */ +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size + */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data Register */ +/*! @{ */ +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data + */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status Register */ +/*! @{ */ +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data Register */ +/*! @{ */ +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data + */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x40394000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x40398000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Peripheral LPSPI3 base address */ +#define LPSPI3_BASE (0x4039C000u) +/** Peripheral LPSPI3 base pointer */ +#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) +/** Peripheral LPSPI4 base address */ +#define LPSPI4_BASE (0x403A0000u) +/** Peripheral LPSPI4 base pointer */ +#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ + __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ + __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ + __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set. + * 0b0000000000000011..Standard feature set with MODEM/IrDA support. + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size + */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size + */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset. + * 0b1..Module is reset. + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger is disabled. + * 0b01..Input trigger is used instead of RXD pin input. + * 0b10..Input trigger is used instead of CTS_B pin input. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor. + */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit. + * 0b1..Two stop bits. + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. + * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Resynchronization during received data word is supported + * 0b1..Resynchronization during received data word is disabled + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Receiver samples input data using the rising edge of the baud rate clock. + * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address Match Wakeup + * 0b01..Idle Match Wakeup + * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. + * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. + * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. + * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. + * 0b00111..Oversampling ratio of 8. + * 0b01000..Oversampling ratio of 9. + * 0b01001..Oversampling ratio of 10. + * 0b01010..Oversampling ratio of 11. + * 0b01011..Oversampling ratio of 12. + * 0b01100..Oversampling ratio of 13. + * 0b01101..Oversampling ratio of 14. + * 0b01110..Oversampling ratio of 15. + * 0b01111..Oversampling ratio of 16. + * 0b10000..Oversampling ratio of 17. + * 0b10001..Oversampling ratio of 18. + * 0b10010..Oversampling ratio of 19. + * 0b10011..Oversampling ratio of 20. + * 0b10100..Oversampling ratio of 21. + * 0b10101..Oversampling ratio of 22. + * 0b10110..Oversampling ratio of 23. + * 0b10111..Oversampling ratio of 24. + * 0b11000..Oversampling ratio of 25. + * 0b11001..Oversampling ratio of 26. + * 0b11010..Oversampling ratio of 27. + * 0b11011..Oversampling ratio of 28. + * 0b11100..Oversampling ratio of 29. + * 0b11101..Oversampling ratio of 30. + * 0b11110..Oversampling ratio of 31. + * 0b11111..Oversampling ratio of 32. + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-bit Mode select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. + * 0b1..Receiver and transmitter use 10-bit data characters. + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - LPUART Status Register */ +/*! @{ */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Received data is not equal to MA2 + * 0b1..Received data is equal to MA2 + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Received data is not equal to MA1 + * 0b1..Received data is equal to MA1 + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error. + * 0b1..Parity error. + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. This does not guarantee the framing is correct. + * 0b1..Framing error. + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected. + * 0b1..Noise detected in the received character in the DATA register. + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun. + * 0b1..Receive overrun (new LPUART data lost). + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..No idle line detected. + * 0b1..Idle line was detected. + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Receive data buffer empty. + * 0b1..Receive data buffer full. + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Transmit data buffer full. + * 0b1..Transmit data buffer empty. + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..LPUART receiver idle waiting for a start bit. + * 0b1..LPUART receiver active (RXD input not idle). + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..LIN break detect is disabled, normal break character can be detected. + * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..Break character is transmitted with length of 9 to 13 bit times. + * 0b1..Break character is transmitted with length of 12 to 15 bit times. + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle + * character. During address match wakeup, the IDLE bit does not set when an address does not match. + * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During + * address match wakeup, the IDLE bit does set when an address does not match. + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data not inverted. + * 0b1..Receive data inverted. + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received + * after the start bit is identified as bit0. + * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on + * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is + * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character has been detected. + * 0b1..LIN break character has been detected. + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - LPUART Control Register */ +/*! @{ */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..No hardware parity generation or checking. + * 0b1..Parity enabled. + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Configures RWU for idle-line wakeup. + * 0b1..Configures RWU with address-mark wakeup. + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit or 8-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit data characters. + * 0b1..Receiver and transmitter use 9-bit data characters. + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Enable + * 0b0..LPUART is enabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode. + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation - RXD and TXD use separate pins. + * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 idle character + * 0b001..2 idle characters + * 0b010..4 idle characters + * 0b011..8 idle characters + * 0b100..16 idle characters + * 0b101..32 idle characters + * 0b110..64 idle characters + * 0b111..128 idle characters + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. + * 0b1..Receiver and transmitter use 7-bit data characters. + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 Interrupt Enable + * 0b0..MA2F interrupt disabled + * 0b1..MA2F interrupt enabled + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 Interrupt Enable + * 0b0..MA1F interrupt disabled + * 0b1..MA1F interrupt enabled + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break character(s) to be sent. + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal receiver operation. + * 0b1..LPUART receiver in standby waiting for wakeup condition. + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Receiver disabled. + * 0b1..Receiver enabled. + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Transmitter disabled. + * 0b1..Transmitter enabled. + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Hardware interrupts from IDLE disabled; use polling. + * 0b1..Hardware interrupt requested when IDLE flag is 1. + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Hardware interrupts from RDRF disabled; use polling. + * 0b1..Hardware interrupt requested when RDRF flag is 1. + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable for + * 0b0..Hardware interrupts from TC disabled; use polling. + * 0b1..Hardware interrupt requested when TC flag is 1. + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Hardware interrupts from TDRE disabled; use polling. + * 0b1..Hardware interrupt requested when TDRE flag is 1. + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupts disabled; use polling). + * 0b1..Hardware interrupt requested when PF is set. + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when FE is set. + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when NF is set. + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..OR interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when OR is set. + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Transmit data not inverted. + * 0b1..Transmit data inverted. + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..TXD pin is an input in single-wire mode. + * 0b1..TXD pin is an output in single-wire mode. + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 / Transmit Bit 8 + */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 / Transmit Bit 9 + */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - LPUART Data Register */ +/*! @{ */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - R0T0 + */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - R1T1 + */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - R2T2 + */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - R3T3 + */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - R4T4 + */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - R5T5 + */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - R6T6 + */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - R7T7 + */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - R8T8 + */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - R9T9 + */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Receiver was not idle before receiving this character. + * 0b1..Receiver was idle before receiving this character. + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Receive buffer contains valid data. + * 0b1..Receive buffer is empty, data returned on read is not valid. + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error / Transmit Special Character + * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 + */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 + */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a + * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the + * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent + * do not affect its transmission. + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the + * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and + * shift register are completely sent, including the last stop bit. + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause + * the receiver data register to become full. RTS is asserted if the receiver data register is not full and + * has not detected a start bit that would cause the receiver data register to become full. + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..CTS input is sampled at the start of each character. + * 0b1..CTS input is sampled when the transmitter is idle. + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..CTS input is the CTS_B pin. + * 0b1..CTS input is the inverted Receiver Match result. + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration + */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter narrow pulse + * 0b00..1/OSR. + * 0b01..2/OSR. + * 0b10..3/OSR. + * 0b11..4/OSR. + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Receive FIFO/Buffer depth = 256 datawords. + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Transmit FIFO/Buffer depth = 256 datawords + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. + * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - LPUART Watermark Register */ +/*! @{ */ +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark + */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter + */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark + */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter + */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x40184000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x40188000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x4018C000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x40190000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x40194000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Peripheral LPUART6 base address */ +#define LPUART6_BASE (0x40198000u) +/** Peripheral LPUART6 base pointer */ +#define LPUART6 ((LPUART_Type *)LPUART6_BASE) +/** Peripheral LPUART7 base address */ +#define LPUART7_BASE (0x4019C000u) +/** Peripheral LPUART7 base pointer */ +#define LPUART7 ((LPUART_Type *)LPUART7_BASE) +/** Peripheral LPUART8 base address */ +#define LPUART8_BASE (0x401A0000u) +/** Peripheral LPUART8 base pointer */ +#define LPUART8 ((LPUART_Type *)LPUART8_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + uint8_t RESERVED_5[32]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_6[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_7[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_15[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ + uint8_t RESERVED_23[140]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_24[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_25[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_30[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_33[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_34[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_35[12]; + __IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ + uint8_t RESERVED_36[28]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_37[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ + +/*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ + +/*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ + +/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ + +/*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +/*! @} */ + +/*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ + +/*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ + +/*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) +#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) +#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) +#define OCOTP_LOCK_SW_GP1_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP1_SHIFT (16U) +#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK) +#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U) +#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U) +#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U) +#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U) +#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U) +#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK) +#define OCOTP_LOCK_GP3_MASK (0xC000000U) +#define OCOTP_LOCK_GP3_SHIFT (26U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) +#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) +#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ + +/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ + +/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ + +/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ +#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_BITS_SHIFT (0U) +#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ + +/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ + +/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP20_BITS_SHIFT (0U) +#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ + +/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP21_BITS_SHIFT (0U) +#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ + +/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP22_BITS_SHIFT (0U) +#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ + +/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP23_BITS_SHIFT (0U) +#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF0_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF1_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x401F4000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[544]; + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */ + uint8_t RESERVED_1[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ + +/*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x400F4000u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[220]; + __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ + __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ + uint8_t RESERVED_1[24]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +/*! @{ */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ + +/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) +#define PIT_LTMR64H_LTH_SHIFT (0U) +/*! LTH - Life Timer value + */ +#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ + +/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) +#define PIT_LTMR64L_LTL_SHIFT (0U) +/*! LTL - Life Timer value + */ +#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ + +/*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +/*! TSV - Timer Start Value + */ +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +/*! @{ */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +/*! TVL - Current Timer Value + */ +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +/*! @{ */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +/*! @{ */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40084000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[272]; + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ + __IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */ + __IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */ + __IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */ + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ + __IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */ + __IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */ + __IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */ + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ + __IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */ + __IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */ + __IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */ + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ + __IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */ + __IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */ + __IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */ + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) +#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK) +#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK) +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK) +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK) +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) +#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK) +#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) +#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) +#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) +#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) +#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) +#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) +#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) +#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) +#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) +#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_OSC_I_MASK (0x6000U) +#define PMU_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) +#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK) +#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) +#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) +#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_SET_OSC_I_MASK (0x6000U) +#define PMU_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) +#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) +#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) +#define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) +#define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) +#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK) +#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK) +#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK) +#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK) +#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) +#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK) +#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_REG2_OK_SHIFT (22U) +#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) +#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) +#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) +#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_SET_REG2_OK_SHIFT (22U) +#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) +#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U) +#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) +#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U) +#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) +#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x400D8000u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + uint8_t RESERVED_1[8]; + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits + */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits + */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it will force the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization + */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master + * reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it + * will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value + */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value + */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value + */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) +#define PWM_CTRL2_WAITEN_MASK (0x4000U) +#define PWM_CTRL2_WAITEN_SHIFT (14U) +/*! WAITEN - WAIT Enable + */ +#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable + */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA + * output that is high at the end of a period will maintain this state until a match with VAL3 clears the + * output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWMA output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime + */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value Register 0 + */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +/*! FRACVAL1 - Fractional Value 1 Register + */ +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value Register 1 + */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +/*! FRACVAL2 - Fractional Value 2 + */ +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value Register 2 + */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +/*! FRACVAL3 - Fractional Value 3 + */ +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value Register 3 + */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +/*! FRACVAL4 - Fractional Value 4 + */ +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value Register 4 + */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +/*! FRACVAL5 - Fractional Value 5 + */ +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value Register 5 + */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) +#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) +#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +/*! FRAC_PU - Fractional Delay Circuit Power Up + * 0b0..Turn off fractional delay logic. + * 0b1..Power up fractional delay logic. + */ +#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +/*! TEST - Test Status Bit + */ +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input + */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input + */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input + */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 + */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 + */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +/*! CFB0 - Capture Flag B0 + */ +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +/*! CFB1 - Capture Flag B1 + */ +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +/*! CFA0 - Capture Flag A0 + */ +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +/*! CFA1 - Capture Flag A1 + */ +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable + */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable + */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +/*! CB0DE - Capture B0 FIFO DMA Enable + */ +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +/*! CB1DE - Capture B1 FIFO DMA Enable + */ +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +/*! CA0DE - Capture A0 FIFO DMA Enable + */ +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +/*! CA1DE - Capture A1 FIFO DMA Enable + */ +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to + * which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 + */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) +#define PWM_DISMAP_DIS1A_MASK (0xFU) +#define PWM_DISMAP_DIS1A_SHIFT (0U) +/*! DIS1A - PWM_A Fault Disable Mask 1 + */ +#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 + */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) +#define PWM_DISMAP_DIS1B_MASK (0xF0U) +#define PWM_DISMAP_DIS1B_SHIFT (4U) +/*! DIS1B - PWM_B Fault Disable Mask 1 + */ +#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 + */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +/*! DIS1X - PWM_X Fault Disable Mask 1 + */ +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (2U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ +#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - DTCNT0 + */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ +#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - DTCNT1 + */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 + * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. + * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No + * further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is + * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and + * CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +/*! CFAWM - Capture A FIFOs Water Mark + */ +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +/*! CA0CNT - Capture A0 FIFO Word Count + */ +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +/*! CA1CNT - Capture A1 FIFO Word Count + */ +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +/*! EDGCMPA - Edge Compare A + */ +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +/*! EDGCNTA - Edge Counter A + */ +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 + * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. + * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No + * further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is + * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and + * CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +/*! CFBWM - Capture B FIFOs Water Mark + */ +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +/*! CB0CNT - Capture B0 FIFO Word Count + */ +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +/*! CB1CNT - Capture B1 FIFO Word Count + */ +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +/*! EDGCMPB - Edge Compare B + */ +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +/*! EDGCNTB - Edge Counter B + */ +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The + * process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further + * captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, + * then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and + * CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark + */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count + */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count + */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X + */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X + */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - CAPTVAL0 + */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - CVAL0CYC + */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - CAPTVAL1 + */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - CVAL1CYC + */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +/*! CAPTVAL2 - CAPTVAL2 + */ +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +/*! CVAL2CYC - CVAL2CYC + */ +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +/*! CAPTVAL3 - CAPTVAL3 + */ +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +/*! CVAL3CYC - CVAL3CYC + */ +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +/*! CAPTVAL4 - CAPTVAL4 + */ +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +/*! CVAL4CYC - CVAL4CYC + */ +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +/*! CAPTVAL5 - CAPTVAL5 + */ +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +/*! CVAL5CYC - CVAL5CYC + */ +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay + */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM generator is disabled in the corresponding submodule. + * 0b0001..PWM generator is enabled in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ +#define PWM_MCTRL2_MONPLL_MASK (0x3U) +#define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock + * will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL + * encounters problems. These bits are write protected until the next reset. + */ +#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of + * FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual + * FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as + * programmed in DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further + * controlled by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the + * state of FSTS[FFLAGx]. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins + */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period + */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count + */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x403DC000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x403E0000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x403E4000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x403E8000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[348]; + __IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */ + uint8_t RESERVED_25[220]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_26[60]; + __IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_RSVD0_MASK (0xE0U) +#define PXP_CTRL_RSVD0_SHIFT (5U) +#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK) +#define PXP_CTRL_ROTATE_MASK (0x300U) +#define PXP_CTRL_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) +#define PXP_CTRL_HFLIP_MASK (0x400U) +#define PXP_CTRL_HFLIP_SHIFT (10U) +#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK) +#define PXP_CTRL_VFLIP_MASK (0x800U) +#define PXP_CTRL_VFLIP_SHIFT (11U) +#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK) +#define PXP_CTRL_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_RSVD1_SHIFT (12U) +#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK) +#define PXP_CTRL_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_ROT_POS_SHIFT (22U) +#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_RSVD3_SHIFT (24U) +#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_RSVD4_SHIFT (29U) +#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_SET_RSVD0_MASK (0xE0U) +#define PXP_CTRL_SET_RSVD0_SHIFT (5U) +#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK) +#define PXP_CTRL_SET_ROTATE_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) +#define PXP_CTRL_SET_HFLIP_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK) +#define PXP_CTRL_SET_VFLIP_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK) +#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_SET_RSVD1_SHIFT (12U) +#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK) +#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_SET_ROT_POS_SHIFT (22U) +#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_SET_RSVD3_SHIFT (24U) +#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_SET_RSVD4_SHIFT (29U) +#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U) +#define PXP_CTRL_CLR_RSVD0_SHIFT (5U) +#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK) +#define PXP_CTRL_CLR_ROTATE_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) +#define PXP_CTRL_CLR_HFLIP_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK) +#define PXP_CTRL_CLR_VFLIP_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK) +#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_CLR_RSVD1_SHIFT (12U) +#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK) +#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U) +#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_CLR_RSVD3_SHIFT (24U) +#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_CLR_RSVD4_SHIFT (29U) +#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U) +#define PXP_CTRL_TOG_RSVD0_SHIFT (5U) +#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK) +#define PXP_CTRL_TOG_ROTATE_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) +#define PXP_CTRL_TOG_HFLIP_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK) +#define PXP_CTRL_TOG_VFLIP_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK) +#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_TOG_RSVD1_SHIFT (12U) +#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK) +#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U) +#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_TOG_RSVD3_SHIFT (24U) +#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_TOG_RSVD4_SHIFT (29U) +#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ +#define PXP_STAT_IRQ_MASK (0x1U) +#define PXP_STAT_IRQ_SHIFT (0U) +#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_RSVD2_MASK (0xFE00U) +#define PXP_STAT_RSVD2_SHIFT (9U) +#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_SET - Status Register */ +/*! @{ */ +#define PXP_STAT_SET_IRQ_MASK (0x1U) +#define PXP_STAT_SET_IRQ_SHIFT (0U) +#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_RSVD2_MASK (0xFE00U) +#define PXP_STAT_SET_RSVD2_SHIFT (9U) +#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_CLR - Status Register */ +/*! @{ */ +#define PXP_STAT_CLR_IRQ_MASK (0x1U) +#define PXP_STAT_CLR_IRQ_SHIFT (0U) +#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U) +#define PXP_STAT_CLR_RSVD2_SHIFT (9U) +#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_TOG - Status Register */ +/*! @{ */ +#define PXP_STAT_TOG_IRQ_MASK (0x1U) +#define PXP_STAT_TOG_IRQ_SHIFT (0U) +#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U) +#define PXP_STAT_TOG_RSVD2_SHIFT (9U) +#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) +/*! @} */ + +/*! @name OUT_CTRL - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +/*! @{ */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +/*! @{ */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) +/*! @} */ + +/*! @name OUT_PITCH - Output Buffer Pitch */ +/*! @{ */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) +#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_OUT_PITCH_RSVD_SHIFT (16U) +#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) +#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +/*! @{ */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U) +#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U) +#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) +#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) +#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) +#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +/*! @{ */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U) +#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U) +#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) +#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) +#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) +#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) +#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) +#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) +#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) +#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name PS_BUF - PS Input Buffer Address */ +/*! @{ */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +/*! @{ */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +/*! @{ */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_PITCH - Processed Surface Pitch */ +/*! @{ */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) +#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_PS_PITCH_RSVD_SHIFT (16U) +#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name PS_BACKGROUND - PS Background Color */ +/*! @{ */ +#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) +#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) +#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) +#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) +/*! @} */ + +/*! @name PS_SCALE - PS Scale Factor Register */ +/*! @{ */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_RSVD1_MASK (0x8000U) +#define PXP_PS_SCALE_RSVD1_SHIFT (15U) +#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) +#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) +#define PXP_PS_SCALE_RSVD2_SHIFT (31U) +#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) +/*! @} */ + +/*! @name PS_OFFSET - PS Scale Offset Register */ +/*! @{ */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U) +#define PXP_PS_OFFSET_RSVD1_SHIFT (12U) +#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) +#define PXP_PS_OFFSET_RSVD2_SHIFT (28U) +#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) +/*! @} */ + +/*! @name PS_CLRKEYLOW - PS Color Key Low */ +/*! @{ */ +#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) +#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CLRKEYHIGH - PS Color Key High */ +/*! @{ */ +#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) +#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CTRL - Alpha Surface Control */ +/*! @{ */ +#define PXP_AS_CTRL_RSVD0_MASK (0x1U) +#define PXP_AS_CTRL_RSVD0_SHIFT (0U) +#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +/*! ALPHA_CTRL + * 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + * 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + * 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel + * alpha is multiplied by the value in the ALPHA field. + * 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + */ +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +/*! FORMAT + * 0b0000..32-bit pixels with alpha + * 0b0100..32-bit pixels without alpha (unpacked 24-bit format) + * 0b1000..16-bit pixels with alpha + * 0b1001..16-bit pixels with alpha + * 0b1100..16-bit pixels without alpha + * 0b1101..16-bit pixels without alpha + * 0b1110..16-bit pixels without alpha + */ +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +/*! ROP + * 0b0000..AS AND PS + * 0b0001..nAS AND PS + * 0b0010..AS AND nPS + * 0b0011..AS OR PS + * 0b0100..nAS OR PS + * 0b0101..AS OR nPS + * 0b0110..nAS + * 0b0111..nPS + * 0b1000..AS NAND PS + * 0b1001..AS NOR PS + * 0b1010..AS XOR PS + * 0b1011..AS XNOR PS + */ +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK) +#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) +#define PXP_AS_CTRL_RSVD1_SHIFT (21U) +#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) +/*! @} */ + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +/*! @{ */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name AS_PITCH - Alpha Surface Pitch */ +/*! @{ */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) +#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_AS_PITCH_RSVD_SHIFT (16U) +#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name AS_CLRKEYLOW - Overlay Color Key Low */ +/*! @{ */ +#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) +#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CLRKEYHIGH - Overlay Color Key High */ +/*! @{ */ +#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) +#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U) +#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U) +#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) +/*! @} */ + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U) +#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U) +#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) +#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) +#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) +#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) +/*! @} */ + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U) +#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U) +#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) +#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) +#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) +#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) +/*! @} */ + +/*! @name POWER - PXP Power Control Register */ +/*! @{ */ +#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) +/*! ROT_MEM_LP_STATE + * 0b000..Memory is not in low power state. + * 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents. + * 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents. + * 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention. + */ +#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) +#define PXP_POWER_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_CTRL_SHIFT (12U) +#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) +/*! @} */ + +/*! @name NEXT - Next Frame Pointer */ +/*! @{ */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_RSVD_MASK (0x2U) +#define PXP_NEXT_RSVD_SHIFT (1U) +#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) +/*! @} */ + +/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ +/*! @{ */ +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x402B4000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ + +/*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x40180000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTWDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer + * @{ + */ + +/** RTWDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ + __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ + __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ +} RTWDOG_Type; + +/* ---------------------------------------------------------------------------- + -- RTWDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks + * @{ + */ + +/*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ +#define RTWDOG_CS_STOP_MASK (0x1U) +#define RTWDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Watchdog disabled in chip stop mode. + * 0b1..Watchdog enabled in chip stop mode. + */ +#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) +#define RTWDOG_CS_WAIT_MASK (0x2U) +#define RTWDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Watchdog disabled in chip wait mode. + * 0b1..Watchdog enabled in chip wait mode. + */ +#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) +#define RTWDOG_CS_DBG_MASK (0x4U) +#define RTWDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Watchdog disabled in chip debug mode. + * 0b1..Watchdog enabled in chip debug mode. + */ +#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) +#define RTWDOG_CS_TST_MASK (0x18U) +#define RTWDOG_CS_TST_SHIFT (3U) +/*! TST - Watchdog Test + * 0b00..Watchdog test mode disabled. + * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should + * use this setting to indicate that the watchdog is functioning normally in user mode. + * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + */ +#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) +#define RTWDOG_CS_UPDATE_MASK (0x20U) +#define RTWDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Allow updates + * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + */ +#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) +#define RTWDOG_CS_INT_MASK (0x40U) +#define RTWDOG_CS_INT_SHIFT (6U) +/*! INT - Watchdog Interrupt + * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. + * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + */ +#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) +#define RTWDOG_CS_EN_MASK (0x80U) +#define RTWDOG_CS_EN_SHIFT (7U) +/*! EN - Watchdog Enable + * 0b0..Watchdog disabled. + * 0b1..Watchdog enabled. + */ +#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) +#define RTWDOG_CS_CLK_MASK (0x300U) +#define RTWDOG_CS_CLK_SHIFT (8U) +/*! CLK - Watchdog Clock + * 0b00..Bus clock + * 0b01..LPO clock + * 0b10..INTCLK (internal clock) + * 0b11..ERCLK (external reference clock) + */ +#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) +#define RTWDOG_CS_RCS_MASK (0x400U) +#define RTWDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Reconfiguring WDOG. + * 0b1..Reconfiguration is successful. + */ +#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) +#define RTWDOG_CS_ULK_MASK (0x800U) +#define RTWDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock status + * 0b0..WDOG is locked. + * 0b1..WDOG is unlocked. + */ +#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) +#define RTWDOG_CS_PRES_MASK (0x1000U) +#define RTWDOG_CS_PRES_SHIFT (12U) +/*! PRES - Watchdog prescaler + * 0b0..256 prescaler disabled. + * 0b1..256 prescaler enabled. + */ +#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) +#define RTWDOG_CS_CMD32EN_MASK (0x2000U) +#define RTWDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + */ +#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) +#define RTWDOG_CS_FLG_MASK (0x4000U) +#define RTWDOG_CS_FLG_SHIFT (14U) +/*! FLG - Watchdog Interrupt Flag + * 0b0..No interrupt occurred. + * 0b1..An interrupt occurred. + */ +#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) +#define RTWDOG_CS_WIN_MASK (0x8000U) +#define RTWDOG_CS_WIN_SHIFT (15U) +/*! WIN - Watchdog Window + * 0b0..Window mode disabled. + * 0b1..Window mode enabled. + */ +#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - Watchdog Counter Register */ +/*! @{ */ +#define RTWDOG_CNT_CNTLOW_MASK (0xFFU) +#define RTWDOG_CNT_CNTLOW_SHIFT (0U) +/*! CNTLOW - Low byte of the Watchdog Counter + */ +#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) +#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define RTWDOG_CNT_CNTHIGH_SHIFT (8U) +/*! CNTHIGH - High byte of the Watchdog Counter + */ +#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ +#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) +/*! TOVALLOW - Low byte of the timeout value + */ +#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) +#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) +/*! TOVALHIGH - High byte of the timeout value + */ +#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window Register */ +/*! @{ */ +#define RTWDOG_WIN_WINLOW_MASK (0xFFU) +#define RTWDOG_WIN_WINLOW_SHIFT (0U) +/*! WINLOW - Low byte of Watchdog Window + */ +#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) +#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) +#define RTWDOG_WIN_WINHIGH_SHIFT (8U) +/*! WINHIGH - High byte of Watchdog Window + */ +#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTWDOG_Register_Masks */ + + +/* RTWDOG - Peripheral instance base addresses */ +/** Peripheral RTWDOG base address */ +#define RTWDOG_BASE (0x400BC000u) +/** Peripheral RTWDOG base pointer */ +#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE) +/** Array initializer of RTWDOG peripheral base addresses */ +#define RTWDOG_BASE_ADDRS { RTWDOG_BASE } +/** Array initializer of RTWDOG peripheral base pointers */ +#define RTWDOG_BASE_PTRS { RTWDOG } +/** Interrupt vectors for the RTWDOG peripheral type */ +#define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group RTWDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer + * @{ + */ + +/** SEMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ + __IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */ + __IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */ + __IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */ + __IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */ + __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ + __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ + __IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */ + __IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */ + __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ + __IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */ + __IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */ + __IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */ + __IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */ + __IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */ + __IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */ + __IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */ + uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */ + __IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */ + __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ + __IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */ + uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */ + __IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */ + __IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */ + uint8_t RESERVED_1[8]; + __IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */ + __IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */ + __IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */ + __IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */ + __IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */ + uint8_t RESERVED_2[12]; + __I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */ + uint8_t RESERVED_3[12]; + __I uint32_t STS0; /**< Status register 0, offset: 0xC0 */ + uint32_t STS1; /**< Status register 1, offset: 0xC4 */ + __I uint32_t STS2; /**< Status register 2, offset: 0xC8 */ + uint32_t STS3; /**< Status register 3, offset: 0xCC */ + uint32_t STS4; /**< Status register 4, offset: 0xD0 */ + uint32_t STS5; /**< Status register 5, offset: 0xD4 */ + uint32_t STS6; /**< Status register 6, offset: 0xD8 */ + uint32_t STS7; /**< Status register 7, offset: 0xDC */ + uint32_t STS8; /**< Status register 8, offset: 0xE0 */ + uint32_t STS9; /**< Status register 9, offset: 0xE4 */ + uint32_t STS10; /**< Status register 10, offset: 0xE8 */ + uint32_t STS11; /**< Status register 11, offset: 0xEC */ + __I uint32_t STS12; /**< Status register 12, offset: 0xF0 */ + uint32_t STS13; /**< Status register 13, offset: 0xF4 */ + uint32_t STS14; /**< Status register 14, offset: 0xF8 */ + uint32_t STS15; /**< Status register 15, offset: 0xFC */ +} SEMC_Type; + +/* ---------------------------------------------------------------------------- + -- SEMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Register_Masks SEMC Register Masks + * @{ + */ + +/*! @name MCR - Module Control Register */ +/*! @{ */ +#define SEMC_MCR_SWRST_MASK (0x1U) +#define SEMC_MCR_SWRST_SHIFT (0U) +/*! SWRST - Software Reset + */ +#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) +#define SEMC_MCR_MDIS_MASK (0x2U) +#define SEMC_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..Module enabled + * 0b1..Module disabled. + */ +#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) +#define SEMC_MCR_DQSMD_MASK (0x4U) +#define SEMC_MCR_DQSMD_SHIFT (2U) +/*! DQSMD - DQS (read strobe) mode + * 0b0..Dummy read strobe loopbacked internally + * 0b1..Dummy read strobe loopbacked from DQS pad + */ +#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) +#define SEMC_MCR_WPOL0_MASK (0x40U) +#define SEMC_MCR_WPOL0_SHIFT (6U) +/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM + * 0b0..Low active + * 0b1..High active + */ +#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) +#define SEMC_MCR_WPOL1_MASK (0x80U) +#define SEMC_MCR_WPOL1_SHIFT (7U) +/*! WPOL1 - WAIT/RDY# polarity for NAND + * 0b0..Low active + * 0b1..High active + */ +#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) +#define SEMC_MCR_CTO_MASK (0xFF0000U) +#define SEMC_MCR_CTO_SHIFT (16U) +/*! CTO - Command Execution timeout cycles + */ +#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) +#define SEMC_MCR_BTO_MASK (0x1F000000U) +#define SEMC_MCR_BTO_SHIFT (24U) +/*! BTO - Bus timeout cycles + * 0b00000..255*1 + * 0b00001-0b11110..255*2 - 255*2^30 + * 0b11111..255*2^31 + */ +#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ + +/*! @name IOCR - IO Mux Control Register */ +/*! @{ */ +#define SEMC_IOCR_MUX_A8_MASK (0x7U) +#define SEMC_IOCR_MUX_A8_SHIFT (0U) +/*! MUX_A8 - SEMC_A8 output selection + * 0b000..SDRAM Address bit (A8) + * 0b001..NAND CE# + * 0b010..NOR CE# + * 0b011..PSRAM CE# + * 0b100..DBI CSX + * 0b101..SDRAM Address bit (A8) + * 0b110..SDRAM Address bit (A8) + * 0b111..SDRAM Address bit (A8) + */ +#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) +#define SEMC_IOCR_MUX_CSX0_MASK (0x38U) +#define SEMC_IOCR_MUX_CSX0_SHIFT (3U) +/*! MUX_CSX0 - SEMC_CSX0 output selection + * 0b000..NOR/PSRAM Address bit 24 (A24) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) +#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) +#define SEMC_IOCR_MUX_CSX1_SHIFT (6U) +/*! MUX_CSX1 - SEMC_CSX1 output selection + * 0b000..NOR/PSRAM Address bit 25 (A25) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) +#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) +#define SEMC_IOCR_MUX_CSX2_SHIFT (9U) +/*! MUX_CSX2 - SEMC_CSX2 output selection + * 0b000..NOR/PSRAM Address bit 26 (A26) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) +#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) +#define SEMC_IOCR_MUX_CSX3_SHIFT (12U) +/*! MUX_CSX3 - SEMC_CSX3 output selection + * 0b000..NOR/PSRAM Address bit 27 (A27) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) +#define SEMC_IOCR_MUX_RDY_MASK (0x38000U) +#define SEMC_IOCR_MUX_RDY_SHIFT (15U) +/*! MUX_RDY - SEMC_RDY function selection + * 0b000..NAND Ready/Wait# input + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NOR CE# + * 0b101..PSRAM CE# + * 0b110..DBI CSX + * 0b111..NOR/PSRAM Address bit 27 + */ +#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +/*! @} */ + +/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ +#define SEMC_BMCR0_WQOS_MASK (0xFU) +#define SEMC_BMCR0_WQOS_SHIFT (0U) +/*! WQOS - Weight of QoS + */ +#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) +#define SEMC_BMCR0_WAGE_MASK (0xF0U) +#define SEMC_BMCR0_WAGE_SHIFT (4U) +/*! WAGE - Weight of Aging + */ +#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) +#define SEMC_BMCR0_WSH_MASK (0xFF00U) +#define SEMC_BMCR0_WSH_SHIFT (8U) +/*! WSH - Weight of Slave Hit (no read/write switch) + */ +#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) +#define SEMC_BMCR0_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR0_WRWS_SHIFT (16U) +/*! WRWS - Weight of Slave Hit (Read/Write switch) + */ +#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ + +/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ +#define SEMC_BMCR1_WQOS_MASK (0xFU) +#define SEMC_BMCR1_WQOS_SHIFT (0U) +/*! WQOS - Weight of QoS + */ +#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) +#define SEMC_BMCR1_WAGE_MASK (0xF0U) +#define SEMC_BMCR1_WAGE_SHIFT (4U) +/*! WAGE - Weight of Aging + */ +#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) +#define SEMC_BMCR1_WPH_MASK (0xFF00U) +#define SEMC_BMCR1_WPH_SHIFT (8U) +/*! WPH - Weight of Page Hit + */ +#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) +#define SEMC_BMCR1_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR1_WRWS_SHIFT (16U) +/*! WRWS - Weight of Read/Write switch + */ +#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) +#define SEMC_BMCR1_WBR_MASK (0xFF000000U) +#define SEMC_BMCR1_WBR_SHIFT (24U) +/*! WBR - Weight of Bank Rotation + */ +#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ + +/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ +#define SEMC_BR_VLD_MASK (0x1U) +#define SEMC_BR_VLD_SHIFT (0U) +/*! VLD - Valid + */ +#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) +#define SEMC_BR_MS_MASK (0x3EU) +#define SEMC_BR_MS_SHIFT (1U) +/*! MS - Memory size + * 0b00000..4KB + * 0b00001..8KB + * 0b00010..16KB + * 0b00011..32KB + * 0b00100..64KB + * 0b00101..128KB + * 0b00110..256KB + * 0b00111..512KB + * 0b01000..1MB + * 0b01001..2MB + * 0b01010..4MB + * 0b01011..8MB + * 0b01100..16MB + * 0b01101..32MB + * 0b01110..64MB + * 0b01111..128MB + * 0b10000..256MB + * 0b10001..512MB + * 0b10010..1GB + * 0b10011..2GB + * 0b10100..4GB + * 0b10101..4GB + * 0b10110..4GB + * 0b10111..4GB + * 0b11000..4GB + * 0b11001..4GB + * 0b11010..4GB + * 0b11011..4GB + * 0b11100..4GB + * 0b11101..4GB + * 0b11110..4GB + * 0b11111..4GB + */ +#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) +#define SEMC_BR_BA_MASK (0xFFFFF000U) +#define SEMC_BR_BA_SHIFT (12U) +/*! BA - Base Address + */ +#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ + +/* The count of SEMC_BR */ +#define SEMC_BR_COUNT (9U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) +#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) +/*! IPCMDDONEEN - IP command done interrupt enable + */ +#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) +#define SEMC_INTEN_IPCMDERREN_MASK (0x2U) +#define SEMC_INTEN_IPCMDERREN_SHIFT (1U) +/*! IPCMDERREN - IP command error interrupt enable + */ +#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) +#define SEMC_INTEN_AXICMDERREN_MASK (0x4U) +#define SEMC_INTEN_AXICMDERREN_SHIFT (2U) +/*! AXICMDERREN - AXI command error interrupt enable + */ +#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) +#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U) +#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U) +/*! AXIBUSERREN - AXI bus error interrupt enable + */ +#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) +#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) +#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) +/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ +#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) +#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) +#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) +/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ +#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTR_IPCMDDONE_MASK (0x1U) +#define SEMC_INTR_IPCMDDONE_SHIFT (0U) +/*! IPCMDDONE - IP command normal done interrupt + */ +#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) +#define SEMC_INTR_IPCMDERR_MASK (0x2U) +#define SEMC_INTR_IPCMDERR_SHIFT (1U) +/*! IPCMDERR - IP command error done interrupt + */ +#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) +#define SEMC_INTR_AXICMDERR_MASK (0x4U) +#define SEMC_INTR_AXICMDERR_SHIFT (2U) +/*! AXICMDERR - AXI command error interrupt + */ +#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) +#define SEMC_INTR_AXIBUSERR_MASK (0x8U) +#define SEMC_INTR_AXIBUSERR_SHIFT (3U) +/*! AXIBUSERR - AXI bus error interrupt + */ +#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) +#define SEMC_INTR_NDPAGEEND_MASK (0x10U) +#define SEMC_INTR_NDPAGEEND_SHIFT (4U) +/*! NDPAGEEND - This interrupt is generated when the last address of one page in NAND device is written by AXI command + */ +#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) +#define SEMC_INTR_NDNOPEND_MASK (0x20U) +#define SEMC_INTR_NDNOPEND_SHIFT (5U) +/*! NDNOPEND - This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface. + */ +#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ + +/*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ +#define SEMC_SDRAMCR0_PS_MASK (0x1U) +#define SEMC_SDRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) +#define SEMC_SDRAMCR0_BL_MASK (0x70U) +#define SEMC_SDRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..8 + * 0b101..8 + * 0b110..8 + * 0b111..8 + */ +#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) +#define SEMC_SDRAMCR0_COL_MASK (0x300U) +#define SEMC_SDRAMCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b00..12 bit + * 0b01..11 bit + * 0b10..10 bit + * 0b11..9 bit + */ +#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) +#define SEMC_SDRAMCR0_CL_MASK (0xC00U) +#define SEMC_SDRAMCR0_CL_SHIFT (10U) +/*! CL - CAS Latency + * 0b00..1 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +/*! @} */ + +/*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ +#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) +/*! PRE2ACT - PRECHARGE to ACT/Refresh wait time + */ +#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) +#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) +#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) +/*! ACT2RW - ACT to Read/Write wait time + */ +#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) +#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) +#define SEMC_SDRAMCR1_RFRC_SHIFT (8U) +/*! RFRC - Refresh recovery time + */ +#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) +#define SEMC_SDRAMCR1_WRC_MASK (0xE000U) +#define SEMC_SDRAMCR1_WRC_SHIFT (13U) +/*! WRC - Write recovery time + */ +#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) +#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) +#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) +/*! CKEOFF - CKE OFF minimum time + */ +#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) +#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) +/*! ACT2PRE - ACT to Precharge minimum time + */ +#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ + +/*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ +#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) +#define SEMC_SDRAMCR2_SRRC_SHIFT (0U) +/*! SRRC - Self Refresh Recovery time + */ +#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) +#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) +#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U) +/*! REF2REF - Refresh to Refresh wait time + */ +#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) +#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) +/*! ACT2ACT - ACT to ACT wait time + */ +#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) +#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) +#define SEMC_SDRAMCR2_ITO_SHIFT (24U) +/*! ITO - SDRAM Idle timeout + * 0b00000000..IDLE timeout period is 256*Prescale period. + * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period. + */ +#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ + +/*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ +#define SEMC_SDRAMCR3_REN_MASK (0x1U) +#define SEMC_SDRAMCR3_REN_SHIFT (0U) +/*! REN - Refresh enable + */ +#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) +#define SEMC_SDRAMCR3_REBL_MASK (0xEU) +#define SEMC_SDRAMCR3_REBL_SHIFT (1U) +/*! REBL - Refresh burst length + * 0b000..1 + * 0b001..2 + * 0b010..3 + * 0b011..4 + * 0b100..5 + * 0b101..6 + * 0b110..7 + * 0b111..8 + */ +#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) +#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) +#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) +/*! PRESCALE - Prescaler timer period + * 0b00000000..256*16 cycle + * 0b00000001-0b11111111..PRESCALE*16 cycle + */ +#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) +#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) +#define SEMC_SDRAMCR3_RT_SHIFT (16U) +/*! RT - Refresh timer period + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..RT*Prescaler period + */ +#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) +#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) +#define SEMC_SDRAMCR3_UT_SHIFT (24U) +/*! UT - Refresh urgent threshold + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..UT*Prescaler period + */ +#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ + +/*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ +#define SEMC_NANDCR0_PS_MASK (0x1U) +#define SEMC_NANDCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) +#define SEMC_NANDCR0_BL_MASK (0x70U) +#define SEMC_NANDCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) +#define SEMC_NANDCR0_EDO_MASK (0x80U) +#define SEMC_NANDCR0_EDO_SHIFT (7U) +/*! EDO - EDO mode enabled + * 0b0..EDO mode disabled + * 0b1..EDO mode enabled + */ +#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) +#define SEMC_NANDCR0_COL_MASK (0x700U) +#define SEMC_NANDCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b000..16 + * 0b001..15 + * 0b010..14 + * 0b011..13 + * 0b100..12 + * 0b101..11 + * 0b110..10 + * 0b111..9 + */ +#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ + +/*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ +#define SEMC_NANDCR1_CES_MASK (0xFU) +#define SEMC_NANDCR1_CES_SHIFT (0U) +/*! CES - CE setup time + */ +#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) +#define SEMC_NANDCR1_CEH_MASK (0xF0U) +#define SEMC_NANDCR1_CEH_SHIFT (4U) +/*! CEH - CE hold time + */ +#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) +#define SEMC_NANDCR1_WEL_MASK (0xF00U) +#define SEMC_NANDCR1_WEL_SHIFT (8U) +/*! WEL - WE# LOW time + */ +#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) +#define SEMC_NANDCR1_WEH_MASK (0xF000U) +#define SEMC_NANDCR1_WEH_SHIFT (12U) +/*! WEH - WE# HIGH time + */ +#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) +#define SEMC_NANDCR1_REL_MASK (0xF0000U) +#define SEMC_NANDCR1_REL_SHIFT (16U) +/*! REL - RE# LOW time + */ +#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) +#define SEMC_NANDCR1_REH_MASK (0xF00000U) +#define SEMC_NANDCR1_REH_SHIFT (20U) +/*! REH - RE# HIGH time + */ +#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) +#define SEMC_NANDCR1_TA_MASK (0xF000000U) +#define SEMC_NANDCR1_TA_SHIFT (24U) +/*! TA - Turnaround time + */ +#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) +#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) +#define SEMC_NANDCR1_CEITV_SHIFT (28U) +/*! CEITV - CE# interval time + */ +#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ + +/*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ +#define SEMC_NANDCR2_TWHR_MASK (0x3FU) +#define SEMC_NANDCR2_TWHR_SHIFT (0U) +/*! TWHR - WE# HIGH to RE# LOW wait time + */ +#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) +#define SEMC_NANDCR2_TRHW_MASK (0xFC0U) +#define SEMC_NANDCR2_TRHW_SHIFT (6U) +/*! TRHW - RE# HIGH to WE# LOW wait time + */ +#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) +#define SEMC_NANDCR2_TADL_MASK (0x3F000U) +#define SEMC_NANDCR2_TADL_SHIFT (12U) +/*! TADL - ALE to WRITE Data start wait time + */ +#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) +#define SEMC_NANDCR2_TRR_MASK (0xFC0000U) +#define SEMC_NANDCR2_TRR_SHIFT (18U) +/*! TRR - Ready to RE# LOW min wait time + */ +#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) +#define SEMC_NANDCR2_TWB_MASK (0x3F000000U) +#define SEMC_NANDCR2_TWB_SHIFT (24U) +/*! TWB - WE# HIGH to busy wait time + */ +#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ + +/*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ +#define SEMC_NANDCR3_NDOPT1_MASK (0x1U) +#define SEMC_NANDCR3_NDOPT1_SHIFT (0U) +/*! NDOPT1 - NAND option bit 1 + */ +#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) +#define SEMC_NANDCR3_NDOPT2_MASK (0x2U) +#define SEMC_NANDCR3_NDOPT2_SHIFT (1U) +/*! NDOPT2 - NAND option bit 2 + */ +#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) +#define SEMC_NANDCR3_NDOPT3_MASK (0x4U) +#define SEMC_NANDCR3_NDOPT3_SHIFT (2U) +/*! NDOPT3 - NAND option bit 3 + */ +#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +/*! @} */ + +/*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ +#define SEMC_NORCR0_PS_MASK (0x1U) +#define SEMC_NORCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) +#define SEMC_NORCR0_BL_MASK (0x70U) +#define SEMC_NORCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) +#define SEMC_NORCR0_AM_MASK (0x300U) +#define SEMC_NORCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ +#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) +#define SEMC_NORCR0_ADVP_MASK (0x400U) +#define SEMC_NORCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ +#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) +#define SEMC_NORCR0_COL_MASK (0xF000U) +#define SEMC_NORCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ + +/*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ +#define SEMC_NORCR1_CES_MASK (0xFU) +#define SEMC_NORCR1_CES_SHIFT (0U) +/*! CES - CE setup time cycle + */ +#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) +#define SEMC_NORCR1_CEH_MASK (0xF0U) +#define SEMC_NORCR1_CEH_SHIFT (4U) +/*! CEH - CE hold min time (CEH+1) cycle + */ +#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) +#define SEMC_NORCR1_AS_MASK (0xF00U) +#define SEMC_NORCR1_AS_SHIFT (8U) +/*! AS - Address setup time + */ +#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) +#define SEMC_NORCR1_AH_MASK (0xF000U) +#define SEMC_NORCR1_AH_SHIFT (12U) +/*! AH - Address hold time + */ +#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) +#define SEMC_NORCR1_WEL_MASK (0xF0000U) +#define SEMC_NORCR1_WEL_SHIFT (16U) +/*! WEL - WE LOW time (WEL+1) cycle + */ +#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) +#define SEMC_NORCR1_WEH_MASK (0xF00000U) +#define SEMC_NORCR1_WEH_SHIFT (20U) +/*! WEH - WE HIGH time (WEH+1) cycle + */ +#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) +#define SEMC_NORCR1_REL_MASK (0xF000000U) +#define SEMC_NORCR1_REL_SHIFT (24U) +/*! REL - RE LOW time (REL+1) cycle + */ +#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) +#define SEMC_NORCR1_REH_MASK (0xF0000000U) +#define SEMC_NORCR1_REH_SHIFT (28U) +/*! REH - RE HIGH time (REH+1) cycle + */ +#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ + +/*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ +#define SEMC_NORCR2_WDS_MASK (0xFU) +#define SEMC_NORCR2_WDS_SHIFT (0U) +/*! WDS - Write Data setup time (WDS+1) cycle + */ +#define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) +#define SEMC_NORCR2_WDH_MASK (0xF0U) +#define SEMC_NORCR2_WDH_SHIFT (4U) +/*! WDH - Write Data hold time (WDH+1) cycle + */ +#define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK) +#define SEMC_NORCR2_TA_MASK (0xF00U) +#define SEMC_NORCR2_TA_SHIFT (8U) +/*! TA - Turnaround time cycle + */ +#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) +#define SEMC_NORCR2_AWDH_MASK (0xF000U) +#define SEMC_NORCR2_AWDH_SHIFT (12U) +/*! AWDH - Address to write data hold time cycle + */ +#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) +#define SEMC_NORCR2_LC_MASK (0xF0000U) +#define SEMC_NORCR2_LC_SHIFT (16U) +/*! LC - Latency count + */ +#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) +#define SEMC_NORCR2_RD_MASK (0xF00000U) +#define SEMC_NORCR2_RD_SHIFT (20U) +/*! RD - Read cycle time + */ +#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) +#define SEMC_NORCR2_CEITV_MASK (0xF000000U) +#define SEMC_NORCR2_CEITV_SHIFT (24U) +/*! CEITV - CE# interval min time + */ +#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +/*! @} */ + +/*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ +#define SEMC_SRAMCR0_PS_MASK (0x1U) +#define SEMC_SRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) +#define SEMC_SRAMCR0_BL_MASK (0x70U) +#define SEMC_SRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) +#define SEMC_SRAMCR0_AM_MASK (0x300U) +#define SEMC_SRAMCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ +#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) +#define SEMC_SRAMCR0_ADVP_MASK (0x400U) +#define SEMC_SRAMCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ +#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) +#define SEMC_SRAMCR0_COL_MASK (0xF000U) +#define SEMC_SRAMCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ + +/*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ +#define SEMC_SRAMCR1_CES_MASK (0xFU) +#define SEMC_SRAMCR1_CES_SHIFT (0U) +/*! CES - CE setup time cycle + */ +#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) +#define SEMC_SRAMCR1_CEH_MASK (0xF0U) +#define SEMC_SRAMCR1_CEH_SHIFT (4U) +/*! CEH - CE hold min time (CEH+1) cycle + */ +#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) +#define SEMC_SRAMCR1_AS_MASK (0xF00U) +#define SEMC_SRAMCR1_AS_SHIFT (8U) +/*! AS - Address setup time + */ +#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) +#define SEMC_SRAMCR1_AH_MASK (0xF000U) +#define SEMC_SRAMCR1_AH_SHIFT (12U) +/*! AH - Address hold time + */ +#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) +#define SEMC_SRAMCR1_WEL_MASK (0xF0000U) +#define SEMC_SRAMCR1_WEL_SHIFT (16U) +/*! WEL - WE LOW time (WEL+1) cycle + */ +#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) +#define SEMC_SRAMCR1_WEH_MASK (0xF00000U) +#define SEMC_SRAMCR1_WEH_SHIFT (20U) +/*! WEH - WE HIGH time (WEH+1) cycle + */ +#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) +#define SEMC_SRAMCR1_REL_MASK (0xF000000U) +#define SEMC_SRAMCR1_REL_SHIFT (24U) +/*! REL - RE LOW time (REL+1) cycle + */ +#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) +#define SEMC_SRAMCR1_REH_MASK (0xF0000000U) +#define SEMC_SRAMCR1_REH_SHIFT (28U) +/*! REH - RE HIGH time (REH+1) cycle + */ +#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ + +/*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ +#define SEMC_SRAMCR2_WDS_MASK (0xFU) +#define SEMC_SRAMCR2_WDS_SHIFT (0U) +/*! WDS - Write Data setup time (WDS+1) cycle + */ +#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) +#define SEMC_SRAMCR2_WDH_MASK (0xF0U) +#define SEMC_SRAMCR2_WDH_SHIFT (4U) +/*! WDH - Write Data hold time (WDH+1) cycle + */ +#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) +#define SEMC_SRAMCR2_TA_MASK (0xF00U) +#define SEMC_SRAMCR2_TA_SHIFT (8U) +/*! TA - Turnaround time cycle + */ +#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) +#define SEMC_SRAMCR2_AWDH_MASK (0xF000U) +#define SEMC_SRAMCR2_AWDH_SHIFT (12U) +/*! AWDH - Address to write data hold time cycle + */ +#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) +#define SEMC_SRAMCR2_LC_MASK (0xF0000U) +#define SEMC_SRAMCR2_LC_SHIFT (16U) +/*! LC - Latency count + */ +#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) +#define SEMC_SRAMCR2_RD_MASK (0xF00000U) +#define SEMC_SRAMCR2_RD_SHIFT (20U) +/*! RD - Read cycle time + */ +#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) +#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) +#define SEMC_SRAMCR2_CEITV_SHIFT (24U) +/*! CEITV - CE# interval min time + */ +#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +/*! @} */ + +/*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ +#define SEMC_DBICR0_PS_MASK (0x1U) +#define SEMC_DBICR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) +#define SEMC_DBICR0_BL_MASK (0x70U) +#define SEMC_DBICR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) +#define SEMC_DBICR0_COL_MASK (0xF000U) +#define SEMC_DBICR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ + +/*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ +#define SEMC_DBICR1_CES_MASK (0xFU) +#define SEMC_DBICR1_CES_SHIFT (0U) +/*! CES - CSX Setup Time + */ +#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) +#define SEMC_DBICR1_CEH_MASK (0xF0U) +#define SEMC_DBICR1_CEH_SHIFT (4U) +/*! CEH - CSX Hold Time + */ +#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) +#define SEMC_DBICR1_WEL_MASK (0xF00U) +#define SEMC_DBICR1_WEL_SHIFT (8U) +/*! WEL - WRX Low Time + */ +#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) +#define SEMC_DBICR1_WEH_MASK (0xF000U) +#define SEMC_DBICR1_WEH_SHIFT (12U) +/*! WEH - WRX High Time + */ +#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) +#define SEMC_DBICR1_REL_MASK (0xF0000U) +#define SEMC_DBICR1_REL_SHIFT (16U) +/*! REL - RDX Low Time bit [3:0] + */ +#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) +#define SEMC_DBICR1_REH_MASK (0xF00000U) +#define SEMC_DBICR1_REH_SHIFT (20U) +/*! REH - RDX High Time bit [3:0] + */ +#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) +#define SEMC_DBICR1_CEITV_MASK (0xF000000U) +#define SEMC_DBICR1_CEITV_SHIFT (24U) +/*! CEITV - CSX interval min time + */ +#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR1_REL2_MASK (0x30000000U) +#define SEMC_DBICR1_REL2_SHIFT (28U) +/*! REL2 - RDX Low Time bit [5:4] + */ +#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) +#define SEMC_DBICR1_REH2_MASK (0xC0000000U) +#define SEMC_DBICR1_REH2_SHIFT (30U) +/*! REH2 - RDX High Time bit [5:4] + */ +#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ +#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) +#define SEMC_IPCR0_SA_SHIFT (0U) +/*! SA - Slave address + */ +#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ +#define SEMC_IPCR1_DATSZ_MASK (0x7U) +#define SEMC_IPCR1_DATSZ_SHIFT (0U) +/*! DATSZ - Data Size in Byte + * 0b000..4 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..4 + * 0b110..4 + * 0b111..4 + */ +#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +/*! @} */ + +/*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ +#define SEMC_IPCR2_BM0_MASK (0x1U) +#define SEMC_IPCR2_BM0_SHIFT (0U) +/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) +#define SEMC_IPCR2_BM1_MASK (0x2U) +#define SEMC_IPCR2_BM1_SHIFT (1U) +/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) +#define SEMC_IPCR2_BM2_MASK (0x4U) +#define SEMC_IPCR2_BM2_SHIFT (2U) +/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) +#define SEMC_IPCR2_BM3_MASK (0x8U) +#define SEMC_IPCR2_BM3_SHIFT (3U) +/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command register */ +/*! @{ */ +#define SEMC_IPCMD_CMD_MASK (0xFFFFU) +#define SEMC_IPCMD_CMD_SHIFT (0U) +#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) +#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) +#define SEMC_IPCMD_KEY_SHIFT (16U) +/*! KEY - This field should be written with 0xA55A when trigging an IP command. + */ +#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ + +/*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPTXDAT_DAT_SHIFT (0U) +#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ + +/*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPRXDAT_DAT_SHIFT (0U) +#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ + +/*! @name STS0 - Status register 0 */ +/*! @{ */ +#define SEMC_STS0_IDLE_MASK (0x1U) +#define SEMC_STS0_IDLE_SHIFT (0U) +/*! IDLE - Indicating whether SEMC is in IDLE state. + */ +#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) +#define SEMC_STS0_NARDY_MASK (0x2U) +#define SEMC_STS0_NARDY_SHIFT (1U) +/*! NARDY - Indicating NAND device Ready/WAIT# pin level. + * 0b0..NAND device is not ready + * 0b1..NAND device is ready + */ +#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ + +/*! @name STS2 - Status register 2 */ +/*! @{ */ +#define SEMC_STS2_NDWRPEND_MASK (0x8U) +#define SEMC_STS2_NDWRPEND_SHIFT (3U) +/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. + * 0b0..No pending + * 0b1..Pending + */ +#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ + +/*! @name STS12 - Status register 12 */ +/*! @{ */ +#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) +#define SEMC_STS12_NDADDR_SHIFT (0U) +/*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). + */ +#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMC_Register_Masks */ + + +/* SEMC - Peripheral instance base addresses */ +/** Peripheral SEMC base address */ +#define SEMC_BASE (0x402F0000u) +/** Peripheral SEMC base pointer */ +#define SEMC ((SEMC_Type *)SEMC_BASE) +/** Array initializer of SEMC peripheral base addresses */ +#define SEMC_BASE_ADDRS { SEMC_BASE } +/** Array initializer of SEMC peripheral base pointers */ +#define SEMC_BASE_PTRS { SEMC } +/** Interrupt vectors for the SEMC peripheral type */ +#define SEMC_IRQS { SEMC_IRQn } + +/*! + * @} + */ /* end of group SEMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + uint8_t RESERVED_2[96]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) +#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) +#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +/*! LPTDCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ + +/*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ + +/*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ + +/*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) +#define SNVS_HPSR_LPDIS_MASK (0x10U) +#define SNVS_HPSR_LPDIS_SHIFT (4U) +#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ + +/*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) +#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) +#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +/*! LPTDCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ + +/*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ + +/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ +#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ +#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) +#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) +#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ +#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) +#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) +#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +/*! ET1_EN + * 0b0..External tamper 1 is disabled. + * 0b1..External tamper 1 is enabled. + */ +#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) +#define SNVS_LPTDCR_ET1P_MASK (0x800U) +#define SNVS_LPTDCR_ET1P_SHIFT (11U) +/*! ET1P + * 0b0..External tamper 1 is active low. + * 0b1..External tamper 1 is active high. + */ +#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) +#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) +#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) +#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) +#define SNVS_LPTDCR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ +#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ + +/*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) +#define SNVS_LPSR_ET1D_MASK (0x200U) +#define SNVS_LPSR_ET1D_SHIFT (9U) +/*! ET1D + * 0b0..External tampering 1 not detected. + * 0b1..External tampering 1 detected. + */ +#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) +#define SNVS_LPSR_SED_MASK (0x100000U) +#define SNVS_LPSR_SED_SHIFT (20U) +/*! SED + * 0b0..Scan exit was not detected. + * 0b1..Scan exit was detected. + */ +#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (8U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x400D4000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ + +/*! @name SRCD - CDText Control Register */ +/*! @{ */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ + +/*! @name SRPC - PhaseConfig Register */ +/*! @{ */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ + +/*! @name SIE - InterruptEn Register */ +/*! @{ */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ + +/*! @name SIC - InterruptClear Register */ +/*! @{ */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ + +/*! @name SIS - InterruptStat Register */ +/*! @{ */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ + +/*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ + +/*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ + +/*! @name SRU - UchannelRx Register */ +/*! @{ */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ + +/*! @name SRQ - QchannelRx Register */ +/*! @{ */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ + +/*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ + +/*! @name STR - SPDIFTxRight Register */ +/*! @{ */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ + +/*! @name SRFM - FreqMeas Register */ +/*! @{ */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ + +/*! @name STC - SPDIFTxClk Register */ +/*! @{ */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b011..SPDIF_EXT_CLK, from pads + * 0b101..ipg_clk input (frequency divided) + */ +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x40380000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[16]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +/*! @{ */ +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +/*! mask_wdog_rst + * 0b0101..wdog_rst_b is masked + * 0b1010..wdog_rst_b is not masked (default) + */ +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +/*! core0_rst + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +/*! core0_dbg_rst + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +/*! dbg_rst_msk_pg + * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) + * 0b1..mask core debug resets (debug resets won't be asserted after power gating event) + */ +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +/*! mask_wdog3_rst + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +/*! ipp_reset_b + * 0b0..Reset is not a result of ipp_reset_b pin. + * 0b1..Reset is a result of ipp_reset_b pin. + */ +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) +/*! lockup_sysresetreq + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is a result of the mentioned case. + */ +#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +/*! wdog_rst_b + * 0b0..Reset is not a result of the watchdog time-out event. + * 0b1..Reset is a result of the watchdog time-out event. + */ +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of software reset from JTAG. + * 0b1..Reset is a result of software reset from JTAG. + */ +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +/*! @{ */ +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x400F8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +/* Backward compatibility */ +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[384]; + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ + uint8_t RESERVED_1[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x400D8000u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer + * @{ + */ + +/** TMR - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */ + __IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */ + __IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */ + __IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */ + __IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */ + __IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */ + __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */ + __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */ + __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */ + __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */ + __IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */ + __IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */ + uint8_t RESERVED_0[4]; + __IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */ + } CHANNEL[4]; +} TMR_Type; + +/* ---------------------------------------------------------------------------- + -- TMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Register_Masks TMR Register Masks + * @{ + */ + +/*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ +#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) +#define TMR_COMP1_COMPARISON_1_SHIFT (0U) +/*! COMPARISON_1 - Comparison Value 1 + */ +#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ + +/* The count of TMR_COMP1 */ +#define TMR_COMP1_COUNT (4U) + +/*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ +#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) +#define TMR_COMP2_COMPARISON_2_SHIFT (0U) +/*! COMPARISON_2 - Comparison Value 2 + */ +#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ + +/* The count of TMR_COMP2 */ +#define TMR_COMP2_COUNT (4U) + +/*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ +#define TMR_CAPT_CAPTURE_MASK (0xFFFFU) +#define TMR_CAPT_CAPTURE_SHIFT (0U) +/*! CAPTURE - Capture Value + */ +#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ + +/* The count of TMR_CAPT */ +#define TMR_CAPT_COUNT (4U) + +/*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ +#define TMR_LOAD_LOAD_MASK (0xFFFFU) +#define TMR_LOAD_LOAD_SHIFT (0U) +/*! LOAD - Timer Load Register + */ +#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ + +/* The count of TMR_LOAD */ +#define TMR_LOAD_COUNT (4U) + +/*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ +#define TMR_HOLD_HOLD_MASK (0xFFFFU) +#define TMR_HOLD_HOLD_SHIFT (0U) +#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ + +/* The count of TMR_HOLD */ +#define TMR_HOLD_COUNT (4U) + +/*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ +#define TMR_CNTR_COUNTER_MASK (0xFFFFU) +#define TMR_CNTR_COUNTER_SHIFT (0U) +#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ + +/* The count of TMR_CNTR */ +#define TMR_CNTR_COUNT (4U) + +/*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ +#define TMR_CTRL_OUTMODE_MASK (0x7U) +#define TMR_CTRL_OUTMODE_SHIFT (0U) +/*! OUTMODE - Output Mode + * 0b000..Asserted while counter is active + * 0b001..Clear OFLAG output on successful compare + * 0b010..Set OFLAG output on successful compare + * 0b011..Toggle OFLAG output on successful compare + * 0b100..Toggle OFLAG output using alternating compare registers + * 0b101..Set on compare, cleared on secondary source input edge + * 0b110..Set on compare, cleared on counter rollover + * 0b111..Enable gated clock output while counter is active + */ +#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) +#define TMR_CTRL_COINIT_MASK (0x8U) +#define TMR_CTRL_COINIT_SHIFT (3U) +/*! COINIT - Co-Channel Initialization + * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer + * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer + */ +#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) +#define TMR_CTRL_DIR_MASK (0x10U) +#define TMR_CTRL_DIR_SHIFT (4U) +/*! DIR - Count Direction + * 0b0..Count up. + * 0b1..Count down. + */ +#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) +#define TMR_CTRL_LENGTH_MASK (0x20U) +#define TMR_CTRL_LENGTH_SHIFT (5U) +/*! LENGTH - Count Length + * 0b0..Count until roll over at $FFFF and continue from $0000. + * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter + * reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. + * When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful + * comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 + * value is reached, re-initializes, counts until COMP1 value is reached, and so on. + */ +#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) +#define TMR_CTRL_ONCE_MASK (0x40U) +#define TMR_CTRL_ONCE_SHIFT (6U) +/*! ONCE - Count Once + * 0b0..Count repeatedly. + * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a + * COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When + * output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to + * the COMP2 value, and then stops. + */ +#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) +#define TMR_CTRL_SCS_MASK (0x180U) +#define TMR_CTRL_SCS_SHIFT (7U) +/*! SCS - Secondary Count Source + * 0b00..Counter 0 input pin + * 0b01..Counter 1 input pin + * 0b10..Counter 2 input pin + * 0b11..Counter 3 input pin + */ +#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) +#define TMR_CTRL_PCS_MASK (0x1E00U) +#define TMR_CTRL_PCS_SHIFT (9U) +/*! PCS - Primary Count Source + * 0b0000..Counter 0 input pin + * 0b0001..Counter 1 input pin + * 0b0010..Counter 2 input pin + * 0b0011..Counter 3 input pin + * 0b0100..Counter 0 output + * 0b0101..Counter 1 output + * 0b0110..Counter 2 output + * 0b0111..Counter 3 output + * 0b1000..IP bus clock divide by 1 prescaler + * 0b1001..IP bus clock divide by 2 prescaler + * 0b1010..IP bus clock divide by 4 prescaler + * 0b1011..IP bus clock divide by 8 prescaler + * 0b1100..IP bus clock divide by 16 prescaler + * 0b1101..IP bus clock divide by 32 prescaler + * 0b1110..IP bus clock divide by 64 prescaler + * 0b1111..IP bus clock divide by 128 prescaler + */ +#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) +#define TMR_CTRL_CM_MASK (0xE000U) +#define TMR_CTRL_CM_SHIFT (13U) +/*! CM - Count Mode + * 0b000..No operation + * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges + * are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising + * edges are counted regardless of the value of SCTRL[IPS]. + * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + * 0b011..Count rising edges of primary source while secondary input high active + * 0b100..Quadrature count mode, uses primary and secondary sources + * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only + * when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + * 0b110..Edge of secondary source triggers primary count until compare + * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + */ +#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ + +/* The count of TMR_CTRL */ +#define TMR_CTRL_COUNT (4U) + +/*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ +#define TMR_SCTRL_OEN_MASK (0x1U) +#define TMR_SCTRL_OEN_SHIFT (0U) +/*! OEN - Output Enable + * 0b0..The external pin is configured as an input. + * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as + * their input see the driven value. The polarity of the signal is determined by OPS. + */ +#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) +#define TMR_SCTRL_OPS_MASK (0x2U) +#define TMR_SCTRL_OPS_SHIFT (1U) +/*! OPS - Output Polarity Select + * 0b0..True polarity. + * 0b1..Inverted polarity. + */ +#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) +#define TMR_SCTRL_FORCE_MASK (0x4U) +#define TMR_SCTRL_FORCE_SHIFT (2U) +/*! FORCE - Force OFLAG Output + */ +#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) +#define TMR_SCTRL_VAL_MASK (0x8U) +#define TMR_SCTRL_VAL_SHIFT (3U) +/*! VAL - Forced OFLAG Value + */ +#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) +#define TMR_SCTRL_EEOF_MASK (0x10U) +#define TMR_SCTRL_EEOF_SHIFT (4U) +/*! EEOF - Enable External OFLAG Force + */ +#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) +#define TMR_SCTRL_MSTR_MASK (0x20U) +#define TMR_SCTRL_MSTR_SHIFT (5U) +/*! MSTR - Master Mode + */ +#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) +#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) +#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +/*! CAPTURE_MODE - Input Capture Mode + * 0b00..Capture function is disabled + * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + * 0b11..Load capture register on both edges of input + */ +#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) +#define TMR_SCTRL_INPUT_MASK (0x100U) +#define TMR_SCTRL_INPUT_SHIFT (8U) +/*! INPUT - External Input Signal + */ +#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) +#define TMR_SCTRL_IPS_MASK (0x200U) +#define TMR_SCTRL_IPS_SHIFT (9U) +/*! IPS - Input Polarity Select + */ +#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) +#define TMR_SCTRL_IEFIE_MASK (0x400U) +#define TMR_SCTRL_IEFIE_SHIFT (10U) +/*! IEFIE - Input Edge Flag Interrupt Enable + */ +#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) +#define TMR_SCTRL_IEF_MASK (0x800U) +#define TMR_SCTRL_IEF_SHIFT (11U) +/*! IEF - Input Edge Flag + */ +#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) +#define TMR_SCTRL_TOFIE_MASK (0x1000U) +#define TMR_SCTRL_TOFIE_SHIFT (12U) +/*! TOFIE - Timer Overflow Flag Interrupt Enable + */ +#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) +#define TMR_SCTRL_TOF_MASK (0x2000U) +#define TMR_SCTRL_TOF_SHIFT (13U) +/*! TOF - Timer Overflow Flag + */ +#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) +#define TMR_SCTRL_TCFIE_MASK (0x4000U) +#define TMR_SCTRL_TCFIE_SHIFT (14U) +/*! TCFIE - Timer Compare Flag Interrupt Enable + */ +#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) +#define TMR_SCTRL_TCF_MASK (0x8000U) +#define TMR_SCTRL_TCF_SHIFT (15U) +/*! TCF - Timer Compare Flag + */ +#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ + +/* The count of TMR_SCTRL */ +#define TMR_SCTRL_COUNT (4U) + +/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ +#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) +#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) +#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ + +/* The count of TMR_CMPLD1 */ +#define TMR_CMPLD1_COUNT (4U) + +/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ +#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) +#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) +#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ + +/* The count of TMR_CMPLD2 */ +#define TMR_CMPLD2_COUNT (4U) + +/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ +#define TMR_CSCTRL_CL1_MASK (0x3U) +#define TMR_CSCTRL_CL1_SHIFT (0U) +/*! CL1 - Compare Load Control 1 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) +#define TMR_CSCTRL_CL2_MASK (0xCU) +#define TMR_CSCTRL_CL2_SHIFT (2U) +/*! CL2 - Compare Load Control 2 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) +#define TMR_CSCTRL_TCF1_MASK (0x10U) +#define TMR_CSCTRL_TCF1_SHIFT (4U) +/*! TCF1 - Timer Compare 1 Interrupt Flag + */ +#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) +#define TMR_CSCTRL_TCF2_MASK (0x20U) +#define TMR_CSCTRL_TCF2_SHIFT (5U) +/*! TCF2 - Timer Compare 2 Interrupt Flag + */ +#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) +#define TMR_CSCTRL_TCF1EN_MASK (0x40U) +#define TMR_CSCTRL_TCF1EN_SHIFT (6U) +/*! TCF1EN - Timer Compare 1 Interrupt Enable + */ +#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) +#define TMR_CSCTRL_TCF2EN_MASK (0x80U) +#define TMR_CSCTRL_TCF2EN_SHIFT (7U) +/*! TCF2EN - Timer Compare 2 Interrupt Enable + */ +#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) +#define TMR_CSCTRL_UP_MASK (0x200U) +#define TMR_CSCTRL_UP_SHIFT (9U) +/*! UP - Counting Direction Indicator + * 0b0..The last count was in the DOWN direction. + * 0b1..The last count was in the UP direction. + */ +#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) +#define TMR_CSCTRL_TCI_MASK (0x400U) +#define TMR_CSCTRL_TCI_SHIFT (10U) +/*! TCI - Triggered Count Initialization Control + * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. + * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + */ +#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) +#define TMR_CSCTRL_ROC_MASK (0x800U) +#define TMR_CSCTRL_ROC_SHIFT (11U) +/*! ROC - Reload on Capture + * 0b0..Do not reload the counter on a capture event. + * 0b1..Reload the counter on a capture event. + */ +#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) +#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) +#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +/*! ALT_LOAD - Alternative Load Enable + * 0b0..Counter can be re-initialized only with the LOAD register. + * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + */ +#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) +#define TMR_CSCTRL_FAULT_MASK (0x2000U) +#define TMR_CSCTRL_FAULT_SHIFT (13U) +/*! FAULT - Fault Enable + * 0b0..Fault function disabled. + * 0b1..Fault function enabled. + */ +#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) +#define TMR_CSCTRL_DBG_EN_MASK (0xC000U) +#define TMR_CSCTRL_DBG_EN_SHIFT (14U) +/*! DBG_EN - Debug Actions Enable + * 0b00..Continue with normal operation during debug mode. (default) + * 0b01..Halt TMR counter during debug mode. + * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + * 0b11..Both halt counter and force output to 0 during debug mode. + */ +#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ + +/* The count of TMR_CSCTRL */ +#define TMR_CSCTRL_COUNT (4U) + +/*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ +#define TMR_FILT_FILT_PER_MASK (0xFFU) +#define TMR_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period + */ +#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) +#define TMR_FILT_FILT_CNT_MASK (0x700U) +#define TMR_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count + */ +#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of TMR_FILT */ +#define TMR_FILT_COUNT (4U) + +/*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ +#define TMR_DMA_IEFDE_MASK (0x1U) +#define TMR_DMA_IEFDE_SHIFT (0U) +/*! IEFDE - Input Edge Flag DMA Enable + */ +#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) +#define TMR_DMA_CMPLD1DE_MASK (0x2U) +#define TMR_DMA_CMPLD1DE_SHIFT (1U) +/*! CMPLD1DE - Comparator Preload Register 1 DMA Enable + */ +#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) +#define TMR_DMA_CMPLD2DE_MASK (0x4U) +#define TMR_DMA_CMPLD2DE_SHIFT (2U) +/*! CMPLD2DE - Comparator Preload Register 2 DMA Enable + */ +#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ + +/* The count of TMR_DMA */ +#define TMR_DMA_COUNT (4U) + +/*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ +#define TMR_ENBL_ENBL_MASK (0xFU) +#define TMR_ENBL_ENBL_SHIFT (0U) +/*! ENBL - Timer Channel Enable + * 0b0000..Timer channel is disabled. + * 0b0001..Timer channel is enabled. (default) + */ +#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ + +/* The count of TMR_ENBL */ +#define TMR_ENBL_COUNT (4U) + + +/*! + * @} + */ /* end of group TMR_Register_Masks */ + + +/* TMR - Peripheral instance base addresses */ +/** Peripheral TMR1 base address */ +#define TMR1_BASE (0x401DC000u) +/** Peripheral TMR1 base pointer */ +#define TMR1 ((TMR_Type *)TMR1_BASE) +/** Peripheral TMR2 base address */ +#define TMR2_BASE (0x401E0000u) +/** Peripheral TMR2 base pointer */ +#define TMR2 ((TMR_Type *)TMR2_BASE) +/** Peripheral TMR3 base address */ +#define TMR3_BASE (0x401E4000u) +/** Peripheral TMR3 base pointer */ +#define TMR3 ((TMR_Type *)TMR3_BASE) +/** Peripheral TMR4 base address */ +#define TMR4_BASE (0x401E8000u) +/** Peripheral TMR4 base pointer */ +#define TMR4 ((TMR_Type *)TMR4_BASE) +/** Array initializer of TMR peripheral base addresses */ +#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE } +/** Array initializer of TMR peripheral base pointers */ +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 } +/** Interrupt vectors for the TMR peripheral type */ +#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn } + +/*! + * @} + */ /* end of group TMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @{ + */ + +/** TRNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ + __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ + __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ + __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ + }; + __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ + union { /* offset: 0x14 */ + __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ + __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ + }; + __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ + union { /* offset: 0x1C */ + __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ + __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ + }; + union { /* offset: 0x20 */ + __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ + __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ + }; + union { /* offset: 0x24 */ + __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ + __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ + }; + union { /* offset: 0x28 */ + __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ + __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ + }; + union { /* offset: 0x2C */ + __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ + __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ + }; + union { /* offset: 0x30 */ + __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ + __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ + }; + union { /* offset: 0x34 */ + __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ + __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ + }; + union { /* offset: 0x38 */ + __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ + __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ + }; + __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ + __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ + __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ + __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ + __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ + __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ + __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ + __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ + __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ + __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ + __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ + __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ + uint8_t RESERVED_0[64]; + __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ + __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ +} TRNG_Type; + +/* ---------------------------------------------------------------------------- + -- TRNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @{ + */ + +/*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ +#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) +#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +/*! SAMP_MODE + * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker + * 0b01..use raw data into both Entropy shifter and Statistical Checker + * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + * 0b11..undefined/reserved. + */ +#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) +#define TRNG_MCTL_OSC_DIV_MASK (0xCU) +#define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ +#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRNG_MCTL_UNUSED4_MASK (0x10U) +#define TRNG_MCTL_UNUSED4_SHIFT (4U) +#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) +#define TRNG_MCTL_UNUSED5_MASK (0x20U) +#define TRNG_MCTL_UNUSED5_SHIFT (5U) +#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK) +#define TRNG_MCTL_RST_DEF_MASK (0x40U) +#define TRNG_MCTL_RST_DEF_SHIFT (6U) +#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) +#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) +#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) +#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) +#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) +#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) +#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) +#define TRNG_MCTL_FCT_VAL_MASK (0x200U) +#define TRNG_MCTL_FCT_VAL_SHIFT (9U) +#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) +#define TRNG_MCTL_ENT_VAL_MASK (0x400U) +#define TRNG_MCTL_ENT_VAL_SHIFT (10U) +#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) +#define TRNG_MCTL_TST_OUT_MASK (0x800U) +#define TRNG_MCTL_TST_OUT_SHIFT (11U) +#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) +#define TRNG_MCTL_ERR_MASK (0x1000U) +#define TRNG_MCTL_ERR_SHIFT (12U) +#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) +#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) +#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) +#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) +#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) +#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) +#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) +#define TRNG_MCTL_PRGM_MASK (0x10000U) +#define TRNG_MCTL_PRGM_SHIFT (16U) +#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ + +/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ +#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) +#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) +#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) +#define TRNG_SCMISC_RTY_CT_SHIFT (16U) +#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ + +/*! @name PKRRNG - Poker Range Register */ +/*! @{ */ +#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) +#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) +#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ + +/*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ +#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) +#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) +/*! PKR_MAX - Poker Maximum Limit. + */ +#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ + +/*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ +#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) +#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) +/*! PKR_SQ - Poker Square Calculation Result. + */ +#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ + +/*! @name SDCTL - Seed Control Register */ +/*! @{ */ +#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) +#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) +#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) +#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) +#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) +#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ + +/*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ +#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) +#define TRNG_SBLIM_SB_LIM_SHIFT (0U) +#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ + +/*! @name TOTSAM - Total Samples Register */ +/*! @{ */ +#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) +#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) +#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ + +/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ +#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) +#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) +#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ + +/*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ +#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) +#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ +#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) +#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) +#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ + +/*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ +#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) +#define TRNG_SCMC_MONO_CT_SHIFT (0U) +#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ + +/*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ +#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) +#define TRNG_SCML_MONO_MAX_SHIFT (0U) +#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) +#define TRNG_SCML_MONO_RNG_SHIFT (16U) +#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ + +/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ +#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) +#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) +#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) +#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) +#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ + +/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ +#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) +#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) +#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) +#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) +#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ + +/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ +#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) +#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) +#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) +#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) +#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ + +/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ +#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) +#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) +#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) +#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) +#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) +#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ + +/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ +#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) +#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) +#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) +#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) +#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) +#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ + +/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ +#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) +#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) +#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) +#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) +#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) +#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ + +/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ +#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) +#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) +#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) +#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) +#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) +#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ + +/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ +#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) +#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) +#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) +#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) +#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) +#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ + +/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ +#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) +#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) +#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) +#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) +#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ + +/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ +#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) +#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) +#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) +#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) +#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) +#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ + +/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ +#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) +#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) +#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) +#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) +#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ + +/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ +#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) +#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) +#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) +#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) +#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) +#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ +#define TRNG_STATUS_TF1BR0_MASK (0x1U) +#define TRNG_STATUS_TF1BR0_SHIFT (0U) +#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) +#define TRNG_STATUS_TF1BR1_MASK (0x2U) +#define TRNG_STATUS_TF1BR1_SHIFT (1U) +#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) +#define TRNG_STATUS_TF2BR0_MASK (0x4U) +#define TRNG_STATUS_TF2BR0_SHIFT (2U) +#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) +#define TRNG_STATUS_TF2BR1_MASK (0x8U) +#define TRNG_STATUS_TF2BR1_SHIFT (3U) +#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) +#define TRNG_STATUS_TF3BR0_MASK (0x10U) +#define TRNG_STATUS_TF3BR0_SHIFT (4U) +#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) +#define TRNG_STATUS_TF3BR1_MASK (0x20U) +#define TRNG_STATUS_TF3BR1_SHIFT (5U) +#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) +#define TRNG_STATUS_TF4BR0_MASK (0x40U) +#define TRNG_STATUS_TF4BR0_SHIFT (6U) +#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) +#define TRNG_STATUS_TF4BR1_MASK (0x80U) +#define TRNG_STATUS_TF4BR1_SHIFT (7U) +#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) +#define TRNG_STATUS_TF5BR0_MASK (0x100U) +#define TRNG_STATUS_TF5BR0_SHIFT (8U) +#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) +#define TRNG_STATUS_TF5BR1_MASK (0x200U) +#define TRNG_STATUS_TF5BR1_SHIFT (9U) +#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) +#define TRNG_STATUS_TF6PBR0_MASK (0x400U) +#define TRNG_STATUS_TF6PBR0_SHIFT (10U) +#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) +#define TRNG_STATUS_TF6PBR1_MASK (0x800U) +#define TRNG_STATUS_TF6PBR1_SHIFT (11U) +#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) +#define TRNG_STATUS_TFSB_MASK (0x1000U) +#define TRNG_STATUS_TFSB_SHIFT (12U) +#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) +#define TRNG_STATUS_TFLR_MASK (0x2000U) +#define TRNG_STATUS_TFLR_SHIFT (13U) +#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) +#define TRNG_STATUS_TFP_MASK (0x4000U) +#define TRNG_STATUS_TFP_SHIFT (14U) +#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) +#define TRNG_STATUS_TFMB_MASK (0x8000U) +#define TRNG_STATUS_TFMB_SHIFT (15U) +#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) +#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) +#define TRNG_STATUS_RETRY_CT_SHIFT (16U) +#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ + +/*! @name ENT - Entropy Read Register */ +/*! @{ */ +#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) +#define TRNG_ENT_ENT_SHIFT (0U) +#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ + +/* The count of TRNG_ENT */ +#define TRNG_ENT_COUNT (16U) + +/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ +#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) +#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) +#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) +#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ + +/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ +#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) +#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) +#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) +#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ + +/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ +#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) +#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) +#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) +#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ + +/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ +#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) +#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) +#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) +#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ + +/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ +#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) +#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) +#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) +#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ + +/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ +#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) +#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) +#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) +#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ + +/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ +#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) +#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) +#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) +#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ + +/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ +#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) +#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) +#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) +#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ + +/*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ +#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) +#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) +#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) +#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) +#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + */ +#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) +#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) +#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) +#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ + +/*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ +#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) +#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding bit of INT_STATUS register cleared. + * 0b1..Corresponding bit of INT_STATUS register active. + */ +#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) +#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) +#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) +#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) +#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) +#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ + +/*! @name INT_MASK - Mask Register */ +/*! @{ */ +#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) +#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding interrupt of INT_STATUS is masked. + * 0b1..Corresponding bit of INT_STATUS is active. + */ +#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) +#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) +#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) +#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) +#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..no error + * 0b1..error detected. + */ +#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) +#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) +#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generation entropy. Any value read is invalid. + * 0b1..TRNG can be stopped and entropy is valid if read. + */ +#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ +#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ +#define TRNG_VID1_MIN_REV_MASK (0xFFU) +#define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00000000..Minor revision number for TRNG. + */ +#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) +#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) +#define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00000001..Major revision number for TRNG. + */ +#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) +#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) +#define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ +#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ + +/*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ +#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) +#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ +#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) +#define TRNG_VID2_ECO_REV_MASK (0xFF00U) +#define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ +#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) +#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) +#define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00000000..INTG_OPT for TRNG. + */ +#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) +#define TRNG_VID2_ERA_MASK (0xFF000000U) +#define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00000000..COMPILE_OPT for TRNG. + */ +#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRNG_Register_Masks */ + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG base address */ +#define TRNG_BASE (0x400CC000u) +/** Peripheral TRNG base pointer */ +#define TRNG ((TRNG_Type *)TRNG_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG_IRQn } + +/*! + * @} + */ /* end of group TRNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< Basic Setting, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PRE_CHARGE_TIME; /**< Pre-charge Time, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< Debug Mode Register, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< Debug Mode Register 2, offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - Basic Setting */ +/*! @{ */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +/*! AUTO_MEASURE - Auto Measure + * 0b0..Disable Auto Measure + * 0b1..Auto Measure + */ +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING_WIRE_4_5_MASK (0x10U) +#define TSC_BASIC_SETTING_WIRE_4_5_SHIFT (4U) +/*! WIRE_4_5 - 4/5 Wire detection + * 0b0..4-Wire Detection Mode + * 0b1..5-Wire Detection Mode + */ +#define TSC_BASIC_SETTING_WIRE_4_5(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_WIRE_4_5_SHIFT)) & TSC_BASIC_SETTING_WIRE_4_5_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +/*! MEASURE_DELAY_TIME - Measure Delay Time + */ +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ + +/*! @name PRE_CHARGE_TIME - Pre-charge Time */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ + +/*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +/*! SW_RST - Soft Reset + */ +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +/*! START_MEASURE - Start Measure + * 0b0..Do not start measure for now + * 0b1..Start measure the X/Y coordinate value + */ +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +/*! DROP_MEASURE - Drop Measure + * 0b0..Do not drop measure for now + * 0b1..Drop the measure and controller return to idle status + */ +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +/*! START_SENSE - Start Sense + * 0b0..Stay at idle status + * 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch + */ +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +/*! DISABLE + * 0b0..Leave HW state machine control + * 0b1..SW set to idle status + */ +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ + +/*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +/*! Y_VALUE - Y Value + */ +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +/*! X_VALUE - X Value + */ +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ + +/*! @name INT_EN - Interrupt Enable */ +/*! @{ */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +/*! MEASURE_INT_EN - Measure Interrupt Enable + * 0b0..Disable measure interrupt + * 0b1..Enable measure interrupt + */ +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +/*! DETECT_INT_EN - Detect Interrupt Enable + * 0b0..Disable detect interrupt + * 0b1..Enable detect interrupt + */ +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable + * 0b0..Disable idle software interrupt + * 0b1..Enable idle software interrupt + */ +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +/*! MEASURE_SIG_EN - Measure Signal Enable + */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +/*! DETECT_SIG_EN - Detect Signal Enable + * 0b0..Disable detect signal + * 0b1..Enable detect signal + */ +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +/*! VALID_SIG_EN - Valid Signal Enable + * 0b0..Disable valid signal + * 0b1..Enable valid signal + */ +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +/*! IDLE_SW_SIG_EN - Idle Software Signal Enable + * 0b0..Disable idle software signal + * 0b1..Enable idle software signal + */ +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ + +/*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +/*! MEASURE - Measure Signal + * 0b0..Does not exist a measure signal + * 0b1..Exist a measure signal + */ +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +/*! DETECT - Detect Signal + * 0b0..Does not exist a detect signal + * 0b1..Exist detect signal + */ +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +/*! VALID - Valid Signal + * 0b0..There is no touch detected after measurement, indicates that the measured value is not valid + * 0b1..There is touch detection after measurement, indicates that the measure is valid + */ +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +/*! IDLE_SW - Idle Software + * 0b0..Haven't return to idle status + * 0b1..Already return to idle status + */ +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ + +/*! @name DEBUG_MODE - Debug Mode Register */ +/*! @{ */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +/*! ADC_CONV_VALUE - ADC Conversion Value + */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +/*! ADC_COCO - ADC COCO Signal + */ +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +/*! EXT_HWTS - Hardware Trigger Select Signal + */ +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger + * 0b0..No hardware trigger signal + * 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period + */ +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +/*! ADC_COCO_CLEAR - ADC Coco Clear + * 0b0..No ADC COCO clear + * 0b1..Set ADC COCO clear + */ +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable + * 0b0..Allow TSC hardware generates ADC COCO clear + * 0b1..Prevent TSC from generate ADC COCO clear signal + */ +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +/*! DEBUG_EN - Debug Enable + * 0b0..Enable debug mode + * 0b1..Disable debug mode + */ +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ + +/*! @name DEBUG_MODE2 - Debug Mode Register 2 */ +/*! @{ */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open the switch + */ +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +/*! DETECT_FOUR_WIRE - Detect Four Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +/*! DETECT_FIVE_WIRE - Detect Five Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +/*! STATE_MACHINE - State Machine + * 0b000..Idle + * 0b001..Pre-charge + * 0b010..Detect + * 0b011..X-measure + * 0b100..Y-measure + * 0b101..Pre-charge + * 0b110..Detect + */ +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +/*! INTERMEDIATE - Intermediate State + * 0b0..Not in intermedia + * 0b1..Intermedia + */ +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire + * 0b0..Do not read four wire detect value, read default value from analogue + * 0b1..Read four wire detect status from analogue + */ +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire + * 0b0..Do not read five wire detect value, read default value from analogue + * 0b1..Read five wire detect status from analogue + */ +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +/*! DE_GLITCH + * 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + * 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + * 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + * 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + */ +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x400E0000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_DIG_IRQn } +/* Backward compatibility */ +#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_WIRE_4_5_MASK +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_WIRE_4_5_SHIFT +#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_WIRE_4_5(x) + + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW + * 0b00..8 bit wide data bus Software non-programmable + * 0b01..16 bit wide data bus Software non-programmable + * 0b10..Reset to 8 bit wide data bus Software programmable + * 0b11..Reset to 16 bit wide data bus Software programmable + */ +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +/*! SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +/*! HC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command Register */ +/*! @{ */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 + * 0b0..1024 elements (4096 bytes) Default value + * 0b1..512 elements (2048 bytes) + */ +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status Register */ +/*! @{ */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition. + */ +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +/*! LS + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + */ +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +/*! CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +/*! ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + */ +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x402E0000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x402E0200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } +#define USBHS_IRQHandler USB_OTG1_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */ + uint8_t RESERVED_1[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS + * 0b1..Disables overcurrent detection + * 0b0..Enables overcurrent detection + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +/*! PWR_POL + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +/*! WIE + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +/*! WKUP_SW + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN + * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. + */ +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +/*! WIR + * 0b1..Wake-up Interrupt Request received + * 0b0..No wake-up interrupt request received + */ +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ + +/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x402E0000u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x402E0004u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ + +/*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x400D9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x400DA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[416]; + struct { /* offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t LOOPBACK; /**< USB Loopback Test Register, array offset: 0x1E0, array step: 0x60 */ + __IO uint32_t LOOPBACK_SET; /**< USB Loopback Test Register, array offset: 0x1E4, array step: 0x60 */ + __IO uint32_t LOOPBACK_CLR; /**< USB Loopback Test Register, array offset: 0x1E8, array step: 0x60 */ + __IO uint32_t LOOPBACK_TOG; /**< USB Loopback Test Register, array offset: 0x1EC, array step: 0x60 */ + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..The USB plug has not made contact. + * 0b1..The USB plug has made good contact. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..The USB port is not connected to a charger. + * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name LOOPBACK - USB Loopback Test Register */ +/*! @{ */ +#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U) +#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U) +#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK) +/*! @} */ + +/* The count of USB_ANALOG_LOOPBACK */ +#define USB_ANALOG_LOOPBACK_COUNT (2U) + +/*! @name LOOPBACK_SET - USB Loopback Test Register */ +/*! @{ */ +#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U) +#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U) +#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK) +/*! @} */ + +/* The count of USB_ANALOG_LOOPBACK_SET */ +#define USB_ANALOG_LOOPBACK_SET_COUNT (2U) + +/*! @name LOOPBACK_CLR - USB Loopback Test Register */ +/*! @{ */ +#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U) +#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U) +#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK) +/*! @} */ + +/* The count of USB_ANALOG_LOOPBACK_CLR */ +#define USB_ANALOG_LOOPBACK_CLR_COUNT (2U) + +/*! @name LOOPBACK_TOG - USB Loopback Test Register */ +/*! @{ */ +#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U) +#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U) +#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK) +/*! @} */ + +/* The count of USB_ANALOG_LOOPBACK_TOG */ +#define USB_ANALOG_LOOPBACK_TOG_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +/*! SILICON_REVISION + * 0b00000000011010100000000000000001..Silicon revision 1.1 + */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x400D8000u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +/*! DS_ADDR - DS_ADDR + */ +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Block Size + * 0b1000000000000..4096 Bytes + * 0b0100000000000..2048 Bytes + * 0b0001000000000..512 Bytes + * 0b0000111111111..511 Bytes + * 0b0000000000100..4 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000010..2 Bytes + * 0b0000000000001..1 Byte + * 0b0000000000000..No data transfer + */ +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Block Count + * 0b1111111111111111..65535 blocks + * 0b0000000000000010..2 blocks + * 0b0000000000000001..1 block + * 0b0000000000000000..Stop Count + */ +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +/*! CMDARG - Command Argument + */ +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No Response + * 0b01..Response Length 136 + * 0b10..Response Length 48 + * 0b11..Response Length 48, check Busy after response + */ +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b1..Data Present + * 0b0..No Data Present + */ +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + * 0b10..Resume CMD52 for writing Function Select in CCCR + * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR + * 0b00..Normal Other commands + */ +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +/*! CMDINX - Command Index + */ +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +/*! CMDRSP0 - Command Response 0 + */ +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +/*! CMDRSP1 - Command Response 1 + */ +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +/*! CMDRSP2 - Command Response 2 + */ +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +/*! CMDRSP3 - Command Response 3 + */ +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +/*! DATCONT - Data Content + */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b1..Cannot issue command + * 0b0..Can issue command using only CMD line + */ +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DATA) + * 0b1..Cannot issue command which uses the DATA line + * 0b0..Can issue command which uses the DATA line + */ +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b1..DATA Line Active + * 0b0..DATA Line Inactive + */ +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b1..Clock is stable. + * 0b0..Clock is changing frequency and not stable. + */ +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +/*! IPGOFF - IPG_CLK Gated Off Internally + * 0b1..IPG_CLK is gated off. + * 0b0..IPG_CLK is active. + */ +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +/*! HCKOFF - HCLK Gated Off Internally + * 0b1..HCLK is gated off. + * 0b0..HCLK is active. + */ +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +/*! PEROFF - IPG_PERCLK Gated Off Internally + * 0b1..IPG_PERCLK is gated off. + * 0b0..IPG_PERCLK is active. + */ +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b1..SD Clock is gated off. + * 0b0..SD Clock is active. + */ +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b1..Write enable + * 0b0..Write disable + */ +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b1..Read enable + * 0b0..Read disable + */ +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Sampling clock needs re-tuning + * 0b0..Fixed or well tuned sampling clock + */ +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tape Select Change Done + * 0b1..Delay cell select change is finished. + * 0b0..Delay cell select change is not finished. + */ +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card Inserted + * 0b1..Card Inserted + * 0b0..Power on Reset or No Card + */ +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card Detect Pin Level + * 0b1..Card present (CD_B = 0) + * 0b0..No card present (CD_B = 1) + */ +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write Protect Switch Pin Level + * 0b1..Write enabled (WP = 0) + * 0b0..Write protected (WP = 1) + */ +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +/*! CLSL - CMD Line Signal Level + */ +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] Line Signal Level + * 0b00000111..Data 7 line signal level + * 0b00000110..Data 6 line signal level + * 0b00000101..Data 5 line signal level + * 0b00000100..Data 4 line signal level + * 0b00000011..Data 3 line signal level + * 0b00000010..Data 2 line signal level + * 0b00000001..Data 1 line signal level + * 0b00000000..Data 0 line signal level + */ +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b1..LED on + * 0b0..LED off + */ +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b10..8-bit mode + * 0b01..4-bit mode + * 0b00..1-bit mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as Card Detection Pin + * 0b1..DATA3 as Card Detection Pin + * 0b0..DATA3 does not monitor Card Insertion + */ +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big Endian Mode + * 0b01..Half Word Big Endian Mode + * 0b10..Little Endian Mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b1..Card Detect Test Level is 1, card inserted + * 0b0..Card Detect Test Level is 0, no card inserted + */ +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b1..Card Detection Test Level is selected (for test purpose). + * 0b0..Card Detection Level is selected (for normal purpose). + */ +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA Select + * 0b00..No DMA or Simple DMA is selected + * 0b01..ADMA1 is selected + * 0b10..ADMA2 is selected + * 0b11..reserved + */ +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b1..Stop + * 0b0..Transfer + */ +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b1..Restart + * 0b0..No effect + */ +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + */ +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b1..Enabled + * 0b0..Disabled + */ +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +/*! RD_DONE_NO_8CLK - RD_DONE_NO_8CLK + */ +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + * 0bxx1..Burst length is enabled for INCR + * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 + * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + */ +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + */ +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +/*! SDCLKFS - SDCLK Frequency Select + */ +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +/*! IPP_RST_N - IPP_RST_N + */ +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DATA Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +/*! INITA - Initialization Active + */ +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +/*! RSTT - Reset Tuning + */ +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b1..Command complete + * 0b0..Command not complete + */ +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b1..Transfer complete + * 0b0..Transfer not complete + */ +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b1..Transaction stopped at block gap + * 0b0..No block gap event + */ +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b1..DMA Interrupt is generated + * 0b0..No DMA Interrupt + */ +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b1..Ready to write buffer: + * 0b0..Not ready to write buffer + */ +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b1..Ready to read buffer + * 0b0..Not ready to read buffer + */ +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b1..Card inserted + * 0b0..Card state unstable or removed + */ +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b1..Card removed + * 0b0..Card state unstable or inserted + */ +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b1..Generate Card Interrupt + * 0b0..No Card Interrupt + */ +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Re-Tuning should be performed + * 0b0..Re-Tuning is not required + */ +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +/*! TP - Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) + */ +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b1..CRC Error Generated. + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +/*! TNE - Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + */ +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card Insertion Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-Tuning Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +/*! TPSEN - Tuning Pass Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-Tuning Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b1..Enable + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b1..Not executed + * 0b0..Executed + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 Timeout Error + * 0b1..Time out + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 / 23 End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 / 23 CRC Error + * 0b1..CRC Error Met in Auto CMD12/23 Response + * 0b0..No CRC error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 Index Error + * 0b1..Error, the CMD index in response is not CMD12/23 + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b1..Not Issued + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +/*! EXECUTE_TUNING - Execute Tuning + */ +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample Clock Select + * 0b1..Tuned clock is used to sample data + * 0b0..Fixed clock is used to sample data + */ +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +/*! SDR50_SUPPORT - SDR50 support + */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +/*! SDR104_SUPPORT - SDR104 support + */ +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +/*! DDR50_SUPPORT - DDR50 support + */ +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +/*! TIME_COUNT_RETUNING - Time Counter for Retuning + */ +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b1..SDR50 requires tuning + * 0b0..SDR does not require tuning + */ +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +/*! RETUNING_MODE - Retuning Mode + * 0b00..Mode 1 + * 0b01..Mode 2 + * 0b10..Mode 3 + * 0b11..Reserved + */ +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b1..Advanced DMA Supported + * 0b0..Advanced DMA Not supported + */ +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b1..High Speed Supported + * 0b0..High Speed Not Supported + */ +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b1..DMA Supported + * 0b0..DMA not supported + */ +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / Resume Support + * 0b1..Supported + * 0b0..Not supported + */ +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3V + * 0b1..3.3V supported + * 0b0..3.3V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage Support 3.0 V + * 0b1..3.0V supported + * 0b0..3.0V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage Support 1.8 V + * 0b1..1.8V supported + * 0b0..1.8V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +/*! RD_WML - Read Watermark Level + */ +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +/*! RD_BRST_LEN - Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + */ +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +/*! WR_WML - Write Watermark Level + */ +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +/*! WR_BRST_LEN - Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + */ +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +/*! DDR_EN - Dual Data Rate mode selection + */ +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b1..Read (Card to Host) + * 0b0..Write (Host to Card) + */ +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single Block Select + * 0b1..Multiple Blocks + * 0b0..Single Block + */ +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +/*! NIBBLE_POS - NIBBLE_POS + */ +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +/*! AC23EN - Auto CMD23 Enable + */ +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Execute Tuning + * 0b0..Not Tuned or Tuning Completed + */ +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - SMP_CLK_SEL + * 0b1..Tuned clock is used to sample data / cmd + * 0b0..Fixed clock is used to sample data / cmd + */ +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + * 0b1..Enable auto tuning + * 0b0..Disable auto tuning + */ +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Feedback clock comes from the ipp_card_clk_out + * 0b0..Feedback clock comes from the loopback CLK + */ +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +/*! FEVTAC12NE - Force Event Auto Command 12 Not Executed + */ +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +/*! FEVTAC12TOE - Force Event Auto Command 12 Time Out Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +/*! FEVTAC12CE - Force Event Auto Command 12 CRC Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +/*! FEVTAC12EBE - Force Event Auto Command 12 End Bit Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +/*! FEVTAC12IE - Force Event Auto Command 12 Index Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +/*! FEVTCNIBAC12E - Force Event Command Not Executed By Auto Command 12 Error + */ +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +/*! FEVTCTOE - Force Event Command Time Out Error + */ +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +/*! FEVTCCE - Force Event Command CRC Error + */ +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +/*! FEVTCEBE - Force Event Command End Bit Error + */ +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +/*! FEVTCIE - Force Event Command Index Error + */ +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +/*! FEVTDTOE - Force Event Data Time Out Error + */ +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +/*! FEVTDCE - Force Event Data CRC Error + */ +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +/*! FEVTDEBE - Force Event Data End Bit Error + */ +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +/*! FEVTAC12E - Force Event Auto Command 12 Error + */ +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +/*! FEVTTNE - Force Tuning Error + */ +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +/*! FEVTDMAE - Force Event DMA Error + */ +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +/*! FEVTCINT - Force Event Card Interrupt + */ +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +/*! ADMAES - ADMA Error State (when ADMA Error is occurred) + */ +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descriptor Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +/*! ADS_ADDR - ADMA System Address + */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +/*! DLL_CTRL_ENABLE - DLL_CTRL_ENABLE + */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +/*! DLL_CTRL_RESET - DLL_CTRL_RESET + */ +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +/*! DLL_CTRL_SLV_FORCE_UPD - DLL_CTRL_SLV_FORCE_UPD + */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL_CTRL_SLV_DLY_TARGET0 + */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +/*! DLL_CTRL_GATE_UPDATE - DLL_CTRL_GATE_UPDATE + */ +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +/*! DLL_CTRL_SLV_OVERRIDE - DLL_CTRL_SLV_OVERRIDE + */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL_CTRL_SLV_OVERRIDE_VAL + */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL_CTRL_SLV_DLY_TARGET1 + */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +/*! DLL_CTRL_SLV_UPDATE_INT - DLL_CTRL_SLV_UPDATE_INT + */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +/*! DLL_CTRL_REF_UPDATE_INT - DLL_CTRL_REF_UPDATE_INT + */ +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +/*! DLL_STS_SLV_LOCK - DLL_STS_SLV_LOCK + */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +/*! DLL_STS_REF_LOCK - DLL_STS_REF_LOCK + */ +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +/*! DLL_STS_SLV_SEL - DLL_STS_SLV_SEL + */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +/*! DLL_STS_REF_SEL - DLL_STS_REF_SEL + */ +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +/*! DLY_CELL_SET_POST - DLY_CELL_SET_POST + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +/*! DLY_CELL_SET_OUT - DLY_CELL_SET_OUT + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +/*! DLY_CELL_SET_PRE - DLY_CELL_SET_PRE + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +/*! NXT_ERR - NXT_ERR + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +/*! TAP_SEL_POST - TAP_SEL_POST + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +/*! TAP_SEL_OUT - TAP_SEL_OUT + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +/*! TAP_SEL_PRE - TAP_SEL_PRE + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +/*! PRE_ERR - PRE_ERR + */ +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage Selection + * 0b1..Change the voltage to low voltage range, around 1.8 V + * 0b0..Change the voltage to high voltage range, around 3.0 V + */ +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +/*! CONFLICT_CHK_EN - Conflict check enable. + * 0b0..Conflict check disable + * 0b1..Conflict check enable + */ +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - FRC_SDCLK_ON + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active. + */ +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - CMD_BYTE_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^14 + * 0b0001..SDCLK x 2^15 + * 0b0010..SDCLK x 2^16 + * 0b0011..SDCLK x 2^17 + * 0b0100..SDCLK x 2^18 + * 0b0101..SDCLK x 2^19 + * 0b0110..SDCLK x 2^20 + * 0b0111..SDCLK x 2^21 + * 0b1110..SDCLK x 2^28 + * 0b1111..SDCLK x 2^29 + */ +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT_ACK + * 0b0..No ack + * 0b1..Ack + */ +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - BOOT_MODE + * 0b0..Normal boot + * 0b1..Alternative boot + */ +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - BOOT_EN + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +/*! AUTO_SABG_EN - AUTO_SABG_EN + */ +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Disable Time Out + * 0b0..Enable time out + * 0b1..Disable time out + */ +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +/*! BOOT_BLK_CNT - BOOT_BLK_CNT + */ +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card Interrupt Detection Test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +/*! TUNING_8bit_EN - TUNING_8bit_EN + */ +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +/*! TUNING_1bit_EN - TUNING_1bit_EN + */ +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - TUNING_CMD_EN + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + * 0b0..Disable + */ +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +/*! PART_DLL_DEBUG - debug for part dll + */ +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +/*! BUS_RST - BUS reset + */ +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +/*! TUNING_START_TAP - TUNING_START_TAP + */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +/*! TUNING_COUNTER - TUNING_COUNTER + */ +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +/*! TUNING_STEP - TUNING_STEP + */ +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +/*! TUNING_WINDOW - TUNING_WINDOW + */ +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +/*! STD_TUNING_EN - STD_TUNING_EN + */ +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x402C0000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x402C4000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +/*! @{ */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST - WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG - WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE - WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS - SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA - WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - software reset extension, an option way to generate software reset + * 0b0..using original way to generate software reset (default) + * 0b1..using new way to generate software reset. + */ +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW - WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +/*! WT - WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ + +/*! @name WSR - Watchdog Service Register */ +/*! @{ */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR - WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ + +/*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW - SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT - TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +/*! POR - POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ + +/*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT - WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS - WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE - WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE - PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x400B8000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x400D0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer + * @{ + */ + +/** XBARA - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */ + __IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */ + __IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */ + __IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */ + __IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */ + __IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */ + __IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */ + __IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */ + __IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */ + __IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */ + __IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */ + __IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */ + __IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */ + __IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */ + __IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */ + __IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */ + __IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */ + __IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */ + __IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */ + __IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */ + __IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */ + __IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */ + __IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */ + __IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */ + __IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */ + __IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */ + __IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */ + __IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */ + __IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */ + __IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */ + __IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */ + __IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */ + __IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */ + __IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */ + __IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */ + __IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */ + __IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */ + __IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */ + __IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */ + __IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */ + __IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */ + __IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */ + __IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */ + __IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */ + __IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */ + __IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */ + __IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */ + __IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */ + __IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */ + __IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */ + __IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */ + __IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */ + __IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */ + __IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */ + __IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */ + __IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */ + __IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */ + __IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */ + __IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */ + __IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */ + __IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */ +} XBARA_Type; + +/* ---------------------------------------------------------------------------- + -- XBARA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Register_Masks XBARA Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ +#define XBARA_SEL0_SEL0_MASK (0x7FU) +#define XBARA_SEL0_SEL0_SHIFT (0U) +#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) +#define XBARA_SEL0_SEL1_MASK (0x7F00U) +#define XBARA_SEL0_SEL1_SHIFT (8U) +#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ +#define XBARA_SEL1_SEL2_MASK (0x7FU) +#define XBARA_SEL1_SEL2_SHIFT (0U) +#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) +#define XBARA_SEL1_SEL3_MASK (0x7F00U) +#define XBARA_SEL1_SEL3_SHIFT (8U) +#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ +#define XBARA_SEL2_SEL4_MASK (0x7FU) +#define XBARA_SEL2_SEL4_SHIFT (0U) +#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) +#define XBARA_SEL2_SEL5_MASK (0x7F00U) +#define XBARA_SEL2_SEL5_SHIFT (8U) +#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ +#define XBARA_SEL3_SEL6_MASK (0x7FU) +#define XBARA_SEL3_SEL6_SHIFT (0U) +#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) +#define XBARA_SEL3_SEL7_MASK (0x7F00U) +#define XBARA_SEL3_SEL7_SHIFT (8U) +#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ +#define XBARA_SEL4_SEL8_MASK (0x7FU) +#define XBARA_SEL4_SEL8_SHIFT (0U) +#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) +#define XBARA_SEL4_SEL9_MASK (0x7F00U) +#define XBARA_SEL4_SEL9_SHIFT (8U) +#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ +#define XBARA_SEL5_SEL10_MASK (0x7FU) +#define XBARA_SEL5_SEL10_SHIFT (0U) +#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) +#define XBARA_SEL5_SEL11_MASK (0x7F00U) +#define XBARA_SEL5_SEL11_SHIFT (8U) +#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ +#define XBARA_SEL6_SEL12_MASK (0x7FU) +#define XBARA_SEL6_SEL12_SHIFT (0U) +#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) +#define XBARA_SEL6_SEL13_MASK (0x7F00U) +#define XBARA_SEL6_SEL13_SHIFT (8U) +#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ +#define XBARA_SEL7_SEL14_MASK (0x7FU) +#define XBARA_SEL7_SEL14_SHIFT (0U) +#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) +#define XBARA_SEL7_SEL15_MASK (0x7F00U) +#define XBARA_SEL7_SEL15_SHIFT (8U) +#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ + +/*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ +#define XBARA_SEL8_SEL16_MASK (0x7FU) +#define XBARA_SEL8_SEL16_SHIFT (0U) +#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) +#define XBARA_SEL8_SEL17_MASK (0x7F00U) +#define XBARA_SEL8_SEL17_SHIFT (8U) +#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ + +/*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ +#define XBARA_SEL9_SEL18_MASK (0x7FU) +#define XBARA_SEL9_SEL18_SHIFT (0U) +#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) +#define XBARA_SEL9_SEL19_MASK (0x7F00U) +#define XBARA_SEL9_SEL19_SHIFT (8U) +#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ + +/*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ +#define XBARA_SEL10_SEL20_MASK (0x7FU) +#define XBARA_SEL10_SEL20_SHIFT (0U) +#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) +#define XBARA_SEL10_SEL21_MASK (0x7F00U) +#define XBARA_SEL10_SEL21_SHIFT (8U) +#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ + +/*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ +#define XBARA_SEL11_SEL22_MASK (0x7FU) +#define XBARA_SEL11_SEL22_SHIFT (0U) +#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) +#define XBARA_SEL11_SEL23_MASK (0x7F00U) +#define XBARA_SEL11_SEL23_SHIFT (8U) +#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ + +/*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ +#define XBARA_SEL12_SEL24_MASK (0x7FU) +#define XBARA_SEL12_SEL24_SHIFT (0U) +#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) +#define XBARA_SEL12_SEL25_MASK (0x7F00U) +#define XBARA_SEL12_SEL25_SHIFT (8U) +#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ + +/*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ +#define XBARA_SEL13_SEL26_MASK (0x7FU) +#define XBARA_SEL13_SEL26_SHIFT (0U) +#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) +#define XBARA_SEL13_SEL27_MASK (0x7F00U) +#define XBARA_SEL13_SEL27_SHIFT (8U) +#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ + +/*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ +#define XBARA_SEL14_SEL28_MASK (0x7FU) +#define XBARA_SEL14_SEL28_SHIFT (0U) +#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) +#define XBARA_SEL14_SEL29_MASK (0x7F00U) +#define XBARA_SEL14_SEL29_SHIFT (8U) +#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ + +/*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ +#define XBARA_SEL15_SEL30_MASK (0x7FU) +#define XBARA_SEL15_SEL30_SHIFT (0U) +#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) +#define XBARA_SEL15_SEL31_MASK (0x7F00U) +#define XBARA_SEL15_SEL31_SHIFT (8U) +#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ + +/*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ +#define XBARA_SEL16_SEL32_MASK (0x7FU) +#define XBARA_SEL16_SEL32_SHIFT (0U) +#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) +#define XBARA_SEL16_SEL33_MASK (0x7F00U) +#define XBARA_SEL16_SEL33_SHIFT (8U) +#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ + +/*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ +#define XBARA_SEL17_SEL34_MASK (0x7FU) +#define XBARA_SEL17_SEL34_SHIFT (0U) +#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) +#define XBARA_SEL17_SEL35_MASK (0x7F00U) +#define XBARA_SEL17_SEL35_SHIFT (8U) +#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ + +/*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ +#define XBARA_SEL18_SEL36_MASK (0x7FU) +#define XBARA_SEL18_SEL36_SHIFT (0U) +#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) +#define XBARA_SEL18_SEL37_MASK (0x7F00U) +#define XBARA_SEL18_SEL37_SHIFT (8U) +#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ + +/*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ +#define XBARA_SEL19_SEL38_MASK (0x7FU) +#define XBARA_SEL19_SEL38_SHIFT (0U) +#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) +#define XBARA_SEL19_SEL39_MASK (0x7F00U) +#define XBARA_SEL19_SEL39_SHIFT (8U) +#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ + +/*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ +#define XBARA_SEL20_SEL40_MASK (0x7FU) +#define XBARA_SEL20_SEL40_SHIFT (0U) +#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) +#define XBARA_SEL20_SEL41_MASK (0x7F00U) +#define XBARA_SEL20_SEL41_SHIFT (8U) +#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ + +/*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ +#define XBARA_SEL21_SEL42_MASK (0x7FU) +#define XBARA_SEL21_SEL42_SHIFT (0U) +#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) +#define XBARA_SEL21_SEL43_MASK (0x7F00U) +#define XBARA_SEL21_SEL43_SHIFT (8U) +#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ + +/*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ +#define XBARA_SEL22_SEL44_MASK (0x7FU) +#define XBARA_SEL22_SEL44_SHIFT (0U) +#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) +#define XBARA_SEL22_SEL45_MASK (0x7F00U) +#define XBARA_SEL22_SEL45_SHIFT (8U) +#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ + +/*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ +#define XBARA_SEL23_SEL46_MASK (0x7FU) +#define XBARA_SEL23_SEL46_SHIFT (0U) +#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) +#define XBARA_SEL23_SEL47_MASK (0x7F00U) +#define XBARA_SEL23_SEL47_SHIFT (8U) +#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ + +/*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ +#define XBARA_SEL24_SEL48_MASK (0x7FU) +#define XBARA_SEL24_SEL48_SHIFT (0U) +#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) +#define XBARA_SEL24_SEL49_MASK (0x7F00U) +#define XBARA_SEL24_SEL49_SHIFT (8U) +#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ + +/*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ +#define XBARA_SEL25_SEL50_MASK (0x7FU) +#define XBARA_SEL25_SEL50_SHIFT (0U) +#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) +#define XBARA_SEL25_SEL51_MASK (0x7F00U) +#define XBARA_SEL25_SEL51_SHIFT (8U) +#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ + +/*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ +#define XBARA_SEL26_SEL52_MASK (0x7FU) +#define XBARA_SEL26_SEL52_SHIFT (0U) +#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) +#define XBARA_SEL26_SEL53_MASK (0x7F00U) +#define XBARA_SEL26_SEL53_SHIFT (8U) +#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ + +/*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ +#define XBARA_SEL27_SEL54_MASK (0x7FU) +#define XBARA_SEL27_SEL54_SHIFT (0U) +#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) +#define XBARA_SEL27_SEL55_MASK (0x7F00U) +#define XBARA_SEL27_SEL55_SHIFT (8U) +#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ + +/*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ +#define XBARA_SEL28_SEL56_MASK (0x7FU) +#define XBARA_SEL28_SEL56_SHIFT (0U) +#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) +#define XBARA_SEL28_SEL57_MASK (0x7F00U) +#define XBARA_SEL28_SEL57_SHIFT (8U) +#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ + +/*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ +#define XBARA_SEL29_SEL58_MASK (0x7FU) +#define XBARA_SEL29_SEL58_SHIFT (0U) +#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) +#define XBARA_SEL29_SEL59_MASK (0x7F00U) +#define XBARA_SEL29_SEL59_SHIFT (8U) +#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ + +/*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ +#define XBARA_SEL30_SEL60_MASK (0x7FU) +#define XBARA_SEL30_SEL60_SHIFT (0U) +#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) +#define XBARA_SEL30_SEL61_MASK (0x7F00U) +#define XBARA_SEL30_SEL61_SHIFT (8U) +#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ + +/*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ +#define XBARA_SEL31_SEL62_MASK (0x7FU) +#define XBARA_SEL31_SEL62_SHIFT (0U) +#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) +#define XBARA_SEL31_SEL63_MASK (0x7F00U) +#define XBARA_SEL31_SEL63_SHIFT (8U) +#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ + +/*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ +#define XBARA_SEL32_SEL64_MASK (0x7FU) +#define XBARA_SEL32_SEL64_SHIFT (0U) +#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) +#define XBARA_SEL32_SEL65_MASK (0x7F00U) +#define XBARA_SEL32_SEL65_SHIFT (8U) +#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ + +/*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ +#define XBARA_SEL33_SEL66_MASK (0x7FU) +#define XBARA_SEL33_SEL66_SHIFT (0U) +#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) +#define XBARA_SEL33_SEL67_MASK (0x7F00U) +#define XBARA_SEL33_SEL67_SHIFT (8U) +#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ + +/*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ +#define XBARA_SEL34_SEL68_MASK (0x7FU) +#define XBARA_SEL34_SEL68_SHIFT (0U) +#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) +#define XBARA_SEL34_SEL69_MASK (0x7F00U) +#define XBARA_SEL34_SEL69_SHIFT (8U) +#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ + +/*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ +#define XBARA_SEL35_SEL70_MASK (0x7FU) +#define XBARA_SEL35_SEL70_SHIFT (0U) +#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) +#define XBARA_SEL35_SEL71_MASK (0x7F00U) +#define XBARA_SEL35_SEL71_SHIFT (8U) +#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ + +/*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ +#define XBARA_SEL36_SEL72_MASK (0x7FU) +#define XBARA_SEL36_SEL72_SHIFT (0U) +#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) +#define XBARA_SEL36_SEL73_MASK (0x7F00U) +#define XBARA_SEL36_SEL73_SHIFT (8U) +#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ + +/*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ +#define XBARA_SEL37_SEL74_MASK (0x7FU) +#define XBARA_SEL37_SEL74_SHIFT (0U) +#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) +#define XBARA_SEL37_SEL75_MASK (0x7F00U) +#define XBARA_SEL37_SEL75_SHIFT (8U) +#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ + +/*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ +#define XBARA_SEL38_SEL76_MASK (0x7FU) +#define XBARA_SEL38_SEL76_SHIFT (0U) +#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) +#define XBARA_SEL38_SEL77_MASK (0x7F00U) +#define XBARA_SEL38_SEL77_SHIFT (8U) +#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ + +/*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ +#define XBARA_SEL39_SEL78_MASK (0x7FU) +#define XBARA_SEL39_SEL78_SHIFT (0U) +#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) +#define XBARA_SEL39_SEL79_MASK (0x7F00U) +#define XBARA_SEL39_SEL79_SHIFT (8U) +#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ + +/*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ +#define XBARA_SEL40_SEL80_MASK (0x7FU) +#define XBARA_SEL40_SEL80_SHIFT (0U) +#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) +#define XBARA_SEL40_SEL81_MASK (0x7F00U) +#define XBARA_SEL40_SEL81_SHIFT (8U) +#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ + +/*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ +#define XBARA_SEL41_SEL82_MASK (0x7FU) +#define XBARA_SEL41_SEL82_SHIFT (0U) +#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) +#define XBARA_SEL41_SEL83_MASK (0x7F00U) +#define XBARA_SEL41_SEL83_SHIFT (8U) +#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ + +/*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ +#define XBARA_SEL42_SEL84_MASK (0x7FU) +#define XBARA_SEL42_SEL84_SHIFT (0U) +#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) +#define XBARA_SEL42_SEL85_MASK (0x7F00U) +#define XBARA_SEL42_SEL85_SHIFT (8U) +#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ + +/*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ +#define XBARA_SEL43_SEL86_MASK (0x7FU) +#define XBARA_SEL43_SEL86_SHIFT (0U) +#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) +#define XBARA_SEL43_SEL87_MASK (0x7F00U) +#define XBARA_SEL43_SEL87_SHIFT (8U) +#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ + +/*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ +#define XBARA_SEL44_SEL88_MASK (0x7FU) +#define XBARA_SEL44_SEL88_SHIFT (0U) +#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) +#define XBARA_SEL44_SEL89_MASK (0x7F00U) +#define XBARA_SEL44_SEL89_SHIFT (8U) +#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ + +/*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ +#define XBARA_SEL45_SEL90_MASK (0x7FU) +#define XBARA_SEL45_SEL90_SHIFT (0U) +#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) +#define XBARA_SEL45_SEL91_MASK (0x7F00U) +#define XBARA_SEL45_SEL91_SHIFT (8U) +#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ + +/*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ +#define XBARA_SEL46_SEL92_MASK (0x7FU) +#define XBARA_SEL46_SEL92_SHIFT (0U) +#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) +#define XBARA_SEL46_SEL93_MASK (0x7F00U) +#define XBARA_SEL46_SEL93_SHIFT (8U) +#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ + +/*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ +#define XBARA_SEL47_SEL94_MASK (0x7FU) +#define XBARA_SEL47_SEL94_SHIFT (0U) +#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) +#define XBARA_SEL47_SEL95_MASK (0x7F00U) +#define XBARA_SEL47_SEL95_SHIFT (8U) +#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ + +/*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ +#define XBARA_SEL48_SEL96_MASK (0x7FU) +#define XBARA_SEL48_SEL96_SHIFT (0U) +#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) +#define XBARA_SEL48_SEL97_MASK (0x7F00U) +#define XBARA_SEL48_SEL97_SHIFT (8U) +#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ + +/*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ +#define XBARA_SEL49_SEL98_MASK (0x7FU) +#define XBARA_SEL49_SEL98_SHIFT (0U) +#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) +#define XBARA_SEL49_SEL99_MASK (0x7F00U) +#define XBARA_SEL49_SEL99_SHIFT (8U) +#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ + +/*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ +#define XBARA_SEL50_SEL100_MASK (0x7FU) +#define XBARA_SEL50_SEL100_SHIFT (0U) +#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) +#define XBARA_SEL50_SEL101_MASK (0x7F00U) +#define XBARA_SEL50_SEL101_SHIFT (8U) +#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ + +/*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ +#define XBARA_SEL51_SEL102_MASK (0x7FU) +#define XBARA_SEL51_SEL102_SHIFT (0U) +#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) +#define XBARA_SEL51_SEL103_MASK (0x7F00U) +#define XBARA_SEL51_SEL103_SHIFT (8U) +#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ + +/*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ +#define XBARA_SEL52_SEL104_MASK (0x7FU) +#define XBARA_SEL52_SEL104_SHIFT (0U) +#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) +#define XBARA_SEL52_SEL105_MASK (0x7F00U) +#define XBARA_SEL52_SEL105_SHIFT (8U) +#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ + +/*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ +#define XBARA_SEL53_SEL106_MASK (0x7FU) +#define XBARA_SEL53_SEL106_SHIFT (0U) +#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) +#define XBARA_SEL53_SEL107_MASK (0x7F00U) +#define XBARA_SEL53_SEL107_SHIFT (8U) +#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ + +/*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ +#define XBARA_SEL54_SEL108_MASK (0x7FU) +#define XBARA_SEL54_SEL108_SHIFT (0U) +#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) +#define XBARA_SEL54_SEL109_MASK (0x7F00U) +#define XBARA_SEL54_SEL109_SHIFT (8U) +#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ + +/*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ +#define XBARA_SEL55_SEL110_MASK (0x7FU) +#define XBARA_SEL55_SEL110_SHIFT (0U) +#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) +#define XBARA_SEL55_SEL111_MASK (0x7F00U) +#define XBARA_SEL55_SEL111_SHIFT (8U) +#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ + +/*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ +#define XBARA_SEL56_SEL112_MASK (0x7FU) +#define XBARA_SEL56_SEL112_SHIFT (0U) +#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) +#define XBARA_SEL56_SEL113_MASK (0x7F00U) +#define XBARA_SEL56_SEL113_SHIFT (8U) +#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ + +/*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ +#define XBARA_SEL57_SEL114_MASK (0x7FU) +#define XBARA_SEL57_SEL114_SHIFT (0U) +#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) +#define XBARA_SEL57_SEL115_MASK (0x7F00U) +#define XBARA_SEL57_SEL115_SHIFT (8U) +#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ + +/*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ +#define XBARA_SEL58_SEL116_MASK (0x7FU) +#define XBARA_SEL58_SEL116_SHIFT (0U) +#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) +#define XBARA_SEL58_SEL117_MASK (0x7F00U) +#define XBARA_SEL58_SEL117_SHIFT (8U) +#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ + +/*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ +#define XBARA_SEL59_SEL118_MASK (0x7FU) +#define XBARA_SEL59_SEL118_SHIFT (0U) +#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) +#define XBARA_SEL59_SEL119_MASK (0x7F00U) +#define XBARA_SEL59_SEL119_SHIFT (8U) +#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ + +/*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ +#define XBARA_SEL60_SEL120_MASK (0x7FU) +#define XBARA_SEL60_SEL120_SHIFT (0U) +#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) +#define XBARA_SEL60_SEL121_MASK (0x7F00U) +#define XBARA_SEL60_SEL121_SHIFT (8U) +#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ + +/*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ +#define XBARA_SEL61_SEL122_MASK (0x7FU) +#define XBARA_SEL61_SEL122_SHIFT (0U) +#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) +#define XBARA_SEL61_SEL123_MASK (0x7F00U) +#define XBARA_SEL61_SEL123_SHIFT (8U) +#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ + +/*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ +#define XBARA_SEL62_SEL124_MASK (0x7FU) +#define XBARA_SEL62_SEL124_SHIFT (0U) +#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) +#define XBARA_SEL62_SEL125_MASK (0x7F00U) +#define XBARA_SEL62_SEL125_SHIFT (8U) +#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ + +/*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ +#define XBARA_SEL63_SEL126_MASK (0x7FU) +#define XBARA_SEL63_SEL126_SHIFT (0U) +#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) +#define XBARA_SEL63_SEL127_MASK (0x7F00U) +#define XBARA_SEL63_SEL127_SHIFT (8U) +#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ + +/*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ +#define XBARA_SEL64_SEL128_MASK (0x7FU) +#define XBARA_SEL64_SEL128_SHIFT (0U) +#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) +#define XBARA_SEL64_SEL129_MASK (0x7F00U) +#define XBARA_SEL64_SEL129_SHIFT (8U) +#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ + +/*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ +#define XBARA_SEL65_SEL130_MASK (0x7FU) +#define XBARA_SEL65_SEL130_SHIFT (0U) +#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) +#define XBARA_SEL65_SEL131_MASK (0x7F00U) +#define XBARA_SEL65_SEL131_SHIFT (8U) +#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ + +/*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ +#define XBARA_CTRL0_DEN0_MASK (0x1U) +#define XBARA_CTRL0_DEN0_SHIFT (0U) +/*! DEN0 - DMA Enable for XBAR_OUT0 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) +#define XBARA_CTRL0_IEN0_MASK (0x2U) +#define XBARA_CTRL0_IEN0_SHIFT (1U) +/*! IEN0 - Interrupt Enable for XBAR_OUT0 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) +#define XBARA_CTRL0_EDGE0_MASK (0xCU) +#define XBARA_CTRL0_EDGE0_SHIFT (2U) +/*! EDGE0 - Active edge for edge detection on XBAR_OUT0 + * 0b00..STS0 never asserts + * 0b01..STS0 asserts on rising edges of XBAR_OUT0 + * 0b10..STS0 asserts on falling edges of XBAR_OUT0 + * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 + */ +#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) +#define XBARA_CTRL0_STS0_MASK (0x10U) +#define XBARA_CTRL0_STS0_SHIFT (4U) +/*! STS0 - Edge detection status for XBAR_OUT0 + * 0b0..Active edge not yet detected on XBAR_OUT0 + * 0b1..Active edge detected on XBAR_OUT0 + */ +#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) +#define XBARA_CTRL0_DEN1_MASK (0x100U) +#define XBARA_CTRL0_DEN1_SHIFT (8U) +/*! DEN1 - DMA Enable for XBAR_OUT1 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) +#define XBARA_CTRL0_IEN1_MASK (0x200U) +#define XBARA_CTRL0_IEN1_SHIFT (9U) +/*! IEN1 - Interrupt Enable for XBAR_OUT1 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) +#define XBARA_CTRL0_EDGE1_MASK (0xC00U) +#define XBARA_CTRL0_EDGE1_SHIFT (10U) +/*! EDGE1 - Active edge for edge detection on XBAR_OUT1 + * 0b00..STS1 never asserts + * 0b01..STS1 asserts on rising edges of XBAR_OUT1 + * 0b10..STS1 asserts on falling edges of XBAR_OUT1 + * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 + */ +#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) +#define XBARA_CTRL0_STS1_MASK (0x1000U) +#define XBARA_CTRL0_STS1_SHIFT (12U) +/*! STS1 - Edge detection status for XBAR_OUT1 + * 0b0..Active edge not yet detected on XBAR_OUT1 + * 0b1..Active edge detected on XBAR_OUT1 + */ +#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ + +/*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ +#define XBARA_CTRL1_DEN2_MASK (0x1U) +#define XBARA_CTRL1_DEN2_SHIFT (0U) +/*! DEN2 - DMA Enable for XBAR_OUT2 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) +#define XBARA_CTRL1_IEN2_MASK (0x2U) +#define XBARA_CTRL1_IEN2_SHIFT (1U) +/*! IEN2 - Interrupt Enable for XBAR_OUT2 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) +#define XBARA_CTRL1_EDGE2_MASK (0xCU) +#define XBARA_CTRL1_EDGE2_SHIFT (2U) +/*! EDGE2 - Active edge for edge detection on XBAR_OUT2 + * 0b00..STS2 never asserts + * 0b01..STS2 asserts on rising edges of XBAR_OUT2 + * 0b10..STS2 asserts on falling edges of XBAR_OUT2 + * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 + */ +#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) +#define XBARA_CTRL1_STS2_MASK (0x10U) +#define XBARA_CTRL1_STS2_SHIFT (4U) +/*! STS2 - Edge detection status for XBAR_OUT2 + * 0b0..Active edge not yet detected on XBAR_OUT2 + * 0b1..Active edge detected on XBAR_OUT2 + */ +#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) +#define XBARA_CTRL1_DEN3_MASK (0x100U) +#define XBARA_CTRL1_DEN3_SHIFT (8U) +/*! DEN3 - DMA Enable for XBAR_OUT3 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) +#define XBARA_CTRL1_IEN3_MASK (0x200U) +#define XBARA_CTRL1_IEN3_SHIFT (9U) +/*! IEN3 - Interrupt Enable for XBAR_OUT3 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) +#define XBARA_CTRL1_EDGE3_MASK (0xC00U) +#define XBARA_CTRL1_EDGE3_SHIFT (10U) +/*! EDGE3 - Active edge for edge detection on XBAR_OUT3 + * 0b00..STS3 never asserts + * 0b01..STS3 asserts on rising edges of XBAR_OUT3 + * 0b10..STS3 asserts on falling edges of XBAR_OUT3 + * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 + */ +#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) +#define XBARA_CTRL1_STS3_MASK (0x1000U) +#define XBARA_CTRL1_STS3_SHIFT (12U) +/*! STS3 - Edge detection status for XBAR_OUT3 + * 0b0..Active edge not yet detected on XBAR_OUT3 + * 0b1..Active edge detected on XBAR_OUT3 + */ +#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARA_Register_Masks */ + + +/* XBARA - Peripheral instance base addresses */ +/** Peripheral XBARA1 base address */ +#define XBARA1_BASE (0x403BC000u) +/** Peripheral XBARA1 base pointer */ +#define XBARA1 ((XBARA_Type *)XBARA1_BASE) +/** Array initializer of XBARA peripheral base addresses */ +#define XBARA_BASE_ADDRS { XBARA1_BASE } +/** Array initializer of XBARA peripheral base pointers */ +#define XBARA_BASE_PTRS { XBARA1 } + +/*! + * @} + */ /* end of group XBARA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer + * @{ + */ + +/** XBARB - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */ +} XBARB_Type; + +/* ---------------------------------------------------------------------------- + -- XBARB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Register_Masks XBARB Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ +#define XBARB_SEL0_SEL0_MASK (0x3FU) +#define XBARB_SEL0_SEL0_SHIFT (0U) +#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) +#define XBARB_SEL0_SEL1_MASK (0x3F00U) +#define XBARB_SEL0_SEL1_SHIFT (8U) +#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ +#define XBARB_SEL1_SEL2_MASK (0x3FU) +#define XBARB_SEL1_SEL2_SHIFT (0U) +#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) +#define XBARB_SEL1_SEL3_MASK (0x3F00U) +#define XBARB_SEL1_SEL3_SHIFT (8U) +#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ +#define XBARB_SEL2_SEL4_MASK (0x3FU) +#define XBARB_SEL2_SEL4_SHIFT (0U) +#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) +#define XBARB_SEL2_SEL5_MASK (0x3F00U) +#define XBARB_SEL2_SEL5_SHIFT (8U) +#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ +#define XBARB_SEL3_SEL6_MASK (0x3FU) +#define XBARB_SEL3_SEL6_SHIFT (0U) +#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) +#define XBARB_SEL3_SEL7_MASK (0x3F00U) +#define XBARB_SEL3_SEL7_SHIFT (8U) +#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ +#define XBARB_SEL4_SEL8_MASK (0x3FU) +#define XBARB_SEL4_SEL8_SHIFT (0U) +#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) +#define XBARB_SEL4_SEL9_MASK (0x3F00U) +#define XBARB_SEL4_SEL9_SHIFT (8U) +#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ +#define XBARB_SEL5_SEL10_MASK (0x3FU) +#define XBARB_SEL5_SEL10_SHIFT (0U) +#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) +#define XBARB_SEL5_SEL11_MASK (0x3F00U) +#define XBARB_SEL5_SEL11_SHIFT (8U) +#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ +#define XBARB_SEL6_SEL12_MASK (0x3FU) +#define XBARB_SEL6_SEL12_SHIFT (0U) +#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) +#define XBARB_SEL6_SEL13_MASK (0x3F00U) +#define XBARB_SEL6_SEL13_SHIFT (8U) +#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ +#define XBARB_SEL7_SEL14_MASK (0x3FU) +#define XBARB_SEL7_SEL14_SHIFT (0U) +#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) +#define XBARB_SEL7_SEL15_MASK (0x3F00U) +#define XBARB_SEL7_SEL15_SHIFT (8U) +#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARB_Register_Masks */ + + +/* XBARB - Peripheral instance base addresses */ +/** Peripheral XBARB2 base address */ +#define XBARB2_BASE (0x403C0000u) +/** Peripheral XBARB2 base pointer */ +#define XBARB2 ((XBARB_Type *)XBARB2_BASE) +/** Peripheral XBARB3 base address */ +#define XBARB3_BASE (0x403C4000u) +/** Peripheral XBARB3 base pointer */ +#define XBARB3 ((XBARB_Type *)XBARB3_BASE) +/** Array initializer of XBARB peripheral base addresses */ +#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE } +/** Array initializer of XBARB peripheral base pointers */ +#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 } + +/*! + * @} + */ /* end of group XBARB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + uint8_t RESERVED_1[272]; + __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ + uint8_t RESERVED_2[32]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x400D8000u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MIMXRT1052_H_ */ + diff --git a/device/MIMXRT1052_features.h b/device/MIMXRT1052_features.h new file mode 100644 index 0000000..29b13e1 --- /dev/null +++ b/device/MIMXRT1052_features.h @@ -0,0 +1,724 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2018-11-16 +** Build: b200921 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update feature files to align with IMXRT1050RM Rev.1. +** +** ################################################################### +*/ + +#ifndef _MIMXRT1052_FEATURES_H_ +#define _MIMXRT1052_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (2) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (4) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (1) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (4) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (2) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (5) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (4) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (4) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (1) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief SEMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMC_COUNT (1) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (4) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (2) +/* @brief USB_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (1) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (2) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) +/* @brief ROM API Availability */ +#define FSL_FEATURE_BOOT_ROM_HAS_ROMAPI (1) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* @brief Conversion control count (related to number of registers HCn and Rn). */ +#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) + +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) +/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */ +#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (0) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0) +/* @brief Has extra MB interrupt or common one. */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) + +/* CCM module features */ + +/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ +#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (1) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) +/* @brief Has COUTA out of window is zero enable. */ +#define FSL_FEATURE_CMP_HAS_COWZ_BIT_FIELD (0) +/* @brief Use 16 bit registers. */ +#define FSL_FEATURE_CMP_USE_16BIT_REG (0) + +/* DCDC module features */ + +/* @brief Has CTRL register (register CTRL0/1). */ +#define FSL_FEATURE_DCDC_HAS_CTRL_REG (0) +/* @brief DCDC VDD output count. */ +#define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1) +/* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */ +#define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0) +/* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */ +#define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0) +/* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */ +#define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0) +/* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */ +#define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0) +/* @brief Has register bit field REG3[REG_FBK_SEL]). */ +#define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +/* @brief Channel IRQ entry shared offset. */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) +/* @brief If 32 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ +#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) +/* @brief Register CHCFGn width. */ +#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (1) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (0) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) +/* @brief Support Interrupt Coalesce for each instance */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) +/* @brief Queue Size for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) +/* @brief Has AVB Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0) +/* @brief Has Timer Pulse Width control for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1) +/* @brief Has Extend MDIO Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) +/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) +/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ +#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) + +/* FLEXRAM module features */ + +/* @brief Bank size */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) +/* @brief Total Bank numbers */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) +/* @brief Has FLEXRAM_MAGIC_ADDR. */ +#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (0) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0) + +/* GPC module features */ + +/* @brief Has DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) +/* @brief Has GPC interrupt/event masking. */ +#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) +/* @brief Has L2 cache power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) +/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) +/* @brief Has VADC power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) +/* @brief Has Display power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) +/* @brief Supports IRQ 0-31. */ +#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) + +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + +/* LCDIF module features */ + +/* @brief LCDIF does not support alpha support. */ +#define FSL_FEATURE_LCDIF_HAS_NO_AS (1) +/* @brief LCDIF does not support output reset pin to LCD panel. */ +#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1) +/* @brief LCDIF supports LUT. */ +#define FSL_FEATURE_LCDIF_HAS_LUT (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151) + +/* OCOTP module features */ + +/* @brief Has timing control, (register TIMING). */ +#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1) +/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */ +#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0) +/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */ +#define FSL_FEATURE_OCOTP_HAS_STATUS (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) + +/* PMU module features */ + +/* @brief PMU supports lower power control. */ +#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) + +/* PXP module features */ + +/* @brief PXP module has dither engine. */ +#define FSL_FEATURE_PXP_HAS_DITHER (0) +/* @brief PXP module supports repeat run */ +#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1) +/* @brief PXP doesn't have CSC */ +#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1) +/* @brief PXP doesn't have LUT */ +#define FSL_FEATURE_PXP_HAS_NO_LUT (1) + +/* RTWDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) +/* @brief RTWDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ + (((x) == SAI1) ? (4) : \ + (((x) == SAI2) ? (1) : \ + (((x) == SAI3) ? (1) : (-1)))) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) + +/* SEMC module features */ + +/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1) +/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]). */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1) +/* @brief SRAM count SEMC can support (register BRx). */ +#define FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT (1) +/* @brief If SEMC support delay chain control (register DCCR). */ +#define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) +/* @brief Has read hold time feature (register bit field SRAMCR6[RDH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (0) +/* @brief Width of SDRAMCR0[PS] bitfields. */ +#define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) +/* @brief If SEMC has errata 050577. */ +#define FSL_FEATURE_SEMC_ERRATA_050577 (1) +/* @brief If sdram support column address 8 bit (register bit field SRAMCR0[CLO8]). */ +#define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (0) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (1) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is LOCKUP_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is no WRBC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) +/* @brief There is no WRE bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (0) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is JTAG_SW_RST bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) +/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) +/* @brief There is no WBI bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) + +/* SCB module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) + +/* TRNG module features */ + +/* @brief TRNG has no TRNG_ACC bitfield. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) \ + (((x) == USDHC1) ? (0) : \ + (((x) == USDHC2) ? (1) : (-1))) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) + +/* XBARA module features */ + +/* @brief Number of interrupt requests. */ +#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) + +#endif /* _MIMXRT1052_FEATURES_H_ */ + diff --git a/device/device_MIMXRT1052_CMSIS_MIMXRT1052.cmake b/device/device_MIMXRT1052_CMSIS_MIMXRT1052.cmake new file mode 100644 index 0000000..7299c99 --- /dev/null +++ b/device/device_MIMXRT1052_CMSIS_MIMXRT1052.cmake @@ -0,0 +1,12 @@ +if(NOT DEVICE_MIMXRT1052_CMSIS_MIMXRT1052_INCLUDED) + +set(DEVICE_MIMXRT1052_CMSIS_MIMXRT1052_INCLUDED true CACHE BOOL "device_MIMXRT1052_CMSIS component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + +include(CMSIS_Include_core_cm7_MIMXRT1052) + +endif() diff --git a/device/device_MIMXRT1052_system_MIMXRT1052.cmake b/device/device_MIMXRT1052_system_MIMXRT1052.cmake new file mode 100644 index 0000000..1269690 --- /dev/null +++ b/device/device_MIMXRT1052_system_MIMXRT1052.cmake @@ -0,0 +1,17 @@ +if(NOT DEVICE_MIMXRT1052_SYSTEM_MIMXRT1052_INCLUDED) + +set(DEVICE_MIMXRT1052_SYSTEM_MIMXRT1052_INCLUDED true CACHE BOOL "device_MIMXRT1052_system component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/system_MIMXRT1052.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(device_MIMXRT1052_CMSIS_MIMXRT1052) + +endif() diff --git a/device/fsl_device_registers.h b/device/fsl_device_registers.h new file mode 100644 index 0000000..54caf43 --- /dev/null +++ b/device/fsl_device_registers.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ + defined(CPU_MIMXRT1052DVL6B)) + +#define MIMXRT1052_SERIES + +/* CMSIS-style register definitions */ +#include "MIMXRT1052.h" +/* CPU specific feature definitions */ +#include "MIMXRT1052_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/device/system_MIMXRT1052.c b/device/system_MIMXRT1052.c new file mode 100644 index 0000000..d002078 --- /dev/null +++ b/device/system_MIMXRT1052.c @@ -0,0 +1,249 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.3, 2019-04-29 +** Build: b201012 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. +** - rev. 1.3 (2019-04-29) +** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052 + * @version 1.3 + * @date 2019-04-29 + * @brief Device specific configuration file for MIMXRT1052 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ + WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; + WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; + +/* Watchdog disable */ + +#if (DISABLE_WDOG) + if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) + { + WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; + } + if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) + { + WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; + } + if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) + { + RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ + } + else + { + RTWDOG->CNT = 0xC520U; + RTWDOG->CNT = 0xD928U; + } + RTWDOG->TOVAL = 0xFFFF; + RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; +#endif /* (DISABLE_WDOG) */ + + /* Disable Systick which might be enabled by bootrom */ + if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U) + { + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + +/* Enable instruction and data caches */ +#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } +#endif +#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } +#endif + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t freq; + uint32_t PLL1MainClock; + uint32_t PLL2MainClock; + + /* Periph_clk2_clk ---> Periph_clk */ + if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U) + { + freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); + } + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CPU_XTAL_CLK_HZ; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + /* check if pll is bypassed */ + if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U) + { + PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + } + + /* check if pll is bypassed */ + if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U) + { + PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); + } + PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM))); + + + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = PLL2MainClock; + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U; + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U; + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/device/system_MIMXRT1052.h b/device/system_MIMXRT1052.h new file mode 100644 index 0000000..b4e7030 --- /dev/null +++ b/device/system_MIMXRT1052.h @@ -0,0 +1,129 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 +** Version: rev. 1.3, 2019-04-29 +** Build: b191113 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. +** - rev. 1.3 (2019-04-29) +** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052 + * @version 1.3 + * @date 2019-04-29 + * @brief Device specific configuration file for MIMXRT1052 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMXRT1052_H_ +#define _SYSTEM_MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ + +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + +#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMXRT1052_H_ */ diff --git a/doc/readme.txt b/doc/readme.txt new file mode 100644 index 0000000..aa11c55 --- /dev/null +++ b/doc/readme.txt @@ -0,0 +1,46 @@ +Overview +======== +The Hello World project is a simple demonstration program that uses the SDK UART drivere in +combination with FreeRTOS. The purpose of this demo is to show how to use the debug console and to +provide a simple project for debugging and further development. + +The example application creates one task called hello_task. This task print "Hello world." message +via debug console utility and suspend itself. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 8.50.9 +- Keil MDK 5.33 +- GCC ARM Embedded 9.3.1 +- MCUXpresso 11.3.0 + +Hardware requirements +===================== +- Mini/micro USB cable +- EVKB-IMXRT1050 board +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board. +2. Open a serial terminal with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Download the program to the target board. +4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo. +Running the demo +================ +After the board is flashed the Tera Term will print "Hello world" message on terminal. + +Example output: +Hello world. diff --git a/drivers/driver_clock_MIMXRT1052.cmake b/drivers/driver_clock_MIMXRT1052.cmake new file mode 100644 index 0000000..8a7bef4 --- /dev/null +++ b/drivers/driver_clock_MIMXRT1052.cmake @@ -0,0 +1,17 @@ +if(NOT DRIVER_CLOCK_MIMXRT1052_INCLUDED) + +set(DRIVER_CLOCK_MIMXRT1052_INCLUDED true CACHE BOOL "driver_clock component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(driver_common_MIMXRT1052) + +endif() diff --git a/drivers/driver_common_MIMXRT1052.cmake b/drivers/driver_common_MIMXRT1052.cmake new file mode 100644 index 0000000..8b89774 --- /dev/null +++ b/drivers/driver_common_MIMXRT1052.cmake @@ -0,0 +1,19 @@ +if(NOT DRIVER_COMMON_MIMXRT1052_INCLUDED) + +set(DRIVER_COMMON_MIMXRT1052_INCLUDED true CACHE BOOL "driver_common component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_common.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(driver_clock_MIMXRT1052) + +include(device_MIMXRT1052_CMSIS_MIMXRT1052) + +endif() diff --git a/drivers/driver_igpio_MIMXRT1052.cmake b/drivers/driver_igpio_MIMXRT1052.cmake new file mode 100644 index 0000000..7f86e7f --- /dev/null +++ b/drivers/driver_igpio_MIMXRT1052.cmake @@ -0,0 +1,17 @@ +if(NOT DRIVER_IGPIO_MIMXRT1052_INCLUDED) + +set(DRIVER_IGPIO_MIMXRT1052_INCLUDED true CACHE BOOL "driver_igpio component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_gpio.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(driver_common_MIMXRT1052) + +endif() diff --git a/drivers/driver_iomuxc_MIMXRT1052.cmake b/drivers/driver_iomuxc_MIMXRT1052.cmake new file mode 100644 index 0000000..5ee7fdc --- /dev/null +++ b/drivers/driver_iomuxc_MIMXRT1052.cmake @@ -0,0 +1,12 @@ +if(NOT DRIVER_IOMUXC_MIMXRT1052_INCLUDED) + +set(DRIVER_IOMUXC_MIMXRT1052_INCLUDED true CACHE BOOL "driver_iomuxc component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + +include(driver_common_MIMXRT1052) + +endif() diff --git a/drivers/driver_lpuart_MIMXRT1052.cmake b/drivers/driver_lpuart_MIMXRT1052.cmake new file mode 100644 index 0000000..557e245 --- /dev/null +++ b/drivers/driver_lpuart_MIMXRT1052.cmake @@ -0,0 +1,17 @@ +if(NOT DRIVER_LPUART_MIMXRT1052_INCLUDED) + +set(DRIVER_LPUART_MIMXRT1052_INCLUDED true CACHE BOOL "driver_lpuart component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/fsl_lpuart.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +${CMAKE_CURRENT_LIST_DIR}/ +) + + +include(driver_common_MIMXRT1052) + +endif() diff --git a/drivers/fsl_clock.c b/drivers/fsl_clock.c new file mode 100644 index 0000000..ed64bdd --- /dev/null +++ b/drivers/fsl_clock.c @@ -0,0 +1,1509 @@ +/* + * Copyright 2017 - 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if (defined(__ICCARM__)) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif (defined(__GNUC__)) + +#if (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +volatile uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +volatile uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + +/*! + * @brief Get the frequency of PLL USB1 software clock. + * + * @return The frequency of PLL USB1 software clock. + */ +static uint32_t CLOCK_GetPllUsb1SWFreq(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +static uint32_t CLOCK_GetPllUsb1SWFreq(void) +{ + uint32_t freq; + + switch ((CCM->CCSR & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) >> CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT) + { + case 0: + { + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + } + case 1: + { + freq = 24000000UL; + break; + } + default: + freq = 0UL; + break; + } + + return freq; +} + +/*! + * brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0UL) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +/*! + * brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +/*! + * brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + { + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + } + else + { + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; + } +} + +/*! + * brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Gets the AHB clock frequency. + * + * return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the SEMC clock frequency. + * + * return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void) +{ + uint32_t freq; + + /* SEMC alternative clock ---> SEMC Clock */ + if ((CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) != 0U) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if ((CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) != 0U) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the IPG clock frequency. + * + * return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void) +{ + return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the PER clock frequency. + * + * return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void) +{ + uint32_t freq; + + /* Osc_clk ---> PER Clock*/ + if ((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) != 0U) + { + freq = CLOCK_GetOscFreq(); + } + /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */ + else + { + freq = CLOCK_GetIpgFreq(); + } + + freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + case kCLOCK_AhbClk: + freq = CLOCK_GetAhbFreq(); + break; + + case kCLOCK_SemcClk: + freq = CLOCK_GetSemcFreq(); + break; + + case kCLOCK_IpgClk: + freq = CLOCK_GetIpgFreq(); + break; + + case kCLOCK_PerClk: + freq = CLOCK_GetPerClkFreq(); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb1SwClk: + freq = CLOCK_GetPllUsb1SWFreq(); + break; + case kCLOCK_Usb1Sw120MClk: + freq = CLOCK_GetPllUsb1SWFreq() / 4UL; + break; + case kCLOCK_Usb1Sw60MClk: + freq = CLOCK_GetPllUsb1SWFreq() / 8UL; + break; + case kCLOCK_Usb1Sw80MClk: + freq = CLOCK_GetPllUsb1SWFreq() / 6UL; + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Gets the frequency of selected clock root. + * + * param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t. + * return The frequency of selected clock root. + */ +uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot) +{ + const clock_name_t clockRootSourceArray[][6] = CLOCK_ROOT_SOUCE; + const clock_mux_t clockRootMuxTupleArray[] = CLOCK_ROOT_MUX_TUPLE; + const clock_div_t clockRootDivTupleArray[][2] = CLOCK_ROOT_DIV_TUPLE; + uint32_t freq = 0UL; + clock_mux_t clockRootMuxTuple = clockRootMuxTupleArray[(uint8_t)clockRoot]; + clock_div_t clockRootPreDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][0]; + clock_div_t clockRootPostDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][1]; + uint32_t clockRootMuxValue = (CCM_TUPLE_REG(CCM, clockRootMuxTuple) & CCM_TUPLE_MASK(clockRootMuxTuple)) >> + CCM_TUPLE_SHIFT(clockRootMuxTuple); + clock_name_t clockSourceName; + + clockSourceName = clockRootSourceArray[(uint8_t)clockRoot][clockRootMuxValue]; + + assert(clockSourceName != kCLOCK_NoneName); + + freq = CLOCK_GetFreq(clockSourceName); + + if (clockRootPreDivTuple != kCLOCK_NonePreDiv) + { + freq /= ((CCM_TUPLE_REG(CCM, clockRootPreDivTuple) & CCM_TUPLE_MASK(clockRootPreDivTuple)) >> + CCM_TUPLE_SHIFT(clockRootPreDivTuple)) + + 1UL; + } + + freq /= ((CCM_TUPLE_REG(CCM, clockRootPostDivTuple) & CCM_TUPLE_MASK(clockRootPostDivTuple)) >> + CCM_TUPLE_SHIFT(clockRootPostDivTuple)) + + 1UL; + + return freq; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + uint32_t i; + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + uint32_t i = 0; + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) != 0U) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*! + * brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +/*! + * brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; +} + +/*! + * brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +/*! + * brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +/*! + * brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +/*! + * brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = (uint32_t)CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + } + + if (config->enableClkOutput25M) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; +} + +/*! + * brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +/*! + * brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * param pll pll name to get frequency. + * return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + clock_64b_t freqTmp; + + const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); + break; + case kCLOCK_PllSys: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))); + freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (freq * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0UL) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))); + freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2U): + freq = freq >> 0U; + break; + + default: + assert(false); + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0): + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0): + freq >>= 0U; + break; + + default: + assert(false); + break; + } + break; + + case kCLOCK_PllVideo: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))); + freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2U): + freq = freq >> 0U; + break; + + default: + assert(false); + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3U): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1U): + freq >>= 1U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(0U): + case CCM_ANALOG_MISC2_VIDEO_DIV(2U): + freq >>= 0U; + break; + + default: + assert(false); + break; + } + break; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (freq * (((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & + ~(((uint32_t)((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) + << (8UL * pfdIndex))); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | ((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex)); +} + +/*! + * brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= (uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8U * (uint8_t)pfd); +} + +/*! + * brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & + ~(((uint32_t)((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) + << (8UL * pfdIndex))); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | ((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex)); +} + +/*! + * brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= (uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * (uint8_t)pfd); +} + +/*! + * brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! + * brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Set the clock source and the divider of the clock output1. + * + * param selection The clock source to be output, please refer to clock_output1_selection_t. + * param divider The divider of the output clock signal, please refer to clock_output_divider_t. + */ +void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider) +{ + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + if (selection == kCLOCK_DisableClockOutput1) + { + tmp32 &= ~CCM_CCOSR_CLKO1_EN_MASK; + } + else + { + tmp32 |= CCM_CCOSR_CLKO1_EN_MASK; + tmp32 &= ~(CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK); + tmp32 |= CCM_CCOSR_CLKO1_SEL(selection) | CCM_CCOSR_CLKO1_DIV(divider); + } + CCM->CCOSR = tmp32; +} + +/*! + * brief Set the clock source and the divider of the clock output2. + * + * param selection The clock source to be output, please refer to clock_output2_selection_t. + * param divider The divider of the output clock signal, please refer to clock_output_divider_t. + */ +void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider) +{ + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + if (selection == kCLOCK_DisableClockOutput2) + { + tmp32 &= CCM_CCOSR_CLKO2_EN_MASK; + } + else + { + tmp32 |= CCM_CCOSR_CLKO2_EN_MASK; + tmp32 &= ~(CCM_CCOSR_CLKO2_SEL_MASK | CCM_CCOSR_CLKO2_DIV_MASK); + tmp32 |= CCM_CCOSR_CLKO2_SEL(selection) | CCM_CCOSR_CLKO2_DIV(divider); + } + + CCM->CCOSR = tmp32; +} + +/*! + * brief Get the frequency of clock output1 clock signal. + * + * return The frequency of clock output1 clock signal. + */ +uint32_t CLOCK_GetClockOutCLKO1Freq(void) +{ + uint32_t freq = 0U; + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + + if ((tmp32 & CCM_CCOSR_CLKO1_EN_MASK) != 0UL) + { + switch ((tmp32 & CCM_CCOSR_CLKO1_SEL_MASK) >> CCM_CCOSR_CLKO1_SEL_SHIFT) + { + case (uint32_t)kCLOCK_OutputPllUsb1: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 2U; + break; + case (uint32_t)kCLOCK_OutputPllSys: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys) / 2U; + break; + case (uint32_t)kCLOCK_OutputPllVideo: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2U; + break; + case (uint32_t)kCLOCK_OutputSemcClk: + freq = CLOCK_GetSemcFreq(); + break; + case (uint32_t)kCLOCK_OutputLcdifPixClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_LcdifClkRoot); + break; + case (uint32_t)kCLOCK_OutputAhbClk: + freq = CLOCK_GetAhbFreq(); + break; + case (uint32_t)kCLOCK_OutputIpgClk: + freq = CLOCK_GetIpgFreq(); + break; + case (uint32_t)kCLOCK_OutputPerClk: + freq = CLOCK_GetPerClkFreq(); + break; + case (uint32_t)kCLOCK_OutputCkilSyncClk: + freq = CLOCK_GetRtcFreq(); + break; + case (uint32_t)kCLOCK_OutputPll4MainClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + default: + /* This branch should never be hit. */ + break; + } + + freq /= (((tmp32 & CCM_CCOSR_CLKO1_DIV_MASK) >> CCM_CCOSR_CLKO1_DIV_SHIFT) + 1U); + } + else + { + freq = 0UL; + } + + return freq; +} + +/*! + * brief Get the frequency of clock output2 clock signal. + * + * return The frequency of clock output2 clock signal. + */ +uint32_t CLOCK_GetClockOutClkO2Freq(void) +{ + uint32_t freq = 0U; + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + + if ((tmp32 & CCM_CCOSR_CLKO2_EN_MASK) != 0UL) + { + switch ((tmp32 & CCM_CCOSR_CLKO2_SEL_MASK) >> CCM_CCOSR_CLKO2_SEL_SHIFT) + { + case (uint32_t)kCLOCK_OutputUsdhc1Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Usdhc1ClkRoot); + break; + case (uint32_t)kCLOCK_OutputLpi2cClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Lpi2cClkRoot); + break; + case (uint32_t)kCLOCK_OutputCsiClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_CsiClkRoot); + break; + case (uint32_t)kCLOCK_OutputOscClk: + freq = CLOCK_GetOscFreq(); + break; + case (uint32_t)kCLOCK_OutputUsdhc2Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Usdhc2ClkRoot); + break; + case (uint32_t)kCLOCK_OutputSai1Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Sai1ClkRoot); + break; + case (uint32_t)kCLOCK_OutputSai2Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Sai2ClkRoot); + break; + case (uint32_t)kCLOCK_OutputSai3Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Sai3ClkRoot); + break; + case (uint32_t)kCLOCK_OutputCanClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_CanClkRoot); + break; + case (uint32_t)kCLOCK_OutputFlexspiClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_FlexspiClkRoot); + break; + case (uint32_t)kCLOCK_OutputUartClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_UartClkRoot); + break; + case (uint32_t)kCLOCK_OutputSpdif0Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_SpdifClkRoot); + break; + default: + /* This branch should never be hit. */ + break; + } + + freq /= (((tmp32 & CCM_CCOSR_CLKO2_DIV_MASK) >> CCM_CCOSR_CLKO2_DIV_SHIFT) + 1U); + } + else + { + freq = 0UL; + } + + return freq; +} diff --git a/drivers/fsl_clock.h b/drivers/fsl_clock.h new file mode 100644 index 0000000..cedb9c4 --- /dev/null +++ b/drivers/fsl_clock.h @@ -0,0 +1,1738 @@ +/* + * Copyright 2017 - 2020, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.4.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL) +#endif + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ + +/*! + * @brief CCM registers offset. + */ +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 +#define CSCMR1_OFFSET 0x1C +#define CSCMR2_OFFSET 0x20 +#define CSCDR1_OFFSET 0x24 +#define CDCDR_OFFSET 0x30 +#define CSCDR2_OFFSET 0x38 +#define CSCDR3_OFFSET 0x3C +#define CACRR_OFFSET 0x10 +#define CS1CDR_OFFSET 0x28 +#define CS2CDR_OFFSET 0x2C + +/*! + * @brief CCM Analog registers offset. + */ +#define PLL_ARM_OFFSET 0x00 +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 +#define PLL_AUDIO_OFFSET 0x70 +#define PLL_VIDEO_OFFSET 0xA0 +#define PLL_ENET_OFFSET 0xE0 +#define PLL_USB2_OFFSET 0x20 + +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) \ + ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off)))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/* Definition for ERRATA 50235 check */ +#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235) +#define CAN_CLOCK_CHECK_NO_AFFECTS \ + ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \ + (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK))) +#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */ + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); + * CLOCK_SetXtalFreq(240000000); + * @endcode + */ +extern volatile uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern volatile uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief Clock ip name array for LCDIF PIXEL. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \ + {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \ + {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +#define CLOCK_SOURCE_NONE (0xFFU) + +#define CLOCK_ROOT_SOUCE \ + { \ + {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \ + {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \ + {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \ + kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \ + {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \ + kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \ + {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \ + kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \ + {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \ + kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \ + {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \ + {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \ + {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \ + {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \ + {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \ + {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \ + {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \ + kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \ + {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \ + kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \ + {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \ + kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \ + {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \ + kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \ + } + +#define CLOCK_ROOT_MUX_TUPLE \ + { \ + kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_CsiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \ + kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, \ + kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \ + } + +#define CLOCK_ROOT_NONE_PRE_DIV 0UL + +#define CLOCK_ROOT_DIV_TUPLE \ + { \ + {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \ + {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, \ + {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, \ + {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, \ + {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, \ + {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, \ + {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, \ + {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + kCLOCK_Usb1SwClk = 0x17U, /*!< USB1PLLSWCLK */ + kCLOCK_Usb1Sw120MClk = 0x18U, /*!< USB1PLLSw120MCLK */ + kCLOCK_Usb1Sw60MClk = 0x19U, /*!< USB1PLLSw60MCLK */ + kCLOCK_Usb1Sw80MClk = 0x1AU, /*!< USB1PLLSw80MCLK */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + + kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ + kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + + /* CCM CCGR3 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_TRACE_CLK_SEL_SHIFT, + CCM_CBCMR_TRACE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, + CCM_CBCMR_LPSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI3_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_SEL_SHIFT, + CCM_CSCMR2_CAN_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_SEL_SHIFT, + CCM_CSCDR1_UART_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, + CCM_CDCDR_SPDIF0_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, + CCM_CSCDR2_LPI2C_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET, + CCM_CSCDR3_CSI_CLK_SEL_SHIFT, + CCM_CSCDR3_CSI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET, + CCM_CACRR_ARM_PODF_SHIFT, + CCM_CACRR_ARM_PODF_MASK, + CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_AHB_PODF_SHIFT, + CCM_CBCDR_AHB_PODF_MASK, + CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE( + CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_PODF_SHIFT, + CCM_CSCMR1_FLEXSPI_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_PODF_SHIFT, + CCM_CSCMR1_PERCLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_PODF_SHIFT, + CCM_CSCMR2_CAN_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_TRACE_PODF_SHIFT, + CCM_CSCDR1_TRACE_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC2_PODF_SHIFT, + CCM_CSCDR1_USDHC2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC1_PODF_SHIFT, + CCM_CSCDR1_USDHC1_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_PODF_SHIFT, + CCM_CSCDR1_UART_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI3_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, + CCM_CS2CDR_SAI2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRED_SHIFT, + CCM_CSCDR2_LCDIF_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ + + kCLOCK_CsiDiv = CCM_TUPLE( + CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ + + kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */ +} clock_div_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/*! + * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on. + */ +typedef enum _clock_output1_selection +{ + kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */ + kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */ + kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */ + kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */ + kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */ + kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */ + kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */ + kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */ + kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */ + kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */ + kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */ +} clock_output1_selection_t; + +/*! + * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on. + * + */ +typedef enum _clock_output2_selection +{ + kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */ + kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */ + kCLOCK_OutputCsiClk = 0xBU, /*!< Selects CSI clock root output. */ + kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */ + kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */ + kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */ + kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */ + kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */ + kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */ + kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */ + kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */ + kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */ + kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */ +} clock_output2_selection_t; + +/*! + * @brief The enumerator of clock output's divider. + */ +typedef enum _clock_output_divider +{ + kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */ + kCLOCK_DivideBy2, /*!< Output clock divided by 2. */ + kCLOCK_DivideBy3, /*!< Output clock divided by 3. */ + kCLOCK_DivideBy4, /*!< Output clock divided by 4. */ + kCLOCK_DivideBy5, /*!< Output clock divided by 5. */ + kCLOCK_DivideBy6, /*!< Output clock divided by 6. */ + kCLOCK_DivideBy7, /*!< Output clock divided by 7. */ + kCLOCK_DivideBy8, /*!< Output clock divided by 8. */ +} clock_output_divider_t; + +/*! + * @brief The enumerator of clock root. + */ +typedef enum _clock_root +{ + kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */ + kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */ + kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */ + kCLOCK_CsiClkRoot, /*!< CSI clock root. */ + kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */ + kCLOCK_TraceClkRoot, /*!< Trace clock root. */ + kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */ + kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */ + kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */ + kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */ + kCLOCK_CanClkRoot, /*!< CAN clock root. */ + kCLOCK_UartClkRoot, /*!< UART clock root. */ + kCLOCK_LcdifClkRoot, /*!< LCD clock root. */ + kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */ + kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */ + kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */ +} clock_root_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux)); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 6UL); + + reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index])); + *reg = ((*reg) & ~((uint32_t)(3UL << shift))) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param name Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @brief Gets the frequency of selected clock root. + * + * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t. + * @return The frequency of selected clock root. + */ +uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot); + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +/*! + * @name Clock Output Inferfaces + * @{ + */ + +/*! + * @brief Set the clock source and the divider of the clock output1. + * + * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t. + * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t. + */ +void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider); + +/*! + * @brief Set the clock source and the divider of the clock output2. + * + * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t. + * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t. + */ +void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider); + +/*! + * @brief Get the frequency of clock output1 clock signal. + * + * @return The frequency of clock output1 clock signal. + */ +uint32_t CLOCK_GetClockOutCLKO1Freq(void); + +/*! + * @brief Get the frequency of clock output2 clock signal. + * + * @return The frequency of clock output2 clock signal. + */ +uint32_t CLOCK_GetClockOutClkO2Freq(void); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/drivers/fsl_common.c b/drivers/fsl_common.c new file mode 100644 index 0000000..ec52acb --- /dev/null +++ b/drivers/fsl_common.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + SDK_ISR_EXIT_BARRIER; + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc(alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} + +/*! + * @brief Delay function bases on while loop, every loop includes three instructions. + * + * @param count Counts of loop needed for dalay. + */ +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +static void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +static uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#elif defined __XCC__ +extern uint32_t xthal_get_ccount(void); +static void enableCpuCycleCounter(void) +{ + /* do nothing */ +} + +static uint32_t getCpuCycleCount(void) +{ + return xthal_get_ccount(); +} +#endif + +#ifndef __XCC__ +#if (!defined(SDK_DELAY_USE_DWT)) || (!defined(DWT)) +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n"); +} +#endif /* defined(__CC_ARM) */ +#endif /* (!defined(SDK_DELAY_USE_DWT)) || (!defined(DWT)) */ +#endif /* __XCC__ */ +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + assert(0U != delayTime_us); + uint64_t count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) */ +} diff --git a/drivers/fsl_common.h b/drivers/fsl_common.h new file mode 100644 index 0000000..c7da1b5 --- /dev/null +++ b/drivers/fsl_common.h @@ -0,0 +1,954 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 9)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if(defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__XCC__)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/* @} */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile void*)(addr), (val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile void*)(addr), (val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile void*)(addr), (val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile void*)(addr), (bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile void*)(addr), (bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile void*)(addr), (bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile void*)(addr), (clearBits), (setBits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile void*)(addr), (clearBits), (setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile void*)(addr), (clearBits), (setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#endif +/* @} */ + +#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +void DefaultISR(void); +#endif +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + + /* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + + /*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ + void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/drivers/fsl_gpio.c b/drivers/fsl_gpio.c new file mode 100644 index 0000000..d643cf1 --- /dev/null +++ b/drivers/fsl_gpio.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.igpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of GPIO clock name. */ +static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +/*! + * brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * param base GPIO base pointer. + * param pin Specifies the pin number + * param initConfig pointer to a ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable GPIO clock. */ + uint32_t instance = GPIO_GetInstance(base); + + /* If The clock IP is valid, enable the clock gate. */ + if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance])) + { + (void)CLOCK_EnableClock(s_gpioClock[instance]); + } +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Register reset to default value */ + base->IMR &= ~(1UL << pin); + + /* Configure GPIO pin direction */ + if (Config->direction == kGPIO_DigitalInput) + { + base->GDIR &= ~(1UL << pin); + } + else + { + GPIO_PinWrite(base, pin, Config->outputLogic); + base->GDIR |= (1UL << pin); + } + + /* Configure GPIO pin interrupt mode */ + GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); +} + +/*! + * brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + assert(pin < 32U); + if (output == 0U) + { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR) + base->DR_CLEAR = (1UL << pin); +#else + base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ +#endif + } + else + { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET) + base->DR_SET = (1UL << pin); +#else + base->DR |= (1UL << pin); /* Set pin output to high level.*/ +#endif + } +} + +/*! + * brief Sets the current pin interrupt mode. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + /* Register reset to default value */ + base->EDGE_SEL &= ~(1UL << pin); + + if (pin < 16U) + { + icr = &(base->ICR1); + } + else + { + icr = &(base->ICR2); + icrShift -= 16U; + } + switch (pinInterruptMode) + { + case (kGPIO_IntLowLevel): + *icr &= ~(3UL << (2UL * icrShift)); + break; + case (kGPIO_IntHighLevel): + *icr = (*icr & (~(3UL << (2UL * icrShift)))) | (1UL << (2UL * icrShift)); + break; + case (kGPIO_IntRisingEdge): + *icr = (*icr & (~(3UL << (2UL * icrShift)))) | (2UL << (2UL * icrShift)); + break; + case (kGPIO_IntFallingEdge): + *icr |= (3UL << (2UL * icrShift)); + break; + case (kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1UL << pin); + break; + default:; /* Intentional empty default */ + break; + } +} diff --git a/drivers/fsl_gpio.h b/drivers/fsl_gpio.h new file mode 100644 index 0000000..bfbda25 --- /dev/null +++ b/drivers/fsl_gpio.h @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param Config pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + GPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else + base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else + base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#else + base->DR ^= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32U); + + return (((base->DR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current input value of the GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinRead(base, pin); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + +/*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32U); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current GPIO pin pad status. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinReadPadStatus(base, pin); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pinInterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Sets the current pin interrupt mode. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortEnableInterrupts(base, mask); +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortDisableInterrupts(base, mask); +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + return base->ISR; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + return GPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISR = mask; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClearInterruptFlags(base, mask); +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/drivers/fsl_iomuxc.h b/drivers/fsl_iomuxc.h new file mode 100644 index 0000000..4e5e717 --- /dev/null +++ b/drivers/fsl_iomuxc.h @@ -0,0 +1,1242 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.2. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U + +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U +#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U + +#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U + +#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU + +#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U + +#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U + +#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U + +#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU + +#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U + +#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U + +#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU + +#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U + +#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U + +#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U + +#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U + +#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU + +#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U + +#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U + +#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U + +#define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU + +#define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U + +#define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U + +#define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U + +#define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU + +#define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U + +#define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U + +#define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U + +#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U + +#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U + +#define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU + +#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U + +#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U + +#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U + +#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU + +#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U + +#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U + +#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U + +#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U + +#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U + +#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU + +#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U + +#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U + +#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU + +#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U + +#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U + +#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U + +#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU + +#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U + +#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U + +#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U + +#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU + +#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U + +#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U + +#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U + +#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU +#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU + +#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U +#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U + +#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U + +#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U + +#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU + +#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U + +#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U + +#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U + +#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU + +#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U + +#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U + +#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U + +#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU +#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU + +#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U +#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U + +#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U +#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U + +#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U + +#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU + +#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U + +#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U + +#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U + +#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU + +#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U + +#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U + +#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U +#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U + +#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU + +#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U + +#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U + +#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U + +#define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU + +#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U + +#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U + +#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U + +#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU + +#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U + +#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U + +#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U + +#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU + +#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U + +#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U + +#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U + +#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU + +#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U + +#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U + +#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U + +#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU + +#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U + +#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U + +#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U + +#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU + +#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U + +/*@}*/ + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, + kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, + kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister != 0UL) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister != 0UL) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK | + IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | + IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); + base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); + base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/drivers/fsl_lpuart.c b/drivers/fsl_lpuart.c new file mode 100644 index 0000000..c015d03 --- /dev/null +++ b/drivers/fsl_lpuart.c @@ -0,0 +1,2176 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart" +#endif + +/* LPUART transfer state. */ +enum +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART peripheral base address. */ +static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; +/* Array of LPUART handle. */ +static lpuart_handle_t *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)]; +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS; +static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS; +#else +static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of LPUART clock name. */ +static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; + +#if defined(LPUART_PERIPH_CLOCKS) +/* Array of LPUART functional clock name. */ +static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* LPUART ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static lpuart_isr_t s_lpuartIsr = (lpuart_isr_t)DefaultISR; +#else +static lpuart_isr_t s_lpuartIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the LPUART instance from peripheral base address. + * + * param base LPUART peripheral base address. + * return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases); instance++) + { + if (s_lpuartBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpuartBases)); + + return instance; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * userData handle LPUART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + size_t size; + size_t tmpRxRingBufferSize = handle->rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (uint8_t)(base->DATA & 0x7FU); + } + else + { + data[i] = (uint8_t)base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + status_t status = kStatus_Success; + uint32_t temp; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); + tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : + (config->baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPUART_GetInstance(base); + + /* Enable lpuart clock */ + (void)CLOCK_EnableClock(s_lpuartClock[instance]); +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | + LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; + } + + return status; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = LPUART_GetInstance(base); + + /* Disable lpuart clock */ + (void)CLOCK_DisableClock(s_lpuartClock[instance]); + +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0U; + config->rxFifoWatermark = 0U; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + status_t status = kStatus_Success; + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); + + tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + + return status; +} + +/*! + * brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base LPUART peripheral base address. + * param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */ + temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK); + temp |= (uint32_t)LPUART_CTRL_M_MASK; + base->CTRL = temp; + } + else + { + /* Clear LPUART_CTRL_M. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK; + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT + /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */ + base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK; +#endif +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base LPUART peripheral base address. + * param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address) +{ + assert(base != NULL); + + uint32_t temp = base->DATA & 0xFFFFFC00UL; + temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT)); + base->DATA = temp; +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD |= ((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + ((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL |= mask; +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD &= ~((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL &= ~mask; +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + uint32_t temp; + temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8U; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8U; +#endif + temp |= (uint32_t)(base->CTRL & 0xFF0C000u); + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; +#endif + temp = (uint32_t)base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK)); + temp |= mask & LPUART_STAT_LBKDIF_MASK; +#endif + temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK)); + temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK)); + temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK); +#endif + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, + kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, + kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ + status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the data to be sent out to bus. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + + if (kStatus_Success == status) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7FU); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr = LPUART_TransferHandleIRQ; + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartRxIRQ[instance]); + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + LPUART_EnableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Enable transmitter interrupt. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable | (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmptxDataSize = handle->txDataSize; + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + status = kStatus_NoTransferInProgress; + } + else + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + *count = handle->txDataSizeAll - tmptxDataSize - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U) + { + *count = handle->txDataSizeAll - tmptxDataSize; + } + else + { + *count = handle->txDataSizeAll - tmptxDataSize - 1U; + } +#endif + } + + return status; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable LPUART RX IRQ, protect ring buffer. */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = &xfer->data[bytesCurrentReceived]; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + /* Enable LPUART RX IRQ if previously enabled. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = &xfer->data[bytesCurrentReceived]; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Enable RX interrupt. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable | + (uint32_t)kLPUART_IdleLineInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable | + (uint32_t)kLPUART_IdleLineInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmprxDataSize = handle->rxDataSize; + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxDataSizeAll - tmprxDataSize; + } + + return status; +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + uint8_t count; + uint8_t tempCount; + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + uint16_t tpmRxRingBufferHead; + uint32_t tpmData; + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT |= LPUART_STAT_IDLE_MASK; + + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (0U != (handle->rxDataSize)) + { + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_IdleLineInterruptEnable); + } + /* If callback is not NULL and rxDataSize is not 0. */ + if ((0U != handle->rxDataSize) && (NULL != handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + tpmRxRingBufferHead = handle->rxRingBufferHead; + tpmData = base->DATA; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU); + } + else + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } +#else + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + /* Disable TX register empty interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); + /* Enable transmission complete interrupt. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + } + } + } + + /* Transmission complete and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kLPUART_TxIdle; + /* Disable transmission complete interrupt. */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* To be implemented by User. */ +} +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void); +void LPUART0_LPUART1_RX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_LPUART1_TX_DriverIRQHandler(void); +void LPUART0_LPUART1_TX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_LPUART1_DriverIRQHandler(void); +void LPUART0_LPUART1_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void); +void LPUART0_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_RX_DriverIRQHandler(void); +void LPUART0_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_DriverIRQHandler(void); +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void); +void LPUART1_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART1_RX_DriverIRQHandler(void); +void LPUART1_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART1_DriverIRQHandler(void); +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void); +void LPUART2_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART2_RX_DriverIRQHandler(void); +void LPUART2_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART2_DriverIRQHandler(void); +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void); +void LPUART3_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART3_RX_DriverIRQHandler(void); +void LPUART3_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART3_DriverIRQHandler(void); +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void); +void LPUART4_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART4_RX_DriverIRQHandler(void); +void LPUART4_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART4_DriverIRQHandler(void); +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void); +void LPUART5_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART5_RX_DriverIRQHandler(void); +void LPUART5_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART5_DriverIRQHandler(void); +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void); +void LPUART6_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART6_RX_DriverIRQHandler(void); +void LPUART6_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART6_DriverIRQHandler(void); +void LPUART6_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void); +void LPUART7_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART7_RX_DriverIRQHandler(void); +void LPUART7_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART7_DriverIRQHandler(void); +void LPUART7_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void); +void LPUART8_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART8_RX_DriverIRQHandler(void); +void LPUART8_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART8_DriverIRQHandler(void); +void LPUART8_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART9) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART9_TX_DriverIRQHandler(void); +void LPUART9_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART9_RX_DriverIRQHandler(void); +void LPUART9_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART9_DriverIRQHandler(void); +void LPUART9_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART10) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART10_TX_DriverIRQHandler(void); +void LPUART10_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART10_RX_DriverIRQHandler(void); +void LPUART10_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART10_DriverIRQHandler(void); +void LPUART10_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART11) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART11_TX_DriverIRQHandler(void); +void LPUART11_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART11_RX_DriverIRQHandler(void); +void LPUART11_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART11_DriverIRQHandler(void); +void LPUART11_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void); +void M4_0_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void); +void M4_1_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void); +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void); +void DMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void); +void DMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void); +void DMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void); +void DMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void); +void DMA_UART4_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void); +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void); +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void); +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void); +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/drivers/fsl_lpuart.h b/drivers/fsl_lpuart.h new file mode 100644 index 0000000..062b899 --- /dev/null +++ b/drivers/fsl_lpuart.h @@ -0,0 +1,933 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITY bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/* @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base LPUART peripheral base address. + * @param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable); + +/*! + * @brief Set the LPUART address. + * + * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address + * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being + * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one + * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in + * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with + * unmatched address. + * + * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base LPUART peripheral base address. + * @param address1 LPUART slave address1. + * @param address2 LPUART slave address2. + */ +static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2) +{ + /* Configure match address. */ + uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL; + base->MATCH = address; +} + +/*! + * @brief Enable the LPUART match address feature. + * + * @param base LPUART peripheral base address. + * @param match1 true to enable match address1, false to disable. + * @param match2 true to enable match address2, false to disable. + */ +static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2) +{ + /* Configure match address1 enable bit. */ + if (match1) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK; + } + /* Configure match address2 enable bit. */ + if (match2) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base LPUART peripheral base address. + * @param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address); + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/flags.cmake b/flags.cmake new file mode 100644 index 0000000..d345c2e --- /dev/null +++ b/flags.cmake @@ -0,0 +1,524 @@ +SET(CMAKE_ASM_FLAGS_DEBUG " \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_SDRAM_DEBUG " \ + -D__STARTUP_CLEAR_BSS \ + -DDEBUG \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -g \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_ASM_FLAGS_SDRAM_RELEASE " \ + -D__STARTUP_CLEAR_BSS \ + -DNDEBUG \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") 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+ -Os \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG " \ + -DXIP_EXTERNAL_FLASH=1 \ + -DXIP_BOOT_HEADER_ENABLE=1 \ + -DDEBUG \ + -DCPU_MIMXRT1052DVL6B \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DFSL_RTOS_FREE_RTOS \ + -g \ + -O0 \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE " \ + -DXIP_EXTERNAL_FLASH=1 \ + -DXIP_BOOT_HEADER_ENABLE=1 \ + -DNDEBUG \ + -DCPU_MIMXRT1052DVL6B \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DFSL_RTOS_FREE_RTOS \ + -Os \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -g \ + -O0 \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -Os \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_SDRAM_DEBUG " \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -g \ + -O0 \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_SDRAM_RELEASE " \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -Os \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_DEBUG " \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -g \ + -O0 \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_RELEASE " \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -Os \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + -g \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_SDRAM_DEBUG " \ + -g \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_SDRAM_RELEASE " \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_DEBUG " \ + -g \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_RELEASE " \ + -mcpu=cortex-m7 \ + -Wall \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + --specs=nano.specs \ + --specs=nosys.specs \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld -static \ +") diff --git a/freertos/freertos_kernel/croutine.c b/freertos/freertos_kernel/croutine.c new file mode 100644 index 0000000..6d2e479 --- /dev/null +++ b/freertos/freertos_kernel/croutine.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + + +/* Lists for ready and blocked co-routines. --------------------*/ +static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +CRCB_t * pxCurrentCoRoutine = NULL; +static UBaseType_t uxTopCoRoutineReadyPriority = 0; +static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) +{ +BaseType_t xReturn; +CRCB_t *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) +{ +TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckDelayedList( void ) +{ +CRCB_t *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) +{ +CRCB_t *pxUnblockedCRCB; +BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. This function assumes that a + check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +#endif /* configUSE_CO_ROUTINES == 0 */ + diff --git a/freertos/freertos_kernel/event_groups.c b/freertos/freertos_kernel/event_groups.c new file mode 100644 index 0000000..090bf11 --- /dev/null +++ b/freertos/freertos_kernel/event_groups.c @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t const * const pxEventBits = xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t const * pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/freertos/freertos_kernel/include/FreeRTOS.h b/freertos/freertos_kernel/include/FreeRTOS.h new file mode 100644 index 0000000..a3946b6 --- /dev/null +++ b/freertos/freertos_kernel/include/FreeRTOS.h @@ -0,0 +1,1295 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. +The CBMC proofs need a way to track assumptions and assertions. +A configPRECONDITION statement should express an implicit invariant or +assumption made. A configASSERT statement should express an invariant that must +hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT(X) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void *pvDummy5; + TaskFunction_t pvDummy6; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/freertos/freertos_kernel/include/StackMacros.h b/freertos/freertos_kernel/include/StackMacros.h new file mode 100644 index 0000000..00f92dc --- /dev/null +++ b/freertos/freertos_kernel/include/StackMacros.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ + diff --git a/freertos/freertos_kernel/include/atomic.h b/freertos/freertos_kernel/include/atomic.h new file mode 100644 index 0000000..d4f87f9 --- /dev/null +++ b/freertos/freertos_kernel/include/atomic.h @@ -0,0 +1,414 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + + /* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + + /* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ +uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ +void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ +uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ATOMIC_H */ diff --git a/freertos/freertos_kernel/include/croutine.h b/freertos/freertos_kernel/include/croutine.h new file mode 100644 index 0000000..9fae2d9 --- /dev/null +++ b/freertos/freertos_kernel/include/croutine.h @@ -0,0 +1,720 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
+ void vCoRoutineSchedule( void );
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineSchedule() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ crSTART( CoRoutineHandle_t xHandle );
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
+ crEND();
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/freertos/freertos_kernel/include/deprecated_definitions.h b/freertos/freertos_kernel/include/deprecated_definitions.h new file mode 100644 index 0000000..381e9f5 --- /dev/null +++ b/freertos/freertos_kernel/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/freertos/freertos_kernel/include/event_groups.h b/freertos/freertos_kernel/include/event_groups.h new file mode 100644 index 0000000..a373561 --- /dev/null +++ b/freertos/freertos_kernel/include/event_groups.h @@ -0,0 +1,757 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+ */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/freertos/freertos_kernel/include/freertos_tasks_c_additions.h b/freertos/freertos_kernel/include/freertos_tasks_c_additions.h new file mode 100644 index 0000000..4be41bb --- /dev/null +++ b/freertos/freertos_kernel/include/freertos_tasks_c_additions.h @@ -0,0 +1,122 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* freertos_tasks_c_additions.h Rev. 1.3 */ +#ifndef FREERTOS_TASKS_C_ADDITIONS_H +#define FREERTOS_TASKS_C_ADDITIONS_H + +#include + +#if (configUSE_TRACE_FACILITY == 0) +#error "configUSE_TRACE_FACILITY must be enabled" +#endif + +#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1 +#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3 + +/* NOTE!! + * Default to a FreeRTOS version which didn't include these macros. FreeRTOS + * v7.5.3 is used here. + */ +#ifndef tskKERNEL_VERSION_BUILD +#define tskKERNEL_VERSION_BUILD 3 +#endif +#ifndef tskKERNEL_VERSION_MINOR +#define tskKERNEL_VERSION_MINOR 5 +#endif +#ifndef tskKERNEL_VERSION_MAJOR +#define tskKERNEL_VERSION_MAJOR 7 +#endif + +/* NOTE!! + * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value + * 1 - 5 which corresponds to the following schemes: + * + * heap_1 - the very simplest, does not permit memory to be freed + * heap_2 - permits memory to be freed, but not does coalescence adjacent free + * blocks. + * heap_3 - simply wraps the standard malloc() and free() for thread safety + * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes + * absolute address placement option + * heap_5 - as per heap_4, with the ability to span the heap across + * multiple nonOadjacent memory areas + */ +#ifndef configFRTOS_MEMORY_SCHEME +#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */ +#endif + +#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1)) +#error "Invalid configFRTOS_MEMORY_SCHEME setting!" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +extern const uint8_t FreeRTOSDebugConfig[]; + +/* NOTES!! + * IAR documentation is confusing. It suggests the data must be statically + * linked, and the #pragma placed immediately before the symbol definition. + * The IAR supplied examples violate both "rules", so this is a best guess. + */ + +#if (tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2) +#if defined(__GNUC__) +char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME; +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +char *const portArch_Name __attribute__((used)) = portARCH_NAME; +#elif defined(__IAR_SYSTEMS_ICC__) +char *const portArch_Name = portARCH_NAME; +#pragma required=portArch_Name +#endif +#else +char *const portArch_Name = NULL; +#endif // tskKERNEL_VERSION_MAJOR + +#if defined(__GNUC__) +const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) = +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) = +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma required=FreeRTOSDebugConfig +const uint8_t FreeRTOSDebugConfig[] = +#endif +{ + FREERTOS_DEBUG_CONFIG_MAJOR_VERSION, + FREERTOS_DEBUG_CONFIG_MINOR_VERSION, + tskKERNEL_VERSION_MAJOR, + tskKERNEL_VERSION_MINOR, + tskKERNEL_VERSION_BUILD, + configFRTOS_MEMORY_SCHEME, + offsetof(struct tskTaskControlBlock, pxTopOfStack), +#if (tskKERNEL_VERSION_MAJOR > 8) + offsetof(struct tskTaskControlBlock, xStateListItem), +#else + offsetof(struct tskTaskControlBlock, xGenericListItem), +#endif + offsetof(struct tskTaskControlBlock, xEventListItem), + offsetof(struct tskTaskControlBlock, pxStack), + offsetof(struct tskTaskControlBlock, pcTaskName), + offsetof(struct tskTaskControlBlock, uxTCBNumber), + offsetof(struct tskTaskControlBlock, uxTaskNumber), + configMAX_TASK_NAME_LEN, + configMAX_PRIORITIES, + configENABLE_MPU, + configENABLE_FPU, + configENABLE_TRUSTZONE, + configRUN_FREERTOS_SECURE_ONLY, + 0, // 32-bit align + 0, 0, 0, 0 // padding +}; + +#ifdef __cplusplus +} +#endif + +#endif // FREERTOS_TASKS_C_ADDITIONS_H diff --git a/freertos/freertos_kernel/include/list.h b/freertos/freertos_kernel/include/list.h new file mode 100644 index 0000000..6eaa0b8 --- /dev/null +++ b/freertos/freertos_kernel/include/list.h @@ -0,0 +1,412 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/freertos/freertos_kernel/include/message_buffer.h b/freertos/freertos_kernel/include/message_buffer.h new file mode 100644 index 0000000..7430039 --- /dev/null +++ b/freertos/freertos_kernel/include/message_buffer.h @@ -0,0 +1,803 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ 
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 

+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/freertos/freertos_kernel/include/mpu_prototypes.h b/freertos/freertos_kernel/include/mpu_prototypes.h
new file mode 100644
index 0000000..58a2330
--- /dev/null
+++ b/freertos/freertos_kernel/include/mpu_prototypes.h
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/freertos/freertos_kernel/include/mpu_wrappers.h b/freertos/freertos_kernel/include/mpu_wrappers.h
new file mode 100644
index 0000000..30506cd
--- /dev/null
+++ b/freertos/freertos_kernel/include/mpu_wrappers.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
+		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/freertos/freertos_kernel/include/portable.h b/freertos/freertos_kernel/include/portable.h
new file mode 100644
index 0000000..6ee3f61
--- /dev/null
+++ b/freertos/freertos_kernel/include/portable.h
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c to define the start address and size of each memory region
+that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/freertos/freertos_kernel/include/projdefs.h b/freertos/freertos_kernel/include/projdefs.h
new file mode 100644
index 0000000..3ada620
--- /dev/null
+++ b/freertos/freertos_kernel/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/freertos/freertos_kernel/include/queue.h b/freertos/freertos_kernel/include/queue.h
new file mode 100644
index 0000000..a10ba67
--- /dev/null
+++ b/freertos/freertos_kernel/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 

+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 

+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 

+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );

+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);

+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
void vQueueDelete( QueueHandle_t xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 

+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 

+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/freertos/freertos_kernel/include/semphr.h b/freertos/freertos_kernel/include/semphr.h
new file mode 100644
index 0000000..1b61f53
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+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 

+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )

+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 

+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/freertos/freertos_kernel/include/stack_macros.h b/freertos/freertos_kernel/include/stack_macros.h
new file mode 100644
index 0000000..c9d423a
--- /dev/null
+++ b/freertos/freertos_kernel/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/freertos/freertos_kernel/include/stream_buffer.h b/freertos/freertos_kernel/include/stream_buffer.h
new file mode 100644
index 0000000..d3bb267
--- /dev/null
+++ b/freertos/freertos_kernel/include/stream_buffer.h
@@ -0,0 +1,859 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+

+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/freertos/freertos_kernel/include/task.h b/freertos/freertos_kernel/include/task.h
new file mode 100644
index 0000000..8c2a3ad
--- /dev/null
+++ b/freertos/freertos_kernel/include/task.h
@@ -0,0 +1,2543 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.3.0"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 3
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+	 configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+	 if( xHandle != NULL )
+	 {
+	 	vTaskDelete( xHandle );
+	 }
+ }
+   

+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   

+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelete( TaskHandle_t xTask );

+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   

+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskDelay( const TickType_t xTicksToDelay );

+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   

+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
eTaskState eTaskGetState( TaskHandle_t xTask );

+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   

+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   

+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   

+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskResume( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   

+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskStartScheduler( void );

+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   

+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskEndScheduler( void );

+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   

+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspendAll( void );

+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   

+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskResumeAll( void );

+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   

+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCount( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCountFromISR( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint16_t uxTaskGetNumberOfTasks( void );

+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	

+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskList( char *pcWriteBuffer );

+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* 
uint32_t ulTaskGetIdleRunTimeCounter( void );

+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/**
+* task. h
+* 
uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );

+*
+* Clears the bits specified by the ulBitsToClear bit mask in the notification
+* value of the task referenced by xTask.
+*
+* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+* the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+* notification value without clearing any bits.
+*
+* @return The value of the target task's notification value before the bits
+* specified by ulBitsToClear were cleared.
+* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+* \ingroup TaskNotifications
+*/
+uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )

+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );

+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.freertos.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * 
+	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ 

+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/* Correct the tick count value after the application code has held
+interrupts disabled for an extended period.  xTicksToCatchUp is the number
+of tick interrupts that have been missed due to interrupts being disabled.
+Its value is not computed automatically, so must be computed by the
+application writer.
+
+This function is similar to vTaskStepTick(), however, unlike
+vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+time at which a task should be removed from the blocked state.  That means
+tasks may have to be removed from the blocked state as the tick count is
+moved. */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/freertos/freertos_kernel/include/timers.h b/freertos/freertos_kernel/include/timers.h
new file mode 100644
index 0000000..4ad023d
--- /dev/null
+++ b/freertos/freertos_kernel/include/timers.h
@@ -0,0 +1,1309 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+*
+* Queries a timer to determine if it is an auto-reload timer, in which case the timer
+* automatically resets itself each time it expires, or a one-shot timer, in
+* which case the timer will only expire once unless it is manually restarted.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+* pdFALSE is returned.
+*/
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/freertos/freertos_kernel/list.c b/freertos/freertos_kernel/list.c
new file mode 100644
index 0000000..ce493e6
--- /dev/null
+++ b/freertos/freertos_kernel/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c b/freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c
new file mode 100644
index 0000000..696d8d0
--- /dev/null
+++ b/freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrupts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/freertos/freertos_kernel/portable/GCC/ARM_CM4F/portmacro.h b/freertos/freertos_kernel/portable/GCC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..e71ae1b
--- /dev/null
+++ b/freertos/freertos_kernel/portable/GCC/ARM_CM4F/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/freertos/freertos_kernel/portable/MemMang/ReadMe.url b/freertos/freertos_kernel/portable/MemMang/ReadMe.url
new file mode 100644
index 0000000..6c23737
--- /dev/null
+++ b/freertos/freertos_kernel/portable/MemMang/ReadMe.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=http://www.freertos.org/a00111.html
+IDList=
diff --git a/freertos/freertos_kernel/portable/MemMang/heap_4.c b/freertos/freertos_kernel/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..80b926e
--- /dev/null
+++ b/freertos/freertos_kernel/portable/MemMang/heap_4.c
@@ -0,0 +1,492 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+					xNumberOfSuccessfulAllocations++;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+					xNumberOfSuccessfulFrees++;
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t *pxHeapStats )
+{
+BlockLink_t *pxBlock;
+size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+	vTaskSuspendAll();
+	{
+		pxBlock = xStart.pxNextFreeBlock;
+
+		/* pxBlock will be NULL if the heap has not been initialised.  The heap
+		is initialised automatically when the first allocation is made. */
+		if( pxBlock != NULL )
+		{
+			do
+			{
+				/* Increment the number of blocks and record the largest block seen
+				so far. */
+				xBlocks++;
+
+				if( pxBlock->xBlockSize > xMaxSize )
+				{
+					xMaxSize = pxBlock->xBlockSize;
+				}
+
+				if( pxBlock->xBlockSize < xMinSize )
+				{
+					xMinSize = pxBlock->xBlockSize;
+				}
+
+				/* Move to the next block in the chain until the last block is
+				reached. */
+				pxBlock = pxBlock->pxNextFreeBlock;
+			} while( pxBlock != pxEnd );
+		}
+	}
+	xTaskResumeAll();
+
+	pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+	pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+	pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+	taskENTER_CRITICAL();
+	{
+		pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+		pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+		pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+		pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+	}
+	taskEXIT_CRITICAL();
+}
+
diff --git a/freertos/freertos_kernel/portable/readme.txt b/freertos/freertos_kernel/portable/readme.txt
new file mode 100644
index 0000000..b68d2d5
--- /dev/null
+++ b/freertos/freertos_kernel/portable/readme.txt
@@ -0,0 +1,20 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are
+specific to a particular microcontroller and/or compiler.
+
+
++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
+memory allocators as described on the http://www.FreeRTOS.org WEB site.
+
++ The other directories each contain files specific to a particular
+microcontroller or compiler, where the directory name denotes the compiler
+specific files the directory contains.
+
+
+
+For example, if you are interested in the [compiler] port for the [architecture]
+microcontroller, then the port specific files are contained in
+FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
+only port you are interested in then all the other directories can be
+ignored.
+
diff --git a/freertos/freertos_kernel/queue.c b/freertos/freertos_kernel/queue.c
new file mode 100644
index 0000000..abc762b
--- /dev/null
+++ b/freertos/freertos_kernel/queue.c
@@ -0,0 +1,2947 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					
+					/* Not used in this path. */
+					( void ) uxPreviousMessagesWaiting;
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+void *pvBuffer = NULL;
+(void)pvBuffer;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/freertos/freertos_kernel/stream_buffer.c b/freertos/freertos_kernel/stream_buffer.c
new file mode 100644
index 0000000..01cb556
--- /dev/null
+++ b/freertos/freertos_kernel/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/freertos/freertos_kernel/tasks.c b/freertos/freertos_kernel/tasks.c
new file mode 100644
index 0000000..15d1231
--- /dev/null
+++ b/freertos/freertos_kernel/tasks.c
@@ -0,0 +1,5310 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks.
+
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks 			= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready/delayed list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+				portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+				traceTASK_DELETE( pxTCB );
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				traceTASK_DELETE( pxTCB );
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+
+	/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+						} while( xPendedCounts > ( TickType_t ) 0U );
+
+						xPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+BaseType_t xYieldRequired = pdFALSE;
+
+	/* Must not be called with the scheduler suspended as the implementation
+	relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+	configASSERT( uxSchedulerSuspended == 0 );
+
+	/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+	the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+	vTaskSuspendAll();
+	xPendedTicks += xTicksToCatchUp;
+	xYieldRequired = xTaskResumeAll();
+
+	return xYieldRequired;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+						/* This lets the task know it was forcibly removed from the
+						blocked state so it should not re-evaluate its block time and
+						then block again. */
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( xPendedTicks == ( TickType_t ) 0 )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		/* This function must be called from a critical section. */
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			configASSERT( pxTCB != NULL );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )
+	{
+	TCB_t *pxTCB;
+	uint32_t ulReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			/* Return the notification as it was before the bits were cleared,
+			then clear the bit mask. */
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+			pxTCB->ulNotifiedValue &= ~ulBitsToClear;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+	uint32_t ulTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/freertos/freertos_kernel/timers.c b/freertos/freertos_kernel/timers.c
new file mode 100644
index 0000000..6bd2f43
--- /dev/null
+++ b/freertos/freertos_kernel/timers.c
@@ -0,0 +1,1127 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The auto-reload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			auto-reload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+UBaseType_t uxReturn;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+		{
+			/* Not an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdFALSE;
+		}
+		else
+		{
+			/* Is an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/freertos/middleware_freertos-kernel_MIMXRT1052.cmake b/freertos/middleware_freertos-kernel_MIMXRT1052.cmake
new file mode 100644
index 0000000..3971919
--- /dev/null
+++ b/freertos/middleware_freertos-kernel_MIMXRT1052.cmake
@@ -0,0 +1,25 @@
+if(NOT MIDDLEWARE_FREERTOS-KERNEL_MIMXRT1052_INCLUDED)
+
+set(MIDDLEWARE_FREERTOS-KERNEL_MIMXRT1052_INCLUDED true CACHE BOOL "middleware_freertos-kernel component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/croutine.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/event_groups.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/list.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/GCC/ARM_CM4F/port.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/queue.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/stream_buffer.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/tasks.c
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/timers.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/include
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/GCC/ARM_CM4F
+)
+
+
+include(middleware_freertos-kernel_extension_MIMXRT1052)
+
+endif()
diff --git a/freertos/middleware_freertos-kernel_extension_MIMXRT1052.cmake b/freertos/middleware_freertos-kernel_extension_MIMXRT1052.cmake
new file mode 100644
index 0000000..0a4e9cb
--- /dev/null
+++ b/freertos/middleware_freertos-kernel_extension_MIMXRT1052.cmake
@@ -0,0 +1,10 @@
+if(NOT MIDDLEWARE_FREERTOS-KERNEL_EXTENSION_MIMXRT1052_INCLUDED)
+
+set(MIDDLEWARE_FREERTOS-KERNEL_EXTENSION_MIMXRT1052_INCLUDED true CACHE BOOL "middleware_freertos-kernel_extension component is included.")
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/include
+)
+
+endif()
diff --git a/freertos/middleware_freertos-kernel_heap_4_MIMXRT1052.cmake b/freertos/middleware_freertos-kernel_heap_4_MIMXRT1052.cmake
new file mode 100644
index 0000000..ff6dc99
--- /dev/null
+++ b/freertos/middleware_freertos-kernel_heap_4_MIMXRT1052.cmake
@@ -0,0 +1,12 @@
+if(NOT MIDDLEWARE_FREERTOS-KERNEL_HEAP_4_MIMXRT1052_INCLUDED)
+
+set(MIDDLEWARE_FREERTOS-KERNEL_HEAP_4_MIMXRT1052_INCLUDED true CACHE BOOL "middleware_freertos-kernel_heap_4 component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/MemMang/heap_4.c
+)
+
+
+include(middleware_freertos-kernel_MIMXRT1052)
+
+endif()
diff --git a/rt1050_freertos_hello.mex b/rt1050_freertos_hello.mex
new file mode 100644
index 0000000..4a24c52
--- /dev/null
+++ b/rt1050_freertos_hello.mex
@@ -0,0 +1,476 @@
+
+
+   
+      MIMXRT1052xxxxB
+      MIMXRT1052DVL6B
+      IMXRT1050-EVKB
+      ksdk2_0
+      
+         
+      
+      Configuration imported from /home/imi415/Documents/Hardwares/Kinetis_Projects/rt1050_freertos_hello
+   
+   
+      true
+      false
+      false
+   
+   
+      
+         
+            
+            
+         
+         
+            9.0.0
+            
+         
+         
+            
+               Configures pin routing and optionally pin electrical features.
+               
+                  true
+                  core0
+                  true
+               
+               
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+               
+               
+                  
+                     
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                     
+                  
+                  
+                     
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                     
+                  
+               
+            
+         
+      
+      
+         
+            
+            
+         
+         
+            9.0.0
+         
+         
+            
+               
+               
+               
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        INPUT
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        OUTPUT
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        INPUT
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        OUTPUT
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+               
+               
+                  
+               
+               
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+               
+               
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+                  
+               
+               true
+            
+         
+      
+      
+         
+            
+            
+         
+         
+            9.0.0
+            c_array
+         
+         
+            
+               
+               
+               
+                  
+                     
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                        
+                     
+                  
+               
+            
+         
+      
+      
+         
+            
+               
+                  true
+               
+            
+            
+               
+                  2.2.8
+               
+            
+         
+         
+            
+            
+         
+         
+            9.0.0
+         
+         
+            
+               
+               
+               
+                  
+                     
+                        0
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+                  
+                     
+                        true
+                     
+                  
+               
+               
+                  
+                     
+                        
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                           
+                        
+                     
+                  
+               
+            
+         
+         
+            
+               
+                  
+                  
+               
+            
+            
+               
+            
+            
+               
+            
+            
+               
+            
+         
+      
+      
+         
+         
+            N/A
+         
+         
+         
+      
+   
+
\ No newline at end of file
diff --git a/source/FreeRTOSConfig.h b/source/FreeRTOSConfig.h
new file mode 100644
index 0000000..dbe7163
--- /dev/null
+++ b/source/FreeRTOSConfig.h
@@ -0,0 +1,157 @@
+/*
+FreeRTOS Kernel V10.3.0
+Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ http://aws.amazon.com/freertos
+ http://www.FreeRTOS.org
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_TICKLESS_IDLE                 0
+#define configCPU_CLOCK_HZ                      (SystemCoreClock)
+#define configTICK_RATE_HZ                      ((TickType_t)200)
+#define configMAX_PRIORITIES                    5
+#define configMINIMAL_STACK_SIZE                ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN                 20
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_TASK_NOTIFICATIONS            1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE               8
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME               4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+#define configTOTAL_HEAP_SIZE                   ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                     0
+#define configUSE_TICK_HOOK                     0
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#define configUSE_MALLOC_FAILED_HOOK            0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                1
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS         1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES                   0
+#define configMAX_CO_ROUTINE_PRIORITIES         2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                        1
+#define configTIMER_TASK_PRIORITY               (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH                10
+#define configTIMER_TASK_STACK_DEPTH            (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet                1
+#define INCLUDE_uxTaskPriorityGet               1
+#define INCLUDE_vTaskDelete                     1
+#define INCLUDE_vTaskSuspend                    1
+#define INCLUDE_vTaskDelayUntil                 1
+#define INCLUDE_vTaskDelay                      1
+#define INCLUDE_xTaskGetSchedulerState          1
+#define INCLUDE_xTaskGetCurrentTaskHandle       1
+#define INCLUDE_uxTaskGetStackHighWaterMark     0
+#define INCLUDE_xTaskGetIdleTaskHandle          0
+#define INCLUDE_eTaskGetState                   0
+#define INCLUDE_xTimerPendFunctionCall          1
+#define INCLUDE_xTaskAbortDelay                 0
+#define INCLUDE_xTaskGetHandle                  0
+#define INCLUDE_xTaskResumeFromISR              1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+    /* Clock manager provides in this variable system core clock frequency */
+    #include 
+    extern uint32_t SystemCoreClock;
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/source/freertos_hello.c b/source/freertos_hello.c
new file mode 100644
index 0000000..da654ba
--- /dev/null
+++ b/source/freertos_hello.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Task priorities. */
+#define hello_task_PRIORITY (configMAX_PRIORITIES - 1)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void hello_task(void *pvParameters);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Application entry point.
+ */
+int main(void)
+{
+    /* Init board hardware. */
+    BOARD_ConfigMPU();
+    BOARD_InitBootPins();
+    BOARD_InitBootClocks();
+    BOARD_InitDebugConsole();
+    if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) !=
+        pdPASS)
+    {
+        PRINTF("Task creation failed!.\r\n");
+        while (1)
+            ;
+    }
+    vTaskStartScheduler();
+    for (;;)
+        ;
+}
+
+/*!
+ * @brief Task responsible for printing of "Hello world." message.
+ */
+static void hello_task(void *pvParameters)
+{
+    for (;;)
+    {
+        PRINTF("Hello world.\r\n");
+        vTaskSuspend(NULL);
+    }
+}
diff --git a/startup/device_MIMXRT1052_startup_MIMXRT1052.cmake b/startup/device_MIMXRT1052_startup_MIMXRT1052.cmake
new file mode 100644
index 0000000..cd173f3
--- /dev/null
+++ b/startup/device_MIMXRT1052_startup_MIMXRT1052.cmake
@@ -0,0 +1,12 @@
+if(NOT DEVICE_MIMXRT1052_STARTUP_MIMXRT1052_INCLUDED)
+
+set(DEVICE_MIMXRT1052_STARTUP_MIMXRT1052_INCLUDED true CACHE BOOL "device_MIMXRT1052_startup component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/startup_MIMXRT1052.S
+)
+
+
+include(device_MIMXRT1052_system_MIMXRT1052)
+
+endif()
diff --git a/startup/startup_MIMXRT1052.S b/startup/startup_MIMXRT1052.S
new file mode 100644
index 0000000..42279f1
--- /dev/null
+++ b/startup/startup_MIMXRT1052.S
@@ -0,0 +1,1077 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_MIMXRT1052.s                                           */
+/*  @purpose: CMSIS Cortex-M7 Core Device Startup File                       */
+/*            MIMXRT1052                                                     */
+/*  @version: 1.3                                                            */
+/*  @date:    2019-4-29                                                      */
+/*  @build:   b190919                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2019 NXP                                                   */
+/* All rights reserved.                                                      */
+/*                                                                           */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0/16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1/17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2/18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3/19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4/20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5/21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6/22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7/23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8/24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9/25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10/26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11/27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12/28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13/29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14/30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15/31 transfer complete*/
+    .long   DMA_ERROR_IRQHandler                            /* DMA error interrupt channels 0-15 / 16-31*/
+    .long   CTI0_ERROR_IRQHandler                           /* CTI0_Error*/
+    .long   CTI1_ERROR_IRQHandler                           /* CTI1_Error*/
+    .long   CORE_IRQHandler                                 /* CorePlatform exception IRQ*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 TX interrupt and RX interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 TX interrupt and RX interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 TX interrupt and RX interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 TX interrupt and RX interrupt*/
+    .long   LPUART5_IRQHandler                              /* LPUART5 TX interrupt and RX interrupt*/
+    .long   LPUART6_IRQHandler                              /* LPUART6 TX interrupt and RX interrupt*/
+    .long   LPUART7_IRQHandler                              /* LPUART7 TX interrupt and RX interrupt*/
+    .long   LPUART8_IRQHandler                              /* LPUART8 TX interrupt and RX interrupt*/
+    .long   LPI2C1_IRQHandler                               /* LPI2C1 interrupt*/
+    .long   LPI2C2_IRQHandler                               /* LPI2C2 interrupt*/
+    .long   LPI2C3_IRQHandler                               /* LPI2C3 interrupt*/
+    .long   LPI2C4_IRQHandler                               /* LPI2C4 interrupt*/
+    .long   LPSPI1_IRQHandler                               /* LPSPI1 single interrupt vector for all sources*/
+    .long   LPSPI2_IRQHandler                               /* LPSPI2 single interrupt vector for all sources*/
+    .long   LPSPI3_IRQHandler                               /* LPSPI3 single interrupt vector for all sources*/
+    .long   LPSPI4_IRQHandler                               /* LPSPI4  single interrupt vector for all sources*/
+    .long   CAN1_IRQHandler                                 /* CAN1 interrupt*/
+    .long   CAN2_IRQHandler                                 /* CAN2 interrupt*/
+    .long   FLEXRAM_IRQHandler                              /* FlexRAM address out of range Or access hit IRQ*/
+    .long   KPP_IRQHandler                                  /* Keypad nterrupt*/
+    .long   TSC_DIG_IRQHandler                              /* TSC interrupt*/
+    .long   GPR_IRQ_IRQHandler                              /* GPR interrupt*/
+    .long   LCDIF_IRQHandler                                /* LCDIF interrupt*/
+    .long   CSI_IRQHandler                                  /* CSI interrupt*/
+    .long   PXP_IRQHandler                                  /* PXP interrupt*/
+    .long   WDOG2_IRQHandler                                /* WDOG2 interrupt*/
+    .long   SNVS_HP_WRAPPER_IRQHandler                      /* SRTC Consolidated Interrupt. Non TZ*/
+    .long   SNVS_HP_WRAPPER_TZ_IRQHandler                   /* SRTC Security Interrupt. TZ*/
+    .long   SNVS_LP_WRAPPER_IRQHandler                      /* ON-OFF button press shorter than 5 secs (pulse event)*/
+    .long   CSU_IRQHandler                                  /* CSU interrupt*/
+    .long   DCP_IRQHandler                                  /* DCP_IRQ interrupt*/
+    .long   DCP_VMI_IRQHandler                              /* DCP_VMI_IRQ interrupt*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt*/
+    .long   TRNG_IRQHandler                                 /* TRNG interrupt*/
+    .long   SJC_IRQHandler                                  /* SJC interrupt*/
+    .long   BEE_IRQHandler                                  /* BEE interrupt*/
+    .long   SAI1_IRQHandler                                 /* SAI1 interrupt*/
+    .long   SAI2_IRQHandler                                 /* SAI1 interrupt*/
+    .long   SAI3_RX_IRQHandler                              /* SAI3 interrupt*/
+    .long   SAI3_TX_IRQHandler                              /* SAI3 interrupt*/
+    .long   SPDIF_IRQHandler                                /* SPDIF interrupt*/
+    .long   PMU_EVENT_IRQHandler                            /* Brown-out event interrupt*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt*/
+    .long   TEMP_LOW_HIGH_IRQHandler                        /* TempSensor low/high interrupt*/
+    .long   TEMP_PANIC_IRQHandler                           /* TempSensor panic interrupt*/
+    .long   USB_PHY1_IRQHandler                             /* USBPHY (UTMI0), Interrupt*/
+    .long   USB_PHY2_IRQHandler                             /* USBPHY (UTMI0), Interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   ADC2_IRQHandler                                 /* ADC2 interrupt*/
+    .long   DCDC_IRQHandler                                 /* DCDC interrupt*/
+    .long   Reserved86_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved87_IRQHandler                           /* Reserved interrupt*/
+    .long   GPIO1_INT0_IRQHandler                           /* Active HIGH Interrupt from INT0 from GPIO*/
+    .long   GPIO1_INT1_IRQHandler                           /* Active HIGH Interrupt from INT1 from GPIO*/
+    .long   GPIO1_INT2_IRQHandler                           /* Active HIGH Interrupt from INT2 from GPIO*/
+    .long   GPIO1_INT3_IRQHandler                           /* Active HIGH Interrupt from INT3 from GPIO*/
+    .long   GPIO1_INT4_IRQHandler                           /* Active HIGH Interrupt from INT4 from GPIO*/
+    .long   GPIO1_INT5_IRQHandler                           /* Active HIGH Interrupt from INT5 from GPIO*/
+    .long   GPIO1_INT6_IRQHandler                           /* Active HIGH Interrupt from INT6 from GPIO*/
+    .long   GPIO1_INT7_IRQHandler                           /* Active HIGH Interrupt from INT7 from GPIO*/
+    .long   GPIO1_Combined_0_15_IRQHandler                  /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
+    .long   GPIO1_Combined_16_31_IRQHandler                 /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
+    .long   GPIO2_Combined_0_15_IRQHandler                  /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
+    .long   GPIO2_Combined_16_31_IRQHandler                 /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
+    .long   GPIO3_Combined_0_15_IRQHandler                  /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
+    .long   GPIO3_Combined_16_31_IRQHandler                 /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
+    .long   GPIO4_Combined_0_15_IRQHandler                  /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
+    .long   GPIO4_Combined_16_31_IRQHandler                 /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
+    .long   GPIO5_Combined_0_15_IRQHandler                  /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
+    .long   GPIO5_Combined_16_31_IRQHandler                 /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
+    .long   FLEXIO1_IRQHandler                              /* FLEXIO1 interrupt*/
+    .long   FLEXIO2_IRQHandler                              /* FLEXIO2 interrupt*/
+    .long   WDOG1_IRQHandler                                /* WDOG1 interrupt*/
+    .long   RTWDOG_IRQHandler                               /* RTWDOG interrupt*/
+    .long   EWM_IRQHandler                                  /* EWM interrupt*/
+    .long   CCM_1_IRQHandler                                /* CCM IRQ1 interrupt*/
+    .long   CCM_2_IRQHandler                                /* CCM IRQ2 interrupt*/
+    .long   GPC_IRQHandler                                  /* GPC interrupt*/
+    .long   SRC_IRQHandler                                  /* SRC interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   GPT1_IRQHandler                                 /* GPT1 interrupt*/
+    .long   GPT2_IRQHandler                                 /* GPT2 interrupt*/
+    .long   PWM1_0_IRQHandler                               /* PWM1 capture 0, compare 0, or reload 0 interrupt*/
+    .long   PWM1_1_IRQHandler                               /* PWM1 capture 1, compare 1, or reload 0 interrupt*/
+    .long   PWM1_2_IRQHandler                               /* PWM1 capture 2, compare 2, or reload 0 interrupt*/
+    .long   PWM1_3_IRQHandler                               /* PWM1 capture 3, compare 3, or reload 0 interrupt*/
+    .long   PWM1_FAULT_IRQHandler                           /* PWM1 fault or reload error interrupt*/
+    .long   Reserved123_IRQHandler                          /* Reserved interrupt*/
+    .long   FLEXSPI_IRQHandler                              /* FlexSPI0 interrupt*/
+    .long   SEMC_IRQHandler                                 /* Reserved interrupt*/
+    .long   USDHC1_IRQHandler                               /* USDHC1 interrupt*/
+    .long   USDHC2_IRQHandler                               /* USDHC2 interrupt*/
+    .long   USB_OTG2_IRQHandler                             /* USBO2 USB OTG2*/
+    .long   USB_OTG1_IRQHandler                             /* USBO2 USB OTG1*/
+    .long   ENET_IRQHandler                                 /* ENET interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* ENET_1588_Timer interrupt*/
+    .long   XBAR1_IRQ_0_1_IRQHandler                        /* XBAR1 interrupt*/
+    .long   XBAR1_IRQ_2_3_IRQHandler                        /* XBAR1 interrupt*/
+    .long   ADC_ETC_IRQ0_IRQHandler                         /* ADCETC IRQ0 interrupt*/
+    .long   ADC_ETC_IRQ1_IRQHandler                         /* ADCETC IRQ1 interrupt*/
+    .long   ADC_ETC_IRQ2_IRQHandler                         /* ADCETC IRQ2 interrupt*/
+    .long   ADC_ETC_ERROR_IRQ_IRQHandler                    /* ADCETC Error IRQ interrupt*/
+    .long   PIT_IRQHandler                                  /* PIT interrupt*/
+    .long   ACMP1_IRQHandler                                /* ACMP interrupt*/
+    .long   ACMP2_IRQHandler                                /* ACMP interrupt*/
+    .long   ACMP3_IRQHandler                                /* ACMP interrupt*/
+    .long   ACMP4_IRQHandler                                /* ACMP interrupt*/
+    .long   Reserved143_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved144_IRQHandler                          /* Reserved interrupt*/
+    .long   ENC1_IRQHandler                                 /* ENC1 interrupt*/
+    .long   ENC2_IRQHandler                                 /* ENC2 interrupt*/
+    .long   ENC3_IRQHandler                                 /* ENC3 interrupt*/
+    .long   ENC4_IRQHandler                                 /* ENC4 interrupt*/
+    .long   TMR1_IRQHandler                                 /* TMR1 interrupt*/
+    .long   TMR2_IRQHandler                                 /* TMR2 interrupt*/
+    .long   TMR3_IRQHandler                                 /* TMR3 interrupt*/
+    .long   TMR4_IRQHandler                                 /* TMR4 interrupt*/
+    .long   PWM2_0_IRQHandler                               /* PWM2 capture 0, compare 0, or reload 0 interrupt*/
+    .long   PWM2_1_IRQHandler                               /* PWM2 capture 1, compare 1, or reload 0 interrupt*/
+    .long   PWM2_2_IRQHandler                               /* PWM2 capture 2, compare 2, or reload 0 interrupt*/
+    .long   PWM2_3_IRQHandler                               /* PWM2 capture 3, compare 3, or reload 0 interrupt*/
+    .long   PWM2_FAULT_IRQHandler                           /* PWM2 fault or reload error interrupt*/
+    .long   PWM3_0_IRQHandler                               /* PWM3 capture 0, compare 0, or reload 0 interrupt*/
+    .long   PWM3_1_IRQHandler                               /* PWM3 capture 1, compare 1, or reload 0 interrupt*/
+    .long   PWM3_2_IRQHandler                               /* PWM3 capture 2, compare 2, or reload 0 interrupt*/
+    .long   PWM3_3_IRQHandler                               /* PWM3 capture 3, compare 3, or reload 0 interrupt*/
+    .long   PWM3_FAULT_IRQHandler                           /* PWM3 fault or reload error interrupt*/
+    .long   PWM4_0_IRQHandler                               /* PWM4 capture 0, compare 0, or reload 0 interrupt*/
+    .long   PWM4_1_IRQHandler                               /* PWM4 capture 1, compare 1, or reload 0 interrupt*/
+    .long   PWM4_2_IRQHandler                               /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
+    .long   PWM4_3_IRQHandler                               /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
+    .long   PWM4_FAULT_IRQHandler                           /* PWM4 fault or reload error interrupt*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__isr_vector
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      __noncachedata_start__/__noncachedata_end__ : none cachable region
+ *      __ram_function_start__/__ram_function_end__ : ramfunction region
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#else  /* code size implemenation */
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+#endif
+#ifdef __STARTUP_INITIALIZE_RAMFUNCTION
+    ldr    r2, =__ram_function_start__
+    ldr    r3, =__ram_function_end__
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
+    subs    r3, r2
+    ble    .LC_ramfunc_copy_end
+.LC_ramfunc_copy_start:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC_ramfunc_copy_start
+.LC_ramfunc_copy_end:
+#else  /* code size implemenation */
+.LC_ramfunc_copy_start:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC_ramfunc_copy_start
+#endif
+#endif /* __STARTUP_INITIALIZE_RAMFUNCTION */
+#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
+    ldr    r2, =__noncachedata_start__
+    ldr    r3, =__noncachedata_init_end__
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
+    subs    r3, r2
+    ble    .LC3
+.LC2:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC2
+.LC3:
+#else  /* code size implemenation */
+.LC2:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC2
+#endif
+/* zero inited ncache section initialization */
+    ldr r3, =__noncachedata_end__
+    movs    r0,0
+.LC4:
+    cmp    r2,r3
+    itt    lt
+    strlt   r0,[r2],#4
+    blt    .LC4
+#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    movs    r0, 0
+.LC5:
+    cmp     r1, r2
+    itt    lt
+    strlt   r0, [r1], #4
+    blt    .LC5
+#endif /* __STARTUP_CLEAR_BSS */
+
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_DMA16_IRQHandler
+    .type DMA0_DMA16_IRQHandler, %function
+DMA0_DMA16_IRQHandler:
+    ldr   r0,=DMA0_DMA16_DriverIRQHandler
+    bx    r0
+    .size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_DMA17_IRQHandler
+    .type DMA1_DMA17_IRQHandler, %function
+DMA1_DMA17_IRQHandler:
+    ldr   r0,=DMA1_DMA17_DriverIRQHandler
+    bx    r0
+    .size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA2_DMA18_IRQHandler
+    .type DMA2_DMA18_IRQHandler, %function
+DMA2_DMA18_IRQHandler:
+    ldr   r0,=DMA2_DMA18_DriverIRQHandler
+    bx    r0
+    .size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA3_DMA19_IRQHandler
+    .type DMA3_DMA19_IRQHandler, %function
+DMA3_DMA19_IRQHandler:
+    ldr   r0,=DMA3_DMA19_DriverIRQHandler
+    bx    r0
+    .size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA4_DMA20_IRQHandler
+    .type DMA4_DMA20_IRQHandler, %function
+DMA4_DMA20_IRQHandler:
+    ldr   r0,=DMA4_DMA20_DriverIRQHandler
+    bx    r0
+    .size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA5_DMA21_IRQHandler
+    .type DMA5_DMA21_IRQHandler, %function
+DMA5_DMA21_IRQHandler:
+    ldr   r0,=DMA5_DMA21_DriverIRQHandler
+    bx    r0
+    .size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA6_DMA22_IRQHandler
+    .type DMA6_DMA22_IRQHandler, %function
+DMA6_DMA22_IRQHandler:
+    ldr   r0,=DMA6_DMA22_DriverIRQHandler
+    bx    r0
+    .size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA7_DMA23_IRQHandler
+    .type DMA7_DMA23_IRQHandler, %function
+DMA7_DMA23_IRQHandler:
+    ldr   r0,=DMA7_DMA23_DriverIRQHandler
+    bx    r0
+    .size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA8_DMA24_IRQHandler
+    .type DMA8_DMA24_IRQHandler, %function
+DMA8_DMA24_IRQHandler:
+    ldr   r0,=DMA8_DMA24_DriverIRQHandler
+    bx    r0
+    .size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA9_DMA25_IRQHandler
+    .type DMA9_DMA25_IRQHandler, %function
+DMA9_DMA25_IRQHandler:
+    ldr   r0,=DMA9_DMA25_DriverIRQHandler
+    bx    r0
+    .size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA10_DMA26_IRQHandler
+    .type DMA10_DMA26_IRQHandler, %function
+DMA10_DMA26_IRQHandler:
+    ldr   r0,=DMA10_DMA26_DriverIRQHandler
+    bx    r0
+    .size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA11_DMA27_IRQHandler
+    .type DMA11_DMA27_IRQHandler, %function
+DMA11_DMA27_IRQHandler:
+    ldr   r0,=DMA11_DMA27_DriverIRQHandler
+    bx    r0
+    .size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA12_DMA28_IRQHandler
+    .type DMA12_DMA28_IRQHandler, %function
+DMA12_DMA28_IRQHandler:
+    ldr   r0,=DMA12_DMA28_DriverIRQHandler
+    bx    r0
+    .size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA13_DMA29_IRQHandler
+    .type DMA13_DMA29_IRQHandler, %function
+DMA13_DMA29_IRQHandler:
+    ldr   r0,=DMA13_DMA29_DriverIRQHandler
+    bx    r0
+    .size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA14_DMA30_IRQHandler
+    .type DMA14_DMA30_IRQHandler, %function
+DMA14_DMA30_IRQHandler:
+    ldr   r0,=DMA14_DMA30_DriverIRQHandler
+    bx    r0
+    .size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA15_DMA31_IRQHandler
+    .type DMA15_DMA31_IRQHandler, %function
+DMA15_DMA31_IRQHandler:
+    ldr   r0,=DMA15_DMA31_DriverIRQHandler
+    bx    r0
+    .size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA_ERROR_IRQHandler
+    .type DMA_ERROR_IRQHandler, %function
+DMA_ERROR_IRQHandler:
+    ldr   r0,=DMA_ERROR_DriverIRQHandler
+    bx    r0
+    .size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART1_IRQHandler
+    .type LPUART1_IRQHandler, %function
+LPUART1_IRQHandler:
+    ldr   r0,=LPUART1_DriverIRQHandler
+    bx    r0
+    .size LPUART1_IRQHandler, . - LPUART1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART2_IRQHandler
+    .type LPUART2_IRQHandler, %function
+LPUART2_IRQHandler:
+    ldr   r0,=LPUART2_DriverIRQHandler
+    bx    r0
+    .size LPUART2_IRQHandler, . - LPUART2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART3_IRQHandler
+    .type LPUART3_IRQHandler, %function
+LPUART3_IRQHandler:
+    ldr   r0,=LPUART3_DriverIRQHandler
+    bx    r0
+    .size LPUART3_IRQHandler, . - LPUART3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART4_IRQHandler
+    .type LPUART4_IRQHandler, %function
+LPUART4_IRQHandler:
+    ldr   r0,=LPUART4_DriverIRQHandler
+    bx    r0
+    .size LPUART4_IRQHandler, . - LPUART4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART5_IRQHandler
+    .type LPUART5_IRQHandler, %function
+LPUART5_IRQHandler:
+    ldr   r0,=LPUART5_DriverIRQHandler
+    bx    r0
+    .size LPUART5_IRQHandler, . - LPUART5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART6_IRQHandler
+    .type LPUART6_IRQHandler, %function
+LPUART6_IRQHandler:
+    ldr   r0,=LPUART6_DriverIRQHandler
+    bx    r0
+    .size LPUART6_IRQHandler, . - LPUART6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART7_IRQHandler
+    .type LPUART7_IRQHandler, %function
+LPUART7_IRQHandler:
+    ldr   r0,=LPUART7_DriverIRQHandler
+    bx    r0
+    .size LPUART7_IRQHandler, . - LPUART7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART8_IRQHandler
+    .type LPUART8_IRQHandler, %function
+LPUART8_IRQHandler:
+    ldr   r0,=LPUART8_DriverIRQHandler
+    bx    r0
+    .size LPUART8_IRQHandler, . - LPUART8_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPI2C1_IRQHandler
+    .type LPI2C1_IRQHandler, %function
+LPI2C1_IRQHandler:
+    ldr   r0,=LPI2C1_DriverIRQHandler
+    bx    r0
+    .size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPI2C2_IRQHandler
+    .type LPI2C2_IRQHandler, %function
+LPI2C2_IRQHandler:
+    ldr   r0,=LPI2C2_DriverIRQHandler
+    bx    r0
+    .size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPI2C3_IRQHandler
+    .type LPI2C3_IRQHandler, %function
+LPI2C3_IRQHandler:
+    ldr   r0,=LPI2C3_DriverIRQHandler
+    bx    r0
+    .size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPI2C4_IRQHandler
+    .type LPI2C4_IRQHandler, %function
+LPI2C4_IRQHandler:
+    ldr   r0,=LPI2C4_DriverIRQHandler
+    bx    r0
+    .size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPSPI1_IRQHandler
+    .type LPSPI1_IRQHandler, %function
+LPSPI1_IRQHandler:
+    ldr   r0,=LPSPI1_DriverIRQHandler
+    bx    r0
+    .size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPSPI2_IRQHandler
+    .type LPSPI2_IRQHandler, %function
+LPSPI2_IRQHandler:
+    ldr   r0,=LPSPI2_DriverIRQHandler
+    bx    r0
+    .size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPSPI3_IRQHandler
+    .type LPSPI3_IRQHandler, %function
+LPSPI3_IRQHandler:
+    ldr   r0,=LPSPI3_DriverIRQHandler
+    bx    r0
+    .size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPSPI4_IRQHandler
+    .type LPSPI4_IRQHandler, %function
+LPSPI4_IRQHandler:
+    ldr   r0,=LPSPI4_DriverIRQHandler
+    bx    r0
+    .size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQHandler
+    .type CAN1_IRQHandler, %function
+CAN1_IRQHandler:
+    ldr   r0,=CAN1_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQHandler, . - CAN1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN2_IRQHandler
+    .type CAN2_IRQHandler, %function
+CAN2_IRQHandler:
+    ldr   r0,=CAN2_DriverIRQHandler
+    bx    r0
+    .size CAN2_IRQHandler, . - CAN2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SAI1_IRQHandler
+    .type SAI1_IRQHandler, %function
+SAI1_IRQHandler:
+    ldr   r0,=SAI1_DriverIRQHandler
+    bx    r0
+    .size SAI1_IRQHandler, . - SAI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SAI2_IRQHandler
+    .type SAI2_IRQHandler, %function
+SAI2_IRQHandler:
+    ldr   r0,=SAI2_DriverIRQHandler
+    bx    r0
+    .size SAI2_IRQHandler, . - SAI2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SAI3_RX_IRQHandler
+    .type SAI3_RX_IRQHandler, %function
+SAI3_RX_IRQHandler:
+    ldr   r0,=SAI3_RX_DriverIRQHandler
+    bx    r0
+    .size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SAI3_TX_IRQHandler
+    .type SAI3_TX_IRQHandler, %function
+SAI3_TX_IRQHandler:
+    ldr   r0,=SAI3_TX_DriverIRQHandler
+    bx    r0
+    .size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPDIF_IRQHandler
+    .type SPDIF_IRQHandler, %function
+SPDIF_IRQHandler:
+    ldr   r0,=SPDIF_DriverIRQHandler
+    bx    r0
+    .size SPDIF_IRQHandler, . - SPDIF_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXIO1_IRQHandler
+    .type FLEXIO1_IRQHandler, %function
+FLEXIO1_IRQHandler:
+    ldr   r0,=FLEXIO1_DriverIRQHandler
+    bx    r0
+    .size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXIO2_IRQHandler
+    .type FLEXIO2_IRQHandler, %function
+FLEXIO2_IRQHandler:
+    ldr   r0,=FLEXIO2_DriverIRQHandler
+    bx    r0
+    .size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXSPI_IRQHandler
+    .type FLEXSPI_IRQHandler, %function
+FLEXSPI_IRQHandler:
+    ldr   r0,=FLEXSPI_DriverIRQHandler
+    bx    r0
+    .size FLEXSPI_IRQHandler, . - FLEXSPI_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USDHC1_IRQHandler
+    .type USDHC1_IRQHandler, %function
+USDHC1_IRQHandler:
+    ldr   r0,=USDHC1_DriverIRQHandler
+    bx    r0
+    .size USDHC1_IRQHandler, . - USDHC1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USDHC2_IRQHandler
+    .type USDHC2_IRQHandler, %function
+USDHC2_IRQHandler:
+    ldr   r0,=USDHC2_DriverIRQHandler
+    bx    r0
+    .size USDHC2_IRQHandler, . - USDHC2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ENET_IRQHandler
+    .type ENET_IRQHandler, %function
+ENET_IRQHandler:
+    ldr   r0,=ENET_DriverIRQHandler
+    bx    r0
+    .size ENET_IRQHandler, . - ENET_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ENET_1588_Timer_IRQHandler
+    .type ENET_1588_Timer_IRQHandler, %function
+ENET_1588_Timer_IRQHandler:
+    ldr   r0,=ENET_1588_Timer_DriverIRQHandler
+    bx    r0
+    .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    DMA0_DMA16_DriverIRQHandler
+    def_irq_handler    DMA1_DMA17_DriverIRQHandler
+    def_irq_handler    DMA2_DMA18_DriverIRQHandler
+    def_irq_handler    DMA3_DMA19_DriverIRQHandler
+    def_irq_handler    DMA4_DMA20_DriverIRQHandler
+    def_irq_handler    DMA5_DMA21_DriverIRQHandler
+    def_irq_handler    DMA6_DMA22_DriverIRQHandler
+    def_irq_handler    DMA7_DMA23_DriverIRQHandler
+    def_irq_handler    DMA8_DMA24_DriverIRQHandler
+    def_irq_handler    DMA9_DMA25_DriverIRQHandler
+    def_irq_handler    DMA10_DMA26_DriverIRQHandler
+    def_irq_handler    DMA11_DMA27_DriverIRQHandler
+    def_irq_handler    DMA12_DMA28_DriverIRQHandler
+    def_irq_handler    DMA13_DMA29_DriverIRQHandler
+    def_irq_handler    DMA14_DMA30_DriverIRQHandler
+    def_irq_handler    DMA15_DMA31_DriverIRQHandler
+    def_irq_handler    DMA_ERROR_DriverIRQHandler
+    def_irq_handler    CTI0_ERROR_IRQHandler
+    def_irq_handler    CTI1_ERROR_IRQHandler
+    def_irq_handler    CORE_IRQHandler
+    def_irq_handler    LPUART1_DriverIRQHandler
+    def_irq_handler    LPUART2_DriverIRQHandler
+    def_irq_handler    LPUART3_DriverIRQHandler
+    def_irq_handler    LPUART4_DriverIRQHandler
+    def_irq_handler    LPUART5_DriverIRQHandler
+    def_irq_handler    LPUART6_DriverIRQHandler
+    def_irq_handler    LPUART7_DriverIRQHandler
+    def_irq_handler    LPUART8_DriverIRQHandler
+    def_irq_handler    LPI2C1_DriverIRQHandler
+    def_irq_handler    LPI2C2_DriverIRQHandler
+    def_irq_handler    LPI2C3_DriverIRQHandler
+    def_irq_handler    LPI2C4_DriverIRQHandler
+    def_irq_handler    LPSPI1_DriverIRQHandler
+    def_irq_handler    LPSPI2_DriverIRQHandler
+    def_irq_handler    LPSPI3_DriverIRQHandler
+    def_irq_handler    LPSPI4_DriverIRQHandler
+    def_irq_handler    CAN1_DriverIRQHandler
+    def_irq_handler    CAN2_DriverIRQHandler
+    def_irq_handler    FLEXRAM_IRQHandler
+    def_irq_handler    KPP_IRQHandler
+    def_irq_handler    TSC_DIG_IRQHandler
+    def_irq_handler    GPR_IRQ_IRQHandler
+    def_irq_handler    LCDIF_IRQHandler
+    def_irq_handler    CSI_IRQHandler
+    def_irq_handler    PXP_IRQHandler
+    def_irq_handler    WDOG2_IRQHandler
+    def_irq_handler    SNVS_HP_WRAPPER_IRQHandler
+    def_irq_handler    SNVS_HP_WRAPPER_TZ_IRQHandler
+    def_irq_handler    SNVS_LP_WRAPPER_IRQHandler
+    def_irq_handler    CSU_IRQHandler
+    def_irq_handler    DCP_IRQHandler
+    def_irq_handler    DCP_VMI_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    TRNG_IRQHandler
+    def_irq_handler    SJC_IRQHandler
+    def_irq_handler    BEE_IRQHandler
+    def_irq_handler    SAI1_DriverIRQHandler
+    def_irq_handler    SAI2_DriverIRQHandler
+    def_irq_handler    SAI3_RX_DriverIRQHandler
+    def_irq_handler    SAI3_TX_DriverIRQHandler
+    def_irq_handler    SPDIF_DriverIRQHandler
+    def_irq_handler    PMU_EVENT_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    TEMP_LOW_HIGH_IRQHandler
+    def_irq_handler    TEMP_PANIC_IRQHandler
+    def_irq_handler    USB_PHY1_IRQHandler
+    def_irq_handler    USB_PHY2_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    ADC2_IRQHandler
+    def_irq_handler    DCDC_IRQHandler
+    def_irq_handler    Reserved86_IRQHandler
+    def_irq_handler    Reserved87_IRQHandler
+    def_irq_handler    GPIO1_INT0_IRQHandler
+    def_irq_handler    GPIO1_INT1_IRQHandler
+    def_irq_handler    GPIO1_INT2_IRQHandler
+    def_irq_handler    GPIO1_INT3_IRQHandler
+    def_irq_handler    GPIO1_INT4_IRQHandler
+    def_irq_handler    GPIO1_INT5_IRQHandler
+    def_irq_handler    GPIO1_INT6_IRQHandler
+    def_irq_handler    GPIO1_INT7_IRQHandler
+    def_irq_handler    GPIO1_Combined_0_15_IRQHandler
+    def_irq_handler    GPIO1_Combined_16_31_IRQHandler
+    def_irq_handler    GPIO2_Combined_0_15_IRQHandler
+    def_irq_handler    GPIO2_Combined_16_31_IRQHandler
+    def_irq_handler    GPIO3_Combined_0_15_IRQHandler
+    def_irq_handler    GPIO3_Combined_16_31_IRQHandler
+    def_irq_handler    GPIO4_Combined_0_15_IRQHandler
+    def_irq_handler    GPIO4_Combined_16_31_IRQHandler
+    def_irq_handler    GPIO5_Combined_0_15_IRQHandler
+    def_irq_handler    GPIO5_Combined_16_31_IRQHandler
+    def_irq_handler    FLEXIO1_DriverIRQHandler
+    def_irq_handler    FLEXIO2_DriverIRQHandler
+    def_irq_handler    WDOG1_IRQHandler
+    def_irq_handler    RTWDOG_IRQHandler
+    def_irq_handler    EWM_IRQHandler
+    def_irq_handler    CCM_1_IRQHandler
+    def_irq_handler    CCM_2_IRQHandler
+    def_irq_handler    GPC_IRQHandler
+    def_irq_handler    SRC_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    GPT1_IRQHandler
+    def_irq_handler    GPT2_IRQHandler
+    def_irq_handler    PWM1_0_IRQHandler
+    def_irq_handler    PWM1_1_IRQHandler
+    def_irq_handler    PWM1_2_IRQHandler
+    def_irq_handler    PWM1_3_IRQHandler
+    def_irq_handler    PWM1_FAULT_IRQHandler
+    def_irq_handler    Reserved123_IRQHandler
+    def_irq_handler    FLEXSPI_DriverIRQHandler
+    def_irq_handler    SEMC_IRQHandler
+    def_irq_handler    USDHC1_DriverIRQHandler
+    def_irq_handler    USDHC2_DriverIRQHandler
+    def_irq_handler    USB_OTG2_IRQHandler
+    def_irq_handler    USB_OTG1_IRQHandler
+    def_irq_handler    ENET_DriverIRQHandler
+    def_irq_handler    ENET_1588_Timer_DriverIRQHandler
+    def_irq_handler    XBAR1_IRQ_0_1_IRQHandler
+    def_irq_handler    XBAR1_IRQ_2_3_IRQHandler
+    def_irq_handler    ADC_ETC_IRQ0_IRQHandler
+    def_irq_handler    ADC_ETC_IRQ1_IRQHandler
+    def_irq_handler    ADC_ETC_IRQ2_IRQHandler
+    def_irq_handler    ADC_ETC_ERROR_IRQ_IRQHandler
+    def_irq_handler    PIT_IRQHandler
+    def_irq_handler    ACMP1_IRQHandler
+    def_irq_handler    ACMP2_IRQHandler
+    def_irq_handler    ACMP3_IRQHandler
+    def_irq_handler    ACMP4_IRQHandler
+    def_irq_handler    Reserved143_IRQHandler
+    def_irq_handler    Reserved144_IRQHandler
+    def_irq_handler    ENC1_IRQHandler
+    def_irq_handler    ENC2_IRQHandler
+    def_irq_handler    ENC3_IRQHandler
+    def_irq_handler    ENC4_IRQHandler
+    def_irq_handler    TMR1_IRQHandler
+    def_irq_handler    TMR2_IRQHandler
+    def_irq_handler    TMR3_IRQHandler
+    def_irq_handler    TMR4_IRQHandler
+    def_irq_handler    PWM2_0_IRQHandler
+    def_irq_handler    PWM2_1_IRQHandler
+    def_irq_handler    PWM2_2_IRQHandler
+    def_irq_handler    PWM2_3_IRQHandler
+    def_irq_handler    PWM2_FAULT_IRQHandler
+    def_irq_handler    PWM3_0_IRQHandler
+    def_irq_handler    PWM3_1_IRQHandler
+    def_irq_handler    PWM3_2_IRQHandler
+    def_irq_handler    PWM3_3_IRQHandler
+    def_irq_handler    PWM3_FAULT_IRQHandler
+    def_irq_handler    PWM4_0_IRQHandler
+    def_irq_handler    PWM4_1_IRQHandler
+    def_irq_handler    PWM4_2_IRQHandler
+    def_irq_handler    PWM4_3_IRQHandler
+    def_irq_handler    PWM4_FAULT_IRQHandler
+
+    .end
diff --git a/utilities/fsl_assert.c b/utilities/fsl_assert.c
new file mode 100644
index 0000000..d2cbe28
--- /dev/null
+++ b/utilities/fsl_assert.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#else
+    (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#endif
+
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif (defined(__GNUC__))
+#if defined(__REDLIB__)
+void __assertion_failed(char *failedExpr)
+{
+    (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#else
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line,
+                 func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* defined(__REDLIB__) */
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */
diff --git a/utilities/fsl_debug_console.c b/utilities/fsl_debug_console.c
new file mode 100644
index 0000000..324541e
--- /dev/null
+++ b/utilities/fsl_debug_console.c
@@ -0,0 +1,1329 @@
+/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ *      1999-2000 MOTOROLA, INC. All Rights Reserved.
+ *  You are hereby granted a copyright license to use, modify, and
+ *  distribute the SOFTWARE so long as this entire notice is
+ *  retained without alteration in any modified and/or redistributed
+ *  versions, and that such modified versions are clearly identified
+ *  as such. No licenses are granted by implication, estoppel or
+ *  otherwise under any patents or trademarks of Motorola, Inc. This
+ *  software is provided on an "AS IS" basis and without warranty.
+ *
+ *  To the maximum extent permitted by applicable law, MOTOROLA
+ *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ *  ACCOMPANYING WRITTEN MATERIALS.
+ *
+ *  To the maximum extent permitted by applicable law, IN NO EVENT
+ *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ *  Motorola assumes no responsibility for the maintenance and support
+ *  of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include 
+#include 
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#include 
+#endif
+
+#ifdef FSL_RTOS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+#endif
+
+#include "fsl_debug_console_conf.h"
+#include "fsl_str.h"
+
+#include "fsl_common.h"
+#include "fsl_component_serial_manager.h"
+
+#include "fsl_debug_console.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#else
+/* MISRA C-2012 Rule 17.2 */
+#undef assert
+#define assert(n) \
+    while (!(n))  \
+    {             \
+        ;         \
+    }
+#endif
+#endif
+
+#if SDK_DEBUGCONSOLE
+#define DEBUG_CONSOLE_FUNCTION_PREFIX
+#else
+#define DEBUG_CONSOLE_FUNCTION_PREFIX static
+#endif
+
+/*! @brief character backspace ASCII value */
+#define DEBUG_CONSOLE_BACKSPACE 127U
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static volatile bool s_debugConsoleReadWaitSemaphore;
+#endif
+
+#else
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+/* semaphore definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+/* mutex semaphore */
+/* clang-format off */
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)   \
+        do                                             \
+        {                                              \
+            if(NULL != (mutex))                        \
+            {                                          \
+                vSemaphoreDelete(mutex);               \
+                (mutex) = NULL;                          \
+            }                                          \
+        } while(false)
+
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
+{                                                 \
+        if (IS_RUNNING_IN_ISR() == 0U)            \
+        {                                         \
+            (void)xSemaphoreGive(mutex);          \
+        }                                         \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \
+{                                                          \
+        if (IS_RUNNING_IN_ISR() == 0U)                     \
+        {                                                  \
+            (void)xSemaphoreTake(mutex, portMAX_DELAY);    \
+        }                                                  \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+{                                                                     \
+        if (IS_RUNNING_IN_ISR() == 0U)                                \
+        {                                                             \
+            result = xSemaphoreTake(mutex, 0U);                       \
+        }                                                             \
+        else                                                          \
+        {                                                             \
+            result = 1U;                                              \
+        }                                                             \
+}
+
+/* Binary semaphore */
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \
+        do                                             \
+        {                                              \
+            if(NULL != (binary))                       \
+            {                                          \
+                vSemaphoreDelete((binary));              \
+                (binary) = NULL;                         \
+            }                                          \
+        } while(false)
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY))
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL))
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
+
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)         (void)(mutex)
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)        (void)(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)  (void)(mutex)
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)           (void)(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)       (void)(binary)
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary)      (void)(binary)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+    {                                                        \
+        while (!(binary))                                    \
+        {                                                    \
+        }                                                    \
+        (binary) = false;                                      \
+    }
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \
+    do                                                       \
+    {                                                        \
+        (binary) = true;                                       \
+    } while(false)
+#else
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)  (void)(binary)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)  (void)(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+/* clang-format on */
+
+/* add other implementation here
+ *such as :
+ * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+ */
+
+#else
+
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* receive state structure */
+typedef struct _debug_console_write_ring_buffer
+{
+    uint32_t ringBufferSize;
+    volatile uint32_t ringHead;
+    volatile uint32_t ringTail;
+    uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];
+} debug_console_write_ring_buffer_t;
+#endif
+
+typedef struct _debug_console_state_struct
+{
+    serial_handle_t serialHandle; /*!< serial manager handle */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    SERIAL_MANAGER_HANDLE_DEFINE(serialHandleBuffer);
+    debug_console_write_ring_buffer_t writeRingBuffer;
+    uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];
+    SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer);
+    SERIAL_MANAGER_READ_HANDLE_DEFINE(serialReadHandleBuffer);
+#else
+    SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(serialHandleBuffer);
+    SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(serialWriteHandleBuffer);
+    SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(serialReadHandleBuffer);
+#endif
+} debug_console_state_struct_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console state information. */
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0))
+AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState);
+#else
+static debug_console_state_struct_t s_debugConsoleState;
+#endif
+serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf   Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch);
+int DbgConsole_SendData(uint8_t *ch, size_t size);
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);
+int DbgConsole_ReadLine(uint8_t *buf, size_t size);
+int DbgConsole_ReadCharacter(uint8_t *ch);
+
+#if ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+     (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,
+                                               serial_manager_callback_message_t *message,
+                                               serial_manager_status_t status)
+{
+    debug_console_state_struct_t *ioState;
+    uint32_t sendDataLength;
+
+    if ((NULL == callbackParam) || (NULL == message))
+    {
+        return;
+    }
+
+    ioState = (debug_console_state_struct_t *)callbackParam;
+
+    ioState->writeRingBuffer.ringTail += message->length;
+    if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
+    {
+        ioState->writeRingBuffer.ringTail = 0U;
+    }
+
+    if (kStatus_SerialManager_Success == status)
+    {
+        if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)
+        {
+            if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)
+            {
+                sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;
+            }
+            else
+            {
+                sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;
+            }
+
+            (void)SerialManager_WriteNonBlocking(
+                ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),
+                &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength);
+        }
+    }
+    else if (kStatus_SerialManager_Canceled == status)
+    {
+        ioState->writeRingBuffer.ringTail = 0U;
+        ioState->writeRingBuffer.ringHead = 0U;
+    }
+    else
+    {
+        /*MISRA rule 16.4*/
+    }
+}
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,
+                                               serial_manager_callback_message_t *message,
+                                               serial_manager_status_t status)
+{
+    if ((NULL == callbackParam) || (NULL == message))
+    {
+        return;
+    }
+
+    if (kStatus_SerialManager_Notify == status)
+    {
+    }
+    else if (kStatus_SerialManager_Success == status)
+    {
+        /* release s_debugConsoleReadWaitSemaphore from RX callback */
+        DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);
+    }
+    else
+    {
+        /*MISRA rule 16.4*/
+    }
+}
+#endif
+
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+    (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+    return (status_t)kStatus_Fail;
+#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \
+         DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+/* recieve one char every time */
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    status =
+        SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#else  /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/
+    status = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/
+    if (kStatus_SerialManager_Success != status)
+    {
+        status = (serial_manager_status_t)kStatus_Fail;
+    }
+    else
+    {
+        /* wait s_debugConsoleReadWaitSemaphore from RX callback */
+        DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);
+        status = (serial_manager_status_t)kStatus_Success;
+    }
+    return (status_t)status;
+#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \
+          DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/
+
+#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/
+
+    return (status_t)kStatus_Fail;
+
+#endif /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+    /* Due to scanf take \n and \r as end of string,should not echo */
+    if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))
+    {
+        /* recieve one char every time */
+        if (1 != DbgConsole_SendDataReliable(ch, 1U))
+        {
+            return (status_t)kStatus_Fail;
+        }
+    }
+
+    if ((!isGetChar) && (index != NULL))
+    {
+        if (DEBUG_CONSOLE_BACKSPACE == *ch)
+        {
+            if ((*index >= 2))
+            {
+                *index -= 2;
+            }
+            else
+            {
+                *index = 0;
+            }
+        }
+    }
+
+    return (status_t)kStatus_Success;
+}
+#endif
+
+int DbgConsole_SendData(uint8_t *ch, size_t size)
+{
+    status_t status;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    uint32_t sendDataLength;
+    int txBusy = 0;
+#endif
+    assert(NULL != ch);
+    assert(0U != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    uint32_t regPrimask = DisableGlobalIRQ();
+    if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+    {
+        txBusy = 1;
+        sendDataLength =
+            (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+             s_debugConsoleState.writeRingBuffer.ringTail) %
+            s_debugConsoleState.writeRingBuffer.ringBufferSize;
+    }
+    else
+    {
+        sendDataLength = 0U;
+    }
+    sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+    if (sendDataLength < size)
+    {
+        EnableGlobalIRQ(regPrimask);
+        return -1;
+    }
+    for (int i = 0; i < (int)size; i++)
+    {
+        s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];
+        if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)
+        {
+            s_debugConsoleState.writeRingBuffer.ringHead = 0U;
+        }
+    }
+
+    status = (status_t)kStatus_SerialManager_Success;
+
+    if (txBusy == 0)
+    {
+        if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)
+        {
+            sendDataLength =
+                s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;
+        }
+        else
+        {
+            sendDataLength =
+                s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;
+        }
+
+        status = (status_t)SerialManager_WriteNonBlocking(
+            ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+            &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],
+            sendDataLength);
+    }
+    EnableGlobalIRQ(regPrimask);
+#else
+    status = (status_t)SerialManager_WriteBlocking(
+        ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+#endif
+    return (((status_t)kStatus_Success == status) ? (int)size : -1);
+}
+
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+    uint32_t sendDataLength;
+    uint32_t totalLength = size;
+    int sentLength;
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+#else  /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+    serial_manager_status_t status;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+    assert(NULL != ch);
+    assert(0U != size);
+
+    if (NULL == g_serialHandle)
+    {
+        return 0;
+    }
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+    do
+    {
+        uint32_t regPrimask = DisableGlobalIRQ();
+        if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+        {
+            sendDataLength =
+                (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+                 s_debugConsoleState.writeRingBuffer.ringTail) %
+                s_debugConsoleState.writeRingBuffer.ringBufferSize;
+        }
+        else
+        {
+            sendDataLength = 0U;
+        }
+        sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+
+        if (sendDataLength > 0U)
+        {
+            if (sendDataLength > totalLength)
+            {
+                sendDataLength = totalLength;
+            }
+
+            sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength);
+            if (sentLength > 0)
+            {
+                totalLength = totalLength - (uint32_t)sentLength;
+            }
+        }
+        EnableGlobalIRQ(regPrimask);
+
+        if (totalLength != 0U)
+        {
+            status = (serial_manager_status_t)DbgConsole_Flush();
+            if (kStatus_SerialManager_Success != status)
+            {
+                break;
+            }
+        }
+    } while (totalLength != 0U);
+    return ((int)size - (int)totalLength);
+#else  /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+    return DbgConsole_SendData(ch, size);
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else  /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+    status =
+        SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+    return ((kStatus_SerialManager_Success == status) ? (int)size : -1);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+}
+
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)
+{
+    int i = 0;
+
+    assert(buf != NULL);
+
+    if (NULL == g_serialHandle)
+    {
+        return -1;
+    }
+
+    /* take mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+#endif
+
+    do
+    {
+        /* recieve one char every time */
+        if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
+        {
+            /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+            DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+            i = -1;
+            break;
+        }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        (void)DbgConsole_EchoCharacter(&buf[i], false, &i);
+#endif
+        /* analysis data */
+        if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))
+        {
+            /* End of Line. */
+            if (0 == i)
+            {
+                buf[i] = (uint8_t)'\0';
+                continue;
+            }
+            else
+            {
+                break;
+            }
+        }
+        i++;
+    } while (i < (int)size);
+
+    /* get char should not add '\0'*/
+    if (i == (int)size)
+    {
+        buf[i] = (uint8_t)'\0';
+    }
+    else
+    {
+        buf[i + 1] = (uint8_t)'\0';
+    }
+
+    /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+
+    return i;
+}
+
+int DbgConsole_ReadCharacter(uint8_t *ch)
+{
+    int ret;
+
+    assert(ch);
+
+    if (NULL == g_serialHandle)
+    {
+        return -1;
+    }
+
+    /* take mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+#endif
+    /* read one character */
+    if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
+    {
+        ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        (void)DbgConsole_EchoCharacter(ch, true, NULL);
+#endif
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+
+    return ret;
+}
+
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)
+{
+    int i = 0;
+
+    for (i = 0; i < len; i++)
+    {
+        if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+        {
+            (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));
+            *indicator = 0;
+        }
+
+        buf[*indicator] = dbgVal;
+        (*indicator)++;
+    }
+}
+#endif
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U))
+#include "board.h"
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+static const serial_port_uart_config_t uartConfig = {.instance     = BOARD_DEBUG_UART_INSTANCE,
+                                                     .clockRate    = BOARD_DEBUG_UART_CLK_FREQ,
+                                                     .baudRate     = BOARD_DEBUG_UART_BAUDRATE,
+                                                     .parityMode   = kSerialManager_UartParityDisabled,
+                                                     .stopBitCount = kSerialManager_UartOneStopBit,
+#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+                                                     .mode = kSerialManager_UartBlockMode,
+#endif
+#endif
+                                                     .enableRx    = 1U,
+                                                     .enableTx    = 1U,
+                                                     .enableRxRTS = 0U,
+                                                     .enableTxCTS = 0U,
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+                                                     .txFifoWatermark = 0U,
+                                                     .rxFifoWatermark = 0U
+#endif
+};
+#endif
+#endif
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+{
+    serial_manager_config_t serialConfig;
+    serial_manager_status_t status = kStatus_SerialManager_Success;
+
+#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U))
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+    serial_port_uart_config_t uartConfig = {
+        .instance     = instance,
+        .clockRate    = clkSrcFreq,
+        .baudRate     = baudRate,
+        .parityMode   = kSerialManager_UartParityDisabled,
+        .stopBitCount = kSerialManager_UartOneStopBit,
+#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+        .mode = kSerialManager_UartBlockMode,
+#endif
+#endif
+        .enableRx    = 1,
+        .enableTx    = 1,
+        .enableRxRTS = 0U,
+        .enableTxCTS = 0U,
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+        .txFifoWatermark = 0U,
+        .rxFifoWatermark = 0U
+#endif
+    };
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+    serial_port_usb_cdc_config_t usbCdcConfig = {
+        .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,
+    };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+    serial_port_swo_config_t swoConfig = {
+        .clockRate = clkSrcFreq,
+        .baudRate  = baudRate,
+        .port      = instance,
+        .protocol  = kSerialManager_SwoProtocolNrz,
+    };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+    serial_port_virtual_config_t serialPortVirtualConfig = {
+        .controllerIndex = (serial_port_virtual_controller_index_t)instance,
+    };
+#endif
+
+    serialConfig.type = device;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    serialConfig.ringBuffer     = &s_debugConsoleState.readRingBuffer[0];
+    serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;
+#else
+    serialConfig.blockType = kSerialManager_Blocking;
+#endif
+
+    if (kSerialPort_Uart == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U))
+        serialConfig.portConfig = (void *)&uartConfig;
+#else
+        serialConfig.portConfig = &uartConfig;
+#endif
+#else
+        status = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_UsbCdc == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+        serialConfig.portConfig = &usbCdcConfig;
+#else
+        status = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_Swo == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+        serialConfig.portConfig = &swoConfig;
+#else
+        status = kStatus_SerialManager_Error;
+#endif
+    }
+    else if (kSerialPort_Virtual == device)
+    {
+#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
+        serialConfig.portConfig = &serialPortVirtualConfig;
+#else
+        status = kStatus_SerialManager_Error;
+#endif
+    }
+    else
+    {
+        status = kStatus_SerialManager_Error;
+    }
+
+    if (kStatus_SerialManager_Error != status)
+    {
+        (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+        s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;
+#endif
+
+        s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];
+        status                           = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);
+
+        assert(kStatus_SerialManager_Success == status);
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+        DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+        DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+
+        {
+            status =
+                SerialManager_OpenWriteHandle(s_debugConsoleState.serialHandle,
+                                              ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+            assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+            (void)SerialManager_InstallTxCallback(
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+                DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);
+#endif
+        }
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+        {
+            status =
+                SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle,
+                                             ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+            assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+            (void)SerialManager_InstallRxCallback(
+                ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),
+                DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);
+#endif
+        }
+#endif
+
+        g_serialHandle = s_debugConsoleState.serialHandle;
+    }
+    return (status_t)status;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_EnterLowpower(void)
+{
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+    if (s_debugConsoleState.serialHandle != NULL)
+    {
+        status = SerialManager_EnterLowpower(s_debugConsoleState.serialHandle);
+    }
+    return (status_t)status;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_ExitLowpower(void)
+{
+    serial_manager_status_t status = kStatus_SerialManager_Error;
+
+    if (s_debugConsoleState.serialHandle != NULL)
+    {
+        status = SerialManager_ExitLowpower(s_debugConsoleState.serialHandle);
+    }
+    return (status_t)status;
+}
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+    {
+        if (s_debugConsoleState.serialHandle != NULL)
+        {
+            (void)SerialManager_CloseWriteHandle(
+                ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+        }
+    }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+    {
+        if (s_debugConsoleState.serialHandle != NULL)
+        {
+            (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+        }
+    }
+#endif
+    if (NULL != s_debugConsoleState.serialHandle)
+    {
+        if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))
+        {
+            s_debugConsoleState.serialHandle = NULL;
+            g_serialHandle                   = NULL;
+        }
+    }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+    DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+
+    return (status_t)kStatus_Success;
+}
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if ((SDK_DEBUGCONSOLE > 0U) ||                                                   \
+     ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+      (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+
+    if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+    {
+        return (status_t)kStatus_Fail;
+    }
+
+#else
+
+    while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+    {
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+        if (0U == IS_RUNNING_IN_ISR())
+        {
+            if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())
+            {
+                vTaskDelay(1);
+            }
+        }
+        else
+        {
+            return (status_t)kStatus_Fail;
+        }
+#endif
+    }
+
+#endif
+
+#endif
+    return (status_t)kStatus_Success;
+}
+#endif
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *fmt_s, ...)
+{
+    va_list ap;
+    int logLength = 0, dbgResult = 0;
+    char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+    if (NULL != g_serialHandle)
+    {
+        va_start(ap, fmt_s);
+        /* format print log first */
+        logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_PrintCallback);
+        /* print log */
+        dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
+
+        va_end(ap);
+    }
+    return dbgResult;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+    /* print char */
+    return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *formatString, ...)
+{
+    va_list ap;
+    int formatResult;
+    char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};
+
+    /* scanf log */
+    (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+    /* get va_list */
+    va_start(ap, formatString);
+    /* format scanf log */
+    formatResult = StrFormatScanf(scanfBuf, formatString, ap);
+
+    va_end(ap);
+
+    return formatResult;
+}
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_BlockingPrintf(const char *formatString, ...)
+{
+    va_list ap;
+    status_t status;
+    int logLength = 0, dbgResult = 0;
+    char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+    if (NULL == g_serialHandle)
+    {
+        return 0;
+    }
+
+    va_start(ap, formatString);
+    /* format print log first */
+    logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+    (void)SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+#endif
+    /* print log */
+    status =
+        (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+                                              (uint8_t *)printBuf, (size_t)logLength);
+    dbgResult = (((status_t)kStatus_Success == status) ? (int)logLength : -1);
+    va_end(ap);
+
+    return dbgResult;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+status_t DbgConsole_TryGetchar(char *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+    uint32_t length = 0;
+    status_t status = (status_t)kStatus_Fail;
+
+    assert(ch);
+
+    if (NULL == g_serialHandle)
+    {
+        return kStatus_Fail;
+    }
+
+    /* take mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+#endif
+
+    if (kStatus_SerialManager_Success ==
+        SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
+                              &length))
+    {
+        if (length != 0U)
+        {
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+            (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);
+#endif
+            status = (status_t)kStatus_Success;
+        }
+    }
+    /* release mutex lock function */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+    DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#endif
+    return status;
+#else
+    return (status_t)kStatus_Fail;
+#endif
+}
+#endif
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+    int ret    = -1;
+    uint8_t ch = 0U;
+
+    /* Get char */
+    if (DbgConsole_ReadCharacter(&ch) > 0)
+    {
+        ret = (int)ch;
+    }
+
+    return ret;
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#if defined(SDK_DEBUGCONSOLE_UART)
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size);
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+    size_t ret;
+    if (NULL == buffer)
+    {
+        /*
+         * This means that we should flush internal buffers.  Since we don't we just return.
+         * (Remember, "handle" == -1 means that all handles should be flushed.)
+         */
+        ret = 0U;
+    }
+    else if ((handle != 1) && (handle != 2))
+    {
+        /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure.
+         */
+        ret = (size_t)-1;
+    }
+    else
+    {
+        /* Send data. */
+        uint8_t buff[512];
+        (void)memcpy(buff, buffer, size);
+        (void)DbgConsole_SendDataReliable((uint8_t *)buff, size);
+
+        ret = size;
+    }
+    return ret;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size);
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+    uint8_t ch     = 0U;
+    int actualSize = 0;
+
+    /* This function only reads from "standard in", for all other file  handles it returns failure. */
+    if (0 != handle)
+    {
+        actualSize = -1;
+    }
+    else
+    {
+        /* Receive data.*/
+        for (; size > 0U; size--)
+        {
+            (void)DbgConsole_ReadCharacter(&ch);
+            if (0U == ch)
+            {
+                break;
+            }
+
+            *buffer++ = ch;
+            actualSize++;
+        }
+    }
+    return (size_t)actualSize;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* support LPC Xpresso with RedLib */
+#elif (defined(__REDLIB__))
+
+#if (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+    if (NULL == buffer)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+    return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+    char tmp;
+
+    /* Receive data. */
+    DbgConsole_ReadCharacter((uint8_t *)&tmp);
+
+    return tmp;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#if defined(SDK_DEBUGCONSOLE_UART)
+#if defined(__CC_ARM)
+struct __FILE
+{
+    int handle;
+    /*
+     * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+     * no file handling is required.
+     */
+};
+#endif
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+    /* Send data. */
+    return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+    char ch;
+
+    /* Receive data. */
+    DbgConsole_ReadCharacter((uint8_t *)&ch);
+
+    return ch;
+}
+
+/*
+ * Terminate the program, passing a return code back to the user.
+ * This function may not return.
+ */
+void _sys_exit(int returncode)
+{
+    while (1)
+    {
+    }
+}
+
+/*
+ * Writes a character to the output channel. This function is used
+ * for last-resort error message output.
+ */
+void _ttywrch(int ch)
+{
+    char ench = ch;
+    DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);
+}
+
+char *_sys_command_string(char *cmd, int len)
+{
+    return (cmd);
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif (defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \
+     (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))
+int __attribute__((weak)) _write(int handle, char *buffer, int size);
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+    if (NULL == buffer)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);
+
+    return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size);
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+    uint8_t ch     = 0U;
+    int actualSize = 0;
+
+    /* This function only reads from "standard in", for all other file handles it returns failure. */
+    if (handle != 0)
+    {
+        return -1;
+    }
+
+    /* Receive data. */
+    for (; size > 0; size--)
+    {
+        if (DbgConsole_ReadCharacter(&ch) < 0)
+        {
+            break;
+        }
+
+        *buffer++ = (char)ch;
+        actualSize++;
+
+        if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))
+        {
+            break;
+        }
+    }
+
+    return (actualSize > 0) ? actualSize : -1;
+}
+#endif
+
+#endif /* __ICCARM__ */
diff --git a/utilities/fsl_debug_console.h b/utilities/fsl_debug_console.h
new file mode 100644
index 0000000..a42f6d7
--- /dev/null
+++ b/utilities/fsl_debug_console.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ *   - [flags] :'-', '+', '#', ' ', '0'
+ *   - [width]:  number (0,1...)
+ *   - [.precision]: number (0,1...)
+ *   - [length]: do not support
+ *   - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ *   - [*]: is supported.
+ *   - [width]: number (0,1...)
+ *   - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ *   - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+#include "fsl_component_serial_manager.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK       1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE               2U /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
+ * to be redefined in project setting.
+ */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include 
+#endif
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ *  if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ *  if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ *  if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+#define PRINTF(...) \
+    do              \
+    {               \
+    } while (0)
+#define SCANF(...) \
+    do             \
+    {              \
+    } while (0)
+#define PUTCHAR(...) \
+    do               \
+    {                \
+    } while (0)
+#define GETCHAR() -1
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF  DbgConsole_Printf
+#define SCANF   DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
+                                                              */
+#define PRINTF  printf
+#define SCANF   scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance      The instance of the module.If the device is kSerialPort_Uart,
+ *                      the instance is UART peripheral instance. The UART hardware peripheral
+ *                      type is determined by UART adapter. For example, if the instance is 1,
+ *                      if the lpuart_adapter.c is added to the current project, the UART periheral
+ *                      is LPUART1.
+ *                      If the uart_adapter.c is added to the current project, the UART periheral
+ *                      is UART1.
+ * @param baudRate      The desired baud rate in bits per second.
+ * @param device        Low level device type for the debug console, can be one of the following.
+ *                      @arg kSerialPort_Uart,
+ *                      @arg kSerialPort_UsbCdc
+ * @param clkSrcFreq    Frequency of peripheral source clock.
+ *
+ * @return              Indicates whether initialization was successful or not.
+ * @retval kStatus_Success          Execution successfully
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_EnterLowpower(void);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_ExitLowpower(void);
+
+#else
+/*!
+ * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Init(uint8_t instance,
+                                       uint32_t baudRate,
+                                       serial_port_type_t device,
+                                       uint32_t clkSrcFreq)
+{
+    (void)instance;
+    (void)baudRate;
+    (void)device;
+    (void)clkSrcFreq;
+    return (status_t)kStatus_Fail;
+}
+/*!
+ * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Deinit(void)
+{
+    return (status_t)kStatus_Fail;
+}
+
+/*!
+ * Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_EnterLowpower(void)
+{
+    return (status_t)kStatus_Fail;
+}
+
+/*!
+ * Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_ExitLowpower(void)
+{
+    return (status_t)kStatus_Fail;
+}
+
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch Character to be written.
+ * @return  Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @param   formatString Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *formatString, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+/*!
+ * @brief Writes formatted output to the standard output stream with the blocking mode.
+ *
+ * Call this function to write a formatted output to the standard output stream with the blocking mode.
+ * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
+ * or not.
+ * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
+ *
+ * @param   formatString Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_BlockingPrintf(const char *formatString, ...);
+
+/*!
+ * @brief Debug console flush.
+ *
+ * Call this function to wait the tx buffer empty.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief Debug console try to get char
+ * This function provides a API which will not block current task, if character is
+ * available return it, otherwise return fail.
+ * @param ch the address of char to receive
+ * @return Indicates get char was successful or not.
+ */
+status_t DbgConsole_TryGetchar(char *ch);
+#endif
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/utilities/fsl_debug_console_conf.h b/utilities/fsl_debug_console_conf.h
new file mode 100644
index 0000000..0c6af27
--- /dev/null
+++ b/utilities/fsl_debug_console_conf.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2017 - 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+#include "fsl_common.h"
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@ brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ *  \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
diff --git a/utilities/fsl_sbrk.c b/utilities/fsl_sbrk.c
new file mode 100644
index 0000000..5727b2f
--- /dev/null
+++ b/utilities/fsl_sbrk.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#if defined(__GNUC__)
+#include 
+#include 
+#endif
+
+#if defined(__GNUC__)
+/*!
+ * @brief Function to override ARMGCC default function _sbrk
+ *
+ * _sbrk is called by malloc. ARMGCC default _sbrk compares "SP" register and
+ * heap end, if heap end is larger than "SP", then _sbrk returns error and
+ * memory allocation failed. This function changes to compare __HeapLimit with
+ * heap end.
+ */
+caddr_t _sbrk(int incr);
+caddr_t _sbrk(int incr)
+{
+    extern char end __asm("end");
+    extern char heap_limit __asm("__HeapLimit");
+    static char *heap_end;
+    char *prev_heap_end;
+    caddr_t ret;
+
+    if (heap_end == NULL)
+    {
+        heap_end = &end;
+    }
+
+    prev_heap_end = heap_end;
+
+    if ((unsigned int)heap_end + (unsigned int)incr > (unsigned int)(&heap_limit))
+    {
+        errno = ENOMEM;
+
+        ret = (caddr_t)-1;
+    }
+    else
+    {
+        heap_end = (char *)((unsigned int)heap_end + (unsigned int)incr);
+
+        ret = (caddr_t)prev_heap_end;
+    }
+
+    return ret;
+}
+#endif
diff --git a/utilities/fsl_str.c b/utilities/fsl_str.c
new file mode 100644
index 0000000..77087f7
--- /dev/null
+++ b/utilities/fsl_str.c
@@ -0,0 +1,1550 @@
+/*
+ * Copyright 2017, 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include 
+#include 
+#include 
+#include  /* MISRA C-2012 Rule 22.9 */
+#include "fsl_str.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#ifndef MAX_FIELD_WIDTH
+#define MAX_FIELD_WIDTH 99U
+#endif
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+    kPRINTF_Minus             = 0x01U,  /*!< Minus FLag. */
+    kPRINTF_Plus              = 0x02U,  /*!< Plus Flag. */
+    kPRINTF_Space             = 0x04U,  /*!< Space Flag. */
+    kPRINTF_Zero              = 0x08U,  /*!< Zero Flag. */
+    kPRINTF_Pound             = 0x10U,  /*!< Pound Flag. */
+    kPRINTF_LengthChar        = 0x20U,  /*!< Length: Char Flag. */
+    kPRINTF_LengthShortInt    = 0x40U,  /*!< Length: Short Int Flag. */
+    kPRINTF_LengthLongInt     = 0x80U,  /*!< Length: Long Int Flag. */
+    kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+    kSCANF_Suppress   = 0x2U,    /*!< Suppress Flag. */
+    kSCANF_DestMask   = 0x7cU,   /*!< Destination Mask. */
+    kSCANF_DestChar   = 0x4U,    /*!< Destination Char Flag. */
+    kSCANF_DestString = 0x8U,    /*!< Destination String FLag. */
+    kSCANF_DestSet    = 0x10U,   /*!< Destination Set Flag. */
+    kSCANF_DestInt    = 0x20U,   /*!< Destination Int Flag. */
+    kSCANF_DestFloat  = 0x30U,   /*!< Destination Float Flag. */
+    kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+    kSCANF_LengthChar        = 0x100U, /*!< Length Char Flag. */
+    kSCANF_LengthShortInt    = 0x200U, /*!< Length ShortInt Flag. */
+    kSCANF_LengthLongInt     = 0x400U, /*!< Length LongInt Flag. */
+    kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif                                 /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+    kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif                                     /*PRINTF_FLOAT_ENABLE */
+    kSCANF_TypeSinged = 0x2000U,           /*!< TypeSinged Flag. */
+};
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in]   s The address of the string pointer to update.
+ * @return      String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr    Converted string of the number.
+ * @param[in] nump      Pointer to the number.
+ * @param[in] neg       Polarity of the number.
+ * @param[in] radix     The radix to be converted to.
+ * @param[in] use_caps  Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
+
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr            Converted string of the number.
+ * @param[in] nump              Pointer to the number.
+ * @param[in] radix             The radix to be converted to.
+ * @param[in] precision_width   Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*************Code for process formatted data*******************************/
+#if PRINTF_ADVANCED_ENABLE
+static uint8_t PrintGetSignChar(int64_t ival, uint32_t flags_used, char *schar)
+{
+    uint8_t len = 1U;
+    if (ival < 0)
+    {
+        *schar = '-';
+    }
+    else
+    {
+        if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+        {
+            *schar = '+';
+        }
+        else if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+        {
+            *schar = ' ';
+        }
+        else
+        {
+            *schar = '\0';
+            len    = 0U;
+        }
+    }
+    return len;
+}
+#endif
+
+static uint32_t PrintGetWidth(const char **p, va_list *ap)
+{
+    uint32_t field_width = 0;
+    uint8_t done         = 0U;
+    char c;
+
+    while (0U == done)
+    {
+        c = *(++(*p));
+        if ((c >= '0') && (c <= '9'))
+        {
+            (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0');
+        }
+#if PRINTF_ADVANCED_ENABLE
+        else if (c == '*')
+        {
+            (field_width) = (uint32_t)va_arg(*ap, uint32_t);
+        }
+#endif /* PRINTF_ADVANCED_ENABLE */
+        else
+        {
+            /* We've gone one char too far. */
+            --(*p);
+            done = 1U;
+        }
+    }
+    return field_width;
+}
+
+static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width)
+{
+    const char *p            = *s;
+    uint32_t precision_width = 6U;
+    uint8_t done             = 0U;
+
+#if PRINTF_ADVANCED_ENABLE
+    if (NULL != valid_precision_width)
+    {
+        *valid_precision_width = false;
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+    if (*++p == '.')
+    {
+        /* Must get precision field width, if present. */
+        precision_width = 0U;
+        done            = 0U;
+        while (0U == done)
+        {
+            char c = *++p;
+            if ((c >= '0') && (c <= '9'))
+            {
+                precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+#if PRINTF_ADVANCED_ENABLE
+                if (NULL != valid_precision_width)
+                {
+                    *valid_precision_width = true;
+                }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            }
+#if PRINTF_ADVANCED_ENABLE
+            else if (c == '*')
+            {
+                precision_width = (uint32_t)va_arg(*ap, uint32_t);
+                if (NULL != valid_precision_width)
+                {
+                    *valid_precision_width = true;
+                }
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                /* We've gone one char too far. */
+                --p;
+                done = 1U;
+            }
+        }
+    }
+    else
+    {
+        /* We've gone one char too far. */
+        --p;
+    }
+    *s = p;
+    return precision_width;
+}
+
+static uint32_t PrintIsobpu(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t PrintIsdi(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'd') || (c == 'i'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static void PrintOutputdifFobpu(uint32_t flags_used,
+                                uint32_t field_width,
+                                uint32_t vlen,
+                                char schar,
+                                char *vstrp,
+                                printfCb cb,
+                                char *buf,
+                                int32_t *count)
+{
+#if PRINTF_ADVANCED_ENABLE
+    /* Do the ZERO pad. */
+    if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+    {
+        if ('\0' != schar)
+        {
+            cb(buf, count, schar, 1);
+            schar = '\0';
+        }
+        cb(buf, count, '0', (int)field_width - (int)vlen);
+        vlen = field_width;
+    }
+    else
+    {
+        if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+        {
+            cb(buf, count, ' ', (int)field_width - (int)vlen);
+            if ('\0' != schar)
+            {
+                cb(buf, count, schar, 1);
+                schar = '\0';
+            }
+        }
+    }
+    /* The string was built in reverse order, now display in correct order. */
+    if ('\0' != schar)
+    {
+        cb(buf, count, schar, 1);
+    }
+#else
+    cb(buf, count, ' ', (int)field_width - (int)vlen);
+#endif /* PRINTF_ADVANCED_ENABLE */
+    while ('\0' != (*vstrp))
+    {
+        cb(buf, count, *vstrp--, 1);
+    }
+#if PRINTF_ADVANCED_ENABLE
+    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+    {
+        cb(buf, count, ' ', (int)field_width - (int)vlen);
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+}
+
+static void PrintOutputxX(uint32_t flags_used,
+                          uint32_t field_width,
+                          uint32_t vlen,
+                          bool use_caps,
+                          char *vstrp,
+                          printfCb cb,
+                          char *buf,
+                          int32_t *count)
+{
+#if PRINTF_ADVANCED_ENABLE
+    uint8_t dschar = 0;
+    if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+    {
+        if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+        {
+            cb(buf, count, '0', 1);
+            cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+            dschar = 1U;
+        }
+        cb(buf, count, '0', (int)field_width - (int)vlen);
+        vlen = field_width;
+    }
+    else
+    {
+        if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+        {
+            if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+            {
+                vlen += 2U;
+            }
+            cb(buf, count, ' ', (int)field_width - (int)vlen);
+            if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+            {
+                cb(buf, count, '0', 1);
+                cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+                dschar = 1U;
+            }
+        }
+    }
+
+    if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar))
+    {
+        cb(buf, count, '0', 1);
+        cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+        vlen += 2U;
+    }
+#else
+    cb(buf, count, ' ', (int)field_width - (int)vlen);
+#endif /* PRINTF_ADVANCED_ENABLE */
+    while ('\0' != (*vstrp))
+    {
+        cb(buf, count, *vstrp--, 1);
+    }
+#if PRINTF_ADVANCED_ENABLE
+    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+    {
+        cb(buf, count, ' ', (int)field_width - (int)vlen);
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+}
+
+static uint32_t PrintIsfF(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'f') || (c == 'F'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t PrintIsxX(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'x') || (c == 'X'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+#if PRINTF_ADVANCED_ENABLE
+static uint32_t PrintCheckFlags(const char **s)
+{
+    const char *p = *s;
+    /* First check for specification modifier flags. */
+    uint32_t flags_used = 0U;
+    bool done           = false;
+    while (false == done)
+    {
+        switch (*++p)
+        {
+            case '-':
+                flags_used |= (uint32_t)kPRINTF_Minus;
+                break;
+            case '+':
+                flags_used |= (uint32_t)kPRINTF_Plus;
+                break;
+            case ' ':
+                flags_used |= (uint32_t)kPRINTF_Space;
+                break;
+            case '0':
+                flags_used |= (uint32_t)kPRINTF_Zero;
+                break;
+            case '#':
+                flags_used |= (uint32_t)kPRINTF_Pound;
+                break;
+            default:
+                /* We've gone one char too far. */
+                --p;
+                done = true;
+                break;
+        }
+    }
+    *s = p;
+    return flags_used;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+/*
+ * Check for the length modifier.
+ */
+static uint32_t PrintGetLengthFlag(const char **s)
+{
+    const char *p = *s;
+    /* First check for specification modifier flags. */
+    uint32_t flags_used = 0U;
+
+    switch (/* c = */ *++p)
+    {
+        case 'h':
+            if (*++p != 'h')
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+                --p;
+            }
+            else
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthChar;
+            }
+            break;
+        case 'l':
+            if (*++p != 'l')
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+                --p;
+            }
+            else
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+            }
+            break;
+        default:
+            /* we've gone one char too far */
+            --p;
+            break;
+    }
+    *s = p;
+    return flags_used;
+}
+#else
+static void PrintFilterLengthFlag(const char **s)
+{
+    const char *p = *s;
+    char ch;
+
+    do
+    {
+        ch = *++p;
+    } while ((ch == 'h') || (ch == 'l'));
+
+    *s = --p;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+static uint8_t PrintGetRadixFromobpu(const char c)
+{
+    uint8_t radix;
+
+    if (c == 'o')
+    {
+        radix = 8U;
+    }
+    else if (c == 'b')
+    {
+        radix = 2U;
+    }
+    else if (c == 'p')
+    {
+        radix = 16U;
+    }
+    else
+    {
+        radix = 10U;
+    }
+    return radix;
+}
+
+static uint32_t ScanIsWhiteSpace(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+    uint32_t count = 0U;
+    char c;
+
+    c = **s;
+    while (1U == ScanIsWhiteSpace(c))
+    {
+        count++;
+        (*s)++;
+        c = **s;
+    }
+    return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+#if PRINTF_ADVANCED_ENABLE
+    int64_t a;
+    int64_t b;
+    int64_t c;
+
+    uint64_t ua;
+    uint64_t ub;
+    uint64_t uc;
+#else
+    int32_t a;
+    int32_t b;
+    int32_t c;
+
+    uint32_t ua;
+    uint32_t ub;
+    uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    int32_t nlen;
+    char *nstrp;
+
+    nlen     = 0;
+    nstrp    = numstr;
+    *nstrp++ = '\0';
+
+    if (0 != neg)
+    {
+#if PRINTF_ADVANCED_ENABLE
+        a = *(int64_t *)nump;
+#else
+        a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (a == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (a != 0)
+        {
+#if PRINTF_ADVANCED_ENABLE
+            b = (int64_t)a / (int64_t)radix;
+            c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+            if (c < 0)
+            {
+                c = (int64_t)'0' - c;
+            }
+#else
+            b = a / radix;
+            c = a - (b * radix);
+            if (c < 0)
+            {
+                c = (int32_t)'0' - c;
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                c = c + (int32_t)'0';
+            }
+            a        = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    else
+    {
+#if PRINTF_ADVANCED_ENABLE
+        ua = *(uint64_t *)nump;
+#else
+        ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (ua == 0U)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (ua != 0U)
+        {
+#if PRINTF_ADVANCED_ENABLE
+            ub = (uint64_t)ua / (uint64_t)radix;
+            uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
+#else
+            ub = ua / (uint32_t)radix;
+            uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+            if (uc < 10U)
+            {
+                uc = uc + (uint32_t)'0';
+            }
+            else
+            {
+                uc = uc - 10U + (uint32_t)(use_caps ? 'A' : 'a');
+            }
+            ua       = ub;
+            *nstrp++ = (char)uc;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+
+#if PRINTF_FLOAT_ENABLE
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+    int32_t a;
+    int32_t b;
+    int32_t c;
+    int32_t i;
+    double fa;
+    double dc;
+    double fb;
+    double r;
+    double fractpart;
+    double intpart;
+
+    int32_t nlen;
+    char *nstrp;
+    nlen     = 0;
+    nstrp    = numstr;
+    *nstrp++ = '\0';
+    r        = *(double *)nump;
+    if (0.0 == r)
+    {
+        *nstrp = '0';
+        ++nlen;
+        return nlen;
+    }
+    fractpart = modf((double)r, (double *)&intpart);
+    /* Process fractional part. */
+    for (i = 0; i < (int32_t)precision_width; i++)
+    {
+        fractpart *= (double)radix;
+    }
+    if (r >= (double)0.0)
+    {
+        fa = fractpart + (double)0.5;
+        if (fa >= pow((double)10, (double)precision_width))
+        {
+            intpart++;
+        }
+    }
+    else
+    {
+        fa = fractpart - (double)0.5;
+        if (fa <= -pow((double)10, (double)precision_width))
+        {
+            intpart--;
+        }
+    }
+    for (i = 0; i < (int32_t)precision_width; i++)
+    {
+        fb = fa / (double)radix;
+        dc = (fa - (double)(int64_t)fb * (double)radix);
+        c  = (int32_t)dc;
+        if (c < 0)
+        {
+            c = (int32_t)'0' - c;
+        }
+        else
+        {
+            c = c + '0';
+        }
+        fa       = fb;
+        *nstrp++ = (char)c;
+        ++nlen;
+    }
+    *nstrp++ = (char)'.';
+    ++nlen;
+    a = (int32_t)intpart;
+    if (a == 0)
+    {
+        *nstrp++ = '0';
+        ++nlen;
+    }
+    else
+    {
+        while (a != 0)
+        {
+            b = (int32_t)a / (int32_t)radix;
+            c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+            if (c < 0)
+            {
+                c = (int32_t)'0' - c;
+            }
+            else
+            {
+                c = c + '0';
+            }
+            a        = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ * brief This function outputs its parameters according to a formatted string.
+ *
+ * note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * param[in] fmt_ptr   Format string for printf.
+ * param[in] args_ptr  Arguments to printf.
+ * param[in] buf  pointer to the buffer
+ * param cb print callback function pointer
+ *
+ * return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+    /* va_list ap; */
+    const char *p;
+    char c;
+
+    char vstr[33];
+    char *vstrp  = NULL;
+    int32_t vlen = 0;
+
+    int32_t count = 0;
+
+    uint32_t field_width;
+    uint32_t precision_width;
+    char *sval;
+    int32_t cval;
+    bool use_caps;
+    uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+    uint32_t flags_used;
+    char schar;
+    int64_t ival;
+    uint64_t uval = 0;
+    bool valid_precision_width;
+#else
+    int32_t ival;
+    uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_FLOAT_ENABLE
+    double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+    /* Start parsing apart the format string and display appropriate formats and data. */
+    p = fmt;
+    while (true)
+    {
+        if ('\0' == *p)
+        {
+            break;
+        }
+        c = *p;
+        /*
+         * All formats begin with a '%' marker.  Special chars like
+         * '\n' or '\t' are normally converted to the appropriate
+         * character by the __compiler__.  Thus, no need for this
+         * routine to account for the '\' character.
+         */
+        if (c != '%')
+        {
+            cb(buf, &count, c, 1);
+            p++;
+            /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+            continue;
+        }
+
+        use_caps = true;
+
+#if PRINTF_ADVANCED_ENABLE
+        /* First check for specification modifier flags. */
+        flags_used = PrintCheckFlags(&p);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+        /* Next check for minimum field width. */
+        field_width = PrintGetWidth(&p, &ap);
+
+        /* Next check for the width and precision field separator. */
+#if PRINTF_ADVANCED_ENABLE
+        precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width);
+#else
+        precision_width = PrintGetPrecision(&p, &ap, NULL);
+        (void)precision_width;
+#endif
+
+#if PRINTF_ADVANCED_ENABLE
+        /* Check for the length modifier. */
+        flags_used |= PrintGetLengthFlag(&p);
+#else
+        /* Filter length modifier. */
+        PrintFilterLengthFlag(&p);
+#endif
+
+        /* Now we're ready to examine the format. */
+        c = *++p;
+        {
+            if (1U == PrintIsdi(c))
+            {
+#if PRINTF_ADVANCED_ENABLE
+                if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+                {
+                    ival = (int64_t)va_arg(ap, int64_t);
+                }
+                else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                {
+                    ival = (int32_t)va_arg(ap, int32_t);
+                }
+                vlen  = ConvertRadixNumToString(vstr, (void *)&ival, 1, 10, use_caps);
+                vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+                vlen += (int32_t)PrintGetSignChar(ival, flags_used, &schar);
+                PrintOutputdifFobpu(flags_used, field_width, (uint32_t)vlen, schar, vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+            }
+            else if (1U == PrintIsfF(c))
+            {
+#if PRINTF_FLOAT_ENABLE
+                fval  = (double)va_arg(ap, double);
+                vlen  = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+                vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+                vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((int64_t)-1) : ((int64_t)fval)), flags_used, &schar);
+                PrintOutputdifFobpu(flags_used, field_width, (uint32_t)vlen, schar, vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+
+#else
+                (void)va_arg(ap, double);
+#endif /* PRINTF_FLOAT_ENABLE */
+            }
+            else if (1U == PrintIsxX(c))
+            {
+                if (c == 'x')
+                {
+                    use_caps = false;
+                }
+#if PRINTF_ADVANCED_ENABLE
+                if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+                {
+                    uval = (uint64_t)va_arg(ap, uint64_t);
+                }
+                else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                {
+                    uval = (uint32_t)va_arg(ap, uint32_t);
+                }
+                vlen  = ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps);
+                vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+                PrintOutputxX(flags_used, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count);
+#else
+                PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count);
+#endif
+            }
+            else if (1U == PrintIsobpu(c))
+            {
+#if PRINTF_ADVANCED_ENABLE
+                if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+                {
+                    uval = (uint64_t)va_arg(ap, uint64_t);
+                }
+                else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                {
+                    uval = (uint32_t)va_arg(ap, uint32_t);
+                }
+
+                radix = PrintGetRadixFromobpu(c);
+
+                vlen  = ConvertRadixNumToString(vstr, &uval, 0, (int32_t)radix, use_caps);
+                vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+                PrintOutputdifFobpu(flags_used, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+            }
+            else if (c == 'c')
+            {
+                cval = (int32_t)va_arg(ap, uint32_t);
+                cb(buf, &count, cval, 1);
+            }
+            else if (c == 's')
+            {
+                sval = (char *)va_arg(ap, char *);
+                if (NULL != sval)
+                {
+#if PRINTF_ADVANCED_ENABLE
+                    if (valid_precision_width)
+                    {
+                        vlen = (int32_t)precision_width;
+                    }
+                    else
+                    {
+                        vlen = (int32_t)strlen(sval);
+                    }
+#else
+                    vlen = (int32_t)strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+                    if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        cb(buf, &count, ' ', (int)field_width - (int)vlen);
+                    }
+
+#if PRINTF_ADVANCED_ENABLE
+                    if (valid_precision_width)
+                    {
+                        while (('\0' != *sval) && (vlen > 0))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                            vlen--;
+                        }
+                        /* In case that vlen sval is shorter than vlen */
+                        vlen = (int32_t)precision_width - vlen;
+                    }
+                    else
+                    {
+#endif /* PRINTF_ADVANCED_ENABLE */
+                        while ('\0' != (*sval))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                        }
+#if PRINTF_ADVANCED_ENABLE
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+                    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+                    {
+                        cb(buf, &count, ' ', (int32_t)field_width - vlen);
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+            }
+            else
+            {
+                cb(buf, &count, c, 1);
+            }
+        }
+        p++;
+    }
+
+    return count;
+}
+
+#if SCANF_FLOAT_ENABLE
+static uint8_t StrFormatScanIsFloat(char *c)
+{
+    uint8_t ret = 0U;
+    if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) ||
+        ('g' == (*c)) || ('G' == (*c)))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+#endif
+
+static uint8_t StrFormatScanIsFormatStarting(char *c)
+{
+    uint8_t ret = 1U;
+    if ((*c != '%'))
+    {
+        ret = 0U;
+    }
+    else if (*(c + 1) == '%')
+    {
+        ret = 0U;
+    }
+    else
+    {
+        /*MISRA rule 15.7*/
+    }
+
+    return ret;
+}
+
+static uint8_t StrFormatScanGetBase(uint8_t base, const char *s)
+{
+    if (base == 0U)
+    {
+        if (s[0] == '0')
+        {
+            if ((s[1] == 'x') || (s[1] == 'X'))
+            {
+                base = 16;
+            }
+            else
+            {
+                base = 8;
+            }
+        }
+        else
+        {
+            base = 10;
+        }
+    }
+    return base;
+}
+
+static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg)
+{
+    uint8_t len;
+    switch (*p)
+    {
+        case '-':
+            *neg = -1;
+            len  = 1;
+            break;
+        case '+':
+            *neg = 1;
+            len  = 1;
+            break;
+        default:
+            *neg = 1;
+            len  = 0;
+            break;
+    }
+    return len;
+}
+
+static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val)
+{
+#if SCANF_ADVANCED_ENABLE
+    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+    {
+        return 0u;
+    }
+
+    switch (flag & (uint32_t)kSCANF_LengthMask)
+    {
+        case (uint32_t)kSCANF_LengthChar:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed char *) = (signed char)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned char *) = (unsigned char)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthShortInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed short *) = (signed short)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned short *) = (unsigned short)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthLongInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed long int *) = (signed long int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthLongLongInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed long long int *) = (signed long long int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val;
+            }
+            break;
+        default:
+            /* The default type is the type int. */
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed int *) = (signed int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned int *) = (unsigned int)val;
+            }
+            break;
+    }
+#else
+    /* The default type is the type int. */
+    if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+    {
+        *va_arg(*args_ptr, signed int *) = (signed int)val;
+    }
+    else
+    {
+        *va_arg(*args_ptr, unsigned int *) = (unsigned int)val;
+    }
+#endif /* SCANF_ADVANCED_ENABLE */
+
+    return 1u;
+}
+
+#if SCANF_FLOAT_ENABLE
+static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum)
+{
+#if SCANF_ADVANCED_ENABLE
+    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+    {
+        return 0u;
+    }
+    else
+#endif /* SCANF_ADVANCED_ENABLE */
+    {
+        if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble))
+        {
+            *va_arg(*args_ptr, double *) = fnum;
+        }
+        else
+        {
+            *va_arg(*args_ptr, float *) = (float)fnum;
+        }
+        return 1u;
+    }
+}
+#endif /* SCANF_FLOAT_ENABLE */
+
+static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base)
+{
+    uint8_t exitPending = 0U;
+    char *c             = *str;
+
+    /* Loop to get full conversion specification. */
+    while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask)))
+    {
+#if SCANF_ADVANCED_ENABLE
+        if ('*' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_Suppress))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                (*flag) |= (uint32_t)kSCANF_Suppress;
+            }
+        }
+        else if ('h' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                if (c[1] == 'h')
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthChar;
+                    c++;
+                }
+                else
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthShortInt;
+                }
+            }
+        }
+        else if ('l' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                if (c[1] == 'l')
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthLongLongInt;
+                    c++;
+                }
+                else
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthLongInt;
+                }
+            }
+        }
+        else
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+            if ('L' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble;
+            }
+        }
+        else
+#endif /* SCANF_FLOAT_ENABLE */
+            if (((*c) >= '0') && ((*c) <= '9'))
+        {
+            {
+                char *p;
+                errno          = 0;
+                (*field_width) = strtoul(c, &p, 10);
+                if (0 != errno)
+                {
+                    *field_width = 0U;
+                }
+                c = p - 1;
+            }
+        }
+        else if ('d' == (*c))
+        {
+            (*base) = 10U;
+            (*flag) |= (uint32_t)kSCANF_TypeSinged;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('u' == (*c))
+        {
+            (*base) = 10U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('o' == (*c))
+        {
+            (*base) = 8U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if (('x' == (*c)))
+        {
+            (*base) = 16U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('X' == (*c))
+        {
+            (*base) = 16U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('i' == (*c))
+        {
+            (*base) = 0U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+#if SCANF_FLOAT_ENABLE
+        else if (1U == StrFormatScanIsFloat(c))
+        {
+            (*flag) |= (uint32_t)kSCANF_DestFloat;
+        }
+#endif /* SCANF_FLOAT_ENABLE */
+        else if ('c' == (*c))
+        {
+            (*flag) |= (uint32_t)kSCANF_DestChar;
+            if (MAX_FIELD_WIDTH == (*field_width))
+            {
+                (*field_width) = 1;
+            }
+        }
+        else if ('s' == (*c))
+        {
+            (*flag) |= (uint32_t)kSCANF_DestString;
+        }
+        else
+        {
+            exitPending = 1U;
+        }
+
+        if (1U == exitPending)
+        {
+            break;
+        }
+        else
+        {
+            c++;
+        }
+    }
+    *str = c;
+    return exitPending;
+}
+
+/*!
+ * brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * param[in] line_ptr The input line of ASCII data.
+ * param[in] format   Format first points to the format string.
+ * param[in] args_ptr The list of parameters.
+ *
+ * return Number of input items converted and assigned.
+ * retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+    uint8_t base;
+    int8_t neg;
+    /* Identifier for the format string. */
+    char *c = format;
+    char *buf;
+    /* Flag telling the conversion specification. */
+    uint32_t flag = 0;
+    /* Filed width for the matching input streams. */
+    uint32_t field_width;
+    /* How many arguments are assigned except the suppress. */
+    uint32_t nassigned = 0;
+    /* How many characters are read from the input streams. */
+    uint32_t n_decode = 0;
+
+    int32_t val;
+
+    uint8_t added;
+
+    uint8_t exitPending = 0;
+
+    const char *s;
+#if SCANF_FLOAT_ENABLE
+    char *s_temp; /* MISRA C-2012 Rule 11.3 */
+#endif
+
+    /* Identifier for the input string. */
+    const char *p = line_ptr;
+
+#if SCANF_FLOAT_ENABLE
+    double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+    /* Return EOF error before any conversion. */
+    if (*p == '\0')
+    {
+        return -1;
+    }
+
+    /* Decode directives. */
+    while (('\0' != (*c)) && ('\0' != (*p)))
+    {
+        /* Ignore all white-spaces in the format strings. */
+        if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c)))
+        {
+            n_decode += ScanIgnoreWhiteSpace(&p);
+        }
+        else if (0U == StrFormatScanIsFormatStarting(c))
+        {
+            /* Ordinary characters. */
+            c++;
+            if (*p == *c)
+            {
+                n_decode++;
+                p++;
+                c++;
+            }
+            else
+            {
+                /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+                 * However, it is deserted now. */
+                break;
+            }
+        }
+        else
+        {
+            /* convernsion specification */
+            c++;
+            /* Reset. */
+            flag        = 0;
+            field_width = MAX_FIELD_WIDTH;
+            base        = 0;
+            added       = 0U;
+
+            exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base);
+
+            if (1U == exitPending)
+            {
+                /* Format strings are exhausted. */
+                break;
+            }
+
+            /* Matching strings in input streams and assign to argument. */
+            if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar)
+            {
+                s   = (const char *)p;
+                buf = va_arg(args_ptr, char *);
+                while ((0U != (field_width--))
+#if SCANF_ADVANCED_ENABLE
+                       && ('\0' != (*p))
+#endif
+                )
+                {
+#if SCANF_ADVANCED_ENABLE
+                    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+                    {
+                        p++;
+                    }
+                    else
+#endif
+                    {
+                        *buf++ = *p++;
+#if SCANF_ADVANCED_ENABLE
+                        added = 1u;
+#endif
+                    }
+                    n_decode++;
+                }
+
+#if SCANF_ADVANCED_ENABLE
+                if (1u == added)
+#endif
+                {
+                    nassigned++;
+                }
+            }
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                s   = p;
+                buf = va_arg(args_ptr, char *);
+                while ((0U != (field_width--)) && (*p != '\0') && (0U == ScanIsWhiteSpace(*p)))
+                {
+#if SCANF_ADVANCED_ENABLE
+                    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+                    {
+                        p++;
+                    }
+                    else
+#endif
+                    {
+                        *buf++ = *p++;
+#if SCANF_ADVANCED_ENABLE
+                        added = 1u;
+#endif
+                    }
+                    n_decode++;
+                }
+
+#if SCANF_ADVANCED_ENABLE
+                if (1u == added)
+#endif
+                {
+                    /* Add NULL to end of string. */
+                    *buf = '\0';
+                    nassigned++;
+                }
+            }
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                s    = p;
+                val  = 0;
+                base = StrFormatScanGetBase(base, s);
+
+                added = StrFormatScanCheckSymbol(p, &neg);
+                n_decode += added;
+                p += added;
+                field_width -= added;
+
+                s = p;
+                if (strlen(p) > field_width)
+                {
+                    char temp[12];
+                    char *tempEnd;
+                    (void)memcpy(temp, p, sizeof(temp) - 1U);
+                    temp[sizeof(temp) - 1U] = '\0';
+                    errno                   = 0;
+                    val                     = (int32_t)strtoul(temp, &tempEnd, (int)base);
+                    if (0 != errno)
+                    {
+                        break;
+                    }
+                    p = p + (tempEnd - temp);
+                }
+                else
+                {
+                    char *tempEnd;
+                    val   = 0;
+                    errno = 0;
+                    val   = (int32_t)strtoul(p, &tempEnd, (int)base);
+                    if (0 != errno)
+                    {
+                        break;
+                    }
+                    p = tempEnd;
+                }
+                n_decode += (uint32_t)p - (uint32_t)s;
+
+                val *= neg;
+
+                nassigned += StrFormatScanFillInteger(flag, &args_ptr, val);
+            }
+#if SCANF_FLOAT_ENABLE
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                fnum  = 0.0;
+                errno = 0;
+
+                fnum = strtod(p, (char **)&s_temp);
+                s    = s_temp; /* MISRA C-2012 Rule 11.3 */
+
+                /* MISRA C-2012 Rule 22.9 */
+                if (0 != errno)
+                {
+                    break;
+                }
+
+                if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL))
+                {
+                    n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p;
+                    p        = s;
+                    nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum);
+                }
+            }
+#endif /* SCANF_FLOAT_ENABLE */
+            else
+            {
+                break;
+            }
+        }
+    }
+    return (int)nassigned;
+}
diff --git a/utilities/fsl_str.h b/utilities/fsl_str.h
new file mode 100644
index 0000000..bf7adcc
--- /dev/null
+++ b/utilities/fsl_str.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt   Format string for printf.
+ * @param[in] ap  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
diff --git a/utilities/utilities_misc_utilities_MIMXRT1052.cmake b/utilities/utilities_misc_utilities_MIMXRT1052.cmake
new file mode 100644
index 0000000..56f6238
--- /dev/null
+++ b/utilities/utilities_misc_utilities_MIMXRT1052.cmake
@@ -0,0 +1,10 @@
+if(NOT UTILITIES_MISC_UTILITIES_MIMXRT1052_INCLUDED)
+
+set(UTILITIES_MISC_UTILITIES_MIMXRT1052_INCLUDED true CACHE BOOL "utilities_misc_utilities component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/fsl_sbrk.c
+)
+
+
+endif()
diff --git a/utilities/utility_assert_MIMXRT1052.cmake b/utilities/utility_assert_MIMXRT1052.cmake
new file mode 100644
index 0000000..ccbe3f5
--- /dev/null
+++ b/utilities/utility_assert_MIMXRT1052.cmake
@@ -0,0 +1,12 @@
+if(NOT UTILITY_ASSERT_MIMXRT1052_INCLUDED)
+
+set(UTILITY_ASSERT_MIMXRT1052_INCLUDED true CACHE BOOL "utility_assert component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c
+)
+
+
+include(utility_debug_console_MIMXRT1052)
+
+endif()
diff --git a/utilities/utility_debug_console_MIMXRT1052.cmake b/utilities/utility_debug_console_MIMXRT1052.cmake
new file mode 100644
index 0000000..190603b
--- /dev/null
+++ b/utilities/utility_debug_console_MIMXRT1052.cmake
@@ -0,0 +1,20 @@
+if(NOT UTILITY_DEBUG_CONSOLE_MIMXRT1052_INCLUDED)
+
+set(UTILITY_DEBUG_CONSOLE_MIMXRT1052_INCLUDED true CACHE BOOL "utility_debug_console component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/fsl_debug_console.c
+${CMAKE_CURRENT_LIST_DIR}/fsl_str.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/
+)
+
+
+include(component_serial_manager_MIMXRT1052)
+
+include(driver_common_MIMXRT1052)
+
+endif()
diff --git a/xip/driver_xip_board_MIMXRT1052.cmake b/xip/driver_xip_board_MIMXRT1052.cmake
new file mode 100644
index 0000000..04bce05
--- /dev/null
+++ b/xip/driver_xip_board_MIMXRT1052.cmake
@@ -0,0 +1,17 @@
+if(NOT DRIVER_XIP_BOARD_MIMXRT1052_INCLUDED)
+
+set(DRIVER_XIP_BOARD_MIMXRT1052_INCLUDED true CACHE BOOL "driver_xip_board component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/evkbimxrt1050_flexspi_nor_config.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/
+)
+
+
+include(driver_common_MIMXRT1052)
+
+endif()
diff --git a/xip/driver_xip_device_MIMXRT1052.cmake b/xip/driver_xip_device_MIMXRT1052.cmake
new file mode 100644
index 0000000..2ae7a0d
--- /dev/null
+++ b/xip/driver_xip_device_MIMXRT1052.cmake
@@ -0,0 +1,17 @@
+if(NOT DRIVER_XIP_DEVICE_MIMXRT1052_INCLUDED)
+
+set(DRIVER_XIP_DEVICE_MIMXRT1052_INCLUDED true CACHE BOOL "driver_xip_device component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/fsl_flexspi_nor_boot.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+${CMAKE_CURRENT_LIST_DIR}/
+)
+
+
+include(driver_common_MIMXRT1052)
+
+endif()
diff --git a/xip/evkbimxrt1050_flexspi_nor_config.c b/xip/evkbimxrt1050_flexspi_nor_config.c
new file mode 100644
index 0000000..57253af
--- /dev/null
+++ b/xip/evkbimxrt1050_flexspi_nor_config.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkbimxrt1050_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t hyperflash_config = {
+    .memConfig =
+        {
+            .tag                = FLEXSPI_CFG_BLK_TAG,
+            .version            = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc   = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
+            .csHoldTime         = 3u,
+            .csSetupTime        = 3u,
+            .columnAddressWidth = 3u,
+            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
+            .controllerMiscOption =
+                (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
+                (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
+            .sflashPadType = kSerialFlash_8Pads,
+            .serialClkFreq = kFlexSpiSerialClk_133MHz,
+            .sflashA1Size  = 64u * 1024u * 1024u,
+            .dataValidTime = {16u, 16u},
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
+                    FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
+                    FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
+                },
+        },
+    .pageSize           = 512u,
+    .sectorSize         = 256u * 1024u,
+    .blockSize          = 256u * 1024u,
+    .isUniformBlockSize = true,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/xip/evkbimxrt1050_flexspi_nor_config.h b/xip/evkbimxrt1050_flexspi_nor_config.h
new file mode 100644
index 0000000..b2ca517
--- /dev/null
+++ b/xip/evkbimxrt1050_flexspi_nor_config.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
+#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
+
+#include 
+#include 
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG     (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE    (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ        0
+#define CMD_INDEX_READSTATUS  1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE       4
+
+#define CMD_LUT_SEQ_IDX_READ        0
+#define CMD_LUT_SEQ_IDX_READSTATUS  1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE       9
+
+#define CMD_SDR        0x01
+#define CMD_DDR        0x21
+#define RADDR_SDR      0x02
+#define RADDR_DDR      0x22
+#define CADDR_SDR      0x03
+#define CADDR_DDR      0x23
+#define MODE1_SDR      0x04
+#define MODE1_DDR      0x24
+#define MODE2_SDR      0x05
+#define MODE2_DDR      0x25
+#define MODE4_SDR      0x06
+#define MODE4_DDR      0x26
+#define MODE8_SDR      0x07
+#define MODE8_DDR      0x27
+#define WRITE_SDR      0x08
+#define WRITE_DDR      0x28
+#define READ_SDR       0x09
+#define READ_DDR       0x29
+#define LEARN_SDR      0x0A
+#define LEARN_DDR      0x2A
+#define DATSZ_SDR      0x0B
+#define DATSZ_DDR      0x2B
+#define DUMMY_SDR      0x0C
+#define DUMMY_DDR      0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS      0x1F
+#define STOP           0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+    kFlexSpiSerialClk_166MHz = 8,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ        CMD_INDEX_READ        //!< 0
+#define NOR_CMD_INDEX_READSTATUS  CMD_INDEX_READSTATUS  //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE   5                     //!< 5
+#define NOR_CMD_INDEX_DUMMY       6                     //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK  7                     //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK  8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */
diff --git a/xip/fsl_flexspi_nor_boot.c b/xip/fsl_flexspi_nor_boot.c
new file mode 100644
index 0000000..2b52e5a
--- /dev/null
+++ b/xip/fsl_flexspi_nor_boot.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexspi_nor_boot.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_device"
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.ivt"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.ivt"
+#endif
+/*************************************
+ *  IVT Data
+ *************************************/
+const ivt image_vector_table = {
+    IVT_HEADER,                    /* IVT Header */
+    IMAGE_ENTRY_ADDRESS,           /* Image Entry Function */
+    IVT_RSVD,                      /* Reserved = 0 */
+    (uint32_t)DCD_ADDRESS,         /* Address where DCD information is stored */
+    (uint32_t)BOOT_DATA_ADDRESS,   /* Address where BOOT Data Structure is stored */
+    (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
+    (uint32_t)CSF_ADDRESS,         /* Address where CSF file is stored */
+    IVT_RSVD                       /* Reserved = 0 */
+};
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.boot_data"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.boot_data"
+#endif
+/*************************************
+ *  Boot Data
+ *************************************/
+const BOOT_DATA_T boot_data = {
+    FLASH_BASE,  /* boot start location */
+    FLASH_SIZE,  /* size */
+    PLUGIN_FLAG, /* Plugin flag*/
+    0xFFFFFFFFU  /* empty - extra data word */
+};
+#endif
diff --git a/xip/fsl_flexspi_nor_boot.h b/xip/fsl_flexspi_nor_boot.h
new file mode 100644
index 0000000..a83e062
--- /dev/null
+++ b/xip/fsl_flexspi_nor_boot.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FLEXSPI_NOR_BOOT_H__
+#define __FLEXSPI_NOR_BOOT_H__
+
+#include 
+#include "board.h"
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_DEVICE driver version 2.0.2. */
+#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*************************************
+ *  IVT Data
+ *************************************/
+typedef struct _ivt_
+{
+    /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
+     *  (see @ref data)
+     */
+    uint32_t hdr;
+    /** Absolute address of the first instruction to execute from the
+     *  image
+     */
+    uint32_t entry;
+    /** Reserved in this version of HAB: should be NULL. */
+    uint32_t reserved1;
+    /** Absolute address of the image DCD: may be NULL. */
+    uint32_t dcd;
+    /** Absolute address of the Boot Data: may be NULL, but not interpreted
+     *  any further by HAB
+     */
+    uint32_t boot_data;
+    /** Absolute address of the IVT.*/
+    uint32_t self;
+    /** Absolute address of the image CSF.*/
+    uint32_t csf;
+    /** Reserved in this version of HAB: should be zero. */
+    uint32_t reserved2;
+} ivt;
+
+#define IVT_MAJOR_VERSION       0x4
+#define IVT_MAJOR_VERSION_SHIFT 0x4
+#define IVT_MAJOR_VERSION_MASK  0xF
+#define IVT_MINOR_VERSION       0x1
+#define IVT_MINOR_VERSION_SHIFT 0x0
+#define IVT_MINOR_VERSION_MASK  0xF
+
+#define IVT_VERSION(major, minor)                                    \
+    ((((major)&IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
+     (((minor)&IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
+
+/* IVT header */
+#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */
+#define IVT_SIZE       0x2000
+#define IVT_PAR        IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
+#define IVT_HEADER     (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
+
+/* Set resume entry */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern uint32_t __Vectors[];
+#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
+#elif defined(__MCUXPRESSO)
+extern uint32_t __Vectors[];
+#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
+#elif defined(__ICCARM__)
+extern uint32_t __VECTOR_TABLE[];
+#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
+#elif defined(__GNUC__)
+extern uint32_t __VECTOR_TABLE[];
+#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
+#endif
+
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
+#define DCD_ADDRESS dcd_data
+#else
+#define DCD_ADDRESS 0
+#endif
+
+#define BOOT_DATA_ADDRESS &boot_data
+#define CSF_ADDRESS       0
+#define IVT_RSVD          (uint32_t)(0x00000000)
+
+/*************************************
+ *  Boot Data
+ *************************************/
+typedef struct _boot_data_
+{
+    uint32_t start;       /* boot start location */
+    uint32_t size;        /* size */
+    uint32_t plugin;      /* plugin flag - 1 if downloaded application is plugin */
+    uint32_t placeholder; /* placehoder to make even 0x10 size */
+} BOOT_DATA_T;
+
+#define FLASH_BASE FlexSPI_AMBA_BASE
+#if defined(BOARD_FLASH_SIZE)
+#define FLASH_SIZE BOARD_FLASH_SIZE
+#else
+#error "Please define macro BOARD_FLASH_SIZE"
+#endif
+#define PLUGIN_FLAG (uint32_t)0
+
+/* External Variables */
+const BOOT_DATA_T boot_data;
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
+extern const uint8_t dcd_data[];
+#endif
+
+#endif /* __FLEXSPI_NOR_BOOT_H__ */