diff --git a/CMakeLists.txt b/CMakeLists.txt index b1da1e8..836cf19 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -39,6 +39,7 @@ add_executable(${MCUX_SDK_PROJECT_NAME} "${ProjDirPath}/board/peripherals.h" "${ProjDirPath}/source/FreeRTOSConfig.h" "${ProjDirPath}/source/freertos_hello.c" +"${ProjDirPath}/source/user_irqhandlers.c" ) target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE diff --git a/board/board.c b/board/board.c index 0f4335c..fd5b102 100644 --- a/board/board.c +++ b/board/board.c @@ -234,28 +234,6 @@ status_t BOARD_Camera_I2C_ReceiveSCCB( /* MPU configuration. */ void BOARD_ConfigMPU(void) { -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$RW_m_ncache$$Base[]; - /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ - extern uint32_t Image$$RW_m_ncache_unused$$Base[]; - extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; - uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? - 0 : - ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); -#elif defined(__MCUXPRESSO) - extern uint32_t __base_NCACHE_REGION; - extern uint32_t __top_NCACHE_REGION; - uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; -#elif defined(__ICCARM__) || defined(__GNUC__) - extern uint32_t __NCACHE_REGION_START[]; - extern uint32_t __NCACHE_REGION_SIZE[]; - uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; -#endif - volatile uint32_t i = 0; - /* Disable I cache and D cache */ if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { @@ -269,109 +247,21 @@ void BOARD_ConfigMPU(void) /* Disable MPU */ ARM_MPU_Disable(); - /* MPU configure: - * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, - * SubRegionDisable, Size) - * API in mpu_armv7.h. - * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches - * disabled. - * param AccessPermission Data access permissions, allows you to configure read/write access for User and - * Privileged mode. - * Use MACROS defined in mpu_armv7.h: - * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO - * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. - * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache - * 0 x 0 0 Strongly Ordered shareable - * 0 x 0 1 Device shareable - * 0 0 1 0 Normal not shareable Outer and inner write - * through no write allocate - * 0 0 1 1 Normal not shareable Outer and inner write - * back no write allocate - * 0 1 1 0 Normal shareable Outer and inner write - * through no write allocate - * 0 1 1 1 Normal shareable Outer and inner write - * back no write allocate - * 1 0 0 0 Normal not shareable outer and inner - * noncache - * 1 1 0 0 Normal shareable outer and inner - * noncache - * 1 0 1 1 Normal not shareable outer and inner write - * back write/read acllocate - * 1 1 1 1 Normal shareable outer and inner write - * back write/read acllocate - * 2 x 0 0 Device not shareable - * Above are normal use settings, if your want to see more details or want to config different inner/outter cache - * policy. - * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide - * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. - * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in - * mpu_armv7.h. - */ - - /* - * Add default region to deny access to whole address space to workaround speculative prefetch. - * Refer to Arm errata 1013783-B for more details. - * - */ - /* Region 0 setting: Instruction access disabled, No data access permission. */ - MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); - - /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 1, 1, 1, 0, 0, ARM_MPU_REGION_SIZE_32MB); + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) - /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */ - MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); -#endif - - /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - - /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); + + MPU->RBAR = ARM_MPU_RBAR(2, 0x00000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U); + + MPU->RBAR = ARM_MPU_RBAR(3, 0x20000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U); + + MPU->RBAR = ARM_MPU_RBAR(4, 0x20200000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); - - while ((size >> i) > 0x1U) - { - i++; - } - - if (i != 0) - { - /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ - assert(!(nonCacheStart % size)); - assert(size == (uint32_t)(1 << i)); - assert(i >= 5); - - /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); - } - - /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB); - /* Enable MPU */ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); diff --git a/board/clock_config.c b/board/clock_config.c index 1d5f98f..f64f361 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -67,7 +67,7 @@ outputs: - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 33.75 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} @@ -95,6 +95,8 @@ settings: - {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '4', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '4', locked: true} @@ -326,7 +328,7 @@ void BOARD_BootClockRUN(void) /* Disable LCDIF clock gate. */ CLOCK_DisableClock(kCLOCK_LcdPixel); /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 3); /* Set LCDIF_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); /* Set Lcdif pre clock source. */ diff --git a/board/clock_config.c.bak b/board/clock_config.c.bak index 32b6f48..541f491 100644 --- a/board/clock_config.c.bak +++ b/board/clock_config.c.bak @@ -67,7 +67,7 @@ outputs: - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 27 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} @@ -84,7 +84,7 @@ outputs: - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 150 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} @@ -95,9 +95,11 @@ settings: - {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LCDIF_PODF.scale, value: '5', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '4', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.SEMC_PODF.scale, value: '4', locked: true} - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM.TRACE_PODF.scale, value: '4', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} @@ -231,7 +233,7 @@ void BOARD_BootClockRUN(void) /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + CLOCK_SetDiv(kCLOCK_SemcDiv, 3); /* Set Semc alt clock source. */ CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ @@ -326,9 +328,9 @@ void BOARD_BootClockRUN(void) /* Disable LCDIF clock gate. */ CLOCK_DisableClock(kCLOCK_LcdPixel); /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 3); /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + CLOCK_SetDiv(kCLOCK_LcdifDiv, 4); /* Set Lcdif pre clock source. */ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); /* Disable SPDIF clock gate. */ diff --git a/board/clock_config.h b/board/clock_config.h index f5396a2..1bc0353 100644 --- a/board/clock_config.h +++ b/board/clock_config.h @@ -53,7 +53,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 33750000UL #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL diff --git a/board/clock_config.h.bak b/board/clock_config.h.bak index daf5873..90f5d9b 100644 --- a/board/clock_config.h.bak +++ b/board/clock_config.h.bak @@ -53,7 +53,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 27000000UL #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL @@ -72,7 +72,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 150000000UL #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL diff --git a/board/peripherals.c b/board/peripherals.c index b25f4f7..c7ac1b1 100644 --- a/board/peripherals.c +++ b/board/peripherals.c @@ -236,24 +236,24 @@ instance: - config: - panelWidthInt: '800' - panelHeightInt: '480' - - hsw: '1' - - hfp: '22' + - hsw: '20' + - hfp: '210' - hbp: '46' - - vsw: '1' + - vsw: '10' - vfp: '22' - vbp: '23' - frameRate: '60 Hz' - polarityFlags_st: - vSyncActive: 'kELCDIF_VsyncActiveLow' - hSyncActive: 'kELCDIF_HsyncActiveLow' - - dataEnableActive: 'kELCDIF_DataEnableActiveLow' - - driveDataClkEdge: 'kELCDIF_DriveDataOnFallingClkEdge' + - dataEnableActive: 'kELCDIF_DataEnableActiveHigh' + - driveDataClkEdge: 'kELCDIF_DriveDataOnRisingClkEdge' - bufferName: 'defaultBuffer' - bufferAlign: '64' - - pixelFormat: 'kELCDIF_PixelFormatXRGB8888' + - pixelFormat: 'kELCDIF_PixelFormatRGB565' - dataBus: 'kELCDIF_DataBus16Bit' - enablePxpHandShake: 'false' - - start: 'false' + - start: 'true' - isInterruptEnabled: 'true' - elcdifInterruptSources: 'kELCDIF_CurFrameDoneInterruptEnable' - interrupt: @@ -268,19 +268,19 @@ instance: const elcdif_rgb_mode_config_t LCDIF_rgbConfig = { .panelWidth = LCDIF_PANEL_WIDTH, .panelHeight = LCDIF_PANEL_HEIGHT, - .hsw = 1U, - .hfp = 22U, + .hsw = 20U, + .hfp = 210U, .hbp = 46U, - .vsw = 1U, + .vsw = 10U, .vfp = 22U, .vbp = 23U, - .polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | kELCDIF_DriveDataOnFallingClkEdge), + .polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveHigh | kELCDIF_DriveDataOnRisingClkEdge), .bufferAddr = (uint32_t) LCDIF_Buffer[0], - .pixelFormat = kELCDIF_PixelFormatXRGB8888, + .pixelFormat = kELCDIF_PixelFormatRGB565, .dataBus = kELCDIF_DataBus16Bit }; /* RGB buffer */ -AT_NONCACHEABLE_SECTION_ALIGN(uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN); +AT_NONCACHEABLE_SECTION_ALIGN(uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN); static void LCDIF_init(void) { /* RGB mode initialization */ @@ -291,6 +291,8 @@ static void LCDIF_init(void) { NVIC_SetPriority(LCDIF_LCDIF_IRQN, LCDIF_LCDIF_IRQ_PRIORITY); /* Enable interrupt LCDIF_IRQn request in the NVIC. */ EnableIRQ(LCDIF_LCDIF_IRQN); + /* RGB mode start */ + ELCDIF_RgbModeStart(LCDIF_PERIPHERAL); } /*********************************************************************************************************************** diff --git a/board/peripherals.c.bak b/board/peripherals.c.bak index 0a58a6a..5901684 100644 --- a/board/peripherals.c.bak +++ b/board/peripherals.c.bak @@ -218,6 +218,83 @@ static void SEMC_init(void) { SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000); } +/*********************************************************************************************************************** + * LCDIF initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'LCDIF' +- type: 'elcdif' +- mode: 'rgbMode' +- custom_name_enabled: 'false' +- type_id: 'elcdif_1c39bcb43ed1a24bc8980672c7378576' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'LCDIF' +- config_sets: + - fsl_elcdif: + - config: + - panelWidthInt: '800' + - panelHeightInt: '480' + - hsw: '20' + - hfp: '210' + - hbp: '46' + - vsw: '10' + - vfp: '22' + - vbp: '23' + - frameRate: '60 Hz' + - polarityFlags_st: + - vSyncActive: 'kELCDIF_VsyncActiveLow' + - hSyncActive: 'kELCDIF_HsyncActiveLow' + - dataEnableActive: 'kELCDIF_DataEnableActiveLow' + - driveDataClkEdge: 'kELCDIF_DriveDataOnFallingClkEdge' + - bufferName: 'defaultBuffer' + - bufferAlign: '64' + - pixelFormat: 'kELCDIF_PixelFormatRGB565' + - dataBus: 'kELCDIF_DataBus16Bit' + - enablePxpHandShake: 'false' + - start: 'true' + - isInterruptEnabled: 'true' + - elcdifInterruptSources: 'kELCDIF_CurFrameDoneInterruptEnable' + - interrupt: + - IRQn: 'LCDIF_IRQn' + - enable_interrrupt: 'enabled' + - enable_priority: 'true' + - priority: '5' + - enable_custom_name: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +/* RGB mode configuration */ +const elcdif_rgb_mode_config_t LCDIF_rgbConfig = { + .panelWidth = LCDIF_PANEL_WIDTH, + .panelHeight = LCDIF_PANEL_HEIGHT, + .hsw = 20U, + .hfp = 210U, + .hbp = 46U, + .vsw = 10U, + .vfp = 22U, + .vbp = 23U, + .polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | kELCDIF_DriveDataOnFallingClkEdge), + .bufferAddr = (uint32_t) LCDIF_Buffer[0], + .pixelFormat = kELCDIF_PixelFormatRGB565, + .dataBus = kELCDIF_DataBus16Bit +}; +/* RGB buffer */ +AT_NONCACHEABLE_SECTION_ALIGN(uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN); + +static void LCDIF_init(void) { + /* RGB mode initialization */ + ELCDIF_RgbModeInit(LCDIF_PERIPHERAL, &LCDIF_rgbConfig); + /* Enable interrupts */ + ELCDIF_EnableInterrupts(LCDIF_PERIPHERAL, (kELCDIF_CurFrameDoneInterruptEnable)); + /* Interrupt vector LCDIF_IRQn priority settings in the NVIC. */ + NVIC_SetPriority(LCDIF_LCDIF_IRQN, LCDIF_LCDIF_IRQ_PRIORITY); + /* Enable interrupt LCDIF_IRQn request in the NVIC. */ + EnableIRQ(LCDIF_LCDIF_IRQN); + /* RGB mode start */ + ELCDIF_RgbModeStart(LCDIF_PERIPHERAL); +} + /*********************************************************************************************************************** * Initialization functions **********************************************************************************************************************/ @@ -226,6 +303,7 @@ void BOARD_InitPeripherals(void) /* Initialize components */ LPUART1_init(); SEMC_init(); + LCDIF_init(); } /*********************************************************************************************************************** diff --git a/board/peripherals.h b/board/peripherals.h index 1c30ac9..48559da 100644 --- a/board/peripherals.h +++ b/board/peripherals.h @@ -33,7 +33,7 @@ extern "C" { /* Definition of peripheral ID */ #define LCDIF_PERIPHERAL LCDIF /* Definition of the expected display clock frequency */ -#define LCDIF_EXPECTED_DCLK_FREQ 27425640UL +#define LCDIF_EXPECTED_DCLK_FREQ 34539600UL /* Definition of the panel width */ #define LCDIF_PANEL_WIDTH 800 /* Definition of the panel height */ @@ -56,7 +56,7 @@ extern semc_sdram_config_t SEMC_sdram_struct; /* RGB mode configuration */ extern const elcdif_rgb_mode_config_t LCDIF_rgbConfig; /* RGB buffer */ -extern uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH]; +extern uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH]; /*********************************************************************************************************************** * Initialization functions diff --git a/board/peripherals.h.bak b/board/peripherals.h.bak index 78fd912..b14bcc5 100644 --- a/board/peripherals.h.bak +++ b/board/peripherals.h.bak @@ -13,6 +13,7 @@ #include "fsl_lpuart.h" #include "fsl_clock.h" #include "fsl_semc.h" +#include "fsl_elcdif.h" #if defined(__cplusplus) extern "C" { @@ -29,6 +30,22 @@ extern "C" { /* BOARD_InitPeripherals defines for SEMC */ /* Definition of peripheral ID. */ #define SEMC_PERIPHERAL SEMC +/* Definition of peripheral ID */ +#define LCDIF_PERIPHERAL LCDIF +/* Definition of the expected display clock frequency */ +#define LCDIF_EXPECTED_DCLK_FREQ 34539600UL +/* Definition of the panel width */ +#define LCDIF_PANEL_WIDTH 800 +/* Definition of the panel height */ +#define LCDIF_PANEL_HEIGHT 480 +/* Definition of the RGB buffer alignment */ +#define LCDIF_RGB_BUFFER_ALIGN 64 +/* LCDIF interrupt vector ID (number). */ +#define LCDIF_LCDIF_IRQN LCDIF_IRQn +/* LCDIF interrupt vector priority. */ +#define LCDIF_LCDIF_IRQ_PRIORITY 5 +/* LCDIF interrupt handler identifier. */ +#define LCDIF_LCDIF_IRQHANDLER LCDIF_IRQHandler /*********************************************************************************************************************** * Global variables @@ -36,6 +53,10 @@ extern "C" { extern const lpuart_config_t LPUART1_config; extern semc_config_t SEMC_config; extern semc_sdram_config_t SEMC_sdram_struct; +/* RGB mode configuration */ +extern const elcdif_rgb_mode_config_t LCDIF_rgbConfig; +/* RGB buffer */ +extern uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH]; /*********************************************************************************************************************** * Initialization functions diff --git a/board/pin_mux.c b/board/pin_mux.c index 98215c4..9ebeccd 100644 --- a/board/pin_mux.c +++ b/board/pin_mux.c @@ -12,11 +12,17 @@ package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 processor_version: 9.0.0 board: IMXRT1050-EVKB +pin_labels: +- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: LCDIF_RESET, identifier: LCDIF_RESEt;LCDIF_RESET} +- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: LED_BLUE, identifier: INT1_COMBO;LED_BLUE} +- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: LCDIF_BL, identifier: CAN2_RX;LCDIF_BL} +power_domains: {NVCC_GPIO: '3.3'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ #include "fsl_common.h" #include "fsl_iomuxc.h" +#include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -99,6 +105,9 @@ BOARD_InitPins: - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03} - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02} - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01} + - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, identifier: LCDIF_RESET, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: L10, peripheral: GPIO1, signal: 'gpio_io, 15', pin_signal: GPIO_AD_B0_15, identifier: LCDIF_BL, direction: OUTPUT, gpio_init_state: 'true', pull_up_down_config: Pull_Up_100K_Ohm} + - {pin_num: G13, peripheral: GPIO1, signal: 'gpio_io, 10', pin_signal: GPIO_AD_B0_10, identifier: LED_BLUE, direction: OUTPUT, gpio_init_state: 'true'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -111,8 +120,38 @@ BOARD_InitPins: void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); + /* GPIO configuration of LCDIF_RESET on GPIO_AD_B0_02 (pin M11) */ + gpio_pin_config_t LCDIF_RESET_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */ + GPIO_PinInit(GPIO1, 2U, &LCDIF_RESET_config); + + /* GPIO configuration of LED_BLUE on GPIO_AD_B0_10 (pin G13) */ + gpio_pin_config_t LED_BLUE_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_10 (pin G13) */ + GPIO_PinInit(GPIO1, 10U, &LED_BLUE_config); + + /* GPIO configuration of LCDIF_BL on GPIO_AD_B0_15 (pin L10) */ + gpio_pin_config_t LCDIF_BL_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_15 (pin L10) */ + GPIO_PinInit(GPIO1, 15U, &LCDIF_BL_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_GPIO1_IO15, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); @@ -176,6 +215,7 @@ void BOARD_InitPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U); IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_GPIO1_IO15, 0x90B0U); } /*********************************************************************************************************************** diff --git a/board/pin_mux.c.bak b/board/pin_mux.c.bak index 258a1b8..547a0eb 100644 --- a/board/pin_mux.c.bak +++ b/board/pin_mux.c.bak @@ -12,11 +12,17 @@ package_id: MIMXRT1052DVL6B mcu_data: ksdk2_0 processor_version: 9.0.0 board: IMXRT1050-EVKB +pin_labels: +- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: LCDIF_RESET, identifier: LCDIF_RESEt;LCDIF_RESET} +- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: LED_BLUE, identifier: INT1_COMBO;LED_BLUE} +- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: LCDIF_BL, identifier: CAN2_RX;LCDIF_BL} +power_domains: {NVCC_GPIO: '3.3'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ #include "fsl_common.h" #include "fsl_iomuxc.h" +#include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -79,6 +85,29 @@ BOARD_InitPins: - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25} - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40} - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28} + - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00} + - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04} + - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05} + - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06} + - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07} + - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08} + - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09} + - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10} + - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11} + - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12} + - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13} + - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14} + - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15} + - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00} + - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01} + - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02} + - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03} + - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03} + - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02} + - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01} + - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, identifier: LCDIF_RESET, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: L10, peripheral: GPIO1, signal: 'gpio_io, 15', pin_signal: GPIO_AD_B0_15, identifier: LCDIF_BL, direction: OUTPUT, gpio_init_state: 'true'} + - {pin_num: G13, peripheral: GPIO1, signal: 'gpio_io, 10', pin_signal: GPIO_AD_B0_10, identifier: LED_BLUE, direction: OUTPUT, gpio_init_state: 'true'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -91,8 +120,58 @@ BOARD_InitPins: void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); + /* GPIO configuration of LCDIF_RESET on GPIO_AD_B0_02 (pin M11) */ + gpio_pin_config_t LCDIF_RESET_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */ + GPIO_PinInit(GPIO1, 2U, &LCDIF_RESET_config); + + /* GPIO configuration of LED_BLUE on GPIO_AD_B0_10 (pin G13) */ + gpio_pin_config_t LED_BLUE_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_10 (pin G13) */ + GPIO_PinInit(GPIO1, 10U, &LED_BLUE_config); + + /* GPIO configuration of LCDIF_BL on GPIO_AD_B0_15 (pin L10) */ + gpio_pin_config_t LCDIF_BL_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_15 (pin L10) */ + GPIO_PinInit(GPIO1, 15U, &LCDIF_BL_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_GPIO1_IO15, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U); diff --git a/board/pin_mux.h b/board/pin_mux.h index dd65ac5..053082b 100644 --- a/board/pin_mux.h +++ b/board/pin_mux.h @@ -403,6 +403,48 @@ void BOARD_InitBootPins(void); #define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */ #define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */ +/* GPIO_AD_B0_02 (coord M11), LCDIF_RESET */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_RESET_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_RESET_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_RESET_CHANNEL 2U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_LCDIF_RESET_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN 2U /*!< GPIO pin number */ +#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_LCDIF_RESET_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_RESET_PIN 2U /*!< PORT pin number */ +#define BOARD_INITPINS_LCDIF_RESET_PIN_MASK (1U << 2U) /*!< PORT pin mask */ + +/* GPIO_AD_B0_15 (coord L10), LCDIF_BL */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_BL_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_BL_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_BL_CHANNEL 15U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_LCDIF_BL_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN 15U /*!< GPIO pin number */ +#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_LCDIF_BL_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_BL_PIN 15U /*!< PORT pin number */ +#define BOARD_INITPINS_LCDIF_BL_PIN_MASK (1U << 15U) /*!< PORT pin mask */ + +/* GPIO_AD_B0_10 (coord G13), LED_BLUE */ +/* Routed pin properties */ +#define BOARD_INITPINS_LED_BLUE_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_LED_BLUE_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_LED_BLUE_CHANNEL 10U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_LED_BLUE_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_LED_BLUE_GPIO_PIN 10U /*!< GPIO pin number */ +#define BOARD_INITPINS_LED_BLUE_GPIO_PIN_MASK (1U << 10U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_LED_BLUE_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_LED_BLUE_PIN 10U /*!< PORT pin number */ +#define BOARD_INITPINS_LED_BLUE_PIN_MASK (1U << 10U) /*!< PORT pin mask */ + /*! * @brief Configures pin routing and optionally pin electrical features. diff --git a/board/pin_mux.h.bak b/board/pin_mux.h.bak index c581434..5858454 100644 --- a/board/pin_mux.h.bak +++ b/board/pin_mux.h.bak @@ -287,6 +287,150 @@ void BOARD_InitBootPins(void); #define BOARD_INITPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */ #define BOARD_INITPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */ +/* GPIO_B0_00 (coord D7), LCDIF_CLK */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */ + +/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */ + +/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */ + +/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */ + +/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */ + +/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */ + +/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */ + +/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */ + +/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */ + +/* GPIO_B1_00 (coord A11), LCDIF_D12 */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */ + +/* GPIO_B1_01 (coord B11), LCDIF_D13 */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */ + +/* GPIO_B1_02 (coord C11), LCDIF_D14 */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */ + +/* GPIO_B1_03 (coord D11), LCDIF_D15 */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */ + +/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */ + +/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */ + +/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */ + +/* GPIO_AD_B0_02 (coord M11), LCDIF_RESET */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_RESET_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_RESET_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_RESET_CHANNEL 2U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_LCDIF_RESET_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN 2U /*!< GPIO pin number */ +#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_LCDIF_RESET_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_RESET_PIN 2U /*!< PORT pin number */ +#define BOARD_INITPINS_LCDIF_RESET_PIN_MASK (1U << 2U) /*!< PORT pin mask */ + +/* GPIO_AD_B0_15 (coord L10), LCDIF_BL */ +/* Routed pin properties */ +#define BOARD_INITPINS_LCDIF_BL_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_LCDIF_BL_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_LCDIF_BL_CHANNEL 15U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_LCDIF_BL_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN 15U /*!< GPIO pin number */ +#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_LCDIF_BL_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_LCDIF_BL_PIN 15U /*!< PORT pin number */ +#define BOARD_INITPINS_LCDIF_BL_PIN_MASK (1U << 15U) /*!< PORT pin mask */ + /*! * @brief Configures pin routing and optionally pin electrical features. diff --git a/device/MIMXRT1052_features.h b/device/MIMXRT1052_features.h index 29b13e1..86c5c34 100644 --- a/device/MIMXRT1052_features.h +++ b/device/MIMXRT1052_features.h @@ -380,11 +380,11 @@ /* IGPIO module features */ /* @brief Has data register set DR_SET. */ -#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +#define FSL_FEATURE_IGPIO_HAS_DR_SET (0) /* @brief Has data register clear DR_CLEAR. */ -#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (0) /* @brief Has data register toggle DR_TOGGLE. */ -#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (0) /* LCDIF module features */ diff --git a/imxrt1050.cfg b/imxrt1050.cfg index 33c0388..635636e 100644 --- a/imxrt1050.cfg +++ b/imxrt1050.cfg @@ -27,9 +27,7 @@ set _TARGETNAME $_CHIPNAME dap create $_TARGETNAME.dap -chain-position $_TARGETNAME.cpu target create $_TARGETNAME cortex_m -dap $_TARGETNAME.dap -if { ![using_hla] } { - cortex_m reset_config sysresetreq -} +cortex_m reset_config sysresetreq gdb_breakpoint_override hard diff --git a/rt1050_freertos_hello.mex b/rt1050_freertos_hello.mex index e72a54c..0c7d063 100644 --- a/rt1050_freertos_hello.mex +++ b/rt1050_freertos_hello.mex @@ -23,7 +23,14 @@ 9.0.0 - + + + + + + + + @@ -59,6 +66,11 @@ true + + + true + + @@ -148,6 +160,28 @@ + + + + + + + + + + + + + + + + + + + + + + @@ -235,7 +269,7 @@ - + @@ -264,6 +298,8 @@ + + @@ -706,25 +742,25 @@ - - + + - + - - + + - + - + diff --git a/source/freertos_hello.c b/source/freertos_hello.c index f3d2c96..05db4aa 100644 --- a/source/freertos_hello.c +++ b/source/freertos_hello.c @@ -15,6 +15,7 @@ /* Freescale includes. */ #include "fsl_device_registers.h" #include "fsl_debug_console.h" +#include "fsl_gpio.h" #include "pin_mux.h" #include "clock_config.h" #include "peripherals.h" diff --git a/source/user_irqhandlers.c b/source/user_irqhandlers.c new file mode 100644 index 0000000..c90c704 --- /dev/null +++ b/source/user_irqhandlers.c @@ -0,0 +1,13 @@ +#include "peripherals.h" + +/* LCDIF_IRQn interrupt handler */ +void LCDIF_LCDIF_IRQHANDLER(void) { + /* Place your code here */ + uint32_t int_status = ELCDIF_GetInterruptStatus(LCDIF_PERIPHERAL); + ELCDIF_ClearInterruptStatus(LCDIF_PERIPHERAL, int_status); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F + Store immediate overlapping exception return operation might vector to incorrect interrupt. */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +}