Added eLCDIF drivers, modified liner scripts.

2021-02-08 23:09:12 +08:00 · 2021-02-08 23:09:12 +08:00 · 2239e5e6dc
parent 0482ec6dd2
commit 2239e5e6dc
18 changed files with 1930 additions and 9 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -81,6 +81,8 @@ include(component_serial_manager_uart_MIMXRT1052)

 include(driver_semc_MIMXRT1052)

+include(driver_elcdif_MIMXRT1052)
+
 include(driver_lpuart_MIMXRT1052)

 include(device_MIMXRT1052_startup_MIMXRT1052)
--- a/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
+++ b/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
@ -41,6 +41,8 @@ MEMORY
  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000
+  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01800000
+  m_sdram_ncache        (RW)  : ORIGIN = 0x81800000, LENGTH = 0x00800000
 }

 /* Define output sections */
@ -207,7 +209,7 @@ SECTIONS
    *(NonCacheable)
    . = ALIGN(4);
    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
-  } > m_data
+  } > m_sdram_ncache

  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
  text_end = ORIGIN(m_text) + LENGTH(m_text);
--- a/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld
+++ b/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld
@ -38,6 +38,8 @@ MEMORY
  m_text                (RX)  : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000
+  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01800000
+  m_sdram_ncache        (RW)  : ORIGIN = 0x81800000, LENGTH = 0x00800000
 }

 /* Define output sections */
@ -174,7 +176,7 @@ SECTIONS
    *(NonCacheable)
    . = ALIGN(4);
    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
-  } > m_data
+  } > m_sdram_ncache

  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
  text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -194,7 +196,7 @@ SECTIONS
    . = ALIGN(4);
    __bss_end__ = .;
    __END_BSS = .;
-  } > m_data
+  } > m_data2

  .heap :
  {
--- a/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld
+++ b/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld
@ -30,7 +30,7 @@ ENTRY(Reset_Handler)

 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
-NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81E00000 - HEAP_SIZE;
+NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81800000 - HEAP_SIZE;
 NCACHE_HEAP_SIZE  = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000;

 /* Specify the memory areas */
@ -38,8 +38,8 @@ MEMORY
 {
  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
  m_text                (RX)  : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
-  m_data                (RW)  : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01E00000 : 0x01E00000 - HEAP_SIZE
-  m_ncache              (RW)  : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00200000 - HEAP_SIZE : 0x00200000
+  m_data                (RW)  : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01800000 : 0x01800000 - HEAP_SIZE
+  m_ncache              (RW)  : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00800000 - HEAP_SIZE : 0x00800000
  m_data2               (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
  m_data3               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000
  m_heap                (RW)  : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE
--- a/board/peripherals.c
+++ b/board/peripherals.c
@ -218,6 +218,81 @@ static void SEMC_init(void) {
  SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
 }

+/***********************************************************************************************************************
+ * LCDIF initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'LCDIF'
+- type: 'elcdif'
+- mode: 'rgbMode'
+- custom_name_enabled: 'false'
+- type_id: 'elcdif_1c39bcb43ed1a24bc8980672c7378576'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'LCDIF'
+- config_sets:
+  - fsl_elcdif:
+    - config:
+      - panelWidthInt: '800'
+      - panelHeightInt: '480'
+      - hsw: '1'
+      - hfp: '22'
+      - hbp: '46'
+      - vsw: '1'
+      - vfp: '22'
+      - vbp: '23'
+      - frameRate: '60 Hz'
+      - polarityFlags_st:
+        - vSyncActive: 'kELCDIF_VsyncActiveLow'
+        - hSyncActive: 'kELCDIF_HsyncActiveLow'
+        - dataEnableActive: 'kELCDIF_DataEnableActiveLow'
+        - driveDataClkEdge: 'kELCDIF_DriveDataOnFallingClkEdge'
+      - bufferName: 'defaultBuffer'
+      - bufferAlign: '64'
+      - pixelFormat: 'kELCDIF_PixelFormatXRGB8888'
+      - dataBus: 'kELCDIF_DataBus16Bit'
+      - enablePxpHandShake: 'false'
+      - start: 'false'
+    - isInterruptEnabled: 'true'
+    - elcdifInterruptSources: 'kELCDIF_CurFrameDoneInterruptEnable'
+    - interrupt:
+      - IRQn: 'LCDIF_IRQn'
+      - enable_interrrupt: 'enabled'
+      - enable_priority: 'true'
+      - priority: '5'
+      - enable_custom_name: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/* RGB mode configuration */
+const elcdif_rgb_mode_config_t LCDIF_rgbConfig = {
+  .panelWidth = LCDIF_PANEL_WIDTH,
+  .panelHeight = LCDIF_PANEL_HEIGHT,
+  .hsw = 1U,
+  .hfp = 22U,
+  .hbp = 46U,
+  .vsw = 1U,
+  .vfp = 22U,
+  .vbp = 23U,
+  .polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | kELCDIF_DriveDataOnFallingClkEdge),
+  .bufferAddr = (uint32_t) LCDIF_Buffer[0],
+  .pixelFormat = kELCDIF_PixelFormatXRGB8888,
+  .dataBus = kELCDIF_DataBus16Bit
+};
+/* RGB buffer */
+AT_NONCACHEABLE_SECTION_ALIGN(uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN);
+
+static void LCDIF_init(void) {
+  /* RGB mode initialization */
+  ELCDIF_RgbModeInit(LCDIF_PERIPHERAL, &LCDIF_rgbConfig);
+  /* Enable interrupts */
+  ELCDIF_EnableInterrupts(LCDIF_PERIPHERAL, (kELCDIF_CurFrameDoneInterruptEnable));
+  /* Interrupt vector LCDIF_IRQn priority settings in the NVIC. */
+  NVIC_SetPriority(LCDIF_LCDIF_IRQN, LCDIF_LCDIF_IRQ_PRIORITY);
+  /* Enable interrupt LCDIF_IRQn request in the NVIC. */
+  EnableIRQ(LCDIF_LCDIF_IRQN);
+}
+
 /***********************************************************************************************************************
 * Initialization functions
 **********************************************************************************************************************/
@ -226,6 +301,7 @@ void BOARD_InitPeripherals(void)
  /* Initialize components */
  LPUART1_init();
  SEMC_init();
+  LCDIF_init();
 }

 /***********************************************************************************************************************
--- a/board/peripherals.c.bak
+++ b/board/peripherals.c.bak
@ -55,7 +55,7 @@ instance:
    - lpuartConfig:
      - clockSource: 'LpuartClock'
      - lpuartSrcClkFreq: 'BOARD_BootClockRUN'
-      - baudRate_Bps: '115200'
+      - baudRate_Bps: '921600'
      - parityMode: 'kLPUART_ParityDisabled'
      - dataBitsCount: 'kLPUART_EightDataBits'
      - isMsb: 'false'
@ -70,11 +70,10 @@ instance:
      - rxIdleConfig: 'kLPUART_IdleCharacter1'
      - enableTx: 'true'
      - enableRx: 'true'
-    - quick_selection: 'QuickSelection1'
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 /* clang-format on */
 const lpuart_config_t LPUART1_config = {
-  .baudRate_Bps = 115200UL,
+  .baudRate_Bps = 921600UL,
  .parityMode = kLPUART_ParityDisabled,
  .dataBitsCount = kLPUART_EightDataBits,
  .isMsb = false,
--- a/board/peripherals.h
+++ b/board/peripherals.h
@ -13,6 +13,7 @@
 #include "fsl_lpuart.h"
 #include "fsl_clock.h"
 #include "fsl_semc.h"
+#include "fsl_elcdif.h"

 #if defined(__cplusplus)
 extern "C" {
@ -29,6 +30,22 @@ extern "C" {
 /* BOARD_InitPeripherals defines for SEMC */
 /* Definition of peripheral ID. */
 #define SEMC_PERIPHERAL SEMC
+/* Definition of peripheral ID */
+#define LCDIF_PERIPHERAL LCDIF
+/* Definition of the expected display clock frequency */
+#define LCDIF_EXPECTED_DCLK_FREQ 27425640UL
+/* Definition of the panel width */
+#define LCDIF_PANEL_WIDTH 800
+/* Definition of the panel height */
+#define LCDIF_PANEL_HEIGHT 480
+/* Definition of the RGB buffer alignment */
+#define LCDIF_RGB_BUFFER_ALIGN 64
+/* LCDIF interrupt vector ID (number). */
+#define LCDIF_LCDIF_IRQN LCDIF_IRQn
+/* LCDIF interrupt vector priority. */
+#define LCDIF_LCDIF_IRQ_PRIORITY 5
+/* LCDIF interrupt handler identifier. */
+#define LCDIF_LCDIF_IRQHANDLER LCDIF_IRQHandler

 /***********************************************************************************************************************
 * Global variables
@ -36,6 +53,10 @@ extern "C" {
 extern const lpuart_config_t LPUART1_config;
 extern semc_config_t SEMC_config;
 extern semc_sdram_config_t SEMC_sdram_struct;
+/* RGB mode configuration */
+extern const elcdif_rgb_mode_config_t LCDIF_rgbConfig;
+/* RGB buffer */
+extern uint32_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH];

 /***********************************************************************************************************************
 * Initialization functions
--- a/board/peripherals.h.bak
+++ b/board/peripherals.h.bak
@ -12,6 +12,7 @@
 #include "fsl_common.h"
 #include "fsl_lpuart.h"
 #include "fsl_clock.h"
+#include "fsl_semc.h"

 #if defined(__cplusplus)
 extern "C" {
@ -25,11 +26,16 @@ extern "C" {
 #define LPUART1_PERIPHERAL LPUART1
 /* Definition of the clock source frequency */
 #define LPUART1_CLOCK_SOURCE 80000000UL
+/* BOARD_InitPeripherals defines for SEMC */
+/* Definition of peripheral ID. */
+#define SEMC_PERIPHERAL SEMC

 /***********************************************************************************************************************
 * Global variables
 **********************************************************************************************************************/
 extern const lpuart_config_t LPUART1_config;
+extern semc_config_t SEMC_config;
+extern semc_sdram_config_t SEMC_sdram_struct;

 /***********************************************************************************************************************
 * Initialization functions
--- a/board/pin_mux.c
+++ b/board/pin_mux.c
@ -79,6 +79,26 @@ BOARD_InitPins:
  - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
  - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
  - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
+  - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
+  - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
+  - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
+  - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
+  - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
+  - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
+  - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
+  - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
+  - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
+  - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
+  - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
+  - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
+  - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
+  - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
+  - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
+  - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
+  - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
+  - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
+  - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
+  - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
 */

@ -93,6 +113,26 @@ void BOARD_InitPins(void) {

  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U); 
--- a/board/pin_mux.c.bak
+++ b/board/pin_mux.c.bak
@ -38,6 +38,47 @@ BOARD_InitPins:
    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
    pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
+  - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
+  - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
+  - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
+  - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
+  - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
+  - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
+  - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
+  - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
+  - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
+  - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
+  - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
+  - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
+  - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
+  - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
+  - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
+  - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
+  - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
+  - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
+  - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
+  - {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
+  - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
+  - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
+  - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
+  - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
+  - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
+  - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
+  - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
+  - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
+  - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
+  - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
+  - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
+  - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
+  - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
+  - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
+  - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
+  - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
+  - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
+  - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
+  - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
+  - {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
+  - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
 */

@ -52,6 +93,47 @@ void BOARD_InitPins(void) {

  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U); 
+  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); 
 }
--- a/board/pin_mux.h
+++ b/board/pin_mux.h
@ -287,6 +287,122 @@ void BOARD_InitBootPins(void);
 #define BOARD_INITPINS_SEMC_WE_PERIPHERAL                                   SEMC   /*!< Peripheral name */
 #define BOARD_INITPINS_SEMC_WE_SIGNAL                                    semc_we   /*!< Signal name */

+/* GPIO_B0_00 (coord D7), LCDIF_CLK */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_CLK_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_CLK_SIGNAL                                lcdif_clk   /*!< Signal name */
+
+/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D0_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D0_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D0_CHANNEL                                       0U   /*!< Signal channel */
+
+/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D1_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D1_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D1_CHANNEL                                       1U   /*!< Signal channel */
+
+/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D2_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D2_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D2_CHANNEL                                       2U   /*!< Signal channel */
+
+/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D3_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D3_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D3_CHANNEL                                       3U   /*!< Signal channel */
+
+/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D4_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D4_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D4_CHANNEL                                       4U   /*!< Signal channel */
+
+/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D5_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D5_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D5_CHANNEL                                       5U   /*!< Signal channel */
+
+/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D6_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D6_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D6_CHANNEL                                       6U   /*!< Signal channel */
+
+/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D7_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D7_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D7_CHANNEL                                       7U   /*!< Signal channel */
+
+/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D8_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D8_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D8_CHANNEL                                       8U   /*!< Signal channel */
+
+/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D9_PERIPHERAL                                 LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D9_SIGNAL                                lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D9_CHANNEL                                       9U   /*!< Signal channel */
+
+/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D10_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D10_SIGNAL                               lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D10_CHANNEL                                     10U   /*!< Signal channel */
+
+/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D11_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D11_SIGNAL                               lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D11_CHANNEL                                     11U   /*!< Signal channel */
+
+/* GPIO_B1_00 (coord A11), LCDIF_D12 */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D12_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D12_SIGNAL                               lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D12_CHANNEL                                     12U   /*!< Signal channel */
+
+/* GPIO_B1_01 (coord B11), LCDIF_D13 */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D13_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D13_SIGNAL                               lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D13_CHANNEL                                     13U   /*!< Signal channel */
+
+/* GPIO_B1_02 (coord C11), LCDIF_D14 */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D14_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D14_SIGNAL                               lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D14_CHANNEL                                     14U   /*!< Signal channel */
+
+/* GPIO_B1_03 (coord D11), LCDIF_D15 */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_D15_PERIPHERAL                                LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_D15_SIGNAL                               lcdif_data   /*!< Signal name */
+#define BOARD_INITPINS_LCDIF_D15_CHANNEL                                     15U   /*!< Signal channel */
+
+/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_VSYNC_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_VSYNC_SIGNAL                            lcdif_vsync   /*!< Signal name */
+
+/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_HSYNC_PERIPHERAL                              LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_HSYNC_SIGNAL                            lcdif_hsync   /*!< Signal name */
+
+/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
+/* Routed pin properties */
+#define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL                             LCDIF   /*!< Peripheral name */
+#define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL                          lcdif_enable   /*!< Signal name */
+

 /*!
 * @brief Configures pin routing and optionally pin electrical features.
--- a/board/pin_mux.h.bak
+++ b/board/pin_mux.h.bak
@ -47,6 +47,246 @@ void BOARD_InitBootPins(void);
 #define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
 #define BOARD_INITPINS_UART1_TXD_SIGNAL                                       TX   /*!< Signal name */

+/* GPIO_EMC_09 (coord C2), SEMC_A0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A0_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A0_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A0_CHANNEL                                        0U   /*!< Signal channel */
+
+/* GPIO_EMC_10 (coord G1), SEMC_A1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A1_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A1_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A1_CHANNEL                                        1U   /*!< Signal channel */
+
+/* GPIO_EMC_11 (coord G3), SEMC_A2 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A2_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A2_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A2_CHANNEL                                        2U   /*!< Signal channel */
+
+/* GPIO_EMC_12 (coord H1), SEMC_A3 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A3_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A3_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A3_CHANNEL                                        3U   /*!< Signal channel */
+
+/* GPIO_EMC_13 (coord A6), SEMC_A4 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A4_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A4_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A4_CHANNEL                                        4U   /*!< Signal channel */
+
+/* GPIO_EMC_14 (coord B6), SEMC_A5 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A5_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A5_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A5_CHANNEL                                        5U   /*!< Signal channel */
+
+/* GPIO_EMC_15 (coord B1), SEMC_A6 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A6_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A6_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A6_CHANNEL                                        6U   /*!< Signal channel */
+
+/* GPIO_EMC_16 (coord A5), SEMC_A7 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A7_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A7_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A7_CHANNEL                                        7U   /*!< Signal channel */
+
+/* GPIO_EMC_17 (coord A4), SEMC_A8 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A8_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A8_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A8_CHANNEL                                        8U   /*!< Signal channel */
+
+/* GPIO_EMC_18 (coord B2), SEMC_A9 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A9_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A9_SIGNAL                                       ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A9_CHANNEL                                        9U   /*!< Signal channel */
+
+/* GPIO_EMC_23 (coord G2), SEMC_A10 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A10_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A10_SIGNAL                                      ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A10_CHANNEL                                      10U   /*!< Signal channel */
+
+/* GPIO_EMC_19 (coord B4), SEMC_A11 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A11_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A11_SIGNAL                                      ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A11_CHANNEL                                      11U   /*!< Signal channel */
+
+/* GPIO_EMC_20 (coord A3), SEMC_A12 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_A12_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_A12_SIGNAL                                      ADDR   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_A12_CHANNEL                                      12U   /*!< Signal channel */
+
+/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_BA0_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_BA0_SIGNAL                                        BA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_BA0_CHANNEL                                       0U   /*!< Signal channel */
+
+/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_BA1_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_BA1_SIGNAL                                        BA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_BA1_CHANNEL                                       1U   /*!< Signal channel */
+
+/* GPIO_EMC_24 (coord D3), SEMC_CAS */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CAS_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CAS_SIGNAL                                  semc_cas   /*!< Signal name */
+
+/* GPIO_EMC_27 (coord A2), SEMC_CKE */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CKE_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CKE_SIGNAL                                  semc_cke   /*!< Signal name */
+
+/* GPIO_EMC_26 (coord B3), SEMC_CLK */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CLK_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CLK_SIGNAL                                  semc_clk   /*!< Signal name */
+
+/* GPIO_EMC_41 (coord C7), ENET_MDIO */
+/* Routed pin properties */
+#define BOARD_INITPINS_ENET_MDIO_PERIPHERAL                                 SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_ENET_MDIO_SIGNAL                                      CSX   /*!< Signal name */
+#define BOARD_INITPINS_ENET_MDIO_CHANNEL                                      0U   /*!< Signal channel */
+
+/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_CS0_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_CS0_SIGNAL                                        CS   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_CS0_CHANNEL                                       0U   /*!< Signal channel */
+
+/* GPIO_EMC_00 (coord E3), SEMC_D0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D0_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D0_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D0_CHANNEL                                        0U   /*!< Signal channel */
+
+/* GPIO_EMC_01 (coord F3), SEMC_D1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D1_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D1_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D1_CHANNEL                                        1U   /*!< Signal channel */
+
+/* GPIO_EMC_02 (coord F4), SEMC_D2 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D2_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D2_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D2_CHANNEL                                        2U   /*!< Signal channel */
+
+/* GPIO_EMC_03 (coord G4), SEMC_D3 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D3_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D3_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D3_CHANNEL                                        3U   /*!< Signal channel */
+
+/* GPIO_EMC_04 (coord F2), SEMC_D4 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D4_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D4_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D4_CHANNEL                                        4U   /*!< Signal channel */
+
+/* GPIO_EMC_05 (coord G5), SEMC_D5 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D5_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D5_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D5_CHANNEL                                        5U   /*!< Signal channel */
+
+/* GPIO_EMC_06 (coord H5), SEMC_D6 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D6_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D6_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D6_CHANNEL                                        6U   /*!< Signal channel */
+
+/* GPIO_EMC_07 (coord H4), SEMC_D7 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D7_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D7_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D7_CHANNEL                                        7U   /*!< Signal channel */
+
+/* GPIO_EMC_30 (coord C6), SEMC_D8 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D8_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D8_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D8_CHANNEL                                        8U   /*!< Signal channel */
+
+/* GPIO_EMC_31 (coord C5), SEMC_D9 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D9_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D9_SIGNAL                                       DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D9_CHANNEL                                        9U   /*!< Signal channel */
+
+/* GPIO_EMC_32 (coord D5), SEMC_D10 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D10_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D10_SIGNAL                                      DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D10_CHANNEL                                      10U   /*!< Signal channel */
+
+/* GPIO_EMC_33 (coord C4), SEMC_D11 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D11_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D11_SIGNAL                                      DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D11_CHANNEL                                      11U   /*!< Signal channel */
+
+/* GPIO_EMC_34 (coord D4), SEMC_D12 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D12_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D12_SIGNAL                                      DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D12_CHANNEL                                      12U   /*!< Signal channel */
+
+/* GPIO_EMC_35 (coord E5), SEMC_D13 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D13_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D13_SIGNAL                                      DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D13_CHANNEL                                      13U   /*!< Signal channel */
+
+/* GPIO_EMC_36 (coord C3), SEMC_D14 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D14_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D14_SIGNAL                                      DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D14_CHANNEL                                      14U   /*!< Signal channel */
+
+/* GPIO_EMC_37 (coord E4), SEMC_D15 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_D15_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_D15_SIGNAL                                      DATA   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_D15_CHANNEL                                      15U   /*!< Signal channel */
+
+/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_DM0_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_DM0_SIGNAL                                        DM   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_DM0_CHANNEL                                       0U   /*!< Signal channel */
+
+/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_DM1_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_DM1_SIGNAL                                        DM   /*!< Signal name */
+#define BOARD_INITPINS_SEMC_DM1_CHANNEL                                       1U   /*!< Signal channel */
+
+/* GPIO_EMC_25 (coord D2), SEMC_RAS */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_RAS_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_RAS_SIGNAL                                  semc_ras   /*!< Signal name */
+
+/* GPIO_EMC_40 (coord A7), ENET_MDC */
+/* Routed pin properties */
+#define BOARD_INITPINS_ENET_MDC_PERIPHERAL                                  SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_ENET_MDC_SIGNAL                                  semc_rdy   /*!< Signal name */
+
+/* GPIO_EMC_28 (coord D1), SEMC_WE */
+/* Routed pin properties */
+#define BOARD_INITPINS_SEMC_WE_PERIPHERAL                                   SEMC   /*!< Peripheral name */
+#define BOARD_INITPINS_SEMC_WE_SIGNAL                                    semc_we   /*!< Signal name */
+

 /*!
 * @brief Configures pin routing and optionally pin electrical features.
--- a/build_all.sh
+++ b/build_all.sh
@ -13,4 +13,8 @@ bash clean.sh

 for TARGET in "${TARGETS[@]}" ; do
 	ENV=${TARGET} bash build.sh $@
+	RET=$?
+	if [[ ! 0 -eq ${RET} ]]; then
+		exit ${RET}
+	fi
 done
--- a/drivers/driver_elcdif_MIMXRT1052.cmake
+++ b/drivers/driver_elcdif_MIMXRT1052.cmake
@ -0,0 +1,17 @@
+if(NOT DRIVER_ELCDIF_MIMXRT1052_INCLUDED)
+    
+    set(DRIVER_ELCDIF_MIMXRT1052_INCLUDED true CACHE BOOL "driver_elcdif component is included.")
+
+    target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+        ${CMAKE_CURRENT_LIST_DIR}/fsl_elcdif.c
+    )
+
+
+    target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+        ${CMAKE_CURRENT_LIST_DIR}/.
+    )
+
+
+    include(driver_common_MIMXRT1052)
+
+endif()
--- a/drivers/fsl_elcdif.c
+++ b/drivers/fsl_elcdif.c
@ -0,0 +1,386 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_elcdif.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.elcdif"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for ELCDIF module.
+ *
+ * @param base ELCDIF peripheral base address
+ */
+static uint32_t ELCDIF_GetInstance(LCDIF_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to ELCDIF bases for each instance. */
+static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to eLCDIF apb_clk for each instance. */
+static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS;
+#if defined(LCDIF_PERIPH_CLOCKS)
+/*! @brief Pointers to eLCDIF pix_clk for each instance. */
+static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS;
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief The control register value to select different pixel format. */
+static const elcdif_pixel_format_reg_t s_pixelFormatReg[] = {
+    /* kELCDIF_PixelFormatRAW8 */
+    {/* Register CTRL. */
+     LCDIF_CTRL_WORD_LENGTH(1U),
+     /* Register CTRL1. */
+     LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
+    /* kELCDIF_PixelFormatRGB565 */
+    {/* Register CTRL. */
+     LCDIF_CTRL_WORD_LENGTH(0U),
+     /* Register CTRL1. */
+     LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
+    /* kELCDIF_PixelFormatRGB666 */
+    {/* Register CTRL. */
+     LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U),
+     /* Register CTRL1. */
+     LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
+    /* kELCDIF_PixelFormatXRGB8888 */
+    {/* Register CTRL. 24-bit. */
+     LCDIF_CTRL_WORD_LENGTH(3U),
+     /* Register CTRL1. */
+     LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
+    /* kELCDIF_PixelFormatRGB888 */
+    {/* Register CTRL. 24-bit. */
+     LCDIF_CTRL_WORD_LENGTH(3U),
+     /* Register CTRL1. */
+     LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
+};
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++)
+    {
+        if (s_elcdifBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_elcdifBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
+ *
+ * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
+ * to the configuration structure.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
+void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
+{
+    assert(NULL != config);
+    assert((uint32_t)config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = ELCDIF_GetInstance(base);
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_elcdifApbClocks[instance]);
+#if defined(LCDIF_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_elcdifPixClocks[instance]);
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset. */
+    ELCDIF_Reset(base);
+
+    base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) |
+                 LCDIF_CTRL_DOTCLK_MODE_MASK |  /* RGB mode. */
+                 LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */
+                 LCDIF_CTRL_MASTER_MASK;
+
+    base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1;
+
+    base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) |
+                           ((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT);
+
+    base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK |         /* Data enable signal. */
+                    LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK |      /* VSYNC period in the unit of display clock. */
+                    LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */
+                    (uint32_t)config->polarityFlags | (uint32_t)config->vsw;
+
+    base->VDCTRL1 =
+        (uint32_t)config->vsw + (uint32_t)config->panelHeight + (uint32_t)config->vfp + (uint32_t)config->vbp;
+    base->VDCTRL2 =
+        ((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) |
+        (((uint32_t)config->hfp + (uint32_t)config->hbp + (uint32_t)config->panelWidth + (uint32_t)config->hsw))
+            << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT;
+
+    base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) |
+                    (((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT);
+
+    base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
+                    ((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT);
+
+    base->CUR_BUF  = config->bufferAddr;
+    base->NEXT_BUF = config->bufferAddr;
+}
+
+/*!
+ * brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * code
+    config->panelWidth = 480U;
+    config->panelHeight = 272U;
+    config->hsw = 41;
+    config->hfp = 4;
+    config->hbp = 8;
+    config->vsw = 10;
+    config->vfp = 4;
+    config->vbp = 2;
+    config->polarityFlags = kELCDIF_VsyncActiveLow |
+                            kELCDIF_HsyncActiveLow |
+                            kELCDIF_DataEnableActiveLow |
+                            kELCDIF_DriveDataOnFallingClkEdge;
+    config->bufferAddr = 0U;
+    config->pixelFormat = kELCDIF_PixelFormatRGB888;
+    config->dataBus = kELCDIF_DataBus24Bit;
+    code
+ *
+ * param config Pointer to the eLCDIF configuration structure.
+ */
+void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->panelWidth    = 480U;
+    config->panelHeight   = 272U;
+    config->hsw           = 41;
+    config->hfp           = 4;
+    config->hbp           = 8;
+    config->vsw           = 10;
+    config->vfp           = 4;
+    config->vbp           = 2;
+    config->polarityFlags = (uint32_t)kELCDIF_VsyncActiveLow | (uint32_t)kELCDIF_HsyncActiveLow |
+                            (uint32_t)kELCDIF_DataEnableActiveLow | (uint32_t)kELCDIF_DriveDataOnFallingClkEdge;
+    config->bufferAddr  = 0U;
+    config->pixelFormat = kELCDIF_PixelFormatRGB888;
+    config->dataBus     = kELCDIF_DataBus24Bit;
+}
+
+/*!
+ * brief Set the pixel format in RGB (DOTCLK) mode.
+ *
+ * param base eLCDIF peripheral base address.
+ * param pixelFormat The pixel format.
+ */
+void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat)
+{
+    assert((uint32_t)pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
+
+    base->CTRL = (base->CTRL & ~(LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK |
+                                 LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)) |
+                 s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl;
+
+    base->CTRL1 = s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl1;
+}
+
+/*!
+ * brief Deinitializes the eLCDIF peripheral.
+ *
+ * param base eLCDIF peripheral base address.
+ */
+void ELCDIF_Deinit(LCDIF_Type *base)
+{
+    ELCDIF_Reset(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = ELCDIF_GetInstance(base);
+/* Disable the clock. */
+#if defined(LCDIF_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_elcdifPixClocks[instance]);
+#endif
+    CLOCK_DisableClock(s_elcdifApbClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Stop display in RGB (DOTCLK) mode and wait until finished.
+ *
+ * param base eLCDIF peripheral base address.
+ */
+void ELCDIF_RgbModeStop(LCDIF_Type *base)
+{
+    base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
+
+    /* Wait for data transfer finished. */
+    while (0U != (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK))
+    {
+    }
+}
+
+/*!
+ * brief Reset the eLCDIF peripheral.
+ *
+ * param base eLCDIF peripheral base address.
+ */
+void ELCDIF_Reset(LCDIF_Type *base)
+{
+    /*
+     * ELCDIF reset workflow:
+     *
+     * 1. Ungate clock.
+     * 2. Trigger the software reset.
+     * 3. The software reset finished when clk_gate bit is set.
+     * 4. Ungate the clock.
+     * 5. Release the reset.
+     */
+
+    /* Ungate clock. */
+    base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
+
+    /*
+     * If already in reset state, release the reset.
+     * If not, trigger reset.
+     */
+    if (0U == (base->CTRL & LCDIF_CTRL_SFTRST_MASK))
+    {
+        /* Trigger reset. */
+        base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK;
+
+        /* Reset is not finished until CLK_GATE is set. */
+        while (0U == (base->CTRL & LCDIF_CTRL_CLKGATE_MASK))
+        {
+        }
+
+        /* Ungate the clock. */
+        base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
+    }
+
+    /* Release the reset. */
+    base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK;
+}
+
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+/*!
+ * brief Set the configuration for alpha surface buffer.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
+void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
+{
+    assert(NULL != config);
+
+    base->AS_CTRL     = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
+    base->AS_BUF      = config->bufferAddr;
+    base->AS_NEXT_BUF = config->bufferAddr;
+}
+
+/*!
+ * brief Set the alpha surface blending configuration.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
+void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
+{
+    assert(NULL != config);
+    uint32_t reg;
+
+    reg = base->AS_CTRL;
+    reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK |
+             LCDIF_AS_CTRL_ALPHA_CTRL_MASK);
+    reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) |
+            LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode));
+
+    if (config->invertAlpha)
+    {
+        reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK;
+    }
+
+    base->AS_CTRL = reg;
+}
+#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
+
+#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
+/*!
+ * brief Load the LUT value.
+ *
+ * This function loads the LUT value to the specific LUT memory, user can
+ * specify the start entry index.
+ *
+ * param base eLCDIF peripheral base address.
+ * param lut Which LUT to load.
+ * param startIndex The start index of the LUT entry to update.
+ * param lutData The LUT data to load.
+ * param count Count of p lutData.
+ * retval kStatus_Success Initialization success.
+ * retval kStatus_InvalidArgument Wrong argument.
+ */
+status_t ELCDIF_UpdateLut(
+    LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
+{
+    volatile uint32_t *regLutAddr;
+    volatile uint32_t *regLutData;
+    uint32_t i;
+    status_t status;
+
+    /* Only has 256 entries. */
+    if (startIndex + count > ELCDIF_LUT_ENTRY_NUM)
+    {
+        status = kStatus_InvalidArgument;
+    }
+    else
+    {
+        if (kELCDIF_Lut0 == lut)
+        {
+            regLutAddr = &(base->LUT0_ADDR);
+            regLutData = &(base->LUT0_DATA);
+        }
+        else
+        {
+            regLutAddr = &(base->LUT1_ADDR);
+            regLutData = &(base->LUT1_DATA);
+        }
+
+        *regLutAddr = startIndex;
+
+        for (i = 0; i < count; i++)
+        {
+            *regLutData = lutData[i];
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_LCDIF_HAS_LUT */
--- a/drivers/fsl_elcdif.h
+++ b/drivers/fsl_elcdif.h
@ -0,0 +1,747 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_ELCDIF_H_
+#define _FSL_ELCDIF_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup elcdif
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief eLCDIF driver version */
+#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/* All IRQ flags in CTRL1 register. */
+#define ELCDIF_CTRL1_IRQ_MASK                                                                         \
+    (LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \
+     LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
+
+/* All IRQ enable control bits in CTRL1 register. */
+#define ELCDIF_CTRL1_IRQ_EN_MASK                                                                               \
+    (LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \
+     LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
+
+/* All IRQ flags in AS_CTRL register. */
+#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
+#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
+#else
+#define ELCDIF_AS_CTRL_IRQ_MASK 0U
+#endif
+
+/* All IRQ enable control bits in AS_CTRL register. */
+#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
+#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
+#else
+#define ELCDIF_AS_CTRL_IRQ_EN_MASK 0U
+#endif
+
+#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK))
+#error Interrupt bits overlap, need to update the interrupt functions.
+#endif
+
+/* LUT memory entery number. */
+#define ELCDIF_LUT_ENTRY_NUM 256U
+
+/*!
+ * @brief eLCDIF signal polarity flags
+ */
+enum _elcdif_polarity_flags
+{
+    kELCDIF_VsyncActiveLow            = 0U,                            /*!< VSYNC active low. */
+    kELCDIF_VsyncActiveHigh           = LCDIF_VDCTRL0_VSYNC_POL_MASK,  /*!< VSYNC active high. */
+    kELCDIF_HsyncActiveLow            = 0U,                            /*!< HSYNC active low. */
+    kELCDIF_HsyncActiveHigh           = LCDIF_VDCTRL0_HSYNC_POL_MASK,  /*!< HSYNC active high. */
+    kELCDIF_DataEnableActiveLow       = 0U,                            /*!< Data enable line active low. */
+    kELCDIF_DataEnableActiveHigh      = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
+    kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data
+                                                 on rising clock edge. */
+    kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling
+                                                                        clock edge, capture data
+                                                                        on rising clock edge. */
+};
+
+/*!
+ * @brief The eLCDIF interrupts to enable.
+ */
+enum _elcdif_interrupt_enable
+{
+    kELCDIF_BusMasterErrorInterruptEnable  = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK,  /*!< Bus master error interrupt. */
+    kELCDIF_TxFifoOverflowInterruptEnable  = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK,  /*!< TXFIFO overflow interrupt. */
+    kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */
+    kELCDIF_CurFrameDoneInterruptEnable =
+        LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
+    kELCDIF_VsyncEdgeInterruptEnable =
+        LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */
+#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
+    kELCDIF_SciSyncOnInterruptEnable =
+        LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */
+#endif
+};
+
+/*!
+ * @brief The eLCDIF interrupt status flags.
+ */
+enum _elcdif_interrupt_flags
+{
+    kELCDIF_BusMasterError  = LCDIF_CTRL1_BM_ERROR_IRQ_MASK,  /*!< Bus master error interrupt. */
+    kELCDIF_TxFifoOverflow  = LCDIF_CTRL1_OVERFLOW_IRQ_MASK,  /*!< TXFIFO overflow interrupt. */
+    kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */
+    kELCDIF_CurFrameDone =
+        LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK,             /*!< Interrupt when hardware enters vertical blanking state. */
+    kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */
+#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
+    kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */
+#endif
+};
+
+/*!
+ * @brief eLCDIF status flags
+ */
+enum _elcdif_status_flags
+{
+    kELCDIF_LFifoFull   = LCDIF_STAT_LFIFO_FULL_MASK,   /*!< LFIFO full. */
+    kELCDIF_LFifoEmpty  = LCDIF_STAT_LFIFO_EMPTY_MASK,  /*!< LFIFO empty. */
+    kELCDIF_TxFifoFull  = LCDIF_STAT_TXFIFO_FULL_MASK,  /*!< TXFIFO full. */
+    kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */
+#if defined(LCDIF_STAT_BUSY_MASK)
+    kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */
+#endif
+#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
+    kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2,
+                                                               otherwise current filed is 1. */
+#endif
+};
+
+/*!
+ * @brief The pixel format.
+ *
+ * This enumerator should be defined together with the array s_pixelFormatReg.
+ * To support new pixel format, enhance this enumerator and s_pixelFormatReg.
+ */
+typedef enum _elcdif_pixel_format
+{
+    kELCDIF_PixelFormatRAW8   = 0,   /*!< RAW 8 bit, four data use 32 bits. */
+    kELCDIF_PixelFormatRGB565 = 1,   /*!< RGB565, two pixel use 32 bits. */
+    kELCDIF_PixelFormatRGB666 = 2,   /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused,
+                                          upper 2 bits of other bytes unused. */
+    kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */
+    kELCDIF_PixelFormatRGB888   = 4, /*!< RGB888 packed, one pixel uses 24 bits. */
+} elcdif_pixel_format_t;
+
+/*! @brief The LCD data bus type.  */
+typedef enum _elcdif_lcd_data_bus
+{
+    kELCDIF_DataBus8Bit  = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */
+    kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */
+    kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */
+    kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */
+} elcdif_lcd_data_bus_t;
+
+/*!
+ * @brief The register value when using different pixel format.
+ *
+ * These register bits control the pixel format:
+ * - CTRL[DATA_FORMAT_24_BIT]
+ * - CTRL[DATA_FORMAT_18_BIT]
+ * - CTRL[DATA_FORMAT_16_BIT]
+ * - CTRL[WORD_LENGTH]
+ * - CTRL1[BYTE_PACKING_FORMAT]
+ */
+typedef struct _elcdif_pixel_format_reg
+{
+    uint32_t regCtrl;  /*!< Value of register CTRL. */
+    uint32_t regCtrl1; /*!< Value of register CTRL1. */
+} elcdif_pixel_format_reg_t;
+
+/*!
+ * @brief eLCDIF configure structure for RGB mode (DOTCLK mode).
+ */
+typedef struct _elcdif_rgb_mode_config
+{
+    uint16_t panelWidth;    /*!< Display panel width, pixels per line. */
+    uint16_t panelHeight;   /*!< Display panel height, how many lines per panel. */
+    uint8_t hsw;            /*!< HSYNC pulse width. */
+    uint8_t hfp;            /*!< Horizontal front porch. */
+    uint8_t hbp;            /*!< Horizontal back porch. */
+    uint8_t vsw;            /*!< VSYNC pulse width. */
+    uint8_t vfp;            /*!< Vrtical front porch. */
+    uint8_t vbp;            /*!< Vertical back porch. */
+    uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */
+    uint32_t bufferAddr;    /*!< Frame buffer address. */
+    elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */
+    elcdif_lcd_data_bus_t dataBus;     /*!< LCD data bus. */
+} elcdif_rgb_mode_config_t;
+
+/*!
+ * @brief eLCDIF alpha surface pixel format.
+ */
+typedef enum _elcdif_as_pixel_format
+{
+    kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
+    kELCDIF_AsPixelFormatRGB888   = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
+    kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
+    kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
+    kELCDIF_AsPixelFormatRGB555   = 0xC, /*!< 16-bit pixels without alpha. */
+    kELCDIF_AsPixelFormatRGB444   = 0xD, /*!< 16-bit pixels without alpha. */
+    kELCDIF_AsPixelFormatRGB565   = 0xE, /*!< 16-bit pixels without alpha. */
+} elcdif_as_pixel_format_t;
+
+/*!
+ * @brief eLCDIF alpha surface buffer configuration.
+ */
+typedef struct _elcdif_as_buffer_config
+{
+    uint32_t bufferAddr;                  /*!< Buffer address. */
+    elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */
+} elcdif_as_buffer_config_t;
+
+/*!
+ * @brief eLCDIF alpha mode during blending.
+ */
+typedef enum _elcdif_alpha_mode
+{
+    kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
+    kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
+    kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
+                             alpha value will be used for blend, for example, pixel alpha set
+                             set to 200, user defined alpha set to 100, then the reault alpha
+                             is 200 * 100 / 255. */
+    kELCDIF_AlphaRop       /*!< Raster operation. */
+} elcdif_alpha_mode_t;
+
+/*!
+ * @brief eLCDIF ROP mode during blending.
+ *
+ * Explanation:
+ * - AS: Alpha surface
+ * - PS: Process surface
+ * - nAS: Alpha surface NOT value
+ * - nPS: Process surface NOT value
+ */
+typedef enum _elcdif_rop_mode
+{
+    kELCDIF_RopMaskAs     = 0x0, /*!< AS AND PS. */
+    kELCDIF_RopMaskNotAs  = 0x1, /*!< nAS AND PS. */
+    kELCDIF_RopMaskAsNot  = 0x2, /*!< AS AND nPS. */
+    kELCDIF_RopMergeAs    = 0x3, /*!< AS OR PS. */
+    kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
+    kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
+    kELCDIF_RopNotCopyAs  = 0x6, /*!< nAS. */
+    kELCDIF_RopNot        = 0x7, /*!< nPS. */
+    kELCDIF_RopNotMaskAs  = 0x8, /*!< AS NAND PS. */
+    kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
+    kELCDIF_RopXorAs      = 0xA, /*!< AS XOR PS. */
+    kELCDIF_RopNotXorAs   = 0xB  /*!< AS XNOR PS. */
+} elcdif_rop_mode_t;
+
+/*!
+ * @brief eLCDIF alpha surface blending configuration.
+ */
+typedef struct _elcdif_as_blend_config
+{
+    uint8_t alpha;    /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref
+                         kELCDIF_AlphaRop. */
+    bool invertAlpha; /*!< Set true to invert the alpha. */
+    elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */
+    elcdif_rop_mode_t ropMode;     /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */
+} elcdif_as_blend_config_t;
+
+/*!
+ * @brief eLCDIF LUT
+ *
+ * The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel
+ * before output to external displayer.
+ *
+ * There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address
+ * determins which memory to use.
+ */
+typedef enum _elcdif_lut
+{
+    kELCDIF_Lut0 = 0, /*!< LUT 0. */
+    kELCDIF_Lut1,     /*!< LUT 1. */
+} elcdif_lut_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name eLCDIF initialization and de-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
+ *
+ * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
+ * to the configuration structure.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config);
+
+/*!
+ * @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * @code
+    config->panelWidth = 480U;
+    config->panelHeight = 272U;
+    config->hsw = 41;
+    config->hfp = 4;
+    config->hbp = 8;
+    config->vsw = 10;
+    config->vfp = 4;
+    config->vbp = 2;
+    config->polarityFlags = kELCDIF_VsyncActiveLow |
+                            kELCDIF_HsyncActiveLow |
+                            kELCDIF_DataEnableActiveLow |
+                            kELCDIF_DriveDataOnFallingClkEdge;
+    config->bufferAddr = 0U;
+    config->pixelFormat = kELCDIF_PixelFormatRGB888;
+    config->dataBus = kELCDIF_DataBus24Bit;
+   @endcode
+ *
+ * @param config Pointer to the eLCDIF configuration structure.
+ */
+void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config);
+
+/*!
+ * @brief Deinitializes the eLCDIF peripheral.
+ *
+ * @param base eLCDIF peripheral base address.
+ */
+void ELCDIF_Deinit(LCDIF_Type *base);
+
+/* @} */
+
+/*!
+ * @name Module operation
+ * @{
+ */
+
+/*!
+ * @brief Set the pixel format in RGB (DOTCLK) mode.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param pixelFormat The pixel format.
+ */
+void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat);
+
+/*!
+ * @brief Start to display in RGB (DOTCLK) mode.
+ *
+ * @param base eLCDIF peripheral base address.
+ */
+static inline void ELCDIF_RgbModeStart(LCDIF_Type *base)
+{
+    base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK;
+}
+
+/*!
+ * @brief Stop display in RGB (DOTCLK) mode and wait until finished.
+ *
+ * @param base eLCDIF peripheral base address.
+ */
+void ELCDIF_RgbModeStop(LCDIF_Type *base);
+
+/*!
+ * @brief Set the next frame buffer address to display.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param bufferAddr The frame buffer address to set.
+ */
+static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)
+{
+    base->NEXT_BUF = bufferAddr;
+}
+
+/*!
+ * @brief Reset the eLCDIF peripheral.
+ *
+ * @param base eLCDIF peripheral base address.
+ */
+void ELCDIF_Reset(LCDIF_Type *base);
+
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) && FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN)
+/*!
+ * @brief Pull up or down the reset pin for the externel LCD controller.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param pullUp True to pull up reset pin, false to pull down.
+ */
+static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp)
+{
+    if (pullUp)
+    {
+        base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK;
+    }
+    else
+    {
+        base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK;
+    }
+}
+#endif
+
+/*!
+ * @brief Enable or disable the hand shake with PXP.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK;
+    }
+    else
+    {
+        base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK;
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get the CRC value of the frame sent out.
+ *
+ * When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function
+ * can be used to get the CRC value of the frame sent.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @return The CRC value.
+ *
+ * @note The CRC value is dependent on the LCD_DATABUS_WIDTH.
+ */
+static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base)
+{
+    return base->CRC_STAT;
+}
+
+/*!
+ * @brief Get the bus master error virtual address.
+ *
+ * When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function
+ * can get the virtual address at which the AXI master received an error
+ * response from the slave.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @return The error virtual address.
+ */
+static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base)
+{
+    return base->BM_ERROR_STAT;
+}
+
+/*!
+ * @brief Get the eLCDIF status.
+ *
+ * The status flags are returned as a mask value, application could check the
+ * corresponding bit. Example:
+ *
+ * @code
+   uint32_t statusFlags;
+   statusFlags = ELCDIF_GetStatus(LCDIF);
+
+   if (kELCDIF_LFifoFull & statusFlags)
+   {
+   }
+
+   if (kELCDIF_TxFifoEmpty & statusFlags)
+   {
+   }
+   @endcode
+ *
+ * @param base eLCDIF peripheral base address.
+ * @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags.
+ */
+static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base)
+{
+    return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK |
+                         LCDIF_STAT_TXFIFO_EMPTY_MASK
+#if defined(LCDIF_STAT_BUSY_MASK)
+                         | LCDIF_STAT_BUSY_MASK
+#endif
+#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
+                         | LCDIF_STAT_DVI_CURRENT_FIELD_MASK
+#endif
+                        );
+}
+
+/*!
+ * @brief Get current count in Latency buffer (LFIFO).
+ *
+ * @param base eLCDIF peripheral base address.
+ * @return The LFIFO current count
+ */
+static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base)
+{
+    return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables eLCDIF interrupt requests.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable.
+ */
+static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask)
+{
+    base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK);
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+    base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK);
+#endif
+}
+
+/*!
+ * @brief Disables eLCDIF interrupt requests.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable.
+ */
+static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask)
+{
+    base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK);
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+    base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK);
+#endif
+}
+
+/*!
+ * @brief Get eLCDIF interrupt peding status.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags.
+ */
+static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base)
+{
+    uint32_t flags;
+
+    flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK);
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+    flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK);
+#endif
+
+    return flags;
+}
+
+/*!
+ * @brief Clear eLCDIF interrupt peding status.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags.
+ */
+static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask)
+{
+    base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK);
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+    base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK);
+#endif
+}
+
+/* @} */
+
+#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+/*!
+ * @name Alpha surface
+ * @{
+ */
+
+/*!
+ * @brief Set the configuration for alpha surface buffer.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config);
+
+/*!
+ * @brief Set the alpha surface blending configuration.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config);
+
+/*!
+ * @brief Set the next alpha surface buffer address.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param bufferAddr Alpha surface buffer address.
+ */
+static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)
+{
+    base->AS_NEXT_BUF = bufferAddr;
+}
+
+/*!
+ * @brief Set the overlay color key.
+ *
+ * If a pixel in the current overlay image with a color that falls in the range
+ * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface
+ * pixel value for that location.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param colorKeyLow Color key low range.
+ * @param colorKeyHigh Color key high range.
+ *
+ * @note Colorkey operations are higher priority than alpha or ROP operations
+ */
+static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
+{
+    base->AS_CLRKEYLOW  = colorKeyLow;
+    base->AS_CLRKEYHIGH = colorKeyHigh;
+}
+
+/*!
+ * @brief Enable or disable the color key.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK;
+    }
+    else
+    {
+        base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK;
+    }
+}
+
+/*!
+ * @brief Enable or disable the alpha surface.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK;
+    }
+    else
+    {
+        base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief Enable or disable the process surface.
+ *
+ * Process surface is the normal frame buffer. The process surface content
+ * is controlled by ::ELCDIF_SetNextBufferAddr.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK;
+    }
+    else
+    {
+        base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK;
+    }
+}
+
+/* @} */
+#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
+
+#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
+/*!
+ * @name LUT
+ *
+ * The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel
+ * before output to external displayer.
+ *
+ * There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address
+ * determins which memory to use.
+ *
+ * @{
+ */
+
+/*!
+ * @brief Enable or disable the LUT.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void ELCDIF_EnableLut(LCDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LUT_CTRL &= ~LCDIF_LUT_CTRL_LUT_BYPASS_MASK;
+    }
+    else
+    {
+        base->LUT_CTRL |= LCDIF_LUT_CTRL_LUT_BYPASS_MASK;
+    }
+}
+
+/*!
+ * @brief Load the LUT value.
+ *
+ * This function loads the LUT value to the specific LUT memory, user can
+ * specify the start entry index.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param lut Which LUT to load.
+ * @param startIndex The start index of the LUT entry to update.
+ * @param lutData The LUT data to load.
+ * @param count Count of @p lutData.
+ * @retval kStatus_Success Initialization success.
+ * @retval kStatus_InvalidArgument Wrong argument.
+ */
+status_t ELCDIF_UpdateLut(
+    LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count);
+
+/* @} */
+#endif /* FSL_FEATURE_LCDIF_HAS_LUT */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /*_FSL_ELCDIF_H_*/
--- a/rt1050_freertos_hello.mex
+++ b/rt1050_freertos_hello.mex
@ -44,6 +44,11 @@
                        <data>true</data>
                     </feature>
                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
                     <feature name="enabled" evaluation="equal" configuration="core0">
                        <data>true</data>
@ -123,6 +128,26 @@
                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
                  <pin peripheral="SEMC" signal="semc_rdy" pin_num="A7" pin_signal="GPIO_EMC_40"/>
                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"/>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"/>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"/>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"/>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"/>
               </pins>
            </function>
         </functions_list>
@ -446,6 +471,16 @@
                  <data type="Version">2.3.0</data>
               </feature>
            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.elcdif" description="elcdif not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.elcdif" description="Unsupported version of the elcdif in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.0.0</data>
+               </feature>
+            </dependency>
         </dependencies>
         <generated_project_files>
            <file path="board/peripherals.c" update_enabled="true"/>
@ -474,6 +509,111 @@
                        <data type="Boolean">true</data>
                     </feature>
                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_clk" description="Signal CLK of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_enable" description="Signal ENABLE of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_hsync" description="Signal HSYNC of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_vsync" description="Signal VSYNC of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.00" description="Signal DATA of the channel 00 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.01" description="Signal DATA of the channel 01 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.02" description="Signal DATA of the channel 02 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.03" description="Signal DATA of the channel 03 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.04" description="Signal DATA of the channel 04 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.05" description="Signal DATA of the channel 05 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.06" description="Signal DATA of the channel 06 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.07" description="Signal DATA of the channel 07 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.08" description="Signal DATA of the channel 08 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.09" description="Signal DATA of the channel 09 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.10" description="Signal DATA of the channel 10 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.11" description="Signal DATA of the channel 11 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.12" description="Signal DATA of the channel 12 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.13" description="Signal DATA of the channel 13 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.14" description="Signal DATA of the channel 14 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LCDIF.lcdif_data.15" description="Signal DATA of the channel 15 of the peripheral LCDIF is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="ClockOutput" resourceId="LCDIF_CLK_ROOT" description="LCDIF_CLK_ROOT is inactive." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
               </dependencies>
               <instances>
                  <instance name="LPUART1" uuid="c4097945-c1a4-4198-901a-11b1297f9b3d" type="lpuart" type_id="lpuart_54a65a580e3462acdbacefd5299e0cac" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
@ -561,6 +701,46 @@
                        <array name="sdramArray"/>
                     </config_set>
                  </instance>
+                  <instance name="LCDIF" uuid="045e7c7e-f29e-4ee1-8f04-e6a3e59eebc4" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="800"/>
+                           <setting name="panelHeightInt" value="480"/>
+                           <setting name="hsw" value="1"/>
+                           <setting name="hfp" value="22"/>
+                           <setting name="hbp" value="46"/>
+                           <setting name="vsw" value="1"/>
+                           <setting name="vfp" value="22"/>
+                           <setting name="vbp" value="23"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatXRGB8888"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="true"/>
+                           <setting name="priority" value="5"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
               </instances>
            </functional_group>
         </functional_groups>
--- a/source/freertos_hello.c
+++ b/source/freertos_hello.c
@ -45,6 +45,7 @@ int main(void)
    BOARD_InitBootClocks();
    BOARD_InitBootPeripherals();
    BOARD_InitDebugConsole();
+
    if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) !=
        pdPASS)
    {