From b04dfa766abb22d92fd66eb209364998b2402b78 Mon Sep 17 00:00:00 2001 From: imi415 Date: Wed, 10 Mar 2021 00:52:13 +0800 Subject: [PATCH] Added LwIP sources. --- CMakeLists.txt | 96 +++++ .../phy/device/phyksz8081/fsl_phyksz8081.c | 341 ++++++++++++++++++ .../phy/device/phyksz8081/fsl_phyksz8081.h | 163 +++++++++ component/phy/fsl_mdio.h | 128 +++++++ component/phy/fsl_phy.h | 266 ++++++++++++++ component/phy/mdio/enet/fsl_enet_mdio.c | 133 +++++++ component/phy/mdio/enet/fsl_enet_mdio.h | 21 ++ source/lwipopts.h | 336 +++++++++++++++++ 8 files changed, 1484 insertions(+) create mode 100644 component/phy/device/phyksz8081/fsl_phyksz8081.c create mode 100644 component/phy/device/phyksz8081/fsl_phyksz8081.h create mode 100644 component/phy/fsl_mdio.h create mode 100644 component/phy/fsl_phy.h create mode 100644 component/phy/mdio/enet/fsl_enet_mdio.c create mode 100644 component/phy/mdio/enet/fsl_enet_mdio.h create mode 100644 source/lwipopts.h diff --git a/CMakeLists.txt b/CMakeLists.txt index c7fd418..3d7b897 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -45,6 +45,8 @@ set(C_SOURCES "component/serial_manager/fsl_component_serial_manager.c" "component/osa/fsl_os_abstraction_free_rtos.c" "component/uart/fsl_adapter_lpuart.c" + "component/phy/device/phyksz8081/fsl_phyksz8081.c" + "component/phy/mdio/enet/fsl_enet_mdio.c" "source/freertos_hello.c" "source/user_irqhandlers.c" "source/sdmmc_config.c" @@ -70,6 +72,94 @@ set(C_SOURCES "middleware/fatfs/source/diskio.c" "middleware/fatfs/source/ff.c" "middleware/fatfs/source/fsl_sd_disk/fsl_sd_disk.c" + "middleware/lwip/src/core/ipv4/ip4.c" + "middleware/lwip/src/core/ipv4/ip4_frag.c" + "middleware/lwip/src/core/ipv4/acd.c" + "middleware/lwip/src/core/ipv4/dhcp.c" + "middleware/lwip/src/core/ipv4/icmp.c" + "middleware/lwip/src/core/ipv4/ip4_addr.c" + "middleware/lwip/src/core/ipv4/igmp.c" + "middleware/lwip/src/core/ipv4/autoip.c" + "middleware/lwip/src/core/ipv4/etharp.c" + "middleware/lwip/src/core/memp.c" + "middleware/lwip/src/core/sys.c" + "middleware/lwip/src/core/altcp.c" + "middleware/lwip/src/core/ip.c" + "middleware/lwip/src/core/udp.c" + "middleware/lwip/src/core/tcp_in.c" + "middleware/lwip/src/core/mem.c" + "middleware/lwip/src/core/raw.c" + "middleware/lwip/src/core/dns.c" + "middleware/lwip/src/core/tcp.c" + "middleware/lwip/src/core/inet_chksum.c" + "middleware/lwip/src/core/ipv6/mld6.c" + "middleware/lwip/src/core/ipv6/ethip6.c" + "middleware/lwip/src/core/ipv6/ip6_frag.c" + "middleware/lwip/src/core/ipv6/dhcp6.c" + "middleware/lwip/src/core/ipv6/ip6.c" + "middleware/lwip/src/core/ipv6/inet6.c" + "middleware/lwip/src/core/ipv6/ip6_addr.c" + "middleware/lwip/src/core/ipv6/nd6.c" + "middleware/lwip/src/core/ipv6/icmp6.c" + "middleware/lwip/src/core/netif.c" + "middleware/lwip/src/core/def.c" + "middleware/lwip/src/core/tcp_out.c" + "middleware/lwip/src/core/init.c" + "middleware/lwip/src/core/altcp_tcp.c" + "middleware/lwip/src/core/pbuf.c" + "middleware/lwip/src/core/altcp_alloc.c" + "middleware/lwip/src/core/timeouts.c" + "middleware/lwip/src/core/stats.c" + "middleware/lwip/src/api/sockets.c" + "middleware/lwip/src/api/api_msg.c" + "middleware/lwip/src/api/netdb.c" + "middleware/lwip/src/api/api_lib.c" + "middleware/lwip/src/api/tcpip.c" + "middleware/lwip/src/api/netbuf.c" + "middleware/lwip/src/api/if_api.c" + "middleware/lwip/src/api/err.c" + "middleware/lwip/src/api/netifapi.c" + "middleware/lwip/src/netif/ethernet.c" + "middleware/lwip/src/netif/slipif.c" + "middleware/lwip/src/netif/ppp/ccp.c" + "middleware/lwip/src/netif/ppp/utils.c" + "middleware/lwip/src/netif/ppp/chap-md5.c" + "middleware/lwip/src/netif/ppp/upap.c" + "middleware/lwip/src/netif/ppp/eui64.c" + "middleware/lwip/src/netif/ppp/eap.c" + "middleware/lwip/src/netif/ppp/lwip_ecp.c" + "middleware/lwip/src/netif/ppp/mppe.c" + "middleware/lwip/src/netif/ppp/ipcp.c" + "middleware/lwip/src/netif/ppp/ipv6cp.c" + "middleware/lwip/src/netif/ppp/multilink.c" + "middleware/lwip/src/netif/ppp/pppcrypt.c" + "middleware/lwip/src/netif/ppp/polarssl/md4.c" + "middleware/lwip/src/netif/ppp/polarssl/des.c" + "middleware/lwip/src/netif/ppp/polarssl/sha1.c" + "middleware/lwip/src/netif/ppp/polarssl/md5.c" + "middleware/lwip/src/netif/ppp/polarssl/arc4.c" + "middleware/lwip/src/netif/ppp/pppol2tp.c" + "middleware/lwip/src/netif/ppp/demand.c" + "middleware/lwip/src/netif/ppp/pppapi.c" + "middleware/lwip/src/netif/ppp/lcp.c" + "middleware/lwip/src/netif/ppp/vj.c" + "middleware/lwip/src/netif/ppp/ppp.c" + "middleware/lwip/src/netif/ppp/chap-new.c" + "middleware/lwip/src/netif/ppp/pppoe.c" + "middleware/lwip/src/netif/ppp/fsm.c" + "middleware/lwip/src/netif/ppp/pppos.c" + "middleware/lwip/src/netif/ppp/auth.c" + "middleware/lwip/src/netif/ppp/magic.c" + "middleware/lwip/src/netif/ppp/chap_ms.c" + "middleware/lwip/src/netif/zepif.c" + "middleware/lwip/src/netif/lowpan6_ble.c" + "middleware/lwip/src/netif/lowpan6_common.c" + "middleware/lwip/src/netif/bridgeif.c" + "middleware/lwip/src/netif/bridgeif_fdb.c" + "middleware/lwip/src/netif/lowpan6.c" + "middleware/lwip/port/sys_arch.c" + "middleware/lwip/port/enet_ethernetif.c" + "middleware/lwip/port/enet_ethernetif_kinetis.c" ) # Copy them from Makefile @@ -81,6 +171,7 @@ set(ASM_SOURCES add_definitions( "-DCPU_MIMXRT1052DVL6B" "-DFSL_RTOS_FREE_RTOS" + "-DUSE_RTOS" "-DSERIAL_PORT_TYPE_UART=1" "-D__STARTUP_CLEAR_BSS" "-D__STARTUP_INITIALIZE_NONCACHEDATA" @@ -99,6 +190,9 @@ include_directories( "component/serial_manager" "component/osa" "component/uart" + "component/phy" + "component/phy/mdio/enet" + "component/phy/device/phyksz8081" "source" "board" "utilities" @@ -110,6 +204,8 @@ include_directories( "middleware/sdmmc/host/usdhc" "middleware/fatfs/source" "middleware/fatfs/source/fsl_sd_disk" + "middleware/lwip/src/include" + "middleware/lwip/port" ) # Conditional compiler flags diff --git a/component/phy/device/phyksz8081/fsl_phyksz8081.c b/component/phy/device/phyksz8081/fsl_phyksz8081.c new file mode 100644 index 0000000..2662921 --- /dev/null +++ b/component/phy/device/phyksz8081/fsl_phyksz8081.c @@ -0,0 +1,341 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_phyksz8081.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the PHY KSZ8081 vendor defined registers. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +/*! @brief Defines the PHY KSZ8081 ID number. */ +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1 */ + +/*! @brief Defines the mask flag of operation mode in control registers */ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) + +/*! @brief Defines the timeout macro. */ +#define PHY_READID_TIMEOUT_COUNT 1000U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +const phy_operations_t phyksz8081_ops = {.phyInit = PHY_KSZ8081_Init, + .phyWrite = PHY_KSZ8081_Write, + .phyRead = PHY_KSZ8081_Read, + .getAutoNegoStatus = PHY_KSZ8081_GetAutoNegotiationStatus, + .getLinkStatus = PHY_KSZ8081_GetLinkStatus, + .getLinkSpeedDuplex = PHY_KSZ8081_GetLinkSpeedDuplex, + .setLinkSpeedDuplex = PHY_KSZ8081_SetLinkSpeedDuplex, + .enableLoopback = PHY_KSZ8081_EnableLoopback}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_KSZ8081_Init(phy_handle_t *handle, const phy_config_t *config) +{ + uint32_t counter = PHY_READID_TIMEOUT_COUNT; + status_t result = kStatus_Success; + uint32_t regValue = 0; + + /* Init MDIO interface. */ + MDIO_Init(handle->mdioHandle); + + /* Assign phy address. */ + handle->phyAddr = config->phyAddr; + + /* Check PHY ID. */ + do + { + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + counter--; + } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); + + if (counter == 0U) + { + return kStatus_Fail; + } + + /* Reset PHY. */ + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { +#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + result = + MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, (regValue | PHY_CTL2_REFCLK_SELECT_MASK)); + if (result != kStatus_Success) + { + return result; + } +#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + + if (config->autoNeg) + { + /* Set the auto-negotiation then start it. */ + result = + MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK)); + if (result == kStatus_Success) + { + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* This PHY only supports 10/100M speed. */ + assert(config->speed <= kPHY_Speed100M); + + /* Disable isolate mode */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + regValue &= ~PHY_BCTL_ISOLATE_MASK; + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + if (result != kStatus_Success) + { + return result; + } + + /* Disable the auto-negotiation and set user-defined speed/duplex configuration. */ + result = PHY_KSZ8081_SetLinkSpeedDuplex(handle, config->speed, config->duplex); + } + } + return result; +} + +status_t PHY_KSZ8081_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data) +{ + return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data); +} + +status_t PHY_KSZ8081_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr) +{ + return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr); +} + +status_t PHY_KSZ8081_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) +{ + assert(status); + + status_t result; + uint32_t regValue; + + *status = false; + + /* Check auto negotiation complete. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, ®Value); + if (result == kStatus_Success) + { + if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) + { + *status = true; + } + } + return result; +} + +status_t PHY_KSZ8081_GetLinkStatus(phy_handle_t *handle, bool *status) +{ + assert(status); + + status_t result; + uint32_t regValue; + + /* Read the basic status register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, ®Value); + if (result == kStatus_Success) + { + if ((PHY_BSTATUS_LINKSTATUS_MASK & regValue) != 0U) + { + /* Link up. */ + *status = true; + } + else + { + /* Link down. */ + *status = false; + } + } + return result; +} + +status_t PHY_KSZ8081_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(!((speed == NULL) && (duplex == NULL))); + + status_t result; + uint32_t regValue; + uint32_t flag; + + /* Read the control register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL1_REG, ®Value); + if (result == kStatus_Success) + { + if (speed != NULL) + { + flag = regValue & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == flag) || (PHY_CTL1_100FULLDUPLEX_MASK == flag)) + { + *speed = kPHY_Speed100M; + } + else + { + *speed = kPHY_Speed10M; + } + } + + if (duplex != NULL) + { + flag = regValue & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == flag) || (PHY_CTL1_100FULLDUPLEX_MASK == flag)) + { + *duplex = kPHY_FullDuplex; + } + else + { + *duplex = kPHY_HalfDuplex; + } + } + } + return result; +} + +status_t PHY_KSZ8081_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) +{ + /* This PHY only supports 10/100M speed. */ + assert(speed <= kPHY_Speed100M); + + status_t result; + uint32_t regValue; + + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) + { + /* Disable the auto-negotiation and set according to user-defined configuration. */ + regValue &= ~PHY_BCTL_AUTONEG_MASK; + if (speed == kPHY_Speed100M) + { + regValue |= PHY_BCTL_SPEED0_MASK; + } + else + { + regValue &= ~PHY_BCTL_SPEED0_MASK; + } + if (duplex == kPHY_FullDuplex) + { + regValue |= PHY_BCTL_DUPLEX_MASK; + } + else + { + regValue &= ~PHY_BCTL_DUPLEX_MASK; + } + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + } + return result; +} + +status_t PHY_KSZ8081_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) +{ + /* This PHY only supports local/remote loopback and 10/100M speed. */ + assert(mode <= kPHY_RemoteLoop); + assert(speed <= kPHY_Speed100M); + + status_t result; + uint32_t regValue; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + if (speed == kPHY_Speed100M) + { + regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + } + else + { + /* Remote loopback only supports 100M full-duplex. */ + assert(speed == kPHY_Speed100M); + + regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + if (result != kStatus_Success) + { + return result; + } + /* Set the remote loopback bit. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, ®Value); + if (result == kStatus_Success) + { + return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, + (regValue | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) + { + regValue &= ~PHY_BCTL_LOOP_MASK; + return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, + (regValue | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, ®Value); + if (result == kStatus_Success) + { + return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, + (regValue & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} diff --git a/component/phy/device/phyksz8081/fsl_phyksz8081.h b/component/phy/device/phyksz8081/fsl_phyksz8081.h new file mode 100644 index 0000000..5b93c56 --- /dev/null +++ b/component/phy/device/phyksz8081/fsl_phyksz8081.h @@ -0,0 +1,163 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/***************************************************************************** + * PHY KSZ8081 driver change log + *****************************************************************************/ + +/*! +@page driver_log Driver Change Log + +@section phyksz8081 PHYKSZ8081 + The current PHYKSZ8081 driver version is 2.0.0. + + - 2.0.0 + - Initial version. +*/ + +#ifndef _FSL_PHYKSZ8081_H_ +#define _FSL_PHYKSZ8081_H_ + +#include "fsl_phy.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) + +/*! @brief PHY operations structure. */ +extern const phy_operations_t phyksz8081_ops; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize PHY. + * + * @param handle PHY device handle. + * @param config Pointer to structure of phy_config_t. + * @retval kStatus_Success PHY initialization succeeds + * @retval kStatus_Fail PHY initialization fails + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_Init(phy_handle_t *handle, const phy_config_t *config); + +/*! + * @brief PHY Write function. This function writes data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Gets the PHY auto-negotiation status. + * + * @param handle PHY device handle. + * @param status The auto-negotiation status of the PHY. + * - true the auto-negotiation is over. + * - false the auto-negotiation is on-going or not started. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status); + +/*! + * @brief Gets the PHY link status. + * + * @param handle PHY device handle. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY gets link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_GetLinkStatus(phy_handle_t *handle, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @brief This function gets the speed and duplex mode of PHY. User can give one of speed + * and duplex address paramter and set the other as NULL if only wants to get one of them. + * + * @param handle PHY device handle. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY gets link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex); + +/*! + * @brief Sets the PHY link speed and duplex. + * + * @param handle PHY device handle. + * @param speed Specified PHY link speed. + * @param duplex Specified PHY link duplex. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param handle PHY device handle. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * All loopback modes should not be set together, when one loopback mode is set + * another should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_KSZ8081_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHYKSZ8081_H_ */ diff --git a/component/phy/fsl_mdio.h b/component/phy/fsl_mdio.h new file mode 100644 index 0000000..4e4dd2d --- /dev/null +++ b/component/phy/fsl_mdio.h @@ -0,0 +1,128 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MDIO_H_ +#define _FSL_MDIO_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#if defined(MDIO_TIMEOUT_COUNT_NUMBER) && MDIO_TIMEOUT_COUNT_NUMBER +#define MDIO_TIMEOUT_COUNT MDIO_TIMEOUT_COUNT_NUMBER +#endif + +/*! @brief Defines the PHY status. */ +enum _mdio_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0), /*!< ENET PHY SMI visit timeout. */ +}; + +typedef struct _mdio_operations mdio_operations_t; + +/*! @brief MDIO resource. */ +typedef struct _mdio_resource +{ + void *base; /*!< ENET Ip register base. */ + uint32_t csrClock_Hz; /*!< ENET CSR clock. */ +} mdio_resource_t; + +/*! @brief MDIO handle. */ +typedef struct _mdio_handle +{ + mdio_resource_t resource; + const mdio_operations_t *ops; +} mdio_handle_t; + +/*! @brief Camera receiver operations. */ +struct _mdio_operations +{ + void (*mdioInit)(mdio_handle_t *handle); /*!< MDIO interface init. */ + status_t (*mdioWrite)(mdio_handle_t *handle, + uint32_t phyAddr, + uint32_t devAddr, + uint32_t data); /*!< MDIO write data. */ + status_t (*mdioRead)(mdio_handle_t *handle, + uint32_t phyAddr, + uint32_t devAddr, + uint32_t *dataPtr); /*!< MDIO read data. */ + status_t (*mdioWriteExt)(mdio_handle_t *handle, + uint32_t phyAddr, + uint32_t devAddr, + uint32_t data); /*!< MDIO write data. */ + status_t (*mdioReadExt)(mdio_handle_t *handle, + uint32_t phyAddr, + uint32_t devAddr, + uint32_t *dataPtr); /*!< MDIO read data. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif +/*! + * @name MDIO Driver + * @{ + */ + +/*! + * @brief MDIO Write function. This function write data over the SMI to + * the specified MDIO register. This function is called by all MDIO interfaces. + * + * @param handle MDIO device handle. + * @retval kStatus_Success MDIO write success + * @retval kStatus_MDIO_SMIVisitTimeout MDIO SMI visit time out + */ +static inline void MDIO_Init(mdio_handle_t *handle) +{ + handle->ops->mdioInit(handle); +} + +/*! + * @brief MDIO Write function. This function write data over the SMI to + * the specified MDIO register. This function is called by all MDIO interfaces. + * + * @param handle MDIO device handle. + * @param phyAddr MDIO PHY address handle. + * @param devAddr The PHY device register. + * @param data The data written to the MDIO register. + * @retval kStatus_Success MDIO write success + * @retval kStatus_MDIO_SMIVisitTimeout MDIO SMI visit time out + */ +static inline status_t MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data) +{ + return handle->ops->mdioWrite(handle, phyAddr, devAddr, data); +} + +/*! + * @brief MDIO Read function. This interface read data over the SMI from the + * specified MDIO register. This function is called by all MDIO interfaces. + * + * @param handle MDIO device handle. + * @param phyAddr MDIO PHY address handle. + * @param devAddr The PHY device register. + * @param dataPtr The address to store the data read from the MDIO register. + * @retval kStatus_Success MDIO read success + * @retval kStatus_MDIO_SMIVisitTimeout MDIO SMI visit time out + */ +static inline status_t MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr) +{ + return handle->ops->mdioRead(handle, phyAddr, devAddr, dataPtr); +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/component/phy/fsl_phy.h b/component/phy/fsl_phy.h new file mode 100644 index 0000000..101ddcb --- /dev/null +++ b/component/phy/fsl_phy.h @@ -0,0 +1,266 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_mdio.h" + +/*! @note The following PHY registers are the IEEE802.3 standard definition, same register and bit field may + have different names in various PHYs, but the feature they represent should be same or very similar. */ + +/*! @brief Defines the IEEE802.3 standard PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_AUTONEG_LINKPARTNER_REG 0x05U /*!< The PHY auto negotiation link partner ability register. */ +#define PHY_AUTONEG_EXPANSION_REG 0x06U /*!< The PHY auto negotiation expansion register. */ +#define PHY_1000BASET_CONTROL_REG 0x09U /*!< The PHY 1000BASE-T control register. */ +#define PHY_MMD_ACCESS_CONTROL_REG 0x0DU /*!< The PHY MMD access control register. */ +#define PHY_MMD_ACCESS_DATA_REG 0x0EU /*!< The PHY MMD access data register. */ + +/*! @brief Defines the mask flag in basic control register(Address 0x00). */ +#define PHY_BCTL_SPEED1_MASK 0x0040U /*!< The PHY speed bit mask(MSB).*/ +#define PHY_BCTL_ISOLATE_MASK 0x0400U /*!< The PHY isolate mask.*/ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED0_MASK 0x2000U /*!< The PHY speed bit mask(LSB). */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ + +/*! @brief Defines the mask flag in basic status register(Address 0x01). */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register(Address 0x04). */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_IEEE802_3_SELECTOR_MASK 0x001U /*!< The message type being sent by Auto-Nego.*/ + +/*! @brief Defines the mask flag in the 1000BASE-T control register(Address 0x09). */ +#define PHY_1000BASET_FULLDUPLEX_MASK 0x200U /*!< The PHY has the 1000M full duplex ability.*/ +#define PHY_1000BASET_HALFDUPLEX_MASK 0x100U /*!< The PHY has the 1000M half duplex ability.*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _phy_handle phy_handle_t; +/*! @brief Defines the PHY link speed. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M, /*!< ENET PHY 100M speed. */ + kPHY_Speed1000M /*!< ENET PHY 1000M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local/digital loopback. */ + kPHY_RemoteLoop, /*!< ENET PHY remote loopback. */ + kPHY_ExternalLoop, /*!< ENET PHY external loopback. */ +} phy_loop_t; + +/*! @brief Defines the PHY MMD data access mode. */ +typedef enum _phy_mmd_access_mode +{ + kPHY_MMDAccessNoPostIncrement = (1U << 14), /*!< ENET PHY MMD access data with no address post increment. */ + kPHY_MMDAccessRdWrPostIncrement = + (2U << 14), /*!< ENET PHY MMD access data with Read/Write address post increment. */ + kPHY_MMDAccessWrPostIncrement = (3U << 14), /*!< ENET PHY MMD access data with Write address post increment. */ +} phy_mmd_access_mode_t; + +/*! @brief Defines PHY configuration. */ +typedef struct _phy_config +{ + uint32_t phyAddr; /*!< PHY address. */ + phy_speed_t speed; /*!< PHY speed configuration. */ + phy_duplex_t duplex; /*!< PHY duplex configuration. */ + bool autoNeg; /*!< PHY auto-negotiation, true: enable, false: disable. */ + bool enableEEE; /*!< PHY Energy Efficient Ethernet. */ +} phy_config_t; + +/*! @brief PHY device operations. */ +typedef struct _phy_operations +{ + status_t (*phyInit)(phy_handle_t *handle, const phy_config_t *config); + status_t (*phyWrite)(phy_handle_t *handle, uint32_t phyReg, uint32_t data); + status_t (*phyRead)(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr); + status_t (*getAutoNegoStatus)(phy_handle_t *handle, bool *status); + status_t (*getLinkStatus)(phy_handle_t *handle, bool *status); + status_t (*getLinkSpeedDuplex)(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex); + status_t (*setLinkSpeedDuplex)(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex); + status_t (*enableLoopback)(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable); +} phy_operations_t; + +/*! @brief PHY device handle. */ + +struct _phy_handle +{ + uint32_t phyAddr; /*!< PHY address. */ + mdio_handle_t *mdioHandle; /*!< The MDIO handle used by the phy device, it is specified by device. */ + const phy_operations_t *ops; /*!< The device related operations. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize PHY. + * + * @param handle PHY device handle. + * @param config Pointer to structure of phy_config_t. + * @retval kStatus_Success PHY initialization succeeds + * @retval kStatus_Fail PHY initialization fails + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_Init(phy_handle_t *handle, const phy_config_t *config) +{ + return handle->ops->phyInit(handle, config); +} +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data) +{ + return handle->ops->phyWrite(handle, phyReg, data); +} + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr) +{ + return handle->ops->phyRead(handle, phyReg, dataPtr); +} + +/*! + * @brief Gets the PHY auto-negotiation status. + * + * @param handle PHY device handle. + * @param status The auto-negotiation status of the PHY. + * - true the auto-negotiation is over. + * - false the auto-negotiation is on-going or not started. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) +{ + return handle->ops->getAutoNegoStatus(handle, status); +} + +/*! + * @brief Gets the PHY link status. + * + * @param handle PHY device handle. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_GetLinkStatus(phy_handle_t *handle, bool *status) +{ + return handle->ops->getLinkStatus(handle, status); +} + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @brief This function gets the speed and duplex mode of PHY. User can give one of speed + * and duplex address paramter and set the other as NULL if only wants to get one of them. + * + * @param handle PHY device handle. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) +{ + return handle->ops->getLinkSpeedDuplex(handle, speed, duplex); +} + +/*! + * @brief Sets the PHY link speed and duplex. + * + * @param handle PHY device handle. + * @param speed Specified PHY link speed. + * @param duplex Specified PHY link duplex. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) +{ + return handle->ops->setLinkSpeedDuplex(handle, speed, duplex); +} + +/*! + * @brief Enable PHY loopcback mode. + * + * @param handle PHY device handle. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * All loopback modes should not be set together, when one loopback mode is set + * another should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +static inline status_t PHY_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) +{ + return handle->ops->enableLoopback(handle, mode, speed, enable); +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif diff --git a/component/phy/mdio/enet/fsl_enet_mdio.c b/component/phy/mdio/enet/fsl_enet_mdio.c new file mode 100644 index 0000000..d82afe7 --- /dev/null +++ b/component/phy/mdio/enet/fsl_enet_mdio.c @@ -0,0 +1,133 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_enet_mdio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void ENET_MDIO_Init(mdio_handle_t *handle); +static status_t ENET_MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data); +static status_t ENET_MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const mdio_operations_t enet_ops = {.mdioInit = ENET_MDIO_Init, + .mdioWrite = ENET_MDIO_Write, + .mdioRead = ENET_MDIO_Read, + .mdioWriteExt = NULL, + .mdioReadExt = NULL}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void ENET_MDIO_Init(mdio_handle_t *handle) +{ + mdio_resource_t *resource = (mdio_resource_t *)&handle->resource; + ENET_Type *base = (ENET_Type *)resource->base; + uint32_t instance = ENET_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + (void)CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI(base, resource->csrClock_Hz, false); +} + +static status_t ENET_MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data) +{ + mdio_resource_t *resource = (mdio_resource_t *)&handle->resource; + ENET_Type *base = (ENET_Type *)resource->base; + status_t result = kStatus_Success; +#ifdef MDIO_TIMEOUT_COUNT + uint32_t counter; +#endif + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, devAddr, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ +#ifdef MDIO_TIMEOUT_COUNT + for (counter = MDIO_TIMEOUT_COUNT; counter > 0U; counter--) + { + if (ENET_EIR_MII_MASK == (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)) + { + break; + } + } + /* Check for timeout. */ + if (0U == counter) + { + result = kStatus_PHY_SMIVisitTimeout; + } +#else + while (ENET_EIR_MII_MASK != (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)) + { + } +#endif + + /* Clear SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return result; +} + +static status_t ENET_MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr) +{ + assert(dataPtr); + + mdio_resource_t *resource = (mdio_resource_t *)&handle->resource; + ENET_Type *base = (ENET_Type *)resource->base; +#ifdef MDIO_TIMEOUT_COUNT + uint32_t counter; +#endif + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, devAddr, kENET_MiiReadValidFrame); + + /* Wait for SMI complete. */ +#ifdef MDIO_TIMEOUT_COUNT + for (counter = MDIO_TIMEOUT_COUNT; counter > 0U; counter--) + { + if (ENET_EIR_MII_MASK == (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)) + { + break; + } + } + /* Check for timeout. */ + if (0U == counter) + { + return kStatus_PHY_SMIVisitTimeout; + } +#else + while (ENET_EIR_MII_MASK != (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)) + { + } +#endif + + /* Get data from SMI register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} diff --git a/component/phy/mdio/enet/fsl_enet_mdio.h b/component/phy/mdio/enet/fsl_enet_mdio.h new file mode 100644 index 0000000..500985d --- /dev/null +++ b/component/phy/mdio/enet/fsl_enet_mdio.h @@ -0,0 +1,21 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ENET_MDIO_H_ +#define _FSL_ENET_MDIO_H_ + +#include "fsl_enet.h" +#include "fsl_mdio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief ENET MDIO operations structure. */ +extern const mdio_operations_t enet_ops; + +#endif diff --git a/source/lwipopts.h b/source/lwipopts.h new file mode 100644 index 0000000..5f541bc --- /dev/null +++ b/source/lwipopts.h @@ -0,0 +1,336 @@ +/** + ****************************************************************************** + * @file lwipopts.h + * This file is based on \src\include\lwip\opt.h + ****************************************************************************** + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#if USE_RTOS + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#define SYS_LIGHTWEIGHT_PROT 1 + +/** + * NO_SYS==0: Use RTOS + */ +#define NO_SYS 0 +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 1 +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 1 + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#define LWIP_SO_RCVTIMEO 1 + +#else +/** + * NO_SYS==1: Bare metal lwIP + */ +#define NO_SYS 1 +/** + * LWIP_NETCONN==0: Disable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 0 +/** + * LWIP_SOCKET==0: Disable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 0 + +#endif + +/* ---------- Core locking ---------- */ + +#define LWIP_TCPIP_CORE_LOCKING 1 + +void sys_lock_tcpip_core(void); +#define LOCK_TCPIP_CORE() sys_lock_tcpip_core() + +void sys_unlock_tcpip_core(void); +#define UNLOCK_TCPIP_CORE() sys_unlock_tcpip_core() + +void sys_check_core_locking(void); +#define LWIP_ASSERT_CORE_LOCKED() sys_check_core_locking() + +void sys_mark_tcpip_thread(void); +#define LWIP_MARK_TCPIP_THREAD() sys_mark_tcpip_thread() + +/* ---------- Memory options ---------- */ +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE (22 * 1024) +#endif + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 15 +#endif +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 6 +#endif +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 10 +#endif +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 6 +#endif +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 22 +#endif +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT 10 +#endif + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 9 +#endif + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +/* Default value is defined in lwip\src\include\lwip\opt.h as + * LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN)*/ + +/* ---------- TCP options ---------- */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +#ifndef TCP_TTL +#define TCP_TTL 255 +#endif + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ 0 +#endif + +/* TCP Maximum segment size. */ +#ifndef TCP_MSS +#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */ +#endif + +/* TCP sender buffer space (bytes). */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (6 * TCP_MSS) // 2 +#endif + +/* TCP sender buffer space (pbufs). This must be at least = 2 * + TCP_SND_BUF/TCP_MSS for things to work. */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN (3 * TCP_SND_BUF) / TCP_MSS // 6 +#endif + +/* TCP receive window. */ +#ifndef TCP_WND +#define TCP_WND (2 * TCP_MSS) +#endif + +/* Enable backlog*/ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 1 +#endif + +/* ---------- Network Interfaces options ---------- */ +/* Support netif api (in netifapi.c). */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 1 +#endif + +/* ---------- ICMP options ---------- */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/* ---------- RAW options ---------- */ +#if !defined LWIP_RAW +#define LWIP_RAW 1 +#endif + +/* ---------- DHCP options ---------- */ +/* Enable DHCP module. */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 1 +#endif + +/* ---------- UDP options ---------- */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif +#ifndef UDP_TTL +#define UDP_TTL 255 +#endif + +/* ---------- Statistics options ---------- */ +#ifndef LWIP_STATS +#define LWIP_STATS 0 +#endif +#ifndef LWIP_PROVIDE_ERRNO +#define LWIP_PROVIDE_ERRNO 1 +#endif + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ + +/* +Some MCU allow computing and verifying the IP, UDP, TCP and ICMP checksums by hardware: + - To use this feature let the following define uncommented. + - To disable it and process by CPU comment the the checksum. +*/ +//#define CHECKSUM_BY_HARDWARE + +#ifdef CHECKSUM_BY_HARDWARE +/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 0 +/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 0 +/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 0 +/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 0 +/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 0 +/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 0 +#else +/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 1 +/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 1 +/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 1 +/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 1 +/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 1 +/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 3000 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 3 +#endif + +/* + ------------------------------------ + ---------- Debugging options ---------- + ------------------------------------ +*/ + +#define LWIP_DEBUG + +#ifdef LWIP_DEBUG +#define U8_F "c" +#define S8_F "c" +#define X8_F "02x" +#define U16_F "u" +#define S16_F "d" +#define X16_F "x" +#define U32_F "u" +#define S32_F "d" +#define X32_F "x" +#define SZT_F "u" +#endif + +#define TCPIP_MBOX_SIZE 32 +#define TCPIP_THREAD_STACKSIZE 1024 +#define TCPIP_THREAD_PRIO 8 + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_RAW_RECVMBOX_SIZE 12 + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_UDP_RECVMBOX_SIZE 12 + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_TCP_RECVMBOX_SIZE 12 + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#define DEFAULT_ACCEPTMBOX_SIZE 12 + +#if (LWIP_DNS || LWIP_IGMP || LWIP_IPV6) && !defined(LWIP_RAND) +/* When using IGMP or IPv6, LWIP_RAND() needs to be defined to a random-function returning an u32_t random value*/ +#include "lwip/arch.h" +u32_t lwip_rand(void); +#define LWIP_RAND() lwip_rand() +#endif + +#endif /* __LWIPOPTS_H__ */ + +/*****END OF FILE****/