603 lines
23 KiB
C
603 lines
23 KiB
C
/*
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_cache.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
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#endif
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#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
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#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
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#define L2CACHE_8WAYS_MASK 0xFFU
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#define L2CACHE_16WAYS_MASK 0xFFFFU
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#define L2CACHE_SMALLWAYS_NUM 8U
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#define L2CACHE_1KBCOVERTOB 1024U
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#define L2CACHE_SAMLLWAYS_SIZE 16U
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#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Set for all ways and waiting for the operation finished.
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* This is provided for all the background operations.
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*
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* @param auxCtlReg The auxiliary control register.
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* @param regAddr The register address to be operated.
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*/
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static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
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/*!
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* @brief Invalidates the Level 2 cache line by physical address.
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* This function invalidates a cache line by physcial address.
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*
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* @param address The physical addderss of the cache.
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* The format of the address shall be :
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* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
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* Tag | index | 0
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* Note: the physical address shall be aligned to the line size - 32B (256 bit).
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* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
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* If the input address is not aligned, it will be changed to 32-byte aligned address.
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* The n is varies according to the index width.
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* @return The actual 32-byte aligned physical address be operated.
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*/
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static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
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/*!
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* @brief Cleans the Level 2 cache line based on the physical address.
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* This function cleans a cache line based on a physcial address.
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*
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* @param address The physical addderss of the cache.
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* The format of the address shall be :
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* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
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* Tag | index | 0
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* Note: the physical address shall be aligned to the line size - 32B (256 bit).
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* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
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* If the input address is not aligned, it will be changed to 32-byte aligned address.
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* The n is varies according to the index width.
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* @return The actual 32-byte aligned physical address be operated.
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*/
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static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
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/*!
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* @brief Cleans and invalidates the Level 2 cache line based on the physical address.
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* This function cleans and invalidates a cache line based on a physcial address.
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*
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* @param address The physical addderss of the cache.
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* The format of the address shall be :
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* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
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* Tag | index | 0
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* Note: the physical address shall be aligned to the line size - 32B (256 bit).
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* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
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* If the input address is not aligned, it will be changed to 32-byte aligned address.
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* The n is varies according to the index width.
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* @return The actual 32-byte aligned physical address be operated.
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*/
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static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
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/*!
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* @brief Gets the number of the Level 2 cache and the way size.
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* This function cleans and invalidates a cache line based on a physcial address.
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*
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* @param num_ways The number of the cache way.
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* @param size_way The way size.
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*/
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static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
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{
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uint16_t mask = L2CACHE_8WAYS_MASK;
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uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
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/* Check the ways used at first. */
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if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
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{
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mask = L2CACHE_16WAYS_MASK;
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}
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/* Set the opeartion for all ways/entries of the cache. */
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*(uint32_t *)regAddr = mask;
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/* Waiting for until the operation is complete. */
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while ((*(volatile uint32_t *)regAddr & mask) && timeout)
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{
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__ASM("nop");
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timeout--;
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}
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}
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static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
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{
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/* Align the address first. */
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address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
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/* Invalidate the cache line by physical address. */
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L2CACHEC->REG7_INV_PA = address;
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return address;
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}
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static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
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{
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/* Align the address first. */
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address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
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/* Invalidate the cache line by physical address. */
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L2CACHEC->REG7_CLEAN_PA = address;
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return address;
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}
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static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
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{
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/* Align the address first. */
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address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
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/* Clean and invalidate the cache line by physical address. */
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L2CACHEC->REG7_CLEAN_INV_PA = address;
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return address;
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}
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static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
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{
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assert(num_ways);
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assert(size_way);
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uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
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L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
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uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
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L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
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*num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
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if (!size)
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{
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/* 0 internally mapped to the same size as 1 - 16KB.*/
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size += 1;
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}
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*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
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}
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/*!
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* brief Initializes the level 2 cache controller module.
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*
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* param config Pointer to configuration structure. See "l2cache_config_t".
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*/
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void L2CACHE_Init(l2cache_config_t *config)
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{
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assert(config);
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uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
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uint8_t count;
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uint32_t auxReg = 0;
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/*The aux register must be configured when the cachec is disabled
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* So disable first if the cache controller is enabled.
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*/
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if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
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{
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L2CACHE_Disable();
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}
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/* Unlock all entries. */
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if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
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{
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waysNum = 0xFFFFU;
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}
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for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
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{
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L2CACHE_LockdownByWayEnable(count, waysNum, false);
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}
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/* Set the ways and way-size etc. */
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auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
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L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
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L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
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L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
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L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
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L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
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L2CACHEC->REG1_AUX_CONTROL = auxReg;
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/* Set the tag/data ram latency. */
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if (config->lateConfig)
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{
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uint32_t data = 0;
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/* Tag latency. */
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data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
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L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
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L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
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L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
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L2CACHEC->REG1_TAG_RAM_CONTROL = data;
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/* Data latency. */
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data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
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L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
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L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
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L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
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L2CACHEC->REG1_DATA_RAM_CONTROL = data;
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}
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}
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/*!
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* brief Gets an available default settings for the cache controller.
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*
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* This function initializes the cache controller configuration structure with default settings.
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* The default values are:
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* code
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* config->waysNum = kL2CACHE_8ways;
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* config->waySize = kL2CACHE_32KbSize;
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* config->repacePolicy = kL2CACHE_Roundrobin;
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* config->lateConfig = NULL;
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* config->istrPrefetchEnable = false;
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* config->dataPrefetchEnable = false;
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* config->nsLockdownEnable = false;
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* config->writeAlloc = kL2CACHE_UseAwcache;
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* endcode
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* param config Pointer to the configuration structure.
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*/
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void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
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{
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assert(config);
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/* Initializes the configure structure to zero. */
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memset(config, 0, sizeof(*config));
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uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
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L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
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uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
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L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
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/* Get the default value */
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config->wayNum = (l2cache_way_num_t)number;
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config->waySize = (l2cache_way_size)size;
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config->repacePolicy = kL2CACHE_Roundrobin;
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config->lateConfig = NULL;
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config->istrPrefetchEnable = false;
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config->dataPrefetchEnable = false;
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config->nsLockdownEnable = false;
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config->writeAlloc = kL2CACHE_UseAwcache;
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}
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/*!
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* brief Enables the level 2 cache controller.
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* This function enables the cache controller. Must be written using a secure access.
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* If write with a Non-secure access will cause a DECERR response.
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*
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*/
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void L2CACHE_Enable(void)
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{
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/* Invalidate first. */
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L2CACHE_Invalidate();
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/* Enable the level 2 cache controller. */
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L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
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}
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/*!
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* brief Disables the level 2 cache controller.
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* This function disables the cache controller. Must be written using a secure access.
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* If write with a Non-secure access will cause a DECERR response.
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*
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*/
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void L2CACHE_Disable(void)
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{
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/* First CleanInvalidate all enties in the cache. */
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L2CACHE_CleanInvalidate();
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/* Disable the level 2 cache controller. */
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L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
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/* DSB - data sync barrier.*/
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__DSB();
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}
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/*!
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* brief Invalidates the Level 2 cache.
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* This function invalidates all entries in cache.
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*
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*/
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void L2CACHE_Invalidate(void)
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{
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/* Invalidate all entries in cache. */
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L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
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/* Cache sync. */
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L2CACHEC->REG7_CACHE_SYNC = 0;
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}
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/*!
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* brief Cleans the level 2 cache controller.
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* This function cleans all entries in the level 2 cache controller.
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*
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*/
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void L2CACHE_Clean(void)
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{
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/* Clean all entries of the cache. */
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L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
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/* Cache sync. */
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L2CACHEC->REG7_CACHE_SYNC = 0;
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}
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/*!
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* brief Cleans and invalidates the level 2 cache controller.
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* This function cleans and invalidates all entries in the level 2 cache controller.
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*
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*/
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void L2CACHE_CleanInvalidate(void)
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{
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/* Clean all entries of the cache. */
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L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
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/* Cache sync. */
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L2CACHEC->REG7_CACHE_SYNC = 0;
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}
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/*!
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* brief Invalidates the Level 2 cache lines in the range of two physical addresses.
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* This function invalidates all cache lines between two physical addresses.
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*
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* param address The start address of the memory to be invalidated.
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* param size_byte The memory size.
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* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L2 line size if startAddr
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* is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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uint32_t endAddr = address + size_byte;
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/* Invalidate addresses in the range. */
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while (address < endAddr)
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{
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address = L2CACHE_InvalidateLineByAddr(address);
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/* Update the size. */
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address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
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}
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/* Cache sync. */
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L2CACHEC->REG7_CACHE_SYNC = 0;
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}
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/*!
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* brief Cleans the Level 2 cache lines in the range of two physical addresses.
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* This function cleans all cache lines between two physical addresses.
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*
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* param address The start address of the memory to be cleaned.
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* param size_byte The memory size.
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* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L2 line size if startAddr
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* is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
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{
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uint32_t num_ways = 0;
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uint32_t size_way = 0;
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uint32_t endAddr = address + size_byte;
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/* Get the number and size of the cache way. */
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L2CACHE_GetWayNumSize(&num_ways, &size_way);
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/* Check if the clean size is over the cache size. */
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if ((endAddr - address) > num_ways * size_way)
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{
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L2CACHE_Clean();
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return;
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}
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/* Clean addresses in the range. */
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while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
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{
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/* Clean the address in the range. */
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address = L2CACHE_CleanLineByAddr(address);
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address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
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}
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L2CACHEC->REG7_CACHE_SYNC = 0;
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}
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/*!
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* brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
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* This function cleans and invalidates all cache lines between two physical addresses.
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*
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* param address The start address of the memory to be cleaned and invalidated.
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* param size_byte The memory size.
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* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
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* The startAddr here will be forced to align to L2 line size if startAddr
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* is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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uint32_t num_ways = 0;
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uint32_t size_way = 0;
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uint32_t endAddr = address + size_byte;
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/* Get the number and size of the cache way. */
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L2CACHE_GetWayNumSize(&num_ways, &size_way);
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/* Check if the clean size is over the cache size. */
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if ((endAddr - address) > num_ways * size_way)
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{
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L2CACHE_CleanInvalidate();
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return;
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}
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/* Clean addresses in the range. */
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while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
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{
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/* Clean the address in the range. */
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address = L2CACHE_CleanInvalidateLineByAddr(address);
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address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
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}
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L2CACHEC->REG7_CACHE_SYNC = 0;
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}
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/*!
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* brief Enables or disables to lock down the data and instruction by way.
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* This function locks down the cached instruction/data by way and prevent the adresses from
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* being allocated and prevent dara from being evicted out of the level 2 cache.
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* But the normal cache maintenance operations that invalidate, clean or clean
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* and validate cache contents affect the locked-down cache lines as normal.
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*
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* param masterId The master id, range from 0 ~ 7.
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* param mask The ways to be enabled or disabled to lockdown.
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* each bit in value is related to each way of the cache. for example:
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* value: bit 0 ------ way 0.
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* value: bit 1 ------ way 1.
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* --------------------------
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* value: bit 15 ------ way 15.
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* Note: please make sure the value setting is align with your supported ways.
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* param enable True enable the lockdown, false to disable the lockdown.
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*/
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void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
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|
{
|
|
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
|
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
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num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
|
|
|
|
assert(mask < (1U << num_ways));
|
|
assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
|
|
|
|
uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
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|
uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
|
|
|
|
if (enable)
|
|
{
|
|
/* Data lockdown. */
|
|
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
|
|
/* Instruction lockdown. */
|
|
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
|
|
}
|
|
else
|
|
{
|
|
/* Data lockdown. */
|
|
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
|
|
/* Instruction lockdown. */
|
|
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
|
|
}
|
|
}
|
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
|
|
|
/*!
|
|
* brief Invalidate cortex-m7 L1 instruction cache by range.
|
|
*
|
|
* param address The start address of the memory to be invalidated.
|
|
* param size_byte The memory size.
|
|
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
|
* The startAddr here will be forced to align to L1 I-cache line size if
|
|
* startAddr is not aligned. For the size_byte, application should make sure the
|
|
* alignment or make sure the right operation order if the size_byte is not aligned.
|
|
*/
|
|
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
|
|
{
|
|
#if (__DCACHE_PRESENT == 1U)
|
|
uint32_t addr = address & ~((uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1U);
|
|
uint32_t align_len = address - addr;
|
|
int32_t size = (int32_t)size_byte + (int32_t)align_len;
|
|
|
|
__DSB();
|
|
while (size > 0)
|
|
{
|
|
SCB->ICIMVAU = addr;
|
|
addr += (uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
|
|
size -= (int32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
|
|
}
|
|
__DSB();
|
|
__ISB();
|
|
#endif
|
|
}
|
|
|
|
/*!
|
|
* brief Invalidates all instruction caches by range.
|
|
*
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
|
*
|
|
* param address The physical address.
|
|
* param size_byte size of the memory to be invalidated.
|
|
* note address and size should be aligned to cache line size
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
|
*/
|
|
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
|
{
|
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
|
L2CACHE_InvalidateByRange(address, size_byte);
|
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
|
|
|
L1CACHE_InvalidateICacheByRange(address, size_byte);
|
|
}
|
|
|
|
/*!
|
|
* brief Invalidates all data caches by range.
|
|
*
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
|
*
|
|
* param address The physical address.
|
|
* param size_byte size of the memory to be invalidated.
|
|
* note address and size should be aligned to cache line size
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
|
*/
|
|
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
|
{
|
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
|
L2CACHE_InvalidateByRange(address, size_byte);
|
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
|
L1CACHE_InvalidateDCacheByRange(address, size_byte);
|
|
}
|
|
|
|
/*!
|
|
* brief Cleans all data caches by range.
|
|
*
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
|
*
|
|
* param address The physical address.
|
|
* param size_byte size of the memory to be cleaned.
|
|
* note address and size should be aligned to cache line size
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
|
*/
|
|
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
|
{
|
|
L1CACHE_CleanDCacheByRange(address, size_byte);
|
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
|
L2CACHE_CleanByRange(address, size_byte);
|
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
|
}
|
|
|
|
/*!
|
|
* brief Cleans and Invalidates all data caches by range.
|
|
*
|
|
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
|
*
|
|
* param address The physical address.
|
|
* param size_byte size of the memory to be cleaned and invalidated.
|
|
* note address and size should be aligned to cache line size
|
|
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
|
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
|
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
|
*/
|
|
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
|
{
|
|
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
|
|
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
|
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
|
L2CACHE_CleanInvalidateByRange(address, size_byte);
|
|
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
|
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
|
}
|