134 lines
4.2 KiB
C
134 lines
4.2 KiB
C
/*
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_enet_mdio.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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static void ENET_MDIO_Init(mdio_handle_t *handle);
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static status_t ENET_MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data);
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static status_t ENET_MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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const mdio_operations_t enet_ops = {.mdioInit = ENET_MDIO_Init,
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.mdioWrite = ENET_MDIO_Write,
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.mdioRead = ENET_MDIO_Read,
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.mdioWriteExt = NULL,
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.mdioReadExt = NULL};
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void ENET_MDIO_Init(mdio_handle_t *handle)
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{
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mdio_resource_t *resource = (mdio_resource_t *)&handle->resource;
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ENET_Type *base = (ENET_Type *)resource->base;
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uint32_t instance = ENET_GetInstance(base);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Set SMI first. */
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(void)CLOCK_EnableClock(s_enetClock[instance]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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ENET_SetSMI(base, resource->csrClock_Hz, false);
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}
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static status_t ENET_MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data)
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{
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mdio_resource_t *resource = (mdio_resource_t *)&handle->resource;
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ENET_Type *base = (ENET_Type *)resource->base;
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status_t result = kStatus_Success;
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#ifdef MDIO_TIMEOUT_COUNT
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uint32_t counter;
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#endif
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/* Clear the SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI write command. */
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ENET_StartSMIWrite(base, phyAddr, devAddr, kENET_MiiWriteValidFrame, data);
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/* Wait for SMI complete. */
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#ifdef MDIO_TIMEOUT_COUNT
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for (counter = MDIO_TIMEOUT_COUNT; counter > 0U; counter--)
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{
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if (ENET_EIR_MII_MASK == (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
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{
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break;
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}
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}
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/* Check for timeout. */
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if (0U == counter)
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{
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result = kStatus_PHY_SMIVisitTimeout;
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}
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#else
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while (ENET_EIR_MII_MASK != (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
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{
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}
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#endif
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/* Clear SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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return result;
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}
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static status_t ENET_MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr)
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{
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assert(dataPtr);
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mdio_resource_t *resource = (mdio_resource_t *)&handle->resource;
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ENET_Type *base = (ENET_Type *)resource->base;
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#ifdef MDIO_TIMEOUT_COUNT
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uint32_t counter;
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#endif
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/* Clear the SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI read command operation. */
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ENET_StartSMIRead(base, phyAddr, devAddr, kENET_MiiReadValidFrame);
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/* Wait for SMI complete. */
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#ifdef MDIO_TIMEOUT_COUNT
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for (counter = MDIO_TIMEOUT_COUNT; counter > 0U; counter--)
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{
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if (ENET_EIR_MII_MASK == (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
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{
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break;
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}
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}
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/* Check for timeout. */
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if (0U == counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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#else
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while (ENET_EIR_MII_MASK != (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
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{
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}
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#endif
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/* Get data from SMI register. */
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*dataPtr = ENET_ReadSMIData(base);
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/* Clear SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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return kStatus_Success;
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}
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