156 lines
7.5 KiB
C
156 lines
7.5 KiB
C
/* 2015 Petteri Aimonen <jpa@git.mail.kapsi.fi>
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* Public domain. */
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#ifndef ARM_ETM_H
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#define ARM_ETM_H
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#include "core_cm4.h"
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/* ETM Peripheral Register definitions.
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* See here for register documentation:
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0014q/Chdfiagc.html
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*
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* Not all features are supported on Cortex-M3, see here for details:
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337i/CHDBGEED.html
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*
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* The ETM peripheral has a lot of registers, but these are the main ones:
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* - LAR: Allow write access to other ETM registers
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* - CR: Enable/disable tracing
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* - TRIGGER: Select tracing trigger event
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* - SR: Current status
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* - TECR1 Select areas of code where to enable trace
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* - TECR2 Select comparator for trace enable
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* - TEEVR Select event for trace enable
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*/
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typedef struct
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{
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__IO uint32_t CR; /* Main Control Register */
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__IO uint32_t CCR; /* Configuration Code Register */
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__IO uint32_t TRIGGER; /* Trigger Event */
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__IO uint32_t ASICCR; /* ASIC Control Register */
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__IO uint32_t SR; /* ETM Status Register */
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__IO uint32_t SCR; /* System Configuration Register */
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__IO uint32_t TSSCR; /* TraceEnable Start/Stop Control Register */
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__IO uint32_t TECR2; /* TraceEnable Control 2 */
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__IO uint32_t TEEVR; /* TraceEnable Event Register */
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__IO uint32_t TECR1; /* TraceEnable Control 1 */
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__IO uint32_t FFRR; /* FIFOFULL Region Register */
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__IO uint32_t FFLR; /* FIFOFULL Level Register */
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__IO uint32_t VDEVR; /* ViewData Event Register */
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__IO uint32_t VDCR1; /* ViewData Control 1 */
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__IO uint32_t VDCR2; /* ViewData Control 2 */
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__IO uint32_t VDCR3; /* ViewData Control 3 */
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__IO uint32_t ACVR[16]; /* Address Comparator Value Registers */
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__IO uint32_t ACTR[16]; /* Address Comparator Access Type Registers */
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__IO uint32_t DCVR[16]; /* Data Comparator Value Registers */
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__IO uint32_t DCMR[16]; /* Data Comparator Mask Registers */
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__IO uint32_t CNTRLDVR[4]; /* Counter Reload Value Registers */
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__IO uint32_t CNTENR[4]; /* Counter Enable Registers */
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__IO uint32_t CNTRLDEVR[4]; /* Counter Reload Event Registers */
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__IO uint32_t CNTVR[4]; /* Counter Value Registers */
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__IO uint32_t SQabEVR[6]; /* Sequencer State Transition Event Registers */
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__IO uint32_t RESERVED0;
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__IO uint32_t SQR; /* Current Sequencer State Register */
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__IO uint32_t EXTOUTEVR[4]; /* External Output Event Registers */
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__IO uint32_t CIDCVR[3]; /* Context ID Comparator Value Registers */
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__IO uint32_t CIDCMR; /* Context ID Comparator Mask Register */
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__IO uint32_t IMPL[8]; /* Implementation specific registers */
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__IO uint32_t SYNCFR; /* Synchronization Frequency Register */
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__IO uint32_t IDR; /* ETM ID Register */
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__IO uint32_t CCER; /* Configuration Code Extension Register */
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__IO uint32_t EXTINSELR; /* Extended External Input Selection Register */
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__IO uint32_t TESSEICR; /* TraceEnable Start/Stop EmbeddedICE Control Register */
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__IO uint32_t EIBCR; /* EmbeddedICE Behavior Control Register */
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__IO uint32_t TSEVR; /* Timestamp Event Register, ETMv3.5 */
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__IO uint32_t AUXCR; /* Auxiliary Control Register, ETMv3.5 */
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__IO uint32_t TRACEIDR; /* CoreSight Trace ID Register */
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__IO uint32_t RESERVED1;
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__IO uint32_t IDR2; /* ETM ID Register 2 */
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__IO uint32_t RESERVED2[13];
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__IO uint32_t VMIDCVR; /* VMID Comparator Value Register, ETMv3.5 */
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__IO uint32_t RESERVED3[47];
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__IO uint32_t OSLAR; /* OS Lock Access Register */
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__IO uint32_t OSLSR; /* OS Lock Status Register */
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__IO uint32_t OSSRR; /* OS Save and Restore Register */
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__IO uint32_t RESERVED4;
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__IO uint32_t PDCR; /* Power Down Control Register, ETMv3.5 */
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__IO uint32_t PDSR; /* Device Power-Down Status Register */
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__IO uint32_t RESERVED5[762];
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__IO uint32_t ITCTRL; /* Integration Mode Control Register */
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__IO uint32_t RESERVED6[39];
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__IO uint32_t CLAIMSET; /* Claim Tag Set Register */
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__IO uint32_t CLAIMCLR; /* Claim Tag Clear Register */
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__IO uint32_t RESERVED7[2];
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__IO uint32_t LAR; /* Lock Access Register */
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__IO uint32_t LSR; /* Lock Status Register */
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__IO uint32_t AUTHSTATUS; /* Authentication Status Register */
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__IO uint32_t RESERVED8[3];
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__IO uint32_t DEVID; /* CoreSight Device Configuration Register */
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__IO uint32_t DEVTYPE; /* CoreSight Device Type Register */
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__IO uint32_t PIDR4; /* Peripheral ID4 */
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__IO uint32_t PIDR5; /* Peripheral ID5 */
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__IO uint32_t PIDR6; /* Peripheral ID6 */
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__IO uint32_t PIDR7; /* Peripheral ID7 */
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__IO uint32_t PIDR0; /* Peripheral ID0 */
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__IO uint32_t PIDR1; /* Peripheral ID1 */
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__IO uint32_t PIDR2; /* Peripheral ID2 */
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__IO uint32_t PIDR3; /* Peripheral ID3 */
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__IO uint32_t CIDR0; /* Component ID0 */
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__IO uint32_t CIDR1; /* Component ID1 */
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__IO uint32_t CIDR2; /* Component ID2 */
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__IO uint32_t CIDR3; /* Component ID3 */
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} ETM_Type;
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#define ETM_CR_POWERDOWN 0x00000001
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#define ETM_CR_MONITORCPRT 0x00000002
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#define ETM_CR_TRACE_DATA 0x00000004
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#define ETM_CR_TRACE_ADDR 0x00000008
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#define ETM_CR_PORTSIZE_1BIT 0x00200000
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#define ETM_CR_PORTSIZE_2BIT 0x00200010
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#define ETM_CR_PORTSIZE_4BIT 0x00000000
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#define ETM_CR_PORTSIZE_8BIT 0x00000010
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#define ETM_CR_PORTSIZE_16BIT 0x00000020
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#define ETM_CR_STALL_PROCESSOR 0x00000080
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#define ETM_CR_BRANCH_OUTPUT 0x00000100
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#define ETM_CR_DEBUGREQ 0x00000200
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#define ETM_CR_PROGRAMMING 0x00000400
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#define ETM_CR_ETMEN 0x00000800
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#define ETM_CR_CYCLETRACE 0x00001000
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#define ETM_CR_CONTEXTID_8BIT 0x00004000
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#define ETM_CR_CONTEXTID_16BIT 0x00008000
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#define ETM_CR_CONTEXTID_32BIT 0x0000C000
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#define ETM_CR_CONTEXTID_8BIT 0x00004000
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#define ETM_CR_PORTMODE_ONCHIP 0x00000000
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#define ETM_CR_PORTMODE_2_1 0x00010000
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#define ETM_CR_PORTMODE_IMPL 0x00030000
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#define ETM_CR_PORTMODE_1_1 0x00002000
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#define ETM_CR_PORTMODE_1_2 0x00022000
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#define ETM_CR_PORTMODE_1_3 0x00012000
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#define ETM_CR_PORTMODE_1_4 0x00032000
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#define ETM_CR_SUPPRESS_DATA 0x00040000
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#define ETM_CR_FILTER_CPRT 0x00080000
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#define ETM_CR_DATA_ONLY 0x00100000
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#define ETM_CR_BLOCK_DEBUGGER 0x00400000
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#define ETM_CR_BLOCK_SOFTWARE 0x00800000
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#define ETM_CR_ACCESS 0x01000000
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#define ETM_CR_PROCSEL_Pos 25
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#define ETM_CR_TIMESTAMP 0x10000000
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#define ETM_CR_VMID 0x40000000
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#define ETM_SR_PROGSTATUS 0x00000002
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#define ETM_SR_TRIGSTATUS 0x00000008
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#define ETM_TECR1_EXCLUDE 0x01000000
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#define ETM_TECR1_TSSEN 0x02000000
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#define ETM_FFRR_EXCLUDE 0x01000000
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#define ETM_LAR_KEY 0xC5ACCE55
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#define ETM_TraceMode() ETM->CR &= ~ETM_CR_PROGRAMMING
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#define ETM_SetupMode() ETM->CR |= ETM_CR_PROGRAMMING
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#define ETM_BASE 0xE0041000
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#define ETM ((ETM_Type*)ETM_BASE)
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#endif |