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STM32H750VB_Bootloader
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Updated HAL library.

This commit is contained in:
imi415 2020-12-21 00:04:43 +08:00
parent e97b684222
commit 8a92014665
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
203 changed files with 194592 additions and 5999 deletions
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56
CMakeLists.txt
View File

@ -1,56 +0,0 @@
#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE!
SET(CMAKE_SYSTEM_NAME Generic)
SET(CMAKE_SYSTEM_VERSION 1)
cmake_minimum_required(VERSION 3.7)
# specify cross compilers and tools
SET(CMAKE_C_COMPILER_WORKS 1)
SET(CMAKE_C_COMPILER arm-none-eabi-gcc)
SET(CMAKE_CXX_COMPILER_WORKS 1)
SET(CMAKE_CXX_COMPILER arm-none-eabi-g++)
set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
set(CMAKE_AR arm-none-eabi-ar)
set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
set(CMAKE_OBJDUMP arm-none-eabi-objdump)
set(SIZE arm-none-eabi-size)
SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32H750VBTx_FLASH.ld)
#Uncomment for hardware floating point
SET(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv5-d16")
add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1)
#Uncomment for software floating point
#SET(FPU_FLAGS "-mfloat-abi=soft")
SET(COMMON_FLAGS
"-mcpu=cortex-m7 ${FPU_FLAGS} -mthumb -mthumb-interwork -ffunction-sections -fdata-sections \
-g -fno-common -fmessage-length=0 -specs=nosys.specs -specs=nano.specs")
SET(CMAKE_CXX_FLAGS_INIT "${COMMON_FLAGS} -std=c++11")
SET(CMAKE_C_FLAGS_INIT "${COMMON_FLAGS} -std=gnu99")
SET(CMAKE_EXE_LINKER_FLAGS_INIT "-Wl,-gc-sections,--print-memory-usage -T ${LINKER_SCRIPT}")
PROJECT(STM32H750VB_Bootloader C CXX ASM)
set(CMAKE_CXX_STANDARD 11)
#add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1)
add_definitions(-D__weak=__attribute__\(\(weak\)\) -D__packed=__attribute__\(\(__packed__\)\) -DUSE_HAL_DRIVER -DSTM32H750xx)
file(GLOB_RECURSE SOURCES "USB_DEVICE/*.*" "Middlewares/*.*" "startup/*.*" "Drivers/*.*" "Core/*.*")
include_directories(Core/Inc Drivers/STM32H7xx_HAL_Driver/Inc Drivers/STM32H7xx_HAL_Driver/Inc/Legacy Drivers/CMSIS/Device/ST/STM32H7xx/Include Drivers/CMSIS/Include USB_DEVICE/App USB_DEVICE/Target Middlewares/ST/STM32_USB_Device_Library/Core/Inc Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc)
add_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
set(CMAKE_EXE_LINKER_FLAGS
"${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map")
set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)
set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)
add_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

56
CMakeLists_template.txt
View File

@ -1,56 +0,0 @@
#${templateWarning}
SET(CMAKE_SYSTEM_NAME Generic)
SET(CMAKE_SYSTEM_VERSION 1)
cmake_minimum_required(VERSION 3.7)
# specify cross compilers and tools
SET(CMAKE_C_COMPILER_WORKS 1)
SET(CMAKE_C_COMPILER arm-none-eabi-gcc)
SET(CMAKE_CXX_COMPILER_WORKS 1)
SET(CMAKE_CXX_COMPILER arm-none-eabi-g++)
set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
set(CMAKE_AR arm-none-eabi-ar)
set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
set(CMAKE_OBJDUMP arm-none-eabi-objdump)
set(SIZE arm-none-eabi-size)
SET(LINKER_SCRIPT $${CMAKE_SOURCE_DIR}/${linkerScript})
#Uncomment for hardware floating point
SET(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv5-d16")
add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1)
#Uncomment for software floating point
#SET(FPU_FLAGS "-mfloat-abi=soft")
SET(COMMON_FLAGS
"-mcpu=${mcpu} $${FPU_FLAGS} -mthumb -mthumb-interwork -ffunction-sections -fdata-sections \
-g -fno-common -fmessage-length=0 ${linkerFlags}")
SET(CMAKE_CXX_FLAGS_INIT "$${COMMON_FLAGS} -std=c++11")
SET(CMAKE_C_FLAGS_INIT "$${COMMON_FLAGS} -std=gnu99")
SET(CMAKE_EXE_LINKER_FLAGS_INIT "-Wl,-gc-sections,--print-memory-usage -T $${LINKER_SCRIPT}")
PROJECT(${projectName} C CXX ASM)
set(CMAKE_CXX_STANDARD 11)
#add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1)
add_definitions(${defines})
file(GLOB_RECURSE SOURCES ${sources})
include_directories(${includes})
add_executable($${PROJECT_NAME}.elf $${SOURCES} $${LINKER_SCRIPT})
set(CMAKE_EXE_LINKER_FLAGS
"$${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=$${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.map")
set(HEX_FILE $${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.hex)
set(BIN_FILE $${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.bin)
add_custom_command(TARGET $${PROJECT_NAME}.elf POST_BUILD
COMMAND $${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:$${PROJECT_NAME}.elf> $${HEX_FILE}
COMMAND $${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:$${PROJECT_NAME}.elf> $${BIN_FILE}
COMMENT "Building $${HEX_FILE}
Building $${BIN_FILE}")

7
Core/Inc/flash_config.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __FLASH_CONFIG_H
#define __FLASH_CONFIG_H
#define USE_QPI_MODE 1
#define QPI_HIGH_SPEED 0
#endif

3
Core/Inc/main.h
View File

@ -33,6 +33,9 @@ extern "C" {
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "pin_config.h"
#include "flash_config.h"
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/

12
Core/Inc/pin_config.h Normal file
View File

@ -0,0 +1,12 @@
#ifndef __PIN_CONFIG_H
#define __PIN_CONFIG_H
#define LED_PORT GPIOA
#define LED_PIN GPIO_PIN_1
#define BTN_PORT GPIOE
#define BTN_PIN GPIO_PIN_3
#define BTN_INACTIVE_STATE GPIO_PIN_SET
#endif

101
Core/Inc/stm32h7xx_hal_conf.h
View File

@ -15,11 +15,11 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CONF_H
#define __STM32H7xx_HAL_CONF_H
#ifndef STM32H7xx_HAL_CONF_H
#define STM32H7xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
@ -30,14 +30,16 @@
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_FDCAN_MODULE_ENABLED */
/* #define HAL_FMAC_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_COMP_MODULE_ENABLED */
/* #define HAL_CORDIC_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
@ -46,12 +48,17 @@
/* #define HAL_ETH_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_OTFDEC_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_HRTIM_MODULE_ENABLED */
/* #define HAL_HSEM_MODULE_ENABLED */
/* #define HAL_GFXMMU_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_OPAMP_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
@ -78,6 +85,8 @@
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_MDIOS_MODULE_ENABLED */
/* #define HAL_PSSI_MODULE_ENABLED */
/* #define HAL_DTS_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_MDMA_MODULE_ENABLED
@ -93,14 +102,14 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT ((uint32_t)1000U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -110,11 +119,11 @@
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
@ -132,10 +141,16 @@
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
@ -147,47 +162,60 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################### Ethernet Configuration ######################### */
@ -203,14 +231,14 @@
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* #define USE_FULL_ASSERT 1U */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@ -277,6 +305,10 @@
#include "stm32h7xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CORDIC_MODULE_ENABLED
#include "stm32h7xx_hal_cordic.h"
#endif /* HAL_CORDIC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32h7xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
@ -293,6 +325,14 @@
#include "stm32h7xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_FMAC_MODULE_ENABLED
#include "stm32h7xx_hal_fmac.h"
#endif /* HAL_FMAC_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32h7xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32h7xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
@ -349,6 +389,14 @@
#include "stm32h7xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32h7xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_OTFDEC_MODULE_ENABLED
#include "stm32h7xx_hal_otfdec.h"
#endif /* HAL_OTFDEC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32h7xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
@ -428,22 +476,30 @@
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32h7xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32h7xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */
#ifdef HAL_DTS_MODULE_ENABLED
#include "stm32h7xx_hal_dts.h"
#endif /* HAL_DTS_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
@ -451,6 +507,5 @@
#endif
#endif /* __STM32H7xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
Core/Inc/stm32h7xx_it.h
View File

@ -24,7 +24,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */

22
Core/Inc/w25_qspi.h
View File

@ -11,12 +11,17 @@
#define W25_CMD_WRITE_VOLATILE_ENABLE 0x50
#define W25_CMD_PAGE_PROGRAM 0x02
#define W25_CMD_PAGE_PROGRAM_QUAD 0x32
#define W25_CMD_QPI_ENABLE 0x38
#define W25_CMD_QPI_DISABLE 0xFF
#define W25_CMD_READ 0x03
#define W25_CMD_READ_QUAD 0x6B
#define W25_CMD_SECTOR_ERASE 0x20
#define W25_CMD_READ_STATUS_1 0x05
#define W25_CMD_READ_STATUS_2 0x35
#define W25_CMD_WRITE_STATUS_2 0x31
#define W25_CMD_READ_JEDEC_ID 0x9F
#define W25_CMD_READ_MFG_DEV_ID 0x90
#define W25_CMD_QPI_READ_PARAMS 0xC0
typedef enum {
W25_MODE_SINGLE,
@ -29,6 +34,20 @@ typedef enum {
W25_ADDRESS_32BITS
} w25_address_size_t;
typedef enum {
W25_QPI_DUMMY_2 = 0,
W25_QPI_DUMMY_4,
W25_QPI_DUMMY_6,
W25_QPI_DUMMY_8
} w25_qpi_dummy_t;
typedef enum {
W25_QPI_WRAP_LENGTH_8 = 0,
W25_QPI_WRAP_LENGTH_16,
W25_QPI_WRAP_LENGTH_32,
W25_QPI_WRAP_LENGTH_64
} w25_qpi_wrap_t;
typedef struct {
QSPI_HandleTypeDef *interface;
w25_mode_t mode;
@ -42,5 +61,8 @@ HAL_StatusTypeDef W25_QSPI_Init(w25_qspi_t *flash);
HAL_StatusTypeDef W25_QSPI_Erase_Sector(w25_qspi_t *flash, uint32_t address);
HAL_StatusTypeDef W25_QSPI_Program_Page(w25_qspi_t *flash, uint32_t address, uint8_t *data);
HAL_StatusTypeDef W25_QSPI_Read(w25_qspi_t *flash, uint32_t address, uint8_t *data, uint32_t length);
HAL_StatusTypeDef W25_QSPI_QuadEnable(w25_qspi_t *flash, uint8_t permanent);
HAL_StatusTypeDef W25_QPI_Mode(w25_qspi_t *flash, uint8_t enable);
HAL_StatusTypeDef W25_QPI_ReadParams(w25_qspi_t *flash, w25_qpi_dummy_t dummy_clocks, w25_qpi_wrap_t wrap_length);
#endif //STM32H750VB_BOOTLOADER_W25_QSPI_H

1
Core/Src/bootloader_control.c
View File

@ -22,7 +22,6 @@ uint32_t BL_GetEntryPoint(uint32_t base_address) {
void BL_JumpToXIPStart(uint32_t entry_point, uint32_t vector_base) {
__disable_irq();
SCB->VTOR = vector_base;
SysTick->CTRL = 0;
SysTick->LOAD = 0;
SysTick->VAL = 0;

113
Core/Src/main.c
View File

@ -17,7 +17,6 @@
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "usb_device.h"
@ -28,6 +27,7 @@
#include "printf.h"
#include "bootloader_control.h"
#include "w25_qspi.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -79,10 +79,6 @@ int main(void)
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
/* MCU Configuration--------------------------------------------------------*/
@ -111,18 +107,46 @@ int main(void)
QSPI_CommandTypeDef sCommand;
QSPI_MemoryMappedTypeDef sMemMappedCfg;
sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
sCommand.AddressMode = QSPI_ADDRESS_4_LINES;
sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
sCommand.DataMode = QSPI_DATA_4_LINES;
sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES;
sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS;
sCommand.AlternateBytes = 0xFF;
sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
sCommand.Instruction = 0x6B;
sCommand.DummyCycles = 8;
sCommand.Instruction = 0xEB;
sCommand.DummyCycles = 4;
sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
sMemMappedCfg.TimeOutPeriod = 0;
w25_qspi_t w25_flash;
w25_flash.interface = &hqspi;
w25_flash.mode = W25_MODE_QUAD;
w25_flash.address_size = W25_ADDRESS_24BITS;
#if(USE_QPI_MODE == 1)
W25_QPI_Mode(&w25_flash, 0); // Special use case!!
#endif // USE_QPI_MODE
W25_QSPI_Init(&w25_flash);
printf("Main: Mfg: 0x%x\r\n", w25_flash.manufacturer);
W25_QSPI_QuadEnable(&w25_flash, 0);
#if(USE_QPI_MODE == 1)
sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES;
W25_QPI_Mode(&w25_flash, 1);
#if(QPI_HIGH_SPEED == 1) // For 80MHz HIGHHHHHH speed QPI mode(33-80MHz), additional 4 dummy cycles are required.
sCommand.DummyCycles = 4; // In QPI mode, M7-0 are used as dummy clocks.
W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_6, W25_QPI_WRAP_LENGTH_8);
#else
sCommand.DummyCycles = 0; // In QPI mode, M7-0 are used as dummy clocks.
W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8);
#endif // QPI_HIGH_SPEED
#endif // USE_QPI_MODE
if(HAL_QSPI_MemoryMapped(&hqspi, &sCommand, &sMemMappedCfg) == HAL_OK) {
printf("QSPI mapped ok!\r\n");
if(BL_CheckValidImage(0x90000000) == HAL_OK) {
@ -158,33 +182,38 @@ void SystemClock_Config(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Supply configuration update enable
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the CPU, AHB and APB busses clocks
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI
|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 240;
RCC_OscInitStruct.PLL.PLLM = 2;
RCC_OscInitStruct.PLL.PLLN = 40;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 5;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLQ = 1;
RCC_OscInitStruct.PLL.PLLR = 1;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
@ -192,28 +221,26 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USB
|RCC_PERIPHCLK_QSPI;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
|RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_CLKP;
PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI;
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Enables the Clock Security System
*/
HAL_RCC_EnableCSS();
/** Enable USB Voltage detector
/** Enable USB Voltage detector
*/
HAL_PWREx_EnableUSBVoltageDetector();
}
@ -235,12 +262,12 @@ static void MX_QUADSPI_Init(void)
/* USER CODE END QUADSPI_Init 1 */
/* QUADSPI parameter configuration*/
hqspi.Instance = QUADSPI;
hqspi.Init.ClockPrescaler = 16;
hqspi.Init.ClockPrescaler = 2;
hqspi.Init.FifoThreshold = 4;
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE;
hqspi.Init.FlashSize = 23;
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
hqspi.Init.FlashSize = 24;
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE;
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3;
hqspi.Init.FlashID = QSPI_FLASH_ID_1;
hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
@ -314,9 +341,12 @@ static void MX_GPIO_Init(void)
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET);
/*Configure GPIO pin : PE3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
@ -324,6 +354,13 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : PA1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
/* USER CODE BEGIN 4 */
@ -351,7 +388,7 @@ void Error_Handler(void)
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */

24
Core/Src/stm32h7xx_hal_msp.c
View File

@ -109,17 +109,17 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
/* USER CODE END QUADSPI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**QUADSPI GPIO Configuration
/**QUADSPI GPIO Configuration
PE2 ------> QUADSPI_BK1_IO2
PB2 ------> QUADSPI_CLK
PD11 ------> QUADSPI_BK1_IO0
PD12 ------> QUADSPI_BK1_IO1
PD13 ------> QUADSPI_BK1_IO3
PB6 ------> QUADSPI_BK1_NCS
PB6 ------> QUADSPI_BK1_NCS
*/
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@ -174,14 +174,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
/* USER CODE END QUADSPI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_QSPI_CLK_DISABLE();
/**QUADSPI GPIO Configuration
/**QUADSPI GPIO Configuration
PE2 ------> QUADSPI_BK1_IO2
PB2 ------> QUADSPI_CLK
PD11 ------> QUADSPI_BK1_IO0
PD12 ------> QUADSPI_BK1_IO1
PD13 ------> QUADSPI_BK1_IO3
PB6 ------> QUADSPI_BK1_NCS
PB6 ------> QUADSPI_BK1_NCS
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2);
@ -214,11 +214,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USART1 GPIO Configuration
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@ -252,10 +252,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
PA10 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);

3
Core/Src/stm32h7xx_it.c
View File

@ -64,7 +64,7 @@ extern UART_HandleTypeDef huart1;
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
@ -74,7 +74,6 @@ void NMI_Handler(void)
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
HAL_RCC_NMI_IRQHandler();
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */

83
Core/Src/w25_qspi.c
View File

@ -8,6 +8,7 @@
#include "w25_qspi.h"
HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash);
HAL_StatusTypeDef _W25_Write_Volatile_Enable(w25_qspi_t *flash);
HAL_StatusTypeDef _W25_Wait_Ready(w25_qspi_t *flash);
HAL_StatusTypeDef _W25_GetDefaultCommand(w25_qspi_t *flash, QSPI_CommandTypeDef *sCommand);
HAL_StatusTypeDef _W25_QSPI_Identify(w25_qspi_t *flash);
@ -74,17 +75,77 @@ HAL_StatusTypeDef W25_QSPI_Read(w25_qspi_t *flash, uint32_t address, uint8_t *da
return HAL_OK;
}
HAL_StatusTypeDef _W25_Set_Mode(w25_qspi_t *flash) {
HAL_StatusTypeDef W25_QSPI_QuadEnable(w25_qspi_t *flash, uint8_t permanent) {
QSPI_CommandTypeDef sCommand;
_W25_GetDefaultCommand(flash, &sCommand);
sCommand.Instruction = W25_CMD_WRITE_VOLATILE_ENABLE;
sCommand.Instruction = W25_CMD_READ_STATUS_2;
sCommand.AddressMode = QSPI_ADDRESS_NONE;
sCommand.DataMode = QSPI_DATA_1_LINE;
sCommand.NbData = 1;
sCommand.DummyCycles = 0;
uint8_t status_2;
if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) {
return HAL_ERROR;
}
if(HAL_QSPI_Receive(flash->interface, &status_2, 1000) != HAL_OK) {
return HAL_ERROR;
}
if(permanent) {
_W25_Write_Enable(flash);
}
else _W25_Write_Volatile_Enable(flash);
sCommand.Instruction = W25_CMD_WRITE_STATUS_2;
status_2 |= 0x02; // BIT 1 QE
if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) {
return HAL_ERROR;
}
if(HAL_QSPI_Transmit(flash->interface, &status_2, 1000) != HAL_OK) {
return HAL_ERROR;
}
return HAL_OK;
}
HAL_StatusTypeDef W25_QPI_Mode(w25_qspi_t *flash, uint8_t enable) {
QSPI_CommandTypeDef sCommand;
_W25_GetDefaultCommand(flash, &sCommand);
if(enable) {
sCommand.Instruction = W25_CMD_QPI_ENABLE;
}
else {
sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES;
sCommand.Instruction = W25_CMD_QPI_DISABLE;
}
sCommand.AddressMode = QSPI_ADDRESS_NONE;
sCommand.DataMode = QSPI_DATA_NONE;
sCommand.NbData = 0;
sCommand.DummyCycles = 0;
HAL_QSPI_Command(flash->interface, &sCommand, 1000);
return HAL_OK;
return HAL_QSPI_Command(flash->interface, &sCommand, 1000);
}
HAL_StatusTypeDef W25_QPI_ReadParams(w25_qspi_t *flash, w25_qpi_dummy_t dummy_clocks, w25_qpi_wrap_t wrap_length) {
uint8_t rd_params = (dummy_clocks & 0x03) << 4 | (wrap_length & 0x03); // BIT 5-4: DUMMY, BIT 1-0 WRAP
QSPI_CommandTypeDef sCommand;
_W25_GetDefaultCommand(flash, &sCommand);
sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES;
sCommand.Instruction = W25_CMD_QPI_READ_PARAMS;
sCommand.AddressMode = QSPI_ADDRESS_NONE;
sCommand.DataMode = QSPI_DATA_4_LINES;
sCommand.NbData = 1;
sCommand.DummyCycles = 0;
if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) {
return HAL_ERROR;
}
return HAL_QSPI_Transmit(flash->interface, &rd_params, 1000);
}
HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash) {
@ -101,6 +162,20 @@ HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash) {
return HAL_OK;
}
HAL_StatusTypeDef _W25_Write_Volatile_Enable(w25_qspi_t *flash) {
QSPI_CommandTypeDef sCommand;
_W25_GetDefaultCommand(flash, &sCommand);
sCommand.Instruction = W25_CMD_WRITE_VOLATILE_ENABLE;
sCommand.AddressMode = QSPI_ADDRESS_NONE;
sCommand.DataMode = QSPI_DATA_NONE;
sCommand.NbData = 0;
sCommand.DummyCycles = 0;
HAL_QSPI_Command(flash->interface, &sCommand, 1000);
return HAL_OK;
}
HAL_StatusTypeDef _W25_Wait_Ready(w25_qspi_t *flash) {
QSPI_AutoPollingTypeDef sConfig;
sConfig.Match = 0x00;

609
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
View File

File diff suppressed because it is too large Load Diff

47
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
View File

@ -59,7 +59,9 @@
*/
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
!defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
@ -68,6 +70,17 @@
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
/* #define STM32H735xx */ /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */
/* #define STM32H733xx */ /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */
/* #define STM32H730xx */ /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */
/* #define STM32H730xxQ */ /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */
/* #define STM32H725xx */ /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices */
/* #define STM32H723xx */ /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -88,10 +101,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.6.0
* @brief CMSIS Device version number V1.9.0
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -123,6 +136,30 @@
#include "stm32h747xx.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
#endif
@ -149,8 +186,8 @@ typedef enum
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**

193
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

@ -236,12 +236,12 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4)
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -306,8 +306,22 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -365,6 +379,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
@ -460,7 +477,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
/**
* @}
@ -564,7 +583,14 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@ -622,6 +648,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@ -735,6 +765,66 @@
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
@ -874,7 +964,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -933,7 +1023,7 @@
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@ -965,6 +1055,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/**
* @}
*/
@ -1358,6 +1458,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1380,6 +1504,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/**
* @}
*/
@ -1409,16 +1540,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1437,6 +1570,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1509,14 +1649,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@ -3112,9 +3252,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3242,7 +3381,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3350,9 +3489,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@ -3365,7 +3504,7 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
#if defined(STM32H7)
#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@ -3606,12 +3745,12 @@
* @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
@ -3620,9 +3759,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/

236
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
View File

@ -100,6 +100,52 @@ typedef enum
* @}
*/
#if !defined(SYSCFG_PMCR_BOOSTEN)
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
/**
* @}
*/
#endif /* ! SYSCFG_PMCR_BOOSTEN */
#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) || defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
/** @defgroup SYSCFG_Adc2_Alternate_Connection SYSCFG ADC2 Alternate Connection
* @{
*/
/** @brief Adc2 Alternate Connection on Vinp[16] and Vinp[17]
*/
#define SYSCFG_ADC2_ROUT0_DAC1_1 ((uint32_t)0x00000000) /*!< DAC1_out1 connected to ADC2 VINP[16] */
#define SYSCFG_ADC2_ROUT0_VBAT4 SYSCFG_ADC2ALT_ADC2_ROUT0 /*!< VBAT/4 connected to ADC2 VINP[16] */
#define SYSCFG_ADC2_ROUT1_DAC1_2 ((uint32_t)0x00000000) /*!< DAC1_out2 connected to ADC2 VINP[17] */
#define SYSCFG_ADC2_ROUT1_VREFINT SYSCFG_ADC2ALT_ADC2_ROUT1 /*!< VREFINT connected to ADC2 VINP[17] */
#define IS_SYSCFG_ADC2ALT_ROUT0(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT0_DAC1_1) || \
((__VALUE__) == SYSCFG_ADC2_ROUT0_VBAT4))
#define IS_SYSCFG_ADC2ALT_ROUT1(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT1_DAC1_2) || \
((__VALUE__) == SYSCFG_ADC2_ROUT1_VREFINT))
/**
* @}
*/
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0 || SYSCFG_ADC2ALT_ADC2_ROUT1*/
/** @defgroup SYSCFG_Ethernet_Config Ethernet Config
* @{
*/
@ -123,10 +169,6 @@ typedef enum
#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */
#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
(((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
(((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
(((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */
@ -138,6 +180,16 @@ typedef enum
#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */
#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */
/**
* @}
*/
#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
(((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
(((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
(((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
@ -146,9 +198,7 @@ typedef enum
(((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
/**
* @}
*/
/** @defgroup SYSCFG_Boot_Config Boot Config
* @{
@ -241,17 +291,16 @@ typedef enum
#define EXTI_LINE41 ((uint32_t)0x29)
#define EXTI_LINE42 ((uint32_t)0x2A)
#define EXTI_LINE43 ((uint32_t)0x2B)
#define EXTI_LINE44 ((uint32_t)0x2C)
#define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */
/* EXTI_LINE45 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE46 ((uint32_t)0x2E)
#else
/* EXTI_LINE46 Reserved */
#endif
#endif /* DUAL_CORE */
#define EXTI_LINE47 ((uint32_t)0x2F)
#define EXTI_LINE48 ((uint32_t)0x30)
#define EXTI_LINE49 ((uint32_t)0x31)
#define EXTI_LINE50 ((uint32_t)0x32)
#define EXTI_LINE51 ((uint32_t)0x33)
#define EXTI_LINE52 ((uint32_t)0x34)
@ -262,7 +311,6 @@ typedef enum
#define EXTI_LINE57 ((uint32_t)0x39)
#define EXTI_LINE58 ((uint32_t)0x3A)
#define EXTI_LINE59 ((uint32_t)0x3B)
#define EXTI_LINE60 ((uint32_t)0x3C)
#define EXTI_LINE61 ((uint32_t)0x3D)
#define EXTI_LINE62 ((uint32_t)0x3E)
@ -273,45 +321,43 @@ typedef enum
#define EXTI_LINE67 ((uint32_t)0x43)
#define EXTI_LINE68 ((uint32_t)0x44)
#define EXTI_LINE69 ((uint32_t)0x45)
#define EXTI_LINE70 ((uint32_t)0x46)
#define EXTI_LINE71 ((uint32_t)0x47)
#define EXTI_LINE72 ((uint32_t)0x48)
#define EXTI_LINE73 ((uint32_t)0x49)
#define EXTI_LINE74 ((uint32_t)0x4A)
#define EXTI_LINE75 ((uint32_t)0x4B)
#define EXTI_LINE76 ((uint32_t)0x4C)
#define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */
#define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */
#if defined(DUAL_CORE)
#define EXTI_LINE77 ((uint32_t)0x4D)
#define EXTI_LINE78 ((uint32_t)0x4E)
#define EXTI_LINE79 ((uint32_t)0x4F)
#define EXTI_LINE80 ((uint32_t)0x50)
/* EXTI_LINE81 Reserved */
#define EXTI_LINE82 ((uint32_t)0x52)
/* EXTI_LINE83 Reserved */
#define EXTI_LINE84 ((uint32_t)0x54)
#define EXTI_LINE85 ((uint32_t)0x55)
#define EXTI_LINE86 ((uint32_t)0x56)
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#else
/* EXTI_LINE77 Reserved */
/* EXTI_LINE78 Reserved */
/* EXTI_LINE79 Reserved */
/* EXTI_LINE80 Reserved */
/* EXTI_LINE77 Reserved */
/* EXTI_LINE78 Reserved */
/* EXTI_LINE79 Reserved */
/* EXTI_LINE80 Reserved */
#endif /* DUAL_CORE */
/* EXTI_LINE81 Reserved */
/* EXTI_LINE82 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE82 ((uint32_t)0x52)
#else
/* EXTI_LINE82 Reserved */
#endif /* DUAL_CORE */
/* EXTI_LINE83 Reserved */
/* EXTI_LINE84 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE84 ((uint32_t)0x54)
#else
/* EXTI_LINE84 Reserved */
#endif /* DUAL_CORE */
#define EXTI_LINE85 ((uint32_t)0x55)
#define EXTI_LINE86 ((uint32_t)0x56)
#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#endif
#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */
#define EXTI_LINE89 ((uint32_t)0x59) /* Not available in all family lines */
#define EXTI_LINE90 ((uint32_t)0x5A) /* Not available in all family lines */
#define EXTI_LINE91 ((uint32_t)0x5B) /* Not available in all family lines */
#if defined(DUAL_CORE)
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
@ -334,15 +380,15 @@ typedef enum
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
#endif
#endif /* DUAL_CORE */
#if defined(DUAL_CORE)
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
@ -428,7 +474,9 @@ typedef enum
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \
((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
@ -513,7 +561,9 @@ typedef enum
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \
((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
@ -576,7 +626,7 @@ typedef enum
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#else
#elif (POWER_DOMAINS_NUMBER == 3U)
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
@ -591,18 +641,44 @@ typedef enum
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#endif
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88))
#else
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
#endif /*DUAL_CORE*/
#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/
#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/
#if defined (LPTIM4)
#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/
#else
#define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM2 out selected as D3 domain pendclear source*/
#endif /* LPTIM4 */
#if defined (LPTIM5)
#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/
#else
#define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM3 out selected as D3 domain pendclear source*/
#endif /* LPTIM5 */
#if defined (LPTIM4) && defined (LPTIM5)
#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
#else
#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
#endif /* LPTIM4 LPTIM5 */
/**
* @}
*/
@ -624,10 +700,10 @@ typedef enum
/* Exported macro ------------------------------------------------------------*/
#if defined(DUAL_CORE)
/** @defgroup ART_Exported_Macros ART Exported Macros
* @{
*/
#if defined(DUAL_CORE)
/** @brief ART Enable Macro.
* Enable the Cortex-M4 ART cache.
@ -644,10 +720,10 @@ typedef enum
*/
#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
#endif /* DUAL_CORE */
/**
* @}
*/
#endif /* DUAL_CORE */
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
@ -739,6 +815,23 @@ typedef enum
#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
#endif /* DUAL_CORE */
#if !defined(SYSCFG_PMCR_BOOSTEN)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
}while(0)
#endif /* !SYSCFG_PMCR_BOOSTEN */
/**
* @}
*/
@ -760,8 +853,19 @@ typedef enum
#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
#if defined(I2C5)
#define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5))
#endif /*I2C5*/
#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
#if defined(TIM23)
#define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23))
#endif /*TIM23*/
#if defined(TIM24)
#define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24))
#endif /*TIM24*/
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
@ -794,8 +898,19 @@ typedef enum
#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
#if defined(I2C5)
#define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5))
#endif /*I2C5*/
#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
#if defined(TIM23)
#define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23))
#endif /*TIM23*/
#if defined(TIM24)
#define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24))
#endif /*TIM24*/
#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
@ -935,11 +1050,19 @@ uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
#if defined(SYSCFG_PMCR_EPIS_SEL)
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
#endif /* SYSCFG_PMCR_EPIS_SEL */
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
#if defined(SYSCFG_PMCR_BOOSTEN)
void HAL_SYSCFG_EnableBOOST(void);
void HAL_SYSCFG_DisableBOOST(void);
#endif /* SYSCFG_PMCR_BOOSTEN */
#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
#if defined(DUAL_CORE)
void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
void HAL_SYSCFG_EnableCM7BOOT(void);
@ -953,6 +1076,9 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void);
void HAL_SYSCFG_DisableIOSpeedOptimize(void);
void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
#if defined(SYSCFG_CCCR_NCC_MMC)
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
#endif /* SYSCFG_CCCR_NCC_MMC */
void HAL_EnableDBGSleepMode(void);
void HAL_DisableDBGSleepMode(void);
void HAL_EnableDBGStopMode(void);
@ -989,6 +1115,12 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0)
void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0);
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
/**
* @}

228
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
View File

@ -308,7 +308,12 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
#if defined (PSSI)
#define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */
#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */
#else
#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
#endif /* PSSI */
#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
@ -327,8 +332,11 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
#if defined(SAI2)
#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
#endif /* SAI2 */
#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
@ -336,12 +344,14 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
#if defined(HRTIM1)
#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
#endif /* HRTIM1 */
#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
@ -359,11 +369,57 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
#if defined(SAI3)
#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
#endif /* SAI3 */
#if defined(ADC3)
#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */
#endif /* ADC3 */
#if defined(UART9)
#define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */
#define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */
#endif /* UART9 */
#if defined(USART10)
#define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */
#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */
#endif /* USART10 */
#if defined(FMAC)
#define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */
#define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */
#endif /* FMAC */
#if defined(CORDIC)
#define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */
#define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */
#endif /* CORDIC */
#if defined(I2C5)
#define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */
#define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */
#endif /* I2C5 */
#if defined(TIM23)
#define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */
#define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */
#define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */
#define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */
#define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */
#define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */
#endif /* TIM23 */
#if defined(TIM24)
#define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */
#define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */
#define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */
#define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */
#define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */
#define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */
#endif /* TIM24 */
/* DMAMUX2 requests */
#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
@ -381,9 +437,19 @@ typedef struct __DMA_HandleTypeDef
#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
#if defined(SAI4)
#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
#endif /* SAI4 */
#if defined(ADC3)
#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */
#endif /* ADC3 */
#if defined(DAC2)
#define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */
#endif /* DAC2 */
#if defined(DFSDM2_Channel0)
#define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */
#endif /* DFSDM1_Channel0 */
/**
* @}
@ -649,6 +715,42 @@ typedef struct __DMA_HandleTypeDef
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\
(uint32_t)0x00000000)
#else
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
@ -675,12 +777,49 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Return the current DMA Stream half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\
(uint32_t)0x00000000)
#else
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
@ -707,12 +846,49 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Return the current DMA Stream transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\
(uint32_t)0x00000000)
#else
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
@ -739,6 +915,7 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Return the current DMA Stream FIFO error flag.
@ -793,6 +970,26 @@ typedef struct __DMA_HandleTypeDef
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#if defined(BDMA1)
#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
(uint32_t)0x00000000)
#else
#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
@ -803,6 +1000,7 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Get the DMA Stream pending flags.
@ -817,11 +1015,20 @@ typedef struct __DMA_HandleTypeDef
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* @retval The state of FLAG (SET or RESET).
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
#else
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
#endif /* BDMA1 */
/**
* @brief Clear the DMA Stream pending flags.
@ -836,11 +1043,20 @@ typedef struct __DMA_HandleTypeDef
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* @retval None
*/
#if defined(BDMA1)
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
#else
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
#endif /* BDMA1 */
#define DMA_TO_BDMA_IT(__DMA_IT__) \
((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
@ -1019,9 +1235,19 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
* @{
*/
#if defined(TIM24)
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG))
#elif defined(ADC3)
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
#else
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
#endif /* TIM24 */
#if defined(ADC3)
#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
#else
#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
#endif /* ADC3 */
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \

6
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
View File

@ -177,8 +177,12 @@ typedef struct
#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */
#if defined(LPTIM4)
#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */
#endif /* LPTIM4 */
#if defined(LPTIM5)
#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */
#endif /* LPTIM5 */
#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */
@ -190,8 +194,10 @@ typedef struct
#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */
#if defined(ADC3)
#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */
#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
#endif /* ADC3 */
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */

111
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
View File

@ -134,22 +134,46 @@ typedef struct
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
#if !defined(USB2_OTG_FS)
#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU)
#else
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#endif /* USB2_OTG_FS */
#define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU)
#if defined(DSI)
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
#else
#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU)
#endif /* DSI */
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U)
#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U)
#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U)
#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U)
#if defined(LPTIM4)
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U)
#else
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
#endif /*LPTIM4*/
#if defined(LPTIM5)
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U)
#else
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#endif /*LPTIM5*/
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
#if defined(EXTI_IMR2_IM57)
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
#else
#define EXTI_LINE_57 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x19U)
#endif /*EXTI_IMR2_IM57*/
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
#if defined(EXTI_IMR2_IM59)
#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
#else
#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x1BU)
#endif /*EXTI_IMR2_IM59*/
#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
@ -165,37 +189,58 @@ typedef struct
#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
#define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
#define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#if defined(ADC3)
#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
#if defined (DUAL_CORE)
#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
#else
#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#endif /* DUAL_CORE */
#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU)
#endif /* ADC3 */
#if defined(SAI4)
#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#else
#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU)
#endif /* SAI4 */
#if defined (DUAL_CORE)
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
#define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
#else
#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
#endif /* DUAL_CORE */
#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
#if defined (DUAL_CORE)
#define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
#else
#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
#endif /* DUAL_CORE */
#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
#if defined (DUAL_CORE)
#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
#else
#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
#endif /* DUAL_CORE */
#define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#if defined(ETH)
#define EXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#else
#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
#endif /* ETH */
#define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#if defined(DTS)
#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
#endif /* DTS */
#if defined(EXTI_IMR3_IM89)
#define EXTI_LINE_89 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
#endif /*EXTI_IMR3_IM89*/
#if defined(EXTI_IMR3_IM90)
#define EXTI_LINE_90 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
#endif /*EXTI_IMR3_IM90*/
#if defined(I2C5)
#define EXTI_LINE_91 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
#endif /*I2C5*/
/**
* @}
@ -240,7 +285,9 @@ typedef struct
#define EXTI_GPIOF 0x00000005U
#define EXTI_GPIOG 0x00000006U
#define EXTI_GPIOH 0x00000007U
#if defined(GPIOI)
#define EXTI_GPIOI 0x00000008U
#endif /*GPIOI*/
#define EXTI_GPIOJ 0x00000009U
#define EXTI_GPIOK 0x0000000AU
@ -255,8 +302,16 @@ typedef struct
#define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero */
#define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
#define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
#if defined (LPTIM4)
#define EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#else
#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#endif
#if defined (LPTIM5)
#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#else
#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#endif
/**
* @}
*/
@ -339,7 +394,13 @@ typedef struct
/**
* @brief EXTI Line number
*/
#if (STM32H7_DEV_ID == 0x483UL)
#define EXTI_LINE_NB 92UL
#elif (STM32H7_DEV_ID == 0x480UL)
#define EXTI_LINE_NB 89UL
#else
#define EXTI_LINE_NB 88UL
#endif /* EXTI_LINE_91 */
/**
* @}
@ -377,6 +438,7 @@ typedef struct
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00UL)
#if defined(GPIOI)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
@ -388,14 +450,33 @@ typedef struct
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOJ) || \
((__PORT__) == EXTI_GPIOK))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOJ) || \
((__PORT__) == EXTI_GPIOK))
#endif /*GPIOI*/
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL)
#if defined (LPTIM4) && defined (LPTIM5)
#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
#else
#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
#endif /* LPTIM4 && LPTIM5 */
/**
* @}

422
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
View File

@ -91,24 +91,28 @@ typedef struct
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */
#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */
#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
#if defined (FLASH_SR_OPERR)
#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */
#endif /* FLASH_SR_OPERR */
#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */
#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */
#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */
#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */
#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */
#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */
#if defined (FLASH_SR_OPERR)
#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */
#endif /* FLASH_SR_OPERR */
#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */
#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */
#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
@ -119,7 +123,9 @@ typedef struct
#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */
#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */
#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */
#if defined (FLASH_SR_OPERR)
#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */
#endif /* FLASH_SR_OPERR */
#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */
#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */
#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */
@ -134,7 +140,10 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word (256-bit) at a specified address */
#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word at a specified address */
#if defined (FLASH_OPTCR_PG_OTP)
#define FLASH_TYPEPROGRAM_OTPWORD 0x02U /*!< Program an OTP word at a specified address */
#endif /* FLASH_OPTCR_PG_OTP */
/**
* @}
*/
@ -144,77 +153,99 @@ typedef struct
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */
#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */
#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */
#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write Buffer Not Empty flag */
#define FLASH_FLAG_QW FLASH_SR_QW /*!< Wait Queue on flag */
#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC Busy flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe Error flag */
#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */
#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */
#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */
#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */
#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */
#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC End of Calculation flag */
#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */
#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */
#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */
#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */
#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Write Buffer Not Empty on Bank 1 flag */
#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Wait Queue on Bank 1 flag */
#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC Busy on Bank 1 flag */
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */
#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */
#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */
#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< Strobe Error on Bank 1 flag */
#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */
#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */
#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */
#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */
#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */
#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC End of Calculation on Bank 1 flag */
#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \
FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \
FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \
FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1)
FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
#else
#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \
FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | \
FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \
FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \
FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \
FLASH_FLAG_ALL_ERRORS_BANK1)
FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */
#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */
#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */
#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */
#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Write Buffer Not Empty on Bank 2 flag */
#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Wait Queue on Bank 2 flag */
#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC Busy on Bank 2 flag */
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */
#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */
#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */
#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */
#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */
#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */
#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */
#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */
#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC End of Calculation on Bank 2 flag */
#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \
FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \
FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \
FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2)
FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
#else
#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \
FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | \
FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \
FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \
FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \
FLASH_FLAG_ALL_ERRORS_BANK2)
FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
/**
* @}
*/
@ -228,7 +259,9 @@ typedef struct
#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */
#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */
#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */
#endif /* FLASH_CR_OPERRIE */
#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */
#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */
#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */
@ -236,19 +269,30 @@ typedef struct
#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */
#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \
FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \
FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \
FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1)
FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
#else
#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
FLASH_IT_INCERR_BANK1 | FLASH_IT_RDPERR_BANK1 | \
FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | \
FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | \
FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
#endif /* FLASH_CR_OPERRIE */
#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */
#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */
#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */
#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */
#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */
#endif /* FLASH_CR_OPERRIE */
#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */
#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */
#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */
@ -256,16 +300,26 @@ typedef struct
#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */
#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \
FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \
FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \
FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \
FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \
FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2)
FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
#else
#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \
FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \
FLASH_IT_INCERR_BANK2 | FLASH_IT_RDPERR_BANK2 | \
FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | \
FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | \
FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
#endif /* FLASH_CR_OPERRIE */
/**
* @}
*/
#if defined (FLASH_CR_PSIZE)
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
@ -276,6 +330,7 @@ typedef struct
/**
* @}
*/
#endif /* FLASH_CR_PSIZE */
/** @defgroup FLASH_Keys FLASH Keys
@ -300,6 +355,128 @@ typedef struct
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
#if (FLASH_SECTOR_TOTAL == 128)
#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */
#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */
#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */
#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */
#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */
#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */
#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */
#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */
#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */
#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */
#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */
#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */
#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */
#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */
#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */
#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */
#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */
#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */
#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */
#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */
#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */
#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */
#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */
#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */
#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */
#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */
#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */
#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */
#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */
#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */
#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */
#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */
#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */
#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */
#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */
#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */
#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */
#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */
#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */
#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */
#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */
#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */
#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */
#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */
#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */
#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */
#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */
#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */
#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */
#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */
#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */
#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */
#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */
#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */
#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */
#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */
#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */
#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */
#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */
#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */
#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */
#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */
#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */
#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */
#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */
#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */
#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */
#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */
#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */
#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */
#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */
#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */
#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */
#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */
#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */
#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */
#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */
#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */
#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */
#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */
#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */
#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */
#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */
#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */
#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */
#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */
#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */
#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */
#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */
#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */
#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */
#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */
#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */
#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */
#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */
#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */
#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */
#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */
#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */
#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */
#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */
#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */
#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */
#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */
#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */
#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */
#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */
#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */
#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */
#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */
#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */
#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */
#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */
#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */
#endif /* FLASH_SECTOR_TOTAL == 128 */
/**
* @}
*/
@ -344,8 +521,9 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
* In case of Bank 2, this parameter can be any combination of the following values: *
* @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources
*
* In case of Bank 2, this parameter can be any combination of the following values:
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
@ -358,6 +536,7 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
* @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources
* @retval none
*/
@ -365,9 +544,13 @@ typedef struct
#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
#if defined (DUAL_BANK)
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
__HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
__HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
#else
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)
#endif /* DUAL_BANK */
/**
@ -386,8 +569,9 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
* In case of Bank 2, this parameter can be any combination of the following values: *
* @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources
*
* In case of Bank 2, this parameter can be any combination of the following values:
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
@ -400,6 +584,7 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
* @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources
* @retval none
*/
@ -407,18 +592,22 @@ typedef struct
#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
#if defined (DUAL_BANK)
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
__HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
__HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
#else
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)
#endif /* DUAL_BANK */
/**
* @brief Checks whether the specified FLASH flag is set or not.
* @param __FLAG__: specifies the FLASH flag to check.
* In case of Bank 1 This parameter can be any combination of the following values :
* In case of Bank 1 This parameter can be one of the following values :
* @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
* @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag
* @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag
* @arg FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag
* @arg FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag
* @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
@ -433,10 +622,10 @@ typedef struct
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
*
* In case of Bank 2 This parameter can be any combination of the following values :
* In case of Bank 2 This parameter can be one of the following values :
* @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
* @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag
* @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag
* @arg FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag
* @arg FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag
* @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
@ -456,40 +645,48 @@ typedef struct
#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
#if defined (DUAL_BANK)
#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
__HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
#else
#define __HAL_FLASH_GET_FLAG(__FLAG__) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)
#endif /* DUAL_BANK */
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
* In case of Bank 1, this parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
* @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
* @arg FLASH_FLAG_ALL_BANK1 : All Bank 1 flags
*
* In case of Bank 2 This parameter can be any combination of the following values :
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
* @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
* In case of Bank 2, this parameter can be any combination of the following values :
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
* @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
* @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
* @arg FLASH_FLAG_ALL_BANK2 : All Bank 2 flags
* @retval none
*/
@ -497,8 +694,12 @@ typedef struct
#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
#if defined (DUAL_BANK)
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
__HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
__HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
#else
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)
#endif /* DUAL_BANK */
/**
* @}
@ -575,49 +776,62 @@ extern FLASH_ProcessTypeDef pFlash;
* @{
*/
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
* @{
*/
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
/**
* @}
*/
/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
* @{
*/
#if defined (FLASH_OPTCR_PG_OTP)
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
#else
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
#endif /* FLASH_OPTCR_PG_OTP */
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#if defined (DUAL_BANK)
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
#endif /* DUAL_BANK */
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
/**
* @}
*/
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
/** @defgroup FLASH_Address FLASH Address
* @{
*/
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#if defined (DUAL_BANK)
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
#endif /* DUAL_BANK */
#if defined (DUAL_BANK)
#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#else
#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) <= FLASH_END))
#endif /* DUAL_BANK */
#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#if defined (DUAL_BANK)
#if defined (FLASH_OPTCR_PG_OTP)
#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
#else
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#endif /* FLASH_OPTCR_PG_OTP */
#else
#if defined (FLASH_OPTCR_PG_OTP)
#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
#else
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS))
#endif /* FLASH_OPTCR_PG_OTP */
#endif /* DUAL_BANK */
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2))
/**
* @}
*/
#if defined (DUAL_BANK)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2))
#else
#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
#endif /* DUAL_BANK */
/**
* @}

492
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
View File

@ -69,26 +69,26 @@ typedef struct
*/
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .
This parameter must be a value of @ref FLASHEx_Banks */
@ -103,13 +103,13 @@ typedef struct
uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
This parameter must be a value between PCROP Start address and end of a bank */
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
uint32_t BootAddr0; /*!< Boot Address 0.
uint32_t BootAddr0; /*!< Boot Address 0.
This parameter must be a value between begin and end of a bank */
uint32_t BootAddr1; /*!< Boot Address 1.
uint32_t BootAddr1; /*!< Boot Address 1.
This parameter must be a value between begin and end of a bank */
#if defined(DUAL_CORE)
uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
@ -123,9 +123,9 @@ typedef struct
This parameter must be a value between begin and end of a bank */
#endif /*DUAL_CORE*/
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
This parameter must be a value between begin address and end address of bank1 */
@ -133,6 +133,21 @@ typedef struct
uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address.
This parameter must be a value between Secure Area Start address and end address of a bank1 */
#if defined (FLASH_OTPBL_LOCKBL)
uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked.
This parameter must be a value of @ref FLASHEx_OTP_Blocks */
#endif /* FLASH_OTPBL_LOCKBL */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM.
This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost.
This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
} FLASH_OBProgramInitTypeDef;
/**
@ -140,20 +155,20 @@ typedef struct
*/
typedef struct
{
uint32_t TypeCRC; /*!< CRC Selection Type.
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
uint32_t TypeCRC; /*!< CRC Selection Type.
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
uint32_t BurstSize; /*!< CRC Burst Size.
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
uint32_t BurstSize; /*!< CRC Burst Size.
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
uint32_t Bank; /*!< Select bank where CRC computation is enabled.
This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
uint32_t Bank; /*!< Select bank where CRC computation is enabled.
This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
This parameter must be a value of @ref FLASH_Sectors */
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
This parameter must be a value of @ref FLASH_Sectors */
uint32_t NbSectors; /*!< Number of sectors to be computed.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t NbSectors; /*!< Number of sectors to be computed.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t CRCStartAddr; /*!< CRC Start address.
This parameter must be a value between begin address and end address of a bank */
@ -181,6 +196,7 @@ typedef struct
* @}
*/
#if defined (FLASH_CR_PSIZE)
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
@ -191,6 +207,7 @@ typedef struct
/**
* @}
*/
#endif /* FLASH_CR_PSIZE */
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
@ -210,13 +227,40 @@ typedef struct
#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */
#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */
#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */
#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */
#else /* Single core*/
#else /* Single core */
#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */
#endif /*DUAL_CORE*/
#if defined (FLASH_OTPBL_LOCKBL)
#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */
#endif /* FLASH_OTPBL_LOCKBL */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
#if defined (DUAL_CORE)
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */
#elif defined (FLASH_OTPBL_LOCKBL)
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */
#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */
#else
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
OPTIONBYTE_BOOTADD) /*!< All option byte configuration */
#endif /* DUAL_CORE */
/**
* @}
*/
@ -245,8 +289,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */
#define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */
#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */
#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */
/**
* @}
*/
@ -272,8 +316,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
* @{
*/
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
/**
* @}
*/
@ -281,8 +325,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
* @{
*/
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */
/**
* @}
*/
@ -290,10 +334,10 @@ typedef struct
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */
#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */
#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */
#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */
#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */
#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */
/**
* @}
*/
@ -303,13 +347,13 @@ typedef struct
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
* @{
*/
#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */
#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */
/**
* @}
*/
@ -340,9 +384,11 @@ typedef struct
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
*/
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
#define FLASH_BANK_2 0x02U /*!< Bank 2 */
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
#if defined (DUAL_BANK)
#define FLASH_BANK_2 0x02U /*!< Bank 2 */
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
#endif /* DUAL_BANK */
/**
* @}
*/
@ -350,10 +396,10 @@ typedef struct
/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
* @{
*/
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
@ -362,15 +408,51 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */
#if (FLASH_SECTOR_TOTAL == 128)
#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */
#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */
#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */
#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */
#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */
#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */
#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */
#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */
#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */
#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */
#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */
#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */
#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */
#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */
#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */
#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */
#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */
#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */
#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */
#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */
#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */
#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */
#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */
#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */
#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */
#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */
#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */
#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */
#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */
#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */
#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */
#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */
#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */
#else
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */
#endif /* FLASH_SECTOR_TOTAL == 128 */
/**
* @}
*/
@ -387,10 +469,10 @@ typedef struct
/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE
* @{
*/
#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */
/**
* @}
*/
@ -414,7 +496,7 @@ typedef struct
/**
* @}
*/
#endif /*DUAL_CORE*/
#endif /* DUAL_CORE */
/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
* @{
@ -454,7 +536,7 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
#if defined (FLASH_OPTSR_NRST_STOP_D2)
/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
* @{
*/
@ -472,7 +554,7 @@ typedef struct
/**
* @}
*/
#endif
#endif /* FLASH_OPTSR_NRST_STOP_D2 */
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
* @{
@ -486,21 +568,46 @@ typedef struct
/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
* @{
*/
#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
/**
* @}
*/
/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
* @{
*/
#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */
#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
/**
* @}
*/
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST
* @{
*/
#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */
#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */
/**
* @}
*/
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED
* @{
*/
#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */
#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */
#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */
#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */
/**
* @}
*/
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
/** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
* @{
@ -513,15 +620,53 @@ typedef struct
#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */
#define OB_USER_SECURITY 0x0040U /*!< security selection */
#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */
#if defined (DUAL_BANK)
#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */
#endif /* DUAL_BANK */
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
#if defined (DUAL_CORE)
#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */
#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */
#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */
#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/
#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/
#endif /*DUAL_CORE*/
#if defined (FLASH_OPTSR_NRST_STOP_D2)
#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */
#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */
#endif /* FLASH_OPTSR_NRST_STOP_D2 */
#if defined (DUAL_CORE)
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
#elif defined (FLASH_OPTSR_VDDMMC_HSLV)
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
OB_USER_VDDMMC_HSLV)
#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV |\
OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
#else
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
#endif /* DUAL_CORE */
/**
* @}
*/
/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
* @{
*/
#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
/**
* @}
*/
@ -533,7 +678,6 @@ typedef struct
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
*/
@ -570,6 +714,32 @@ typedef struct
* @}
*/
#if defined (FLASH_OTPBL_LOCKBL)
/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
* @{
*/
#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */
#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */
#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */
#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */
#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */
#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */
#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */
#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */
#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */
#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */
#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */
#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */
#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */
#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */
#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */
#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */
#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */
/**
* @}
*/
#endif /* FLASH_OTPBL_LOCKBL */
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
* @{
@ -585,6 +755,7 @@ typedef struct
* @}
*/
#if defined (FLASH_CR_PSIZE)
/**
* @brief Set the FLASH Program/Erase parallelism.
* @param __PSIZE__ FLASH Program/Erase parallelism
@ -592,9 +763,13 @@ typedef struct
* @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
* @retval none
*/
#if defined (DUAL_BANK)
#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
#else
#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
#endif /* DUAL_BANK */
/**
* @brief Get the FLASH Program/Erase parallelism.
@ -602,9 +777,15 @@ typedef struct
* @retval FLASH Program/Erase parallelism
* This return value can be a value of @ref FLASH_Program_Parallelism
*/
#if defined (DUAL_BANK)
#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
#else
#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
#endif /* DUAL_BANK */
#endif /* FLASH_CR_PSIZE */
/**
* @brief Set the FLASH Programming Delay.
@ -637,8 +818,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
#if defined (DUAL_BANK)
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
#endif /* DUAL_BANK */
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
@ -661,66 +844,70 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
((RANGE) == FLASH_VOLTAGE_RANGE_4))
#if defined (FLASH_CR_PSIZE)
#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
((RANGE) == FLASH_VOLTAGE_RANGE_4))
#endif /* FLASH_CR_PSIZE */
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#if defined(DUAL_CORE)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
(((VALUE) & ~OPTIONBYTE_ALL) == 0U))
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || \
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7) || \
((LATENCY) == FLASH_LATENCY_8) || \
((LATENCY) == FLASH_LATENCY_9) || \
((LATENCY) == FLASH_LATENCY_10) || \
((LATENCY) == FLASH_LATENCY_11) || \
((LATENCY) == FLASH_LATENCY_12) || \
((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#if (FLASH_SECTOR_TOTAL == 8U)
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#else
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
#endif /*DUAL_CORE*/
#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
#endif /* FLASH_SECTOR_TOTAL == 8U */
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || \
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7) || \
((LATENCY) == FLASH_LATENCY_8) || \
((LATENCY) == FLASH_LATENCY_9) || \
((LATENCY) == FLASH_LATENCY_10) || \
((LATENCY) == FLASH_LATENCY_11) || \
((LATENCY) == FLASH_LATENCY_12) || \
((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
((CONFIG) == OB_PCROP_RDP_ERASE))
#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
((CONFIG) == OB_PCROP_RDP_ERASE))
#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
((CONFIG) == OB_SECURE_RDP_ERASE))
@ -729,10 +916,14 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
#endif /*DUAL_CORE*/
#endif /* DUAL_CORE */
#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
@ -746,20 +937,29 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
#endif /* DUAL_CORE */
#if defined (FLASH_OPTSR_NRST_STOP_D2)
#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
#else
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
#endif
#endif /* FLASH_OPTSR_NRST_STOP_D2 */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
(((TYPE) & ~OB_USER_ALL) == 0U))
#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
((VALUE) == OB_BOOT_ADD1) || \
@ -768,6 +968,10 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
((VALUE) == FLASH_CRC_SECTORS) || \
((VALUE) == FLASH_CRC_BANK))
#if defined (FLASH_OTPBL_LOCKBL)
#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
#endif /* FLASH_OTPBL_LOCKBL */
/**
* @}
*/

22
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
View File

@ -173,7 +173,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
@ -181,7 +181,7 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
@ -189,7 +189,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
@ -197,7 +197,7 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
#if defined(DUAL_CORE)
/**
@ -206,7 +206,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
@ -214,7 +214,7 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
@ -222,7 +222,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
@ -230,9 +230,9 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
#endif
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check.
@ -296,8 +296,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\

298
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
View File

@ -46,14 +46,16 @@ extern "C" {
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
@ -62,26 +64,40 @@ extern "C" {
#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#endif /* DUAL_CORE */
#endif /* PWR_CPUCR_PDDS_D2 */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#if defined(SAI4)
#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
#endif /* SAI4 */
#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#if defined(FDCAN3)
#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */
#endif /*FDCAN3*/
/**
* @brief AF 3 selection
@ -89,11 +105,18 @@ extern "C" {
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
#if defined(OCTOSPIM)
#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#endif /* OCTOSPIM */
#if defined(HRTIM1)
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
/**
* @brief AF 4 selection
@ -102,11 +125,27 @@ extern "C" {
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#if defined(I2C5)
#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
#endif /* I2C5*/
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#if defined(USART10)
#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
#endif /*USART10*/
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#if defined(PSSI)
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#if defined(OCTOSPIM)
#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
#endif /* OCTOSPIM */
/**
* @brief AF 5 selection
@ -118,18 +157,31 @@ extern "C" {
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#if defined(FDCAN3)
#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */
#endif /*FDCAN3*/
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#if defined(I2C5)
#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */
#endif /* I2C5*/
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
#if defined(SAI3)
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#endif /* SAI3 */
#if defined(OCTOSPIM)
#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 7 selection
@ -142,90 +194,159 @@ extern "C" {
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#if defined(SAI2)
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#endif /*SAI2*/
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#if defined(SAI4)
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#if defined(QUADSPI)
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#endif /* QUADSPI */
#if defined(SAI4)
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
#if defined(OCTOSPIM)
#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
#define GPIO_AF10_SDMMC2 ((uint8_t)0xA) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
#define GPIO_AF10_CRS_SYNC ((uint8_t)0xA) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
#if defined(SAI2)
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
#endif /*SAI2*/
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
#if defined(USB2_OTG_FS)
#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */
#endif /*USB2_OTG_FS*/
#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */
#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */
#endif /*LTDC*/
#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
#if defined(QUADSPI)
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
#endif /* QUADSPI */
#if defined(SAI4)
#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
#if !defined(USB2_OTG_FS)
#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#endif /* !USB2_OTG_FS */
#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */
#if defined(OCTOSPIM)
#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
#if defined(USART10)
#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */
#endif /* USART10 */
#if defined(UART9)
#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
#endif /* UART9 */
#if defined(ETH)
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#endif /* ETH */
#if defined(LTDC)
#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#endif /*LTDC*/
#if defined(OCTOSPIM)
#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */
#endif /*LTDC*/
#if defined(USB2_OTG_FS)
#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */
#endif /* USB2_OTG_FS */
#if defined(OCTOSPIM)
#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#endif /*LTDC*/
#if defined(DSI)
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#endif /* DSI */
#if defined(PSSI)
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
#if defined(TIM23)
#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */
#endif /*TIM23*/
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#if defined(TIM24)
#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */
#endif /*TIM24*/
/**
* @brief AF 15 selection
@ -277,11 +398,21 @@ extern "C" {
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
#if defined(GPIOI)
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
#endif /*GPIOI*/
#if defined(GPIOI)
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#else
#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 )
#endif /* GPIOI */
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
#if defined(GPIOI)
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
#else
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 )
#endif /* GPIOI */
/**
* @}
@ -294,6 +425,7 @@ extern "C" {
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
* @{
*/
#if defined(GPIOI)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
@ -304,6 +436,18 @@ extern "C" {
((__GPIOx__) == (GPIOH))? 7UL :\
((__GPIOx__) == (GPIOI))? 8UL :\
((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
#else
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
((__GPIOx__) == (GPIOD))? 3UL :\
((__GPIOx__) == (GPIOE))? 4UL :\
((__GPIOx__) == (GPIOF))? 5UL :\
((__GPIOx__) == (GPIOG))? 6UL :\
((__GPIOx__) == (GPIOH))? 7UL :\
((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
#endif /* GPIOI */
/**
* @}
*/

6
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
View File

@ -55,6 +55,7 @@ extern "C" {
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
@ -63,6 +64,11 @@ extern "C" {
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#if defined(SYSCFG_PMCR_I2C5_FMP)
#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */
#else
#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */
#endif
/**
* @}
*/

178
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
View File

@ -292,20 +292,43 @@ typedef struct __MDMA_HandleTypeDef
#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */
#if defined (LTDC)
#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */
#endif /* LTDC */
#if defined (JPEG)
#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */
#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */
#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */
#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */
#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */
#endif /* JPEG */
#if defined (OCTOSPI1)
#define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */
#define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */
#endif /* OCTOSPI1 */
#if defined (QUADSPI)
#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */
#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */
#endif /* QUADSPI */
#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */
#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */
#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */
#if defined (DSI)
#define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */
#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */
#endif /* DSI */
#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */
#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */
#define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */
#if defined (OCTOSPI2)
#define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */
#define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */
#endif /* OCTOSPI2 */
#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */
/**
@ -316,9 +339,9 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA Transfer Trigger Mode
* @{
*/
#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
/**
@ -343,10 +366,10 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA Endianness
* @{
*/
#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */
#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */
#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD*/
#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */
#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */
#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */
#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */
/**
* @}
@ -356,14 +379,14 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA Source increment mode
* @{
*/
#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */
#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */
#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */
#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */
#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
/**
@ -374,14 +397,14 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA Destination increment mode
* @{
*/
#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */
#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */
#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */
#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */
#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
/**
@ -392,9 +415,9 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA Source data size
* @{
*/
#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */
/**
@ -405,9 +428,9 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA Destination data size
* @{
*/
#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */
/**
@ -419,11 +442,11 @@ typedef struct __MDMA_HandleTypeDef
* @{
*/
#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size
All data are right aligned, in Little Endien mode. */
#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
All data are right aligned, in Little Endien mode. */
#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
Note : this mode is allowed only if the Source data size is smaller than Destination data size */
#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
/**
* @}
@ -434,12 +457,12 @@ typedef struct __MDMA_HandleTypeDef
* @{
*/
#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
/**
@ -451,12 +474,12 @@ typedef struct __MDMA_HandleTypeDef
* @{
*/
#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
/**
@ -467,11 +490,11 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA interrupt enable definitions
* @{
*/
#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */
#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
/**
* @}
@ -481,12 +504,12 @@ typedef struct __MDMA_HandleTypeDef
* @brief MDMA flag definitions
* @{
*/
#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
/**
* @}
@ -575,8 +598,8 @@ typedef struct __MDMA_HandleTypeDef
/**
* @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* @param __HANDLE__: MDMA handle
* @param __INTERRUPT__: specifies the MDMA interrupt source to check.
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
@ -586,6 +609,21 @@ typedef struct __MDMA_HandleTypeDef
*/
#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Writes the number of data in bytes to be transferred on the MDMA Channelx.
* @param __HANDLE__ : MDMA handle
* @param __COUNTER__: Number of data in bytes to be transferred.
* @retval None
*/
#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT))
/**
* @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer.
* @param __HANDLE__ : MDMA handle
* @retval The number of remaining data in bytes in the current MDMA Channelx transfer.
*/
#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT)
/**
* @}
*/
@ -708,18 +746,22 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \
((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \
((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \
((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \
((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
#if defined (OCTOSPI2)
#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
#else
#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
#endif /* OCTOSPI2 */
#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \
((__INC__) == MDMA_SRC_INC_BYTE ) || \
@ -752,9 +794,9 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
@ -777,9 +819,9 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
((__BURST__) == MDMA_DEST_BURST_128BEATS))
#define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \
((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
((__MODE__) == MDMA_FULL_TRANSFER))
((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
((__MODE__) == MDMA_FULL_TRANSFER))
#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))

30
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
View File

@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@ -244,7 +244,7 @@ typedef enum
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@ -363,14 +363,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

748
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
View File

@ -23,7 +23,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@ -47,11 +47,15 @@
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
parameter can be a value of @ref
PWR_PVD_detection_level.
*/
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */
uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD
event. This parameter can be a value of @ref
PWR_PVD_Mode.
*/
}PWR_PVDTypeDef;
/**
@ -66,14 +70,22 @@ typedef struct
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector level 0 selection : 1V95 */
#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector level 1 selection : 2V1 */
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector level 2 selection : 2V25 */
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector level 3 selection : 2V4 */
#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector level 4 selection : 2V55 */
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector level 5 selection : 2V7 */
#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector level 6 selection : 2V85 */
#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage (Compare internally to VREFINT) */
#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector
level 0 selection : 1V95 */
#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector
level 1 selection : 2V1 */
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector
level 2 selection : 2V25 */
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector
level 3 selection : 2V4 */
#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector
level 4 selection : 2V55 */
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector
level 5 selection : 2V7 */
#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector
level 6 selection : 2V85 */
#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage
(Compare internally to VREF) */
/**
* @}
*/
@ -81,13 +93,13 @@ typedef struct
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@ -95,7 +107,7 @@ typedef struct
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define PWR_MAINREGULATOR_ON (0U)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
/**
* @}
@ -104,8 +116,8 @@ typedef struct
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
#define PWR_SLEEPENTRY_WFI (0x01U)
#define PWR_SLEEPENTRY_WFE (0x02U)
/**
* @}
*/
@ -113,8 +125,8 @@ typedef struct
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
#define PWR_STOPENTRY_WFI (0x01U)
#define PWR_STOPENTRY_WFE (0x02U)
/**
* @}
*/
@ -122,10 +134,17 @@ typedef struct
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#if defined(PWR_SRDCR_VOS)
#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)
#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)
#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U)
#else
#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U)
#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
#endif /* PWR_SRDCR_VOS */
/**
* @}
*/
@ -133,29 +152,48 @@ typedef struct
/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_STOP ((uint8_t)0x01U)
#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)
#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)
#define PWR_FLAG_SB ((uint8_t)0x04U)
#if defined(DUAL_CORE)
#define PWR_FLAG_CPU_HOLD ((uint8_t)0x05U)
#define PWR_FLAG_CPU2_HOLD ((uint8_t)0x06U)
#define PWR_FLAG2_STOP ((uint8_t)0x07U)
#define PWR_FLAG2_SB_D1 ((uint8_t)0x08U)
#define PWR_FLAG2_SB_D2 ((uint8_t)0x09U)
#define PWR_FLAG2_SB ((uint8_t)0x0AU)
#endif /*DUAL_CORE*/
#define PWR_FLAG_PVDO ((uint8_t)0x0BU)
#define PWR_FLAG_AVDO ((uint8_t)0x0CU)
#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU)
#define PWR_FLAG_ACTVOS ((uint8_t)0x0EU)
#define PWR_FLAG_BRR ((uint8_t)0x0FU)
#define PWR_FLAG_VOSRDY ((uint8_t)0x10U)
#if defined(SMPS)
#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U)
/* PWR CPU flag */
#define PWR_FLAG_STOP (0x01U)
#if defined (PWR_CPUCR_SBF_D2)
#define PWR_FLAG_SB_D1 (0x02U)
#define PWR_FLAG_SB_D2 (0x03U)
#endif /* defined (PWR_CPUCR_SBF_D2) */
#define PWR_FLAG_SB (0x04U)
#if defined (DUAL_CORE)
#define PWR_FLAG_CPU_HOLD (0x05U)
#define PWR_FLAG_CPU2_HOLD (0x06U)
#define PWR_FLAG2_STOP (0x07U)
#define PWR_FLAG2_SB_D1 (0x08U)
#define PWR_FLAG2_SB_D2 (0x09U)
#define PWR_FLAG2_SB (0x0AU)
#endif /* defined (DUAL_CORE) */
#define PWR_FLAG_PVDO (0x0BU)
#define PWR_FLAG_AVDO (0x0CU)
#define PWR_FLAG_ACTVOSRDY (0x0DU)
#define PWR_FLAG_ACTVOS (0x0EU)
#define PWR_FLAG_BRR (0x0FU)
#define PWR_FLAG_VOSRDY (0x10U)
#if defined (SMPS)
#define PWR_FLAG_SMPSEXTRDY (0x11U)
#else
#define PWR_FLAG_SCUEN ((uint8_t)0x11U)
#endif /* SMPS */
#define PWR_FLAG_SCUEN (0x11U)
#endif /* defined (SMPS) */
#if defined (PWR_CSR1_MMCVDO)
#define PWR_FLAG_MMCVDO (0x12U)
#endif /* defined (PWR_CSR1_MMCVDO) */
#define PWR_FLAG_USB33RDY (0x13U)
#define PWR_FLAG_TEMPH (0x14U)
#define PWR_FLAG_TEMPL (0x15U)
#define PWR_FLAG_VBATH (0x16U)
#define PWR_FLAG_VBATL (0x17U)
/* PWR Wake up flag */
#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
/**
* @}
*/
@ -163,7 +201,7 @@ typedef struct
/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
* @{
*/
#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)
#define PWR_EWUP_MASK (0x0FFF3F3FU)
/**
* @}
*/
@ -176,141 +214,288 @@ typedef struct
* @{
*/
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
/** @brief Configure the main internal regulator output voltage.
* @param __REGULATOR__ : Specifies the regulator output voltage to achieve a
* trade-off between performance and power consumption
* when the device does not operate at the maximum
* frequency (refer to the datasheet for more details).
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
* @note PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO.
* the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0
* using macro __HAL_RCC_SYSCFG_CLK_ENABLE().
* Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in
* PWR_REGULATOR_VOLTAGE_SCALE1.
* transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1
* then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale.
* After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG
* To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first
* switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode.
*
* @retval None
* @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
* Scale 0 mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
* Scale 1 mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
* Scale 2 mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
* Scale 3 mode.
* @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
* only possible when Vcore is supplied from LDO (Low DropOut). The
* SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
* macro before configuring Voltage Scale 0 using
* __HAL_PWR_VOLTAGESCALING_CONFIG().
* Transition to Voltage Scale 0 is only possible when the system is
* already in Voltage Scale 1.
* Transition from Voltage Scale 0 is only possible to Voltage Scale 1
* then once in Voltage Scale 1 it is possible to switch to another
* voltage scale.
* After each regulator voltage setting, wait on VOSRDY flag to be set
* using macro __HAL_PWR_GET_FLAG().
* To enter low power mode , and if current regulator voltage is
* Voltage Scale 0 then first switch to Voltage Scale 1 before entering
* low power mode.
* @retval None.
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
{ \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \
/* Delay after setting the syscfg boost setting */ \
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
} \
else \
{ \
CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
/* Delay after setting the syscfg boost setting */ \
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
} \
UNUSED(tmpreg); \
#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
/* Configure the Voltage Scaling */ \
MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \
UNUSED(tmpreg); \
} while(0)
#else /* 3 power domains devices */
#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
/* Check the voltage scaling to be configured */ \
if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
{ \
/* Configure the Voltage Scaling 1 */ \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
/* Enable the PWR overdrive */ \
SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
/* Delay after setting the syscfg boost setting */ \
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
} \
else \
{ \
/* Disable the PWR overdrive */ \
CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
/* Delay after setting the syscfg boost setting */ \
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
/* Configure the Voltage Scaling x */ \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
} \
UNUSED(tmpreg); \
} while(0)
#else /* STM32H72xxx and STM32H73xxx lines */
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
/* Configure the Voltage Scaling */ \
MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
UNUSED(tmpreg); \
} while(0)
#endif /* defined(SYSCFG_PWRCR_ODEN) */
#endif /* defined (PWR_SRDCR_VOS) */
#if defined(DUAL_CORE)
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
* @param __FLAG__: specifies the flag to check.
/** @brief Check PWR flags are set or not.
* @param __FLAG__ : Specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the AVDE bit is set.
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag.
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_STOP: STOP flag
* @arg PWR_FLAG_SB_D1: StandBy D1 flag
* @arg PWR_FLAG_SB_D2: StandBy D2 flag
* @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold
* @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold
* @retval The new state of __FLAG__ (TRUE or FALSE).
* @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
* is enabled by the HAL_PWR_EnablePVD()
* function.
* The PVD is stopped by STANDBY mode. For this
* reason, this bit is equal to 0 after STANDBY
* or reset until the PVDE bit is set.
* @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
* is enabled by the HAL_PWREx_EnableAVD()
* function. The AVD is stopped by STANDBY mode.
* For this reason, this bit is equal to 0
* after STANDBY or reset until the AVDE bit
* is set.
* @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
* voltage scaling output selection is
* ready.
* @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
* reset when the device wakes up from STANDBY
* mode or by a system reset or power-on reset.
* @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
* voltage scaling output selection is ready.
* mode or by a system reset or power-on reset.
* @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
* from regulator is ready.
* @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
* equal or above high threshold level.
* @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
* equal or below low threshold level.
* @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
* or above high threshold level.
* @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
* or below low threshold level.
* @arg PWR_FLAG_STOP : This flag indicates that the system entered
* in STOP mode.
* @arg PWR_FLAG_SB : This flag indicates that the system entered in
* STANDBY mode.
* @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
* entered in STANDBY mode.
* @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
* entered in STANDBY mode.
* @arg PWR_FLAG2_STOP : This flag indicates that the system entered
* in STOP mode.
* @arg PWR_FLAG2_SB : This flag indicates that the system entered
* in STANDBY mode.
* @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
* entered in STANDBY mode.
* @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
* entered in STANDBY mode.
* @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
* up with hold.
* @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
* up with hold.
* @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
* External supply is sready.
* @arg PWR_FLAG_SCUEN : This flag indicates that the supply
* configuration update is enabled.
* @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
* above or equal to 1.2 V.
* @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
* PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
* PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
* are used for all H7 family lines.
* The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
* PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
* dual core lines.
* The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
* family except STM32H7Axxx and STM32H7Bxxx lines.
* The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
* STM32H7Bxxx lines.
* The PWR_FLAG_SCUEN flag is used for devices that support only LDO
* regulator.
* The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO
* and SMPS regulators.
* @retval The (__FLAG__) state (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \
((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \
((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \
((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \
((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \
((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \
(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2))
#else
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
* @param __FLAG__: specifies the flag to check.
#if defined (DUAL_CORE) /* Dual core lines */
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\
((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\
((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\
((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
#else /* Single core lines */
#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
#if defined (SMPS) /* STM32H725 and STM32H735 lines */
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
#endif /* defined (SMPS) */
#else /* STM32H7Axxx and STM32H7Bxxx lines */
#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
#else /* STM32H7Axx and STM32H7Bxx lines */
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
#endif /* SMPS */
#endif /* PWR_CPUCR_SBF_D2 */
#endif /* DUAL_CORE */
/** @brief Check PWR wake up flags are set or not.
* @param __FLAG__: specifies the wake up flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the AVDE bit is set.
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_STOP: STOP flag
* @arg PWR_FLAG_SB_D1: StandBy D1 flag
* @arg PWR_FLAG_SB_D2: StandBy D2 flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
* @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
* @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
* @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
* @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
* @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
* @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
* @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
* that support GPIOI port.
* @retval The (__FLAG__) state (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
#endif /*DUAL_CORE*/
#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
#if defined(DUAL_CORE)
/** @brief Clear PWR flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_SB: Standby flag.
* @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
#if defined (DUAL_CORE)
/** @brief Clear CPU PWR flags.
* @param __FLAG__ : Specifies the flag to clear.
* @note This parameter is not used for the STM32H7 family and is kept as
* parameter just to maintain compatibility with other families.
* @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
* This parameter can be one of the following values :
* @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
* CPU flags.
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
@ -319,157 +504,171 @@ do { \
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
} while(0)
#else
/** @brief Clear PWR flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_SB: Standby flag.
* @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
/** @brief Clear CPU PWR flags.
* @param __FLAG__ : Specifies the flag to clear.
* @note This parameter is not used for the STM32H7 family and is kept as
* parameter just to maintain compatibility with other families.
* @note This macro clear all CPU flags.
* For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU
* flags are STOPF, SBF, SBF_D1 and SBF_D2.
* For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF.
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
#endif /*DUAL_CORE*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
#endif /* defined (DUAL_CORE) */
/** @brief Clear PWR wake up flags.
* @param __FLAG__ : Specifies the wake up flag to be cleared.
* This parameter can be one of the following values :
* @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
* @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
* @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
* @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
* @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
* @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
* @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
* that support GPIOI port.
* @retval None.
*/
#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
/**
* @brief Enable the PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Enable the PVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Disable the PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Disable the PVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Enable event on PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Enable event on PVD EXTI D2 Line.
* @brief Enable event on PVD EXTI D2 Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Disable event on PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Disable event on PVD EXTI D2 Line.
* @brief Disable event on PVD EXTI D2 Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @brief Enable the PVD Rising Interrupt Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @brief Disable the PVD Rising Interrupt Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @brief Enable the PVD Falling Interrupt Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @brief Disable the PVD Falling Interrupt Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @brief Enable the PVD Rising & Falling Interrupt Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @brief Disable the PVD Rising & Falling Interrupt Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
* @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI D2 PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
#endif /*DUAL_CORE*/
#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
#endif /* defined (DUAL_CORE) */
/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Clear the PVD EXTI D2 flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Generates a Software interrupt on PVD EXTI line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Include PWR HAL Extension module */
#include "stm32h7xx_hal_pwr_ex.h"
@ -478,44 +677,44 @@ do { \
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
void HAL_PWR_DeInit (void);
void HAL_PWR_EnableBkUpAccess (void);
void HAL_PWR_DisableBkUpAccess (void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @{
*/
/* Peripheral Control functions **********************************************/
/* PVD configuration */
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD (void);
void HAL_PWR_DisablePVD (void);
/* WakeUp pins configuration */
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
/* Low Power modes entry */
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode (void);
/* Power PVD IRQ Handler */
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
void HAL_PWR_PVD_IRQHandler (void);
void HAL_PWR_PVDCallback (void);
/* Cortex System Control functions *******************************************/
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_EnableSleepOnExit (void);
void HAL_PWR_DisableSleepOnExit (void);
void HAL_PWR_EnableSEVOnPend (void);
void HAL_PWR_DisableSEVOnPend (void);
/**
* @}
*/
@ -534,8 +733,8 @@ void HAL_PWR_DisableSEVOnPend(void);
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
* @{
*/
/*!< External interrupt line 16 Connected to the PVD EXTI Line */
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)
#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16
Connected to the PVD EXTI Line */
/**
* @}
*/
@ -551,26 +750,42 @@ void HAL_PWR_DisableSEVOnPend(void);
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
/* Check PVD level parameter */
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
((LEVEL) == PWR_PVDLEVEL_1) ||\
((LEVEL) == PWR_PVDLEVEL_2) ||\
((LEVEL) == PWR_PVDLEVEL_3) ||\
((LEVEL) == PWR_PVDLEVEL_4) ||\
((LEVEL) == PWR_PVDLEVEL_5) ||\
((LEVEL) == PWR_PVDLEVEL_6) ||\
((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
/* Check PVD mode parameter */
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
/* Check low power regulator parameter */
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/* Check low power mode entry parameter */
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
/* Check low power mode entry parameter */
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
((ENTRY) == PWR_STOPENTRY_WFE))
/* Check voltage scale level parameter */
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
/**
* @}
*/
@ -589,8 +804,7 @@ void HAL_PWR_DisableSEVOnPend(void);
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* STM32H7xx_HAL_PWR_H */

665
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
View File

@ -23,7 +23,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@ -45,11 +45,15 @@
*/
typedef struct
{
uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level.
This parameter can be a value of @ref PWREx_AVD_detection_level */
uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
parameter can be a value of @ref
PWREx_AVD_detection_level
*/
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_AVD_Mode */
uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD
event. This parameter can be a value of @ref
PWREx_AVD_Mode.
*/
}PWREx_AVDTypeDef;
/**
@ -57,19 +61,37 @@ typedef struct
*/
typedef struct
{
uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
This parameter can be a value of @ref PWREx_WakeUp_Pins */
uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
This parameter can be a value of @ref
PWREx_WakeUp_Pins
*/
uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
This parameter can be a value of @ref PWREx_PIN_Polarity */
uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
This parameter can be a value of @ref
PWREx_PIN_Polarity
*/
uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull.
This parameter can be a value of @ref PWREx_PIN_Pull */
uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This
parameter can be a value of @ref
PWREx_PIN_Pull
*/
}PWREx_WakeupPinTypeDef;
#if defined (PWR_CSR1_MMCVDO)
/**
* @brief PWR VDDMMC voltage level enum definition
*/
typedef enum
{
PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */
PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
} PWREx_MMC_VoltageLevel;
#endif /* defined (PWR_CSR1_MMCVDO) */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
@ -78,26 +100,41 @@ typedef struct
/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
* @{
*/
#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
/* High level and No pull (default configuration) */
#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
#if defined (PWR_WKUPEPR_WKUPEN5)
#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
#if defined (PWR_WKUPEPR_WKUPEN3)
#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
/* High level and No pull */
#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
#if defined (PWR_WKUPEPR_WKUPEN5)
#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
#if defined (PWR_WKUPEPR_WKUPEN3)
#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
/* Low level and No pull */
#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
#if defined (PWR_WKUPEPR_WKUPP5)
#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
#endif /* defined (PWR_WKUPEPR_WKUPP5) */
#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
#if defined (PWR_WKUPEPR_WKUPP3)
#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
#endif /* defined (PWR_WKUPEPR_WKUPP3) */
#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
/**
* @}
*/
@ -105,8 +142,8 @@ typedef struct
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
* @{
*/
#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)
#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)
#define PWR_PIN_POLARITY_HIGH (0x00000000U)
#define PWR_PIN_POLARITY_LOW (0x00000001U)
/**
* @}
*/
@ -114,44 +151,57 @@ typedef struct
/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
* @{
*/
#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U)
#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U)
#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)
#define PWR_PIN_NO_PULL (0x00000000U)
#define PWR_PIN_PULL_UP (0x00000001U)
#define PWR_PIN_PULL_DOWN (0x00000002U)
/**
* @}
*/
/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
* @{
*/
#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
#if defined (PWR_WKUPFR_WKUPF3)
#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */
#endif /* defined (PWR_WKUPFR_WKUPF3) */
#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
#if defined (PWR_WKUPFR_WKUPF5)
#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
#endif /* defined (PWR_WKUPFR_WKUPF5) */
#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */
#if defined (PWR_WKUPFR_WKUPF3)
#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
#else
#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6)
#endif /* defined (PWR_WKUPFR_WKUPF3) */
/**
* @}
*/
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/** @defgroup PWREx_Core_Select PWREx Core definition
* @{
*/
#define PWR_CORE_CPU1 ((uint32_t)0x00000000U)
#define PWR_CORE_CPU2 ((uint32_t)0x00000001U)
#define PWR_CORE_CPU1 (0x00000000U)
#define PWR_CORE_CPU2 (0x00000001U)
/**
* @}
*/
#endif /*DUAL_CORE*/
#endif /* defined (DUAL_CORE) */
/** @defgroup PWREx_Domains PWREx Domains definition
* @{
*/
#define PWR_D1_DOMAIN ((uint32_t)0x00000000U)
#define PWR_D2_DOMAIN ((uint32_t)0x00000001U)
#define PWR_D3_DOMAIN ((uint32_t)0x00000002U)
#define PWR_D1_DOMAIN (0x00000000U)
#if defined (PWR_CPUCR_PDDS_D2)
#define PWR_D2_DOMAIN (0x00000001U)
#endif /* defined (PWR_CPUCR_PDDS_D2) */
#define PWR_D3_DOMAIN (0x00000002U)
/**
* @}
*/
@ -159,12 +209,13 @@ typedef struct
/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
* @{
*/
#if defined(DUAL_CORE)
#define PWR_D1_DOMAIN_FLAGS ((uint32_t)0x00000000U)
#define PWR_D2_DOMAIN_FLAGS ((uint32_t)0x00000001U)
#if defined (DUAL_CORE)
#define PWR_D1_DOMAIN_FLAGS (0x00000000U)
#define PWR_D2_DOMAIN_FLAGS (0x00000001U)
#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
#else
#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)
#endif /*DUAL_CORE*/
#define PWR_CPU_FLAGS (0x00000000U)
#endif /* defined (DUAL_CORE) */
/**
* @}
*/
@ -172,8 +223,8 @@ typedef struct
/** @defgroup PWREx_D3_State PWREx D3 Domain State
* @{
*/
#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)
#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)
#define PWR_D3_DOMAIN_STOP (0x00000000U)
#define PWR_D3_DOMAIN_RUN (0x00000800U)
/**
* @}
@ -183,23 +234,23 @@ typedef struct
* @{
*/
#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
#if defined(SMPS)
#if defined (SMPS)
#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
#endif /* SMPS */
#endif /* defined (SMPS) */
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
#if defined(SMPS)
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#if defined (SMPS)
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#else
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#endif /* SMPS */
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#endif /* defined (SMPS) */
/**
* @}
*/
@ -208,10 +259,14 @@ typedef struct
/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
* @{
*/
#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
selection : 1V7 */
#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
selection : 2V1 */
#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
selection : 2V5 */
#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
selection : 2V8 */
/**
* @}
*/
@ -219,13 +274,13 @@ typedef struct
/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
* @{
*/
#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@ -233,9 +288,9 @@ typedef struct
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
/**
* @}
*/
@ -243,8 +298,8 @@ typedef struct
/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
@ -252,7 +307,7 @@ typedef struct
/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
* @{
*/
#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
/**
@ -262,7 +317,7 @@ typedef struct
/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
* @{
*/
#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U)
#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
/**
@ -271,14 +326,37 @@ typedef struct
/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
* @{
*/
#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */
#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
Connected to the AVD EXTI Line */
/**
* @}
*/
#if defined (PWR_CR1_SRDRAMSO)
/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
* @{
*/
#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */
#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */
#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */
#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */
#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */
#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */
#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */
#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */
#define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */
#define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */
/**
* @}
*/
#endif /* defined (PWR_CR1_SRDRAMSO) */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
* @{
*/
@ -287,192 +365,202 @@ typedef struct
* @brief Enable the AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Enable the AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Disable the AVD EXTI Line 16
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Disable the AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Enable event on AVD EXTI Line 16.
* @brief Enable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Enable event on AVD EXTI D2 Line 16.
* @brief Enable event on AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Disable event on AVD EXTI Line 16.
* @brief Disable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Disable event on AVD EXTI D2 Line 16.
* @brief Disable event on AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Enable the AVD Extended Interrupt Rising Trigger.
* @brief Enable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Rising Trigger.
* @brief Disable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Falling Trigger.
* @brief Enable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Falling Trigger.
* @brief Disable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief AVD EXTI line configuration: set rising & falling edge trigger.
* @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
* @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified AVD EXTI interrupt flag is set or not.
* @brief Check whether the specified AVD EXTI interrupt flag is set or not.
* @retval EXTI AVD Line Status.
*/
#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
* @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
* @retval EXTI D2 AVD Line Status.
*/
#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
#endif /*DUAL_CORE*/
#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
#endif /* defined (DUAL_CORE) */
/**
* @brief Clear the AVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/**
* @brief Clear the AVD EXTI D2 flag.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
#endif /* defined (DUAL_CORE) */
/**
* @brief Generates a Software interrupt on AVD EXTI line.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions
/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
* @{
*/
/* Power supply control functions */
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
uint32_t HAL_PWREx_GetSupplyConfig(void);
/* Power volatge scaling functions */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource);
uint32_t HAL_PWREx_GetSupplyConfig (void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetVoltageRange (void);
HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetStopModeVoltageRange (void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions
/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
* @{
*/
/* System low power control functions */
void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
#if defined(DUAL_CORE)
void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
/* Power core holding functions */
HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
void HAL_PWREx_ReleaseCore(uint32_t CPU);
#endif /*DUAL_CORE*/
/* Clear pending event function */
void HAL_PWREx_ClearPendingEvent(void);
#if defined (PWR_CPUCR_RETDS_CD)
void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry);
#endif /* defined (PWR_CPUCR_RETDS_CD) */
void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain);
void HAL_PWREx_ConfigD3Domain (uint32_t D3State);
/* Clear Cortex-Mx pending flag */
void HAL_PWREx_ClearPendingEvent (void);
#if defined (DUAL_CORE)
/* Clear domain flags */
void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags);
/* Core Hold/Release functions */
HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU);
void HAL_PWREx_ReleaseCore (uint32_t CPU);
#endif /* defined (DUAL_CORE) */
/* Flash low power control functions */
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
void HAL_PWREx_EnableFlashPowerDown (void);
void HAL_PWREx_DisableFlashPowerDown (void);
#if defined (PWR_CR1_SRDRAMSO)
/* Memory shut-off functions */
void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock);
void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock);
#endif /* defined(PWR_CR1_SRDRAMSO) */
/* Wakeup Pins control functions */
void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams);
void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin);
uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag);
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag);
/* Power Wakeup PIN IRQ Handler */
void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
void HAL_PWREx_WKUP1_Callback(void);
void HAL_PWREx_WKUP2_Callback(void);
void HAL_PWREx_WKUP3_Callback(void);
void HAL_PWREx_WKUP4_Callback(void);
void HAL_PWREx_WKUP5_Callback(void);
void HAL_PWREx_WKUP6_Callback(void);
void HAL_PWREx_WAKEUP_PIN_IRQHandler (void);
void HAL_PWREx_WKUP1_Callback (void);
void HAL_PWREx_WKUP2_Callback (void);
#if defined (PWR_WKUPEPR_WKUPEN3)
void HAL_PWREx_WKUP3_Callback (void);
#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
void HAL_PWREx_WKUP4_Callback (void);
#if defined (PWR_WKUPEPR_WKUPEN5)
void HAL_PWREx_WKUP5_Callback (void);
#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
void HAL_PWREx_WKUP6_Callback (void);
/**
* @}
*/
@ -481,18 +569,21 @@ void HAL_PWREx_WKUP6_Callback(void);
* @{
*/
/* Backup regulator control functions */
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void);
/* USB regulator control functions */
HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
void HAL_PWREx_EnableUSBVoltageDetector(void);
void HAL_PWREx_DisableUSBVoltageDetector(void);
HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void);
HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void);
void HAL_PWREx_EnableUSBVoltageDetector (void);
void HAL_PWREx_DisableUSBVoltageDetector (void);
/* Battery control functions */
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
void HAL_PWREx_DisableBatteryCharging(void);
void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue);
void HAL_PWREx_DisableBatteryCharging (void);
#if defined (PWR_CR1_BOOSTE)
/* Analog Booster functions */
void HAL_PWREx_EnableAnalogBooster (void);
void HAL_PWREx_DisableAnalogBooster (void);
#endif /* PWR_CR1_BOOSTE */
/**
* @}
*/
@ -501,20 +592,20 @@ void HAL_PWREx_DisableBatteryCharging(void);
* @{
*/
/* Power VBAT/Temperature monitoring functions */
void HAL_PWREx_EnableMonitoring(void);
void HAL_PWREx_DisableMonitoring(void);
uint32_t HAL_PWREx_GetTemperatureLevel(void);
uint32_t HAL_PWREx_GetVBATLevel(void);
void HAL_PWREx_EnableMonitoring (void);
void HAL_PWREx_DisableMonitoring (void);
uint32_t HAL_PWREx_GetTemperatureLevel (void);
uint32_t HAL_PWREx_GetVBATLevel (void);
#if defined (PWR_CSR1_MMCVDO)
PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void);
#endif /* PWR_CSR1_MMCVDO */
/* Power AVD configuration functions */
void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
void HAL_PWREx_EnableAVD(void);
void HAL_PWREx_DisableAVD(void);
void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD);
void HAL_PWREx_EnableAVD (void);
void HAL_PWREx_DisableAVD (void);
/* Power PVD/AVD IRQ Handler */
void HAL_PWREx_PVD_AVD_IRQHandler(void);
void HAL_PWREx_AVDCallback(void);
void HAL_PWREx_PVD_AVD_IRQHandler (void);
void HAL_PWREx_AVDCallback (void);
/**
* @}
*/
@ -533,87 +624,149 @@ void HAL_PWREx_AVDCallback(void);
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
* @{
*/
#if defined(SMPS)
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
/* Check PWR regulator configuration parameter */
#if defined (SMPS)
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#else
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#endif /*SMPS*/
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#endif /* defined (SMPS) */
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
/* Check PWR regulator configuration in STOP mode parameter */
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \
((DOMAIN) == PWR_D2_DOMAIN) || \
((DOMAIN) == PWR_D3_DOMAIN))
/* Check PWR domain parameter */
#if defined (PWR_CPUCR_PDDS_D2)
#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
((DOMAIN) == PWR_D2_DOMAIN) ||\
((DOMAIN) == PWR_D3_DOMAIN))
#else
#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
((DOMAIN) == PWR_D3_DOMAIN))
#endif /* defined (PWR_CPUCR_PDDS_D2) */
#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
/* Check D3/SRD domain state parameter */
#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
((STATE) == PWR_D3_DOMAIN_RUN))
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
((PIN) == PWR_WAKEUP_PIN6_HIGH) || \
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW) || \
((PIN) == PWR_WAKEUP_PIN6_LOW))
/* Check wake up pin parameter */
#if defined (PWR_WKUPEPR_WKUPEN3)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
((PIN) == PWR_WAKEUP_PIN2) ||\
((PIN) == PWR_WAKEUP_PIN3) ||\
((PIN) == PWR_WAKEUP_PIN4) ||\
((PIN) == PWR_WAKEUP_PIN5) ||\
((PIN) == PWR_WAKEUP_PIN6) ||\
((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN1_LOW) ||\
((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
((PIN) == PWR_WAKEUP_PIN3_LOW) ||\
((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
((PIN) == PWR_WAKEUP_PIN5_LOW) ||\
((PIN) == PWR_WAKEUP_PIN6_LOW))
#else
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
((PIN) == PWR_WAKEUP_PIN2) ||\
((PIN) == PWR_WAKEUP_PIN4) ||\
((PIN) == PWR_WAKEUP_PIN6) ||\
((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN1_LOW) ||\
((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
((PIN) == PWR_WAKEUP_PIN6_LOW))
#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
((POLARITY) == PWR_PIN_POLARITY_LOW))
/* Check wake up pin polarity parameter */
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
((POLARITY) == PWR_PIN_POLARITY_LOW))
#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \
((PULL) == PWR_PIN_PULL_UP) || \
((PULL) == PWR_PIN_PULL_DOWN))
/* Check wake up pin pull configuration parameter */
#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
((PULL) == PWR_PIN_PULL_UP) ||\
((PULL) == PWR_PIN_PULL_DOWN))
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \
((FLAG) == PWR_WAKEUP_FLAG2) || \
((FLAG) == PWR_WAKEUP_FLAG3) || \
((FLAG) == PWR_WAKEUP_FLAG4) || \
((FLAG) == PWR_WAKEUP_FLAG5) || \
((FLAG) == PWR_WAKEUP_FLAG6))
/* Check wake up flag parameter */
#if defined (PWR_WKUPEPR_WKUPEN3)
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
((FLAG) == PWR_WAKEUP_FLAG2) ||\
((FLAG) == PWR_WAKEUP_FLAG3) ||\
((FLAG) == PWR_WAKEUP_FLAG4) ||\
((FLAG) == PWR_WAKEUP_FLAG5) ||\
((FLAG) == PWR_WAKEUP_FLAG6) ||\
((FLAG) == PWR_WAKEUP_FLAG_ALL))
#else
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
((FLAG) == PWR_WAKEUP_FLAG2) ||\
((FLAG) == PWR_WAKEUP_FLAG4) ||\
((FLAG) == PWR_WAKEUP_FLAG6) ||\
((FLAG) == PWR_WAKEUP_FLAG_ALL))
#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
/* Check wake up flag parameter */
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
((LEVEL) == PWR_AVDLEVEL_1) ||\
((LEVEL) == PWR_AVDLEVEL_2) ||\
((LEVEL) == PWR_AVDLEVEL_3))
#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_AVD_MODE_NORMAL))
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
/* Check AVD mode parameter */
#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\
((MODE) == PWR_AVD_MODE_IT_FALLING) ||\
((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_AVD_MODE_NORMAL) ||\
((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
/* Check resistor battery parameter */
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
/* Check D1/CD CPU ID parameter */
#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/* Check CPU parameter */
#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
/* Check D2 CPU ID parameter */
#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
/* Check PWR domain flag parameter */
#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
((FLAG) == PWR_D2_DOMAIN_FLAGS))
#endif /*DUAL_CORE*/
((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
((FLAG) == PWR_ALL_DOMAIN_FLAGS))
#endif /* defined (DUAL_CORE) */
#if defined (PWR_CR1_SRDRAMSO)
/* Check memory block parameter */
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \
((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \
((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
#endif /* defined (PWR_CR1_SRDRAMSO) */
/**
* @}
*/
@ -630,7 +783,7 @@ void HAL_PWREx_AVDCallback(void);
*/
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* STM32H7xx_HAL_PWR_EX_H */

121
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h
View File

@ -12,7 +12,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -28,6 +28,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined(QUADSPI)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@ -44,35 +46,27 @@
/**
* @brief QSPI Init structure definition
*/
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
@ -100,7 +94,7 @@ typedef enum
typedef struct __QSPI_HandleTypeDef
#else
typedef struct
#endif/* USE_HAL_QSPI_REGISTER_CALLBACKS */
#endif
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
@ -110,7 +104,7 @@ typedef struct
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
@ -155,13 +149,13 @@ typedef struct
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
uint32_t NbData; /* Specifies the number of data to transfer.
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
system clock in DDR mode.
uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
@ -193,7 +187,7 @@ typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@ -233,11 +227,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
@ -248,7 +242,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
@ -257,7 +251,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
@ -272,7 +266,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
@ -281,7 +275,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
@ -291,7 +285,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
*/
@ -299,7 +293,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@ -310,7 +304,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@ -321,7 +315,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@ -332,7 +326,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@ -343,7 +337,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@ -354,7 +348,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@ -365,7 +359,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
@ -374,8 +368,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
/**
* @}
*/
@ -383,7 +377,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@ -392,7 +386,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
@ -401,7 +395,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
@ -410,7 +404,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
@ -445,7 +439,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @brief QSPI Timeout definition
* @{
*/
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
*/
@ -459,7 +453,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @{
*/
/** @brief Reset QSPI handle state.
* @param __HANDLE__: QSPI handle.
* @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@ -473,20 +467,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#endif
/** @brief Enable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -499,8 +493,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @brief Disable the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -512,8 +506,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@ -526,8 +520,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/**
* @brief Check whether the selected QSPI flag is set or not.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI flag to check.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
@ -540,8 +534,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
@ -558,12 +552,22 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
/** @addtogroup QSPI_Exported_Functions
* @{
*/
/** @addtogroup QSPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@ -626,12 +630,15 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
* @{
*/
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
@ -653,7 +660,6 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
((FLASH_ID) == QSPI_FLASH_ID_2))
@ -730,9 +736,8 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3
* @}
*/
/**
* @}
*/
#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
#ifdef __cplusplus
}
#endif

1983
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
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File diff suppressed because it is too large Load Diff

1674
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
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File diff suppressed because it is too large Load Diff

231
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
View File

@ -167,7 +167,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -179,7 +179,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -304,6 +304,26 @@ typedef enum
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef;
/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;
/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;
/**
* @brief HAL Active channel structures definition
*/
@ -327,13 +347,16 @@ typedef struct __TIM_HandleTypeDef
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@ -460,7 +483,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_DMABASE_AF1 0x00000018U
#define TIM_DMABASE_AF2 0x00000019U
#endif /* TIM_BREAK_INPUT_SUPPORT */
#define TIM_DMABASE_TISEL 0x00000020U
#define TIM_DMABASE_TISEL 0x0000001AU
/**
* @}
*/
@ -523,6 +546,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
* @{
*/
#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
/**
* @}
*/
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
@ -616,6 +648,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@ -980,6 +1021,11 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */
#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */
#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
/**
* @}
@ -1093,25 +1139,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@ -1313,6 +1383,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
*/
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
/**
* @brief Disable update interrupt flag (UIF) remapping.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
/**
* @brief Get update interrupt flag (UIF) copy status.
* @param __COUNTER__ Counter value.
* @retval The state of UIFCPY (TRUE or FALSE).
mode.
*/
#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
@ -1332,6 +1427,8 @@ mode.
/**
* @brief Set the TIM Counter Register value on runtime.
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@ -1673,6 +1770,9 @@ mode.
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
((__MODE__) == TIM_UIFREMAP_ENALE))
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
@ -1695,6 +1795,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@ -1862,7 +1965,9 @@ mode.
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR12) || \
((__SELECTION__) == TIM_TS_ITR13))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
@ -1873,6 +1978,8 @@ mode.
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR12) || \
((__SELECTION__) == TIM_TS_ITR13) || \
((__SELECTION__) == TIM_TS_NONE))
#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
@ -1891,15 +1998,15 @@ mode.
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@ -1948,6 +2055,50 @@ mode.
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
} while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
} while(0)
/**
* @}
*/
@ -2173,6 +2324,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@ -2192,7 +2348,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);

72
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
View File

@ -93,9 +93,9 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD1 */
#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC2 AWD2 */
#define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD3 */
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
@ -123,6 +123,18 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
#define TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
#define TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
/**
* @}
*/
@ -184,26 +196,22 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */
#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
#define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */
#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */
#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */
#if defined(TIM12_TI1_GPIO_SUPPORT)
#define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */
#endif /* TIM12_TI1_GPIO_SUPPORT */
#if defined(TIM12_TI1_SPDIF_FS_SUPPORT)
#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */
#endif /* TIM12_TI1_SPDIF_FS_SUPPORT */
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_3) /* !< TIM15_TI1 is connected to RCC LSE */
#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */
#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */
@ -216,11 +224,19 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
#if defined(TIM17_TI1_SPDIF_FS_SUPPORT)
#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */
#endif /* TIM17_TI1_SPDIF_FS_SUPPORT */
#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
#define TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */
#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */
#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */
#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
#define TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */
#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */
#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */
#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
/**
* @}
*/
@ -273,6 +289,8 @@ TIMEx_BreakInputConfigTypeDef;
((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\
((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\
((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\
((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\
((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\
@ -291,12 +309,20 @@ TIMEx_BreakInputConfigTypeDef;
((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\
((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1))
((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\
((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\
((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\
((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\
((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\
((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\
((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
@ -321,8 +347,15 @@ TIMEx_BreakInputConfigTypeDef;
((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB))
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\
((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\
((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
/**
* @}
@ -458,6 +491,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/

12
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
View File

@ -1170,13 +1170,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
@ -1185,7 +1186,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
@ -1194,7 +1195,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
@ -1514,6 +1515,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#include "stm32h7xx_hal_uart_ex.h"
/* Prescaler Table used in BRR computation macros.
Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */
extern const uint16_t UARTPrescTable[12];
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{

41
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
View File

@ -155,7 +155,7 @@ typedef struct
typedef struct
{
uint8_t dev_addr ; /*!< USB device address.
uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@ -199,10 +199,10 @@ typedef struct
uint32_t ErrCnt; /*!< Host channel error count.*/
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@ -237,11 +237,11 @@ typedef struct
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_HS_SPEED 0U
#define USBD_HSINFS_SPEED 1U
#define USBH_HS_SPEED 0U
#define USBD_FS_SPEED 2U
#define USBH_FS_SPEED 1U
#define USBD_HS_SPEED 0U
#define USBD_HSINFS_SPEED 1U
#define USBH_HS_SPEED 0U
#define USBD_FS_SPEED 2U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
@ -269,11 +269,11 @@ typedef struct
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
#define USBD_HS_TRDT_VALUE 9U
#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@ -282,9 +282,9 @@ typedef struct
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@ -294,7 +294,6 @@ typedef struct
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
@ -403,7 +402,7 @@ typedef struct
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#define EP_ADDR_MSK 0xFU
#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@ -468,13 +467,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);

158
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
View File

@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32H7xx HAL Driver version number V1.6.0
* @brief STM32H7xx HAL Driver version number V1.9.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x09UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@ -134,6 +134,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
HAL_StatusTypeDef HAL_Init(void)
{
uint32_t common_system_clock;
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
@ -145,10 +147,24 @@ HAL_StatusTypeDef HAL_Init(void)
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
/* Update the SystemD2Clock global variable */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
@ -251,32 +267,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
return HAL_ERROR;
}
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Cortex-M7 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
else
{
/* Cortex-M4 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
#else
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
#endif
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
@ -361,14 +356,26 @@ uint32_t HAL_GetTickPrio(void)
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
@ -581,6 +588,7 @@ void HAL_SYSCFG_DisableVREFBUF(void)
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
#if defined(SYSCFG_PMCR_EPIS_SEL)
/**
* @brief Ethernet PHY Interface Selection either MII or RMII
* @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
@ -596,7 +604,7 @@ void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
}
#endif /* SYSCFG_PMCR_EPIS_SEL */
/**
* @brief Analog Switch control for dual analog pads.
@ -628,7 +636,7 @@ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCF
MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
}
#if defined(SYSCFG_PMCR_BOOSTEN)
/**
* @brief Enables the booster to reduce the total harmonic distortion of the analog
* switch when the supply voltage is lower than 2.7 V.
@ -653,8 +661,9 @@ void HAL_SYSCFG_DisableBOOST(void)
{
CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
}
#endif /* SYSCFG_PMCR_BOOSTEN */
#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
/**
* @brief BootCM7 address 0 configuration
* @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
@ -687,8 +696,8 @@ void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
#endif /*DUAL_CORE*/
}
}
#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
#if defined(DUAL_CORE)
/**
@ -757,7 +766,6 @@ void HAL_SYSCFG_DisableCM4BOOT(void)
CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
}
#endif /*DUAL_CORE*/
/**
* @brief Enables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
@ -790,7 +798,11 @@ void HAL_DisableCompensationCell(void)
*/
void HAL_SYSCFG_EnableIOSpeedOptimize(void)
{
#if defined(SYSCFG_CCCSR_HSLV)
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
#else
SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
#endif /* SYSCFG_CCCSR_HSLV */
}
/**
@ -802,7 +814,11 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void)
*/
void HAL_SYSCFG_DisableIOSpeedOptimize(void)
{
#if defined(SYSCFG_CCCSR_HSLV)
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
#else
CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
#endif /* SYSCFG_CCCSR_HSLV */
}
/**
@ -838,9 +854,64 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
}
#if defined(SYSCFG_CCCR_NCC_MMC)
/**
* @brief Code selection for the I/O Compensation cell
* @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code
* This code is applied to the I/O compensation cell when the CS bit of the
* SYSCFG_CMPCR is set
* @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code
* This code is applied to the I/O compensation cell when the CS bit of the
* SYSCFG_CMPCR is set
* @retval None
*/
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
{
/* Check the parameter */
assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
}
#endif /* SYSCFG_CCCR_NCC_MMC */
#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0)
/** @brief SYSCFG ADC2 internal input alternate connection macros
* @param Adc2AltRout0 This parameter can be a value of :
* @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16]
* @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16]
*/
void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)
{
/* Check the parameters */
assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0));
MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0);
}
/**
* @}
*/
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
/** @brief SYSCFG ADC2 internal input alternate connection macros
* @param Adc2AltRout1 This parameter can be a value of :
* @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17]
* @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17]
*/
void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)
{
/* Check the parameters */
assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1));
MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1);
}
/**
* @}
*/
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
/**
* @brief Enable the Debug Module during Domain1 SLEEP mode
* @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
*/
void HAL_EnableDBGSleepMode(void)
@ -849,7 +920,7 @@ void HAL_EnableDBGSleepMode(void)
}
/**
* @brief Disable the Debug Module during Domain1 SLEEP mode
* @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
*/
void HAL_DisableDBGSleepMode(void)
@ -857,8 +928,9 @@ void HAL_DisableDBGSleepMode(void)
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
}
/**
* @brief Enable the Debug Module during Domain1 STOP mode
* @brief Enable the Debug Module during Domain1/CDomain STOP mode
* @retval None
*/
void HAL_EnableDBGStopMode(void)
@ -867,7 +939,7 @@ void HAL_EnableDBGStopMode(void)
}
/**
* @brief Disable the Debug Module during Domain1 STOP mode
* @brief Disable the Debug Module during Domain1/CDomain STOP mode
* @retval None
*/
void HAL_DisableDBGStopMode(void)
@ -876,7 +948,7 @@ void HAL_DisableDBGStopMode(void)
}
/**
* @brief Enable the Debug Module during Domain1 STANDBY mode
* @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
* @retval None
*/
void HAL_EnableDBGStandbyMode(void)
@ -885,7 +957,7 @@ void HAL_EnableDBGStandbyMode(void)
}
/**
* @brief Disable the Debug Module during Domain1 STANDBY mode
* @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
* @retval None
*/
void HAL_DisableDBGStandbyMode(void)
@ -949,18 +1021,16 @@ void HAL_DisableDomain2DBGStandbyMode(void)
}
#endif /*DUAL_CORE*/
/**
* @brief Enable the Debug Module during Domain3 STOP mode
* @brief Enable the Debug Module during Domain3/SRDomain STOP mode
* @retval None
*/
void HAL_EnableDomain3DBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
}
/**
* @brief Disable the Debug Module during Domain3 STOP mode
* @brief Disable the Debug Module during Domain3/SRDomain STOP mode
* @retval None
*/
void HAL_DisableDomain3DBGStopMode(void)
@ -969,7 +1039,7 @@ void HAL_DisableDomain3DBGStopMode(void)
}
/**
* @brief Enable the Debug Module during Domain3 STANDBY mode
* @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode
* @retval None
*/
void HAL_EnableDomain3DBGStandbyMode(void)
@ -978,7 +1048,7 @@ void HAL_EnableDomain3DBGStandbyMode(void)
}
/**
* @brief Disable the Debug Module during Domain3 STANDBY mode
* @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode
* @retval None
*/
void HAL_DisableDomain3DBGStandbyMode(void)
@ -1066,7 +1136,7 @@ void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_D1_LINE(EXTI_Line));
SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
@ -1081,7 +1151,7 @@ void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_D2_LINE(EXTI_Line));
SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
#endif /*DUAL_CORE*/

316
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
View File

@ -146,6 +146,19 @@ typedef struct
#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
#if defined(UART9)
#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
#else
#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
#endif
/**
* @}
*/
@ -278,6 +291,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
}
/* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
lock when transfering data to/from USART/UART */
#if (STM32H7_DEV_ID == 0x450UL)
if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
{
#endif /* STM32H7_DEV_ID == 0x450UL */
if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
{
registerValue |= DMA_SxCR_TRBUFF;
}
#if (STM32H7_DEV_ID == 0x450UL)
}
#endif /* STM32H7_DEV_ID == 0x450UL */
/* Write to DMA Stream CR register */
((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
@ -325,8 +352,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
}
else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
{
/* Check the request parameter */
assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
{
/* Check the request parameter */
assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
@ -344,12 +374,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
BDMA_CCR_CT));
/* Prepare the DMA Channel configuration */
registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | \
DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | \
DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | \
DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | \
DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | \
DMA_TO_BDMA_MODE(hdma->Init.Mode) | \
registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) |
DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) |
DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) |
DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) |
DMA_TO_BDMA_MODE(hdma->Init.Mode) |
DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
/* Write to DMA Channel CR register */
@ -373,43 +403,46 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
return HAL_ERROR;
}
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
}
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
}
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Initialize parameters for DMAMUX request generator :
if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
*/
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
*/
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
else
{
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
else
{
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
}
}
/* Initialize the error code */
@ -496,35 +529,41 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
return HAL_ERROR;
}
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->DMAmuxChannel != 0U)
#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
#endif /* BDMA1 */
{
/* Resett he DMAMUX channel that corresponds to the DMA stream */
hdma->DMAmuxChannel->CCR = 0U;
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxChannel != 0U)
{
/* Resett he DMAMUX channel that corresponds to the DMA stream */
hdma->DMAmuxChannel->CCR = 0U;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
}
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
}
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
@ -687,18 +726,21 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
}
}
/* Check if DMAMUX Synchronization is enabled */
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
/* Check if DMAMUX Synchronization is enabled */
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
}
}
/* Enable the Peripheral */
@ -775,8 +817,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR));
}
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
}
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
@ -812,17 +857,20 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
}
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Process Unlocked */
@ -874,24 +922,27 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear all flags */
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Clear all flags */
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Process Unlocked */
@ -1069,42 +1120,46 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* if timeout then abort the current transfer */
/* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */
(void) HAL_DMA_Abort(hdma);
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
return HAL_ERROR;
}
}
/* Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
/* Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
}
}
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
}
}
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
}
}
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
@ -1715,13 +1770,16 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */

59
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
View File

@ -175,16 +175,19 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
}
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Enable the peripheral */
@ -271,13 +274,16 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
@ -304,18 +310,21 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
}
}
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
}
}
/* Enable the peripheral */

258
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
View File

@ -134,11 +134,11 @@ FLASH_ProcessTypeDef pFlash;
*/
/**
* @brief Program flash word of 256 bits at a specified address
* @brief Program flash word at a specified address
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param FlashAddress specifies the address to be programmed.
* @param DataAddress specifies the address of data (256 bits) to be programmed
* @param DataAddress specifies the address of data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
@ -157,14 +157,24 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
/* Process Locked */
__HAL_LOCK(&pFlash);
#if defined (FLASH_OPTCR_PG_OTP)
if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
#else
if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
#endif /* FLASH_OPTCR_PG_OTP */
{
bank = FLASH_BANK_1;
}
else
#if defined (DUAL_BANK)
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
{
bank = FLASH_BANK_2;
}
#endif /* DUAL_BANK */
else
{
return HAL_ERROR;
}
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
@ -174,28 +184,63 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
if(status == HAL_OK)
{
#if defined (DUAL_BANK)
if(bank == FLASH_BANK_1)
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* Set OTP_PG bit */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
}
}
else
{
/* Set PG bit */
SET_BIT(FLASH->CR2, FLASH_CR_PG);
}
#else /* Single Bank */
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* Set OTP_PG bit */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
}
#endif /* DUAL_BANK */
__ISB();
__DSB();
/* Program the 256 bits flash word */
do
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
/* Program an OTP word (16 bits) */
*(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Program the flash word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
}
__ISB();
__DSB();
@ -203,16 +248,41 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
if(bank == FLASH_BANK_1)
#if defined (DUAL_BANK)
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* If the program operation is completed, disable the OTP_PG */
CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
if(bank == FLASH_BANK_1)
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
}
else
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
}
}
#else /* Single Bank */
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* If the program operation is completed, disable the OTP_PG */
CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
}
else
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
}
#endif /* DUAL_BANK */
}
/* Process Unlocked */
@ -248,14 +318,24 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
#if defined (FLASH_OPTCR_PG_OTP)
if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
#else
if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
#endif /* FLASH_OPTCR_PG_OTP */
{
bank = FLASH_BANK_1;
}
else
#if defined (DUAL_BANK)
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
{
bank = FLASH_BANK_2;
}
#endif /* DUAL_BANK */
else
{
return HAL_ERROR;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
@ -269,17 +349,33 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
{
pFlash.Address = FlashAddress;
#if defined (DUAL_BANK)
if(bank == FLASH_BANK_1)
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* Set OTP_PG bit */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
}
/* Enable End of Operation and Error interrupts for Bank 1 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#else
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
}
else
{
@ -290,21 +386,62 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
SET_BIT(FLASH->CR2, FLASH_CR_PG);
/* Enable End of Operation and Error interrupts for Bank2 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#else
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
}
#else /* Single Bank */
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* Set OTP_PG bit */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
}
/* Enable End of Operation and Error interrupts for Bank 1 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#else
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
#endif /* DUAL_BANK */
__ISB();
__DSB();
/* Program the 256 bits flash word */
do
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
/* Program an OTP word (16 bits) */
*(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Program the flash word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
}
__ISB();
__DSB();
@ -391,6 +528,7 @@ void HAL_FLASH_IRQHandler(void)
}
}
#if defined (DUAL_BANK)
/* Check FLASH Bank2 End of Operation flag */
if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
{
@ -458,10 +596,16 @@ void HAL_FLASH_IRQHandler(void)
}
}
}
#endif /* DUAL_BANK */
/* Check FLASH Bank1 operation error flags */
#if defined (FLASH_SR_OPERR)
errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
#else
errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
FLASH_FLAG_INCERR_BANK1);
#endif /* FLASH_SR_OPERR */
if(errorflag != 0U)
{
@ -497,11 +641,16 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_OperationErrorCallback(temp);
}
#if defined (DUAL_BANK)
/* Check FLASH Bank2 operation error flags */
#if defined (FLASH_SR_OPERR)
errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
#else
errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
#endif /* FLASH_SR_OPERR */
/* Check FLASH Bank2 operation error flags */
if(errorflag != 0U)
{
/* Save the error code */
@ -535,16 +684,31 @@ void HAL_FLASH_IRQHandler(void)
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(temp);
}
#endif /* DUAL_BANK */
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
#if defined (FLASH_CR_OPERRIE)
/* Disable Bank1 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#if defined (DUAL_BANK)
/* Disable Bank2 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#endif /* DUAL_BANK */
#else
/* Disable Bank1 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#if defined (DUAL_BANK)
/* Disable Bank2 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* DUAL_BANK */
#endif /* FLASH_CR_OPERRIE */
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
@ -626,6 +790,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
}
}
#if defined (DUAL_BANK)
if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Bank2 Registers access */
@ -638,6 +803,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
return HAL_ERROR;
}
}
#endif /* DUAL_BANK */
return HAL_OK;
}
@ -657,6 +823,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
return HAL_ERROR;
}
#if defined (DUAL_BANK)
/* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
@ -665,6 +832,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
return HAL_ERROR;
}
#endif /* DUAL_BANK */
return HAL_OK;
}
@ -722,10 +890,12 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
status = HAL_ERROR;
}
#if defined (DUAL_BANK)
else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
{
status = HAL_ERROR;
}
#endif /* DUAL_BANK */
else
{
status = HAL_OK;
@ -820,20 +990,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
Even if the FLASH operation fails, the QW flag will be reset and an error
flag will be set */
uint32_t bsyflag, errorflag;
uint32_t bsyflag = FLASH_FLAG_QW_BANK1;
uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
uint32_t tickstart = HAL_GetTick();
assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
/* Select bsyflag depending on Bank */
if(Bank == FLASH_BANK_1)
{
bsyflag = FLASH_FLAG_QW_BANK1;
}
else
#if defined (DUAL_BANK)
if (Bank == FLASH_BANK_2)
{
/* Get Error Flags */
errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
/* Select bsyflag depending on Bank */
bsyflag = FLASH_FLAG_QW_BANK2;
}
#endif /* DUAL_BANK */
while(__HAL_FLASH_GET_FLAG(bsyflag))
{
@ -846,16 +1018,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
}
}
/* Get Error Flags */
if (Bank == FLASH_BANK_1)
{
errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
}
else
{
errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
}
/* In case of error reported in Flash SR1 or SR2 register */
if((errorflag & 0x7FFFFFFFU) != 0U)
{
@ -877,6 +1039,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
}
}
#if defined (DUAL_BANK)
else
{
if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
@ -885,6 +1048,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
}
}
#endif /* DUAL_BANK */
return HAL_OK;
}
@ -976,6 +1140,7 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank
return HAL_ERROR;
}
}
#if defined (DUAL_BANK)
else
{
if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
@ -989,6 +1154,7 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank
return HAL_ERROR;
}
}
#endif /* DUAL_BANK */
/* If there is no error flag set */
return HAL_OK;

303
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
View File

@ -45,6 +45,8 @@
(++) PCROP protection configuration and control per bank
(++) Secure area configuration and control per bank
(++) Core Boot address configuration
(++) TCM / AXI shared RAM configuration
(++) CPU Frequency Boost configuration
(#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
@ -120,10 +122,25 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA
static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
#endif /*DUAL_CORE*/
#if defined (FLASH_OTPBL_LOCKBL)
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
static uint32_t FLASH_OB_OTP_GetLock(void);
#endif /* FLASH_OTPBL_LOCKBL */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig);
static uint32_t FLASH_OB_SharedRAM_GetConfig(void);
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost);
static uint32_t FLASH_OB_CPUFreq_GetBoost(void);
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
/**
* @}
*/
@ -182,6 +199,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
}
}
#if defined (DUAL_BANK)
/* Wait for last operation to be completed on Bank2 */
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
@ -190,6 +208,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
status = HAL_ERROR;
}
}
#endif /* DUAL_BANK */
if(status == HAL_OK)
{
@ -198,7 +217,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Mass erase to be done */
FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
/* Wait for last operation to be completed */
/* Wait for last operation to be completed on Bank 1 */
if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
@ -208,6 +227,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* if the erase operation is completed, disable the Bank1 BER Bit */
FLASH->CR1 &= (~FLASH_CR_BER);
}
#if defined (DUAL_BANK)
/* Wait for last operation to be completed on Bank 2 */
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
@ -217,6 +238,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* if the erase operation is completed, disable the Bank2 BER Bit */
FLASH->CR2 &= (~FLASH_CR_BER);
}
#endif /* DUAL_BANK */
}
else
{
@ -236,6 +258,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
}
#if defined (DUAL_BANK)
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Wait for last operation to be completed */
@ -244,6 +267,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
}
#endif /* DUAL_BANK */
if(status != HAL_OK)
{
@ -282,7 +306,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
/* Wait for last operation to be completed on Bank 1 */
if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
@ -291,6 +315,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
}
}
#if defined (DUAL_BANK)
/* Wait for last operation to be completed on Bank 2 */
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
@ -298,6 +324,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
status = HAL_ERROR;
}
}
#endif /* DUAL_BANK */
if (status != HAL_OK)
{
@ -309,15 +336,27 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
/* Enable End of Operation and Error interrupts for Bank 1 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#else
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
}
#if defined (DUAL_BANK)
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Enable End of Operation and Error interrupts for Bank 2 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#else
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
}
#endif /* DUAL_BANK */
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
@ -326,10 +365,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
}
#if defined (DUAL_BANK)
else if(pEraseInit->Banks == FLASH_BANK_2)
{
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
}
#endif /* DUAL_BANK */
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
@ -340,6 +381,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
else
{
/* Erase by sector to be done */
#if defined (DUAL_BANK)
if(pEraseInit->Banks == FLASH_BANK_1)
{
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
@ -348,6 +390,9 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
}
#else
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
#endif /* DUAL_BANK */
pFlash.NbSectorsToErase = pEraseInit->NbSectors;
pFlash.Sector = pEraseInit->Sector;
@ -386,10 +431,12 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
status = HAL_ERROR;
}
#if defined (DUAL_BANK)
else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
{
status = HAL_ERROR;
}
#endif /* DUAL_BANK */
else
{
status = HAL_OK;
@ -444,30 +491,54 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
}
#if defined(DUAL_CORE)
/*CM7 Boot Address configuration*/
/* CM7 Boot Address configuration */
if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
{
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
/*CM4 Boot Address configuration*/
/* CM4 Boot Address configuration */
if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
{
FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
}
#else /* Single Core*/
/*Boot Address configuration*/
/* Boot Address configuration */
if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
{
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
#endif /*DUAL_CORE*/
/*Bank1 secure area configuration*/
/* Secure area configuration */
if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
{
FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
}
#if defined(FLASH_OTPBL_LOCKBL)
/* OTP Block Lock configuration */
if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
{
FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
}
#endif /* FLASH_OTPBL_LOCKBL */
#if defined(FLASH_OPTSR2_TCM_AXI_SHARED)
/* TCM / AXI Shared RAM configuration */
if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM)
{
FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig);
}
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined(FLASH_OPTSR2_CPUFREQ_BOOST)
/* CPU Frequency Boost configuration */
if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST)
{
FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState);
}
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
}
/* Process Unlocked */
@ -498,7 +569,11 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/*Get BOR Level*/
pOBInit->BORLevel = FLASH_OB_GetBOR();
#if defined (DUAL_BANK)
if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
#else
if (pOBInit->Banks == FLASH_BANK_1)
#endif /* DUAL_BANK */
{
pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
@ -522,6 +597,27 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
#else
pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
#endif /*DUAL_CORE*/
#if defined (FLASH_OTPBL_LOCKBL)
pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
/* Get OTP Block Lock */
pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
#endif /* FLASH_OTPBL_LOCKBL */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM;
/* Get TCM / AXI Shared RAM */
pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig();
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST;
/* Get CPU Frequency Boost */
pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost();
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
}
/**
@ -557,6 +653,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
return HAL_OK;
}
#if defined (DUAL_BANK)
/**
* @brief Unlock the FLASH Bank2 control registers access
* @retval HAL Status
@ -589,6 +686,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
return HAL_OK;
}
#endif /* DUAL_BANK */
/*
* @brief Perform a CRC computation on the specified FLASH memory area
@ -663,6 +761,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
/* Clear CRC flags */
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
}
#if defined (DUAL_BANK)
else
{
/* Enable CRC feature */
@ -711,6 +810,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
/* Clear CRC flags */
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
}
#endif /* DUAL_BANK */
}
return status;
@ -750,12 +850,18 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
{
/* Check the parameters */
#if defined (FLASH_CR_PSIZE)
assert_param(IS_VOLTAGERANGE(VoltageRange));
#else
UNUSED(VoltageRange);
#endif /* FLASH_CR_PSIZE */
assert_param(IS_FLASH_BANK(Banks));
#if defined (DUAL_BANK)
/* Flash Mass Erase */
if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
{
#if defined (FLASH_CR_PSIZE)
/* Reset Program/erase VoltageRange for Bank1 and Bank2 */
FLASH->CR1 &= (~FLASH_CR_PSIZE);
FLASH->CR2 &= (~FLASH_CR_PSIZE);
@ -763,31 +869,40 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
/* Set voltage range */
FLASH->CR1 |= VoltageRange;
FLASH->CR2 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
/* Set Mass Erase Bit */
FLASH->OPTCR |= FLASH_OPTCR_MER;
}
else
#endif /* DUAL_BANK */
{
/* Proceed to erase Flash Bank */
if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
/* Reset Program/erase VoltageRange for Bank1 */
#if defined (FLASH_CR_PSIZE)
/* Set Program/erase VoltageRange for Bank1 */
FLASH->CR1 &= (~FLASH_CR_PSIZE);
FLASH->CR1 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
/* Bank1 will be erased, and set voltage range */
FLASH->CR1 |= FLASH_CR_BER | VoltageRange;
FLASH->CR1 |= FLASH_CR_START;
/* Erase Bank1 */
FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
}
#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Reset Program/erase VoltageRange for Bank2 */
#if defined (FLASH_CR_PSIZE)
/* Set Program/erase VoltageRange for Bank2 */
FLASH->CR2 &= (~FLASH_CR_PSIZE);
FLASH->CR2 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
/* Bank2 will be erased, and set voltage range */
FLASH->CR2 |= FLASH_CR_BER | VoltageRange;
FLASH->CR2 |= FLASH_CR_START;
/* Erase Bank2 */
FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
}
#endif /* DUAL_BANK */
}
}
@ -813,27 +928,43 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
{
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
#if defined (FLASH_CR_PSIZE)
assert_param(IS_VOLTAGERANGE(VoltageRange));
#else
UNUSED(VoltageRange);
#endif /* FLASH_CR_PSIZE */
if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
/* reset Program/erase VoltageRange for Bank1 */
#if defined (FLASH_CR_PSIZE)
/* Reset Program/erase VoltageRange and Sector Number for Bank1 */
FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos));
FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#else
/* Reset Sector Number for Bank1 */
FLASH->CR1 &= ~(FLASH_CR_SNB);
FLASH->CR1 |= FLASH_CR_START;
FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
}
#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* reset Program/erase VoltageRange for Bank2 */
#if defined (FLASH_CR_PSIZE)
/* Reset Program/erase VoltageRange and Sector Number for Bank2 */
FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos));
FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#else
/* Reset Sector Number for Bank2 */
FLASH->CR2 &= ~(FLASH_CR_SNB);
FLASH->CR2 |= FLASH_CR_START;
FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
}
#endif /* DUAL_BANK */
}
/**
@ -862,11 +993,13 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
}
#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Enable Write Protection for bank 2 */
FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
}
#endif /* DUAL_BANK */
}
/**
@ -895,11 +1028,13 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
}
#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Disable Write Protection for bank 2 */
FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
}
#endif /* DUAL_BANK */
}
/**
@ -924,15 +1059,17 @@ static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Ba
{
uint32_t regvalue = 0U;
if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
if(Bank == FLASH_BANK_1)
{
regvalue = FLASH->WPSN_CUR1;
}
if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
#if defined (DUAL_BANK)
if(Bank == FLASH_BANK_2)
{
regvalue = FLASH->WPSN_CUR2;
}
#endif /* DUAL_BANK */
(*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
@ -1145,7 +1282,9 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
optr_reg_mask |= FLASH_OPTSR_BCM7;
}
#endif /* DUAL_CORE */
#if defined (FLASH_OPTSR_NRST_STOP_D2)
if((UserType & OB_USER_NRST_STOP_D2) != 0U)
{
/* NRST_STOP option byte should be modified */
@ -1165,7 +1304,9 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
}
#endif /*DUAL_CORE*/
#endif /* FLASH_OPTSR_NRST_STOP_D2 */
#if defined (DUAL_BANK)
if((UserType & OB_USER_SWAP_BANK) != 0U)
{
/* SWAP_BANK_OPT option byte should be modified */
@ -1175,6 +1316,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
}
#endif /* DUAL_BANK */
if((UserType & OB_USER_IOHSLV) != 0U)
{
@ -1186,6 +1328,18 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
}
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
{
/* VDDMMC_HSLV option byte should be modified */
assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
/* Set value and mask for VDDMMC_HSLV option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
}
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
/* Configure the option bytes register */
MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
}
@ -1259,6 +1413,7 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr,
PCROPConfig;
}
#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
@ -1269,6 +1424,7 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr,
(((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
PCROPConfig;
}
#endif /* DUAL_BANK */
}
/**
@ -1294,17 +1450,19 @@ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, u
uint32_t regvalue = 0;
uint32_t bankBase = 0;
if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
if(Bank == FLASH_BANK_1)
{
regvalue = FLASH->PRAR_CUR1;
bankBase = FLASH_BANK1_BASE;
}
if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
#if defined (DUAL_BANK)
if(Bank == FLASH_BANK_2)
{
regvalue = FLASH->PRAR_CUR2;
bankBase = FLASH_BANK2_BASE;
}
#endif /* DUAL_BANK */
(*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP);
@ -1495,6 +1653,7 @@ static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t Secure
(SecureAreaConfig & FLASH_SCAR_DMES);
}
#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Check the parameters */
@ -1506,6 +1665,7 @@ static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t Secure
(((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
(SecureAreaConfig & FLASH_SCAR_DMES);
}
#endif /* DUAL_BANK */
}
/**
@ -1523,17 +1683,19 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA
uint32_t bankBase = 0;
/* Check Bank parameter value */
if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
if(Bank == FLASH_BANK_1)
{
regvalue = FLASH->SCAR_CUR1;
bankBase = FLASH_BANK1_BASE;
}
if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
#if defined (DUAL_BANK)
if(Bank == FLASH_BANK_2)
{
regvalue = FLASH->SCAR_CUR2;
bankBase = FLASH_BANK2_BASE;
}
#endif /* DUAL_BANK */
/* Get the secure area settings */
(*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
@ -1561,6 +1723,7 @@ static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
/* Select CRC Sector and activate ADD_SECT bit */
FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
}
#if defined (DUAL_BANK)
else
{
/* Clear CRC sector */
@ -1569,6 +1732,7 @@ static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
/* Select CRC Sector and activate ADD_SECT bit */
FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
}
#endif /* DUAL_BANK */
}
/**
@ -1589,6 +1753,7 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr,
FLASH->CRCSADD1 = CRCStartAddr;
FLASH->CRCEADD1 = CRCEndAddr;
}
#if defined (DUAL_BANK)
else
{
assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
@ -1598,11 +1763,93 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr,
FLASH->CRCSADD2 = CRCStartAddr;
FLASH->CRCEADD2 = CRCEndAddr;
}
#endif /* DUAL_BANK */
}
/**
* @}
*/
#if defined (FLASH_OTPBL_LOCKBL)
/**
* @brief Configure the OTP Block Lock.
* @param OTP_Block specifies the OTP Block to lock.
* This parameter can be a value of @ref FLASHEx_OTP_Blocks
* @retval None
*/
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
{
/* Check the parameters */
assert_param(IS_OTP_BLOCK(OTP_Block));
/* Configure the OTP Block lock in the option bytes register */
FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
}
/**
* @brief Get the OTP Block Lock.
* @retval OTP_Block specifies the OTP Block to lock.
* This return value can be a value of @ref FLASHEx_OTP_Blocks
*/
static uint32_t FLASH_OB_OTP_GetLock(void)
{
return (FLASH->OTPBL_CUR);
}
#endif /* FLASH_OTPBL_LOCKBL */
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
/**
* @brief Configure the TCM / AXI Shared RAM.
* @param SharedRamConfig specifies the Shared RAM configuration.
* This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
* @retval None
*/
static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)
{
/* Check the parameters */
assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig));
/* Configure the TCM / AXI Shared RAM in the option bytes register */
MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig);
}
/**
* @brief Get the TCM / AXI Shared RAM configurtion.
* @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration.
* This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
*/
static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
{
return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);;
}
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
/**
* @brief Configure the CPU Frequency Boost.
* @param FreqBoost specifies the CPU Frequency Boost state.
* This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST
* @retval None
*/
static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)
{
/* Check the parameters */
assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost));
/* Configure the CPU Frequency Boost in the option bytes register */
MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost);
}
/**
* @brief Get the CPU Frequency Boost state.
* @retval FreqBoost returns the CPU Frequency Boost state.
* This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST
*/
static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
{
return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);;
}
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
#endif /* HAL_FLASH_MODULE_ENABLED */
/**

54
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
View File

@ -198,26 +198,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@ -243,6 +223,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@ -333,9 +333,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
@ -343,6 +340,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@ -352,14 +352,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
}
position++;

8
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
View File

@ -101,6 +101,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined(DUAL_CORE)
/** @defgroup HSEM_Private_Constants HSEM Private Constants
* @{
*/
#ifndef HSEM_R_MASTERID
#define HSEM_R_MASTERID HSEM_R_COREID
#endif
@ -112,6 +116,10 @@
#ifndef HSEM_CR_MASTERID
#define HSEM_CR_MASTERID HSEM_CR_COREID
#endif
/**
* @}
*/
#endif /* DUAL_CORE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/

257
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
View File

@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
#define I2C_XFER_TX_IT (0x00000001U)
#define I2C_XFER_RX_IT (0x00000002U)
#define I2C_XFER_LISTEN_IT (0x00000004U)
#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
#define I2C_XFER_ERROR_IT (0x00000011U)
#define I2C_XFER_CPLT_IT (0x00000012U)
#define I2C_XFER_RELOAD_IT (0x00000012U)
#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
/* Private function to treat different error callback */
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@ -3200,7 +3203,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount < MAX_NBYTE_SIZE)
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@ -3285,7 +3288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount < MAX_NBYTE_SIZE)
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@ -3446,7 +3449,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount < MAX_NBYTE_SIZE)
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@ -3531,7 +3534,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount < MAX_NBYTE_SIZE)
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Process Locked */
__HAL_LOCK(hi2c);
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@ -4737,6 +4752,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@ -4788,9 +4810,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
{
if (hi2c->XferCount > 0U)
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -4844,13 +4863,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Nothing to do */
}
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5004,10 +5016,18 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@ -5075,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
tmpstate = hi2c->State;
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@ -5092,11 +5128,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
else
{
/* Nothing to do */
@ -5370,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
else
{
/* Do nothing */
}
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@ -5427,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
__IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@ -5448,12 +5514,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
/* Fetch Last receive data if any */
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
tmpreg = (uint8_t)hi2c->Instance->RXDR;
UNUSED(tmpreg);
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@ -5467,6 +5538,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -5501,6 +5573,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -5547,12 +5620,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Disable Interrupts and Store Previous state */
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@ -5566,6 +5653,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@ -5573,6 +5663,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@ -5609,7 +5702,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@ -5632,6 +5724,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5647,6 +5740,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5661,6 +5755,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5734,6 +5829,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@ -5753,7 +5849,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@ -5768,16 +5863,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
tmppreviousstate = hi2c->PreviousState;
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
if (hi2c->hdmatx != NULL)
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@ -5793,13 +5891,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/* Abort DMA RX transfer if any */
else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
if (hi2c->hdmarx != NULL)
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@ -5815,10 +5920,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
else if (hi2c->State == HAL_I2C_STATE_ABORT)
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/**
* @brief I2C Error callback treatment.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5832,6 +5955,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
}
else
{
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -6063,30 +6188,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
hi2c->hdmatx->XferAbortCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
if (hi2c->State == HAL_I2C_STATE_ABORT)
if (hi2c->hdmatx != NULL)
{
hi2c->State = HAL_I2C_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AbortCpltCallback(hi2c);
#else
HAL_I2C_AbortCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->hdmatx->XferAbortCallback = NULL;
}
else
if (hi2c->hdmarx != NULL)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->hdmarx->XferAbortCallback = NULL;
}
I2C_TreatErrorCallback(hi2c);
}
/**
@ -6363,19 +6474,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@ -6401,7 +6512,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@ -6455,19 +6566,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;

4
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
View File

@ -276,6 +276,8 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @note For all I2C5 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C5 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
@ -305,6 +307,8 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @note For all I2C5 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C5 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)

883
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
View File

File diff suppressed because it is too large Load Diff

132
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
View File

@ -1058,6 +1058,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
temp = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
@ -1079,9 +1111,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
@ -1092,10 +1124,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
if (hpcd->Init.dma_enable == 1U)
{
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
@ -1133,16 +1161,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (hpcd->Init.dma_enable == 1U)
{
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if (hpcd->Init.dma_enable == 1U)
{
/* this is ZLP, so prepare EP0 for next setup */
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
{
@ -1150,6 +1169,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
@ -1255,8 +1280,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
@ -1313,38 +1340,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
temp = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
@ -2071,16 +2066,6 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
{
@ -2103,17 +2088,16 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
@ -2146,6 +2130,12 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
}
else
{
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
@ -2171,22 +2161,10 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
/* StupPktRcvd = 1 pending setup packet int */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
}
else
{
if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */

926
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
View File

File diff suppressed because it is too large Load Diff

2142
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
View File

File diff suppressed because it is too large Load Diff

438
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
View File

@ -24,7 +24,7 @@
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
@ -64,7 +64,7 @@
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
(++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
(++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
@ -91,23 +91,23 @@
====================================
[..]
(#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
(++) MDMA settings for write operation :
(+) The DestinationInc should be MDMA_DEST_INC_DISABLE
(++) MDMA settings for write operation :
(+) The DestinationInc should be MDMA_DEST_INC_DISABLE
(+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
(+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
(+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Source_increment_mode .
(+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
(++) MDMA settings for read operation :
(+) The SourceInc should be MDMA_SRC_INC_DISABLE
(+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
(++) MDMA settings for read operation :
(+) The SourceInc should be MDMA_SRC_INC_DISABLE
(+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
(+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
(+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Destination_increment_mode.
(++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
(#)In case of wrong MDMA setting
(++) For write operation :
(#)In case of wrong MDMA setting
(++) For write operation :
(+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA().
(++) For read operation :
(++) For read operation :
(+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA().
*** Memory-mapped functional mode ***
@ -137,7 +137,7 @@
(++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
the transfer complete bi is set.
the transfer complete bit is set.
*** Control functions ***
=========================
@ -146,6 +146,7 @@
(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
(#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
*** Callback registration ***
=============================================
@ -218,7 +219,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@ -226,6 +227,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
#if defined(QUADSPI)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@ -242,7 +245,7 @@
/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
@ -297,7 +300,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
/**
* @brief Initialize the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and initialize the associated handle.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@ -326,13 +329,8 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
@ -356,8 +354,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
#endif
/* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
}
/* Configure QSPI FIFO Threshold */
@ -389,16 +388,13 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
}
/* Release Lock */
__HAL_UNLOCK(hqspi);
/* Return function status */
return status;
}
/**
* @brief De-Initialize the QSPI peripheral.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@ -409,9 +405,6 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hqspi);
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
@ -434,15 +427,12 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hqspi);
return HAL_OK;
}
/**
* @brief Initialize the QSPI MSP.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@ -457,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief DeInitialize the QSPI MSP.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@ -496,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief Handle QSPI interrupt request.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@ -506,7 +496,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
{
data_reg = &hqspi->Instance->DR;
@ -518,7 +508,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->TxXferCount > 0U)
{
/* Fill the FIFO until the threshold is reached */
*(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
*((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@ -539,7 +529,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0U)
{
/* Read the FIFO until the threshold is reached */
*hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@ -556,6 +546,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
{
/* Nothing to do */
}
/* FIFO Threshold callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->FifoThresholdCallback(hqspi);
@ -565,7 +556,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
@ -576,7 +567,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -585,6 +576,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
__HAL_MDMA_DISABLE(hqspi->hmdma);
}
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@ -597,7 +589,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -613,7 +605,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0U)
{
/* Read the last data received in the FIFO until it is empty */
*hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@ -625,6 +617,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
}
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@ -685,7 +678,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
@ -709,7 +702,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
@ -720,7 +713,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -758,7 +751,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
@ -770,6 +763,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
HAL_QSPI_TimeOutCallback(hqspi);
#endif
}
else
{
/* Nothing to do */
@ -778,7 +772,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/**
* @brief Set the command configuration.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
@ -846,7 +840,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/* Update QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
}
}
else
{
@ -869,7 +862,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/**
* @brief Set the command configuration in interrupt mode.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
@ -968,10 +961,11 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
/**
* @brief Transmit an amount of data in blocking mode.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
@ -1010,7 +1004,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
break;
}
*(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
*((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@ -1051,8 +1045,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
@ -1097,7 +1091,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
break;
}
*hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@ -1111,6 +1105,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
}
}
@ -1136,8 +1131,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@ -1196,8 +1191,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@ -1260,18 +1255,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
/**
* @brief Send an amount of data in non-blocking mode with DMA.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If MDMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
* @note If MDMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@ -1283,64 +1275,75 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
if(pData != NULL )
{
/* Configure counters of the handle */
hqspi->TxXferCount = data_size;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Configure counters and size of the handle */
hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pTxBuffPtr = pData;
/* Configure size and pointer of the handle */
hqspi->TxXferSize = hqspi->TxXferCount;
hqspi->pTxBuffPtr = pData;
/* Configure QSPI: CCR register with functional mode as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Configure QSPI: CCR register with functional mode as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Set the QSPI MDMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
/* Set the QSPI MDMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
/* Update MDMA configuration with the correct SourceInc field for Write operation */
if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
}
else
{
/* in case of incorrect source data size */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC);
/* Enable the QSPI transmit MDMA */
if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
}
/* Update MDMA configuration with the correct SourceInc field for Write operation */
if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
}
else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
}
else
{
/* in case of incorrect source data size */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
/* Enable the QSPI transmit MDMA */
if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
{
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
}
else
{
@ -1364,8 +1367,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer.
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@ -1373,6 +1376,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@ -1384,39 +1388,30 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
if(pData != NULL )
{
/* Configure counters of the handle */
hqspi->RxXferCount = data_size;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Configure size and pointer of the handle */
hqspi->RxXferSize = hqspi->RxXferCount;
hqspi->pRxBuffPtr = pData;
/* Configure counters and size of the handle */
hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pRxBuffPtr = pData;
/* Set the QSPI MDMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
/* Set the QSPI DMA transfer complete callback */
hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Set the MDMA error callback */
hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* Clear the MDMA abort callback */
hqspi->hmdma->XferAbortCallback = NULL;
/* QSPI need to be configured to indirect mode before starting
the MDMA to avoid primatury triggering for the MDMA transfert */
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
/* Update MDMA configuration with the correct DestinationInc field for read operation */
if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
{
@ -1430,27 +1425,43 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
{
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
}
else
else
{
/* in case of incorrect destination data size */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
/* Enable the MDMA */
if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
}
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Enable the MDMA */
if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
{
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
}
else
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
@ -1470,9 +1481,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the polling configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
@ -1571,9 +1582,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the polling configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@ -1675,9 +1686,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
/**
* @brief Configure the Memory Mapped mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the memory mapped configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@ -1730,9 +1741,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
@ -1764,7 +1775,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
/**
* @brief Transfer Error callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@ -1779,7 +1790,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1794,7 +1805,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Command completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1809,7 +1820,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Rx Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1824,10 +1835,10 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Tx Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@ -1840,7 +1851,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief FIFO Threshold callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@ -1855,7 +1866,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Status Match callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@ -1870,7 +1881,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Timeout callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@ -2112,7 +2123,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS
/**
* @brief Return the QSPI handle state.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@ -2123,7 +2134,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
/**
* @brief Return the QSPI error code.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@ -2133,7 +2144,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@ -2147,7 +2158,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Process unlocked */
__HAL_UNLOCK(hqspi);
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -2166,7 +2177,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
if(status == HAL_OK)
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
@ -2176,6 +2187,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
if (status == HAL_OK)
{
/* Reset functional mode configuration to indirect write mode by default */
CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@ -2186,7 +2200,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission (non-blocking function)
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@ -2205,7 +2219,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -2214,10 +2228,15 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
{
/* Set error code to DMA */
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
status = HAL_ERROR;
/* Abort Complete callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->AbortCpltCallback(hqspi);
#else
HAL_QSPI_AbortCpltCallback(hqspi);
#endif
}
}
else
@ -2236,8 +2255,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
}
/** @brief Set QSPI timeout.
* @param hqspi: QSPI handle.
* @param Timeout: Timeout for the QSPI memory access.
* @param hqspi : QSPI handle.
* @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@ -2246,8 +2265,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
}
/** @brief Set QSPI Fifo threshold.
* @param hqspi: QSPI handle.
* @param Threshold: Threshold of the Fifo (value between 1 and 16).
* @param hqspi : QSPI handle.
* @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@ -2279,7 +2298,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
}
/** @brief Get QSPI Fifo threshold.
* @param hqspi: QSPI handle.
* @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@ -2328,14 +2347,22 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI
* @}
*/
/**
* @}
*/
/** @defgroup QSPI_Private_Functions QSPI Private Functions
* @{
*/
/**
* @brief DMA QSPI receive process complete callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->RxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@ -2344,12 +2371,12 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
/**
* @brief DMA QSPI transmit process complete callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->TxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@ -2358,12 +2385,12 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
/**
* @brief DMA QSPI communication error callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@ -2379,12 +2406,12 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
/**
* @brief MDMA QSPI abort complete callback.
* @param hmdma: MDMA handle
* @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
{
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@ -2415,13 +2442,14 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
#endif
}
}
/**
* @brief Wait for a flag state until timeout.
* @param hqspi: QSPI handle
* @param Flag: Flag checked
* @param State: Value of the flag expected
* @param Tickstart: Tick start value
* @param Timeout: Duration of the timeout
* @param hqspi : QSPI handle
* @param Flag : Flag checked
* @param State : Value of the flag expected
* @param Tickstart : Tick start value
* @param Timeout : Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@ -2447,9 +2475,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
/**
* @brief Configure the communication registers.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information
* @param FunctionalMode: functional mode to configured
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@ -2612,4 +2640,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
* @}
*/
#endif /* defined(QUADSPI) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

305
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
View File

@ -161,13 +161,15 @@
HSE and PLL.
The AHB clock (HCLK) is derived from System core clock through configurable
pre-scaler and used to clock the CPU, memory and peripherals mapped
on AHB and APB bus of the 3 Domains (D1, D2, D3) through configurable pre-scalers
on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
and used to clock the peripherals mapped on these buses. You can use
"HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
with dual clock domain where kernel source clock could be selected through
RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
(*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
@endverbatim
* @{
*/
@ -189,6 +191,22 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
uint32_t tickstart;
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
{
return HAL_ERROR;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
@ -210,8 +228,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Update the SystemCoreClock global variable */
/* Update the SystemCoreClock and SystemD2Clock global variables */
SystemCoreClock = HSI_VALUE;
SystemD2Clock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
@ -292,6 +311,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
}
}
#if defined(RCC_D1CFGR_HPRE)
/* Reset D1CFGR register */
CLEAR_REG(RCC->D1CFGR);
@ -300,6 +320,16 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* Reset D3CFGR register */
CLEAR_REG(RCC->D3CFGR);
#else
/* Reset CDCFGR1 register */
CLEAR_REG(RCC->CDCFGR1);
/* Reset CDCFGR2 register */
CLEAR_REG(RCC->CDCFGR2);
/* Reset SRDCFGR register */
CLEAR_REG(RCC->SRDCFGR);
#endif
/* Reset PLLCKSELR register to default value */
RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
@ -337,6 +367,21 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* Reset all RSR flags */
SET_BIT(RCC->RSR, RCC_RSR_RMVF);
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
@ -357,6 +402,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart;
uint32_t temp1_pllckcfg, temp2_pllckcfg;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
@ -407,7 +453,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
{
if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
@ -425,12 +471,12 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* When the HSI is used as system clock it will not disabled */
/* When the HSI is used as system clock it will not be disabled */
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
/* When HSI is used as system clock it will not be disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
{
return HAL_ERROR;
@ -438,20 +484,6 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Otherwise, just the calibration is allowed */
else
{
/* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
{
if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
@ -488,7 +520,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
@ -554,7 +586,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till CSI is ready */
/* Wait till CSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
{
if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
@ -692,7 +724,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@ -727,7 +759,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@ -747,7 +779,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Disable PLLFRACN . */
__HAL_RCC_PLLFRACN_DISABLE();
/* Configure PLL PLL1FRACN */
/* Configure PLL PLL1FRACN */
__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
/* Select PLL1 input reference frequency range: VCI */
@ -791,7 +823,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@ -803,7 +835,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
}
else
{
return HAL_ERROR;
/* Do not return HAL_ERROR if request repeats the current configuration */
temp1_pllckcfg = RCC->PLLCKSELR;
temp2_pllckcfg = RCC->PLL1DIVR;
if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
{
return HAL_ERROR;
}
}
}
return HAL_OK;
@ -816,7 +860,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
* contains the configuration information for the RCC peripheral.
* @param FLatency: FLASH Latency, this parameter depend on device selected
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
* and updated by HAL_InitTick() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
@ -839,6 +883,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
HAL_StatusTypeDef halstatus;
uint32_t tickstart;
uint32_t common_system_clock;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
@ -870,55 +915,95 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Increasing the BUS frequency divider */
/*-------------------------- D1PCLK1 Configuration ---------------------------*/
/*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
{
#if defined (RCC_D1CFGR_D1PPRE)
if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
{
assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
}
#else
if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
{
assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
}
#endif
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
#if defined (RCC_D2CFGR_D2PPRE1)
if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
{
assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
}
#else
if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
{
assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
}
#endif
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
#if defined(RCC_D2CFGR_D2PPRE2)
if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
{
assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
}
#else
if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
{
assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
}
#endif
}
/*-------------------------- D3PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
{
#if defined(RCC_D3CFGR_D3PPRE)
if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
{
assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
}
#else
if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
{
assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
}
#endif
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
#if defined (RCC_D1CFGR_HPRE)
if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
{
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
#else
if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
{
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
#endif
}
/*------------------------- SYSCLK Configuration -------------------------*/
@ -926,7 +1011,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
#if defined(RCC_D1CFGR_D1CPRE)
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
#else
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
#endif
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
@ -982,12 +1071,21 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
#if defined(RCC_D1CFGR_HPRE)
if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
{
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
#else
if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
{
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
#endif
}
/* Decreasing the number of wait states because of lower CPU frequency */
@ -1004,48 +1102,96 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/*-------------------------- D1PCLK1 Configuration ---------------------------*/
/*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
{
#if defined(RCC_D1CFGR_D1PPRE)
if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
{
assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
}
#else
if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
{
assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
}
#endif
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
#if defined(RCC_D2CFGR_D2PPRE1)
if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
{
assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
}
#else
if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
{
assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
}
#endif
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
#if defined (RCC_D2CFGR_D2PPRE2)
if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
{
assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
}
#else
if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
{
assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
}
#endif
}
/*-------------------------- D3PCLK1 Configuration ---------------------------*/
/*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
{
#if defined(RCC_D3CFGR_D3PPRE)
if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
{
assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
}
#else
if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
{
assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
}
#endif
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
/* Configure the source of time base considering new system clocks settings*/
halstatus = HAL_InitTick (uwTickPrio);
@ -1298,7 +1444,26 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
uint32_t common_system_clock;
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
return SystemD2Clock;
}
@ -1311,8 +1476,13 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
#if defined (RCC_D2CFGR_D2PPRE1)
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
#else
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}
@ -1325,7 +1495,11 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
#if defined(RCC_D2CFGR_D2PPRE2)
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
#else
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
#endif
}
/**
@ -1342,6 +1516,24 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
/* Get the HSE configuration -----------------------------------------------*/
#if defined(RCC_CR_HSEEXT)
if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
}
else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
else
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
#else
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
@ -1354,6 +1546,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
#endif /* RCC_CR_HSEEXT */
/* Get the CSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
@ -1365,6 +1558,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
}
#if defined(RCC_VER_X)
if(HAL_GetREVID() <= REV_ID_Y)
{
RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
@ -1373,6 +1567,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
}
#else
RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
#endif /*RCC_VER_X*/
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
@ -1384,6 +1581,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
#if defined(RCC_VER_X)
if(HAL_GetREVID() <= REV_ID_Y)
{
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
@ -1392,8 +1590,29 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
}
#else
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
#endif /*RCC_VER_X*/
/* Get the LSE configuration -----------------------------------------------*/
#if defined(RCC_BDCR_LSEEXT)
if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
}
else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
}
else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
{
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
}
else
{
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
}
#else
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
@ -1406,6 +1625,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
}
#endif /* RCC_BDCR_LSEEXT */
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
@ -1464,6 +1684,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
#if defined(RCC_D1CFGR_D1CPRE)
/* Get the SYSCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
@ -1481,7 +1702,25 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
/* Get the APB4 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
#else
/* Get the SYSCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
/* Get the D1HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
/* Get the APB3 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
/* Get the APB4 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
#endif
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);

771
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
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File diff suppressed because it is too large Load Diff

762
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
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File diff suppressed because it is too large Load Diff

456
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
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@ -55,7 +55,7 @@
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
@ -91,9 +91,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
@ -124,6 +126,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
* @note When the timer instance is initialized in Hall Sensor Interface mode,
* timer channels 1 and channel 2 are reserved and cannot be used for
* other purpose.
* @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
@ -209,6 +214,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@ -242,6 +256,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@ -289,12 +312,31 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@ -325,6 +367,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -337,10 +385,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@ -379,6 +446,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -393,29 +466,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@ -464,9 +544,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -513,6 +598,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@ -555,6 +649,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -577,6 +674,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
switch (Channel)
{
case TIM_CHANNEL_1:
@ -685,6 +791,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -709,24 +818,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
switch (Channel)
@ -734,11 +844,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
@ -753,11 +863,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
@ -772,11 +882,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
@ -864,8 +974,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -922,6 +1032,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@ -963,6 +1082,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -985,6 +1107,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
switch (Channel)
{
case TIM_CHANNEL_1:
@ -1093,6 +1224,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1117,35 +1251,37 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
@ -1160,11 +1296,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
@ -1179,11 +1315,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
@ -1271,8 +1407,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -1312,11 +1448,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Enable the complementary One Pulse output */
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@ -1337,12 +1489,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
/* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@ -1350,6 +1504,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1366,17 +1524,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
/* Enable the complementary One Pulse output */
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@ -1397,6 +1571,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@ -1406,8 +1582,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
/* Disable the complementary One Pulse output */
/* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@ -1415,6 +1592,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1460,6 +1641,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
* @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
@ -1476,8 +1659,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
__HAL_LOCK(htim);
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
(InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13))
{
/* Select the Input trigger */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
@ -1516,6 +1700,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
* @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
* @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
@ -1532,8 +1718,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
__HAL_LOCK(htim);
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
(InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13))
{
/* Select the Input trigger */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
@ -1573,7 +1760,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
* @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
* @arg TIM_TS_NONE: No trigger is needed
*
* (*) Value not defined in all devices.
*
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@ -1589,8 +1781,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3
__HAL_LOCK(htim);
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
(InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13))
{
/* Select the Input trigger */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
@ -1636,7 +1829,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@ -1669,16 +1862,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@ -1893,9 +2089,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
* @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO
* @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
* @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
* @arg TIM_TIM1_ETR_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
* @arg TIM_TIM1_ETR_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
* @arg TIM_TIM1_ETR_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
* @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
* @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
* @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
* @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
* @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
* @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
@ -1914,8 +2110,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
*
* For TIM5, the parameter is one of the following values:
* @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO
* @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A
* @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B
* @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
* @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
* @arg TIM_TIM5_ETR_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
* @arg TIM_TIM5_ETR_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
*
* For TIM8, the parameter is one of the following values:
* @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO
@ -1928,6 +2126,20 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
* @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
* @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
*
* For TIM23, the parameter is one of the following values: (*)
* @arg TIM_TIM23_ETR_GPIO TIM23_ETR is connected to GPIO
* @arg TIM_TIM23_ETR_COMP1 TIM23_ETR is connected to COMP1 output
* @arg TIM_TIM23_ETR_COMP2 TIM23_ETR is connected to COMP2 output
*
* For TIM24, the parameter is one of the following values: (*)
* @arg TIM_TIM24_ETR_GPIO TIM24_ETR is connected to GPIO
* @arg TIM_TIM24_ETR_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
* @arg TIM_TIM24_ETR_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
* @arg TIM_TIM24_ETR_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
* @arg TIM_TIM24_ETR_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
*
* (*) Value not defined in all devices.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
@ -2009,6 +2221,18 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
* @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
* @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
*
* For TIM23, the parameter can have the following values: (*)
* @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO
* @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output
* @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output
* @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
*
* For TIM24, the parameter can have the following values: (*)
* @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO
* @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP
* @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP
* @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC
*
* (*) Value not defined in all devices. \n
* @retval HAL status
*/
@ -2189,6 +2413,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
return htim->State;
}
/**
* @brief Return actual state of the TIM complementary channel.
* @param htim TIM handle
* @param ChannelN TIM Complementary channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
* @retval TIM Complementary channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
return channel_state;
}
/**
* @}
*/
@ -2241,6 +2486,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief TIM DMA Delay Pulse complete callback (complementary channel).
* @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
}
}
else
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA error callback (complementary channel)
* @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
else
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral

155
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
View File

@ -191,6 +191,8 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@ -1065,6 +1067,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
pdata16bits = NULL;
}
__HAL_UNLOCK(huart);
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@ -1092,8 +1096,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -1159,6 +1161,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
pdata16bits = NULL;
}
__HAL_UNLOCK(huart);
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@ -1182,8 +1186,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -2857,9 +2859,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv = 0x00000000U;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
uint32_t lpuart_ker_ck_pres = 0x00000000U;
uint32_t lpuart_ker_ck_pres;
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
@ -2928,41 +2930,45 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
switch (clocksource)
{
case UART_CLOCKSOURCE_D3PCLK1:
lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = HAL_RCCEx_GetD3PCLK1Freq();
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = pll2_clocks.PLL2_Q_Frequency;
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = pll3_clocks.PLL3_Q_Frequency;
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
}
else
{
lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = (uint32_t) HSI_VALUE;
}
break;
case UART_CLOCKSOURCE_CSI:
lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = (uint32_t) CSI_VALUE;
break;
case UART_CLOCKSOURCE_LSE:
lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
pclk = (uint32_t) LSE_VALUE;
break;
default:
pclk = 0U;
ret = HAL_ERROR;
break;
}
/* if proper clock source reported */
if (lpuart_ker_ck_pres != 0U)
/* If proper clock source reported */
if (pclk != 0U)
{
/* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
{
@ -2970,42 +2976,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
}
else
{
switch (clocksource)
{
case UART_CLOCKSOURCE_D3PCLK1:
pclk = HAL_RCCEx_GetD3PCLK1Freq();
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
}
else
{
usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
}
break;
case UART_CLOCKSOURCE_CSI:
usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
default:
ret = HAL_ERROR;
break;
}
/* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
{
huart->Instance->BRR = usartdiv;
@ -3014,8 +2987,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
ret = HAL_ERROR;
}
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (lpuart_ker_ck_pres != 0) */
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
@ -3024,51 +2997,54 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
case UART_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = pll2_clocks.PLL2_Q_Frequency;
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = pll3_clocks.PLL3_Q_Frequency;
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
}
else
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t) HSI_VALUE;
}
break;
case UART_CLOCKSOURCE_CSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t) CSI_VALUE;
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t) LSE_VALUE;
break;
default:
pclk = 0U;
ret = HAL_ERROR;
break;
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
if (pclk != 0U)
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
huart->Instance->BRR = brrtemp;
}
else
{
ret = HAL_ERROR;
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
huart->Instance->BRR = brrtemp;
}
else
{
ret = HAL_ERROR;
}
}
}
else
@ -3077,49 +3053,52 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
case UART_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = pll2_clocks.PLL2_Q_Frequency;
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = pll3_clocks.PLL3_Q_Frequency;
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
}
else
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t) HSI_VALUE;
}
break;
case UART_CLOCKSOURCE_CSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t) CSI_VALUE;
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
pclk = (uint32_t) LSE_VALUE;
break;
default:
pclk = 0U;
ret = HAL_ERROR;
break;
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
if (pclk != 0U)
{
huart->Instance->BRR = usartdiv;
}
else
{
ret = HAL_ERROR;
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
huart->Instance->BRR = usartdiv;
}
else
{
ret = HAL_ERROR;
}
}
}
@ -3292,7 +3271,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
@ -3300,10 +3279,10 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
}

4
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
View File

@ -60,10 +60,10 @@
* @{
*/
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
#define RX_FIFO_DEPTH 16U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
#define TX_FIFO_DEPTH 16U
/**
* @}
*/

45
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
View File

@ -289,6 +289,8 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
@ -389,17 +391,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
if (cfg.dma_enable == 1U)
{
/*Set threshold parameters */
USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
USB_OTG_DTHRCTL_RXTHRLEN_6;
USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
USB_OTG_DTHRCTL_ISOTHREN |
USB_OTG_DTHRCTL_NONISOTHREN;
}
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@ -621,6 +612,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
@ -631,6 +628,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
@ -656,11 +659,23 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
}
USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
}
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
@ -1227,13 +1242,9 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
/* Set the MPS of the IN EP based on the enumeration speed */
/* Set the MPS of the IN EP0 to 64 bytes */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
{
USBx_INEP(0U)->DIEPCTL |= 3U;
}
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
return HAL_OK;
@ -1337,7 +1348,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
if ((USBx->CID & (0x1U << 8)) != 0U)
{
if (cfg.speed == USB_OTG_SPEED_FULL)
if (cfg.speed == USBH_FSLS_SPEED)
{
/* Force Device Enumeration to FS/LS mode only */
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;

215
Makefile Normal file
View File

@ -0,0 +1,215 @@
##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Sun Dec 20 04:41:46 CST 2020]
##########################################################################################################################
# ------------------------------------------------
# Generic Makefile (based on gcc)
#
# ChangeLog :
# 2017-02-10 - Several enhancements + project update mode
# 2015-07-22 - first version
# ------------------------------------------------
######################################
# target
######################################
TARGET = STM32H750VB_Bootloader
######################################
# building variables
######################################
# debug build?
DEBUG = 1
# optimization
OPT = -Og
#######################################
# paths
#######################################
# Build path
BUILD_DIR = build
######################################
# source
######################################
# C sources
C_SOURCES = \
Core/Src/main.c \
Core/Src/stm32h7xx_it.c \
Core/Src/stm32h7xx_hal_msp.c \
Core/Src/w25_qspi.c \
Core/Src/port_printf.c \
Core/Src/printf.c \
Core/Src/bootloader_control.c \
USB_DEVICE/App/usb_device.c \
USB_DEVICE/App/usbd_desc.c \
USB_DEVICE/App/usbd_dfu_if.c \
USB_DEVICE/Target/usbd_conf.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \
Core/Src/system_stm32h7xx.c \
Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \
Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \
Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c
# ASM sources
ASM_SOURCES = \
startup_stm32h750xx.s
#######################################
# binaries
#######################################
PREFIX = arm-none-eabi-
# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
# either it can be added to the PATH environment variable.
ifdef GCC_PATH
CC = $(GCC_PATH)/$(PREFIX)gcc
AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
CP = $(GCC_PATH)/$(PREFIX)objcopy
SZ = $(GCC_PATH)/$(PREFIX)size
else
CC = $(PREFIX)gcc
AS = $(PREFIX)gcc -x assembler-with-cpp
CP = $(PREFIX)objcopy
SZ = $(PREFIX)size
endif
HEX = $(CP) -O ihex
BIN = $(CP) -O binary -S
#######################################
# CFLAGS
#######################################
# cpu
CPU = -mcpu=cortex-m7
# fpu
FPU = -mfpu=fpv5-d16
# float-abi
FLOAT-ABI = -mfloat-abi=hard
# mcu
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
# macros for gcc
# AS defines
AS_DEFS =
# C defines
C_DEFS = \
-DUSE_HAL_DRIVER \
-DSTM32H750xx
# AS includes
AS_INCLUDES =
# C includes
C_INCLUDES = \
-IUSB_DEVICE/App \
-IUSB_DEVICE/Target \
-ICore/Inc \
-IDrivers/STM32H7xx_HAL_Driver/Inc \
-IDrivers/STM32H7xx_HAL_Driver/Inc/Legacy \
-IMiddlewares/ST/STM32_USB_Device_Library/Core/Inc \
-IMiddlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc \
-IDrivers/CMSIS/Device/ST/STM32H7xx/Include \
-IDrivers/CMSIS/Include
# compile gcc flags
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
ifeq ($(DEBUG), 1)
CFLAGS += -g -gdwarf-2
endif
# Generate dependency information
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
#######################################
# LDFLAGS
#######################################
# link script
LDSCRIPT = STM32H750VBTx_FLASH.ld
# libraries
LIBS = -lc -lm -lnosys
LIBDIR =
LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
# default action: build all
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
#######################################
# build the application
#######################################
# list of objects
OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
vpath %.c $(sort $(dir $(C_SOURCES)))
# list of ASM program objects
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
vpath %.s $(sort $(dir $(ASM_SOURCES)))
$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
$(AS) -c $(CFLAGS) $< -o $@
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
$(CC) $(OBJECTS) $(LDFLAGS) -o $@
$(SZ) $@
$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
$(HEX) $< $@
$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
$(BIN) $< $@
$(BUILD_DIR):
mkdir $@
#######################################
# clean up
#######################################
clean:
-rm -fR $(BUILD_DIR)
#######################################
# dependencies
#######################################
-include $(wildcard $(BUILD_DIR)/*.d)
# *** EOF ***

36
Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h
View File

@ -115,7 +115,7 @@ extern "C" {
/* Other defines */
/**************************************************/
/* Bit Detach capable = bit 3 in bmAttributes field */
#define DFU_DETACH_MASK (uint8_t)(1 << 4)
#define DFU_DETACH_MASK (1U << 4)
#define DFU_STATUS_DEPTH 6U
typedef enum
@ -133,7 +133,7 @@ typedef void (*pFunction)(void);
/********** Descriptor of DFU interface 0 Alternate setting n ****************/
#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \
#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \
USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ \
0x00, /* bInterfaceNumber: Number of Interface */ \
(n), /* bAlternateSetting: Alternate setting */ \
@ -162,20 +162,19 @@ typedef struct
union
{
uint32_t d32[USBD_DFU_XFER_SIZE / 4U];
uint8_t d8[USBD_DFU_XFER_SIZE];
uint8_t d8[USBD_DFU_XFER_SIZE];
} buffer;
uint32_t wblock_num;
uint32_t wlength;
uint32_t data_ptr;
uint32_t alt_setting;
uint32_t wblock_num;
uint32_t wlength;
uint32_t data_ptr;
uint32_t alt_setting;
uint8_t dev_status[DFU_STATUS_DEPTH];
uint8_t ReservedForAlign[2];
uint8_t dev_state;
uint8_t manif_state;
}
USBD_DFU_HandleTypeDef;
uint8_t dev_status[DFU_STATUS_DEPTH];
uint8_t ReservedForAlign[2];
uint8_t dev_state;
uint8_t manif_state;
} USBD_DFU_HandleTypeDef;
typedef struct
{
@ -186,8 +185,7 @@ typedef struct
uint16_t (* Write)(uint8_t *src, uint8_t *dest, uint32_t Len);
uint8_t *(* Read)(uint8_t *src, uint8_t *dest, uint32_t Len);
uint16_t (* GetStatus)(uint32_t Add, uint8_t cmd, uint8_t *buff);
}
USBD_DFU_MediaTypeDef;
} USBD_DFU_MediaTypeDef;
/**
* @}
*/
@ -206,8 +204,8 @@ USBD_DFU_MediaTypeDef;
* @{
*/
extern USBD_ClassTypeDef USBD_DFU;
#define USBD_DFU_CLASS &USBD_DFU
extern USBD_ClassTypeDef USBD_DFU;
#define USBD_DFU_CLASS &USBD_DFU
/**
* @}
*/
@ -215,8 +213,8 @@ extern USBD_ClassTypeDef USBD_DFU;
/** @defgroup USB_CORE_Exported_Functions
* @{
*/
uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev,
USBD_DFU_MediaTypeDef *fops);
uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev,
USBD_DFU_MediaTypeDef *fops);
/**
* @}
*/

754
Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c
View File

File diff suppressed because it is too large Load Diff

63
Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h
View File

@ -88,53 +88,50 @@ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed);
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed);
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev);
/* USBD Low Level Driver */
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
uint8_t ep_addr,
uint8_t ep_type,
uint16_t ep_mps);
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
uint8_t ep_addr,
uint8_t *pbuf,
uint16_t size);
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
uint8_t ep_type, uint16_t ep_mps);
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
uint8_t ep_addr,
uint8_t *pbuf,
uint16_t size);
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
uint8_t *pbuf, uint32_t size);
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
uint8_t *pbuf, uint32_t size);
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
void USBD_LL_Delay(uint32_t Delay);
/**

12
Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
View File

@ -73,16 +73,14 @@ extern "C" {
* @{
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
/**
* @}
*/

79
Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
View File

@ -65,6 +65,10 @@ extern "C" {
#define USBD_SUPPORT_USER_STRING_DESC 0U
#endif /* USBD_SUPPORT_USER_STRING_DESC */
#ifndef USBD_CLASS_USER_STRING_DESC
#define USBD_CLASS_USER_STRING_DESC 0U
#endif /* USBD_CLASS_USER_STRING_DESC */
#define USB_LEN_DEV_QUALIFIER_DESC 0x0AU
#define USB_LEN_DEV_DESC 0x12U
#define USB_LEN_CFG_DESC 0x09U
@ -165,6 +169,28 @@ typedef struct usb_setup_req
uint16_t wLength;
} USBD_SetupReqTypedef;
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t wDescriptorLengthLow;
uint8_t wDescriptorLengthHigh;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t bMaxPower;
} USBD_ConfigDescTypedef;
typedef struct
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumDeviceCaps;
} USBD_BosDescTypedef;
struct _USBD_HandleTypeDef;
typedef struct _Device_cb
@ -203,34 +229,39 @@ typedef enum
/* Following USB Device status */
typedef enum
{
USBD_OK = 0U,
USBD_OK = 0U,
USBD_BUSY,
USBD_EMEM,
USBD_FAIL,
} USBD_StatusTypeDef;
/* USB Device descriptors structure */
typedef struct
{
uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#if (USBD_LPM_ENABLED == 1U)
uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#if (USBD_CLASS_USER_STRING_DESC == 1)
uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);
#endif
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1))
uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#endif
} USBD_DescriptorsTypeDef;
/* USB Device handle structure */
typedef struct
{
uint32_t status;
uint32_t is_used;
uint32_t total_length;
uint32_t rem_length;
uint32_t maxpacket;
uint32_t status;
uint32_t total_length;
uint32_t rem_length;
uint32_t maxpacket;
uint16_t is_used;
uint16_t bInterval;
} USBD_EndpointTypeDef;
/* USB Device handle structure */
@ -251,6 +282,7 @@ typedef struct _USBD_HandleTypeDef
uint8_t dev_connection_status;
uint8_t dev_test_mode;
uint32_t dev_remote_wakeup;
uint8_t ConfIdx;
USBD_SetupReqTypedef request;
USBD_DescriptorsTypeDef *pDesc;
@ -258,6 +290,8 @@ typedef struct _USBD_HandleTypeDef
void *pClassData;
void *pUserData;
void *pData;
void *pBosDesc;
void *pConfDesc;
} USBD_HandleTypeDef;
/**
@ -269,8 +303,19 @@ typedef struct _USBD_HandleTypeDef
/** @defgroup USBD_DEF_Exported_Macros
* @{
*/
#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
{
uint16_t _SwapVal, _Byte1, _Byte2;
uint8_t *_pbuff = addr;
_Byte1 = *(uint8_t *)_pbuff;
_pbuff++;
_Byte2 = *(uint8_t *)_pbuff;
_SwapVal = (_Byte2 << 8) | _Byte1;
return _SwapVal;
}
#define LOBYTE(x) ((uint8_t)((x) & 0x00FFU))
#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))

27
Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
View File

@ -77,27 +77,22 @@ extern "C" {
* @{
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf,
uint16_t len);
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf,
uint16_t len);
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf,
uint16_t len);
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf,
uint16_t len);
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len);
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev);
uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
/**
* @}

204
Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
View File

@ -89,6 +89,8 @@
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
USBD_StatusTypeDef ret;
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
{
@ -98,12 +100,17 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
return USBD_FAIL;
}
/* Unlink previous class*/
/* Unlink previous class */
if (pdev->pClass != NULL)
{
pdev->pClass = NULL;
}
if (pdev->pConfDesc != NULL)
{
pdev->pConfDesc = NULL;
}
/* Assign USBD Descriptors */
if (pdesc != NULL)
{
@ -113,10 +120,11 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
pdev->id = id;
/* Initialize low level driver */
USBD_LL_Init(pdev);
return USBD_OK;
/* Initialize low level driver */
ret = USBD_LL_Init(pdev);
return ret;
}
/**
@ -127,19 +135,34 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
*/
USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
{
USBD_StatusTypeDef ret;
/* Set Default State */
pdev->dev_state = USBD_STATE_DEFAULT;
/* Free Class Resources */
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
if (pdev->pClass != NULL)
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
}
if (pdev->pConfDesc != NULL)
{
pdev->pConfDesc = NULL;
}
/* Stop the low level driver */
USBD_LL_Stop(pdev);
ret = USBD_LL_Stop(pdev);
if (ret != USBD_OK)
{
return ret;
}
/* Initialize low level driver */
USBD_LL_DeInit(pdev);
ret = USBD_LL_DeInit(pdev);
return USBD_OK;
return ret;
}
/**
@ -149,24 +172,30 @@ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
USBD_StatusTypeDef status = USBD_OK;
if (pclass != NULL)
{
/* link the class to the USB Device handle */
pdev->pClass = pclass;
status = USBD_OK;
}
else
uint16_t len = 0U;
if (pclass == NULL)
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif
status = USBD_FAIL;
return USBD_FAIL;
}
return status;
/* link the class to the USB Device handle */
pdev->pClass = pclass;
/* Get Device Configuration Descriptor */
#ifdef USE_USB_FS
pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len);
#else /* USE_USB_HS */
pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len);
#endif /* USE_USB_FS */
return USBD_OK;
}
/**
@ -175,12 +204,10 @@ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeD
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
/* Start the low level driver */
USBD_LL_Start(pdev);
return USBD_OK;
return USBD_LL_Start(pdev);
}
/**
@ -189,15 +216,25 @@ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev)
USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev)
{
USBD_StatusTypeDef ret;
/* Free Class Resources */
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
if (pdev->pClass != NULL)
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
}
if (pdev->pConfDesc != NULL)
{
pdev->pConfDesc = NULL;
}
/* Stop the low level driver */
USBD_LL_Stop(pdev);
ret = USBD_LL_Stop(pdev);
return USBD_OK;
return ret;
}
/**
@ -206,7 +243,7 @@ USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev)
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
/* Prevent unused argument compilation warning */
UNUSED(pdev);
@ -222,17 +259,14 @@ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
USBD_StatusTypeDef ret = USBD_FAIL;
if (pdev->pClass != NULL)
{
/* Set configuration and Start the Class*/
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
{
ret = USBD_OK;
}
/* Set configuration and Start the Class */
ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx);
}
return ret;
@ -245,10 +279,13 @@ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx
* @param cfgidx: configuration index
* @retval status: USBD_StatusTypeDef
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
/* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx);
/* Clear configuration and De-initialize the Class process */
if (pdev->pClass != NULL)
{
pdev->pClass->DeInit(pdev, cfgidx);
}
return USBD_OK;
}
@ -262,6 +299,8 @@ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
USBD_StatusTypeDef ret;
USBD_ParseSetupRequest(&pdev->request, psetup);
pdev->ep0_state = USBD_EP0_SETUP;
@ -271,23 +310,23 @@ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
switch (pdev->request.bmRequest & 0x1FU)
{
case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq(pdev, &pdev->request);
ret = USBD_StdDevReq(pdev, &pdev->request);
break;
case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request);
ret = USBD_StdItfReq(pdev, &pdev->request);
break;
case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request);
ret = USBD_StdEPReq(pdev, &pdev->request);
break;
default:
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
break;
}
return USBD_OK;
return ret;
}
/**
@ -301,6 +340,7 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret;
if (epnum == 0U)
{
@ -312,8 +352,7 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
{
pep->rem_length -= pep->maxpacket;
USBD_CtlContinueRx(pdev, pdata,
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
(void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket));
}
else
{
@ -322,25 +361,32 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
{
pdev->pClass->EP0_RxReady(pdev);
}
USBD_CtlSendStatus(pdev);
(void)USBD_CtlSendStatus(pdev);
}
}
else
{
#if 0
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
USBD_LL_StallEP(pdev, 0U);
(void)USBD_LL_StallEP(pdev, 0U);
}
#endif
}
}
else if ((pdev->pClass->DataOut != NULL) &&
(pdev->dev_state == USBD_STATE_CONFIGURED))
{
pdev->pClass->DataOut(pdev, epnum);
ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum);
if (ret != USBD_OK)
{
return ret;
}
}
else
{
@ -362,6 +408,7 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret;
if (epnum == 0U)
{
@ -373,23 +420,23 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
{
pep->rem_length -= pep->maxpacket;
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
(void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length);
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->total_length % pep->maxpacket == 0U) &&
if ((pep->maxpacket == pep->rem_length) &&
(pep->total_length >= pep->maxpacket) &&
(pep->total_length < pdev->ep0_data_len))
{
USBD_CtlContinueSendData(pdev, NULL, 0U);
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
pdev->ep0_data_len = 0U;
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
}
else
{
@ -398,30 +445,37 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
{
pdev->pClass->EP0_TxSent(pdev);
}
USBD_LL_StallEP(pdev, 0x80U);
USBD_CtlReceiveStatus(pdev);
(void)USBD_LL_StallEP(pdev, 0x80U);
(void)USBD_CtlReceiveStatus(pdev);
}
}
}
else
{
#if 0
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
(pdev->ep0_state == USBD_EP0_IDLE))
{
USBD_LL_StallEP(pdev, 0x80U);
(void)USBD_LL_StallEP(pdev, 0x80U);
}
#endif
}
if (pdev->dev_test_mode == 1U)
{
USBD_RunTestMode(pdev);
(void)USBD_RunTestMode(pdev);
pdev->dev_test_mode = 0U;
}
}
else if ((pdev->pClass->DataIn != NULL) &&
(pdev->dev_state == USBD_STATE_CONFIGURED))
{
pdev->pClass->DataIn(pdev, epnum);
ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum);
if (ret != USBD_OK)
{
return ret;
}
}
else
{
@ -441,29 +495,29 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
/* Open EP0 OUT */
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
/* Open EP0 IN */
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
pdev->ep0_state = USBD_EP0_IDLE;
pdev->dev_config = 0U;
pdev->dev_remote_wakeup = 0U;
if (pdev->pClassData)
if (pdev->pClassData != NULL)
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
}
/* Open EP0 OUT */
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
/* Open EP0 IN */
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
return USBD_OK;
}
@ -490,8 +544,8 @@ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
pdev->dev_old_state = pdev->dev_state;
pdev->dev_state = USBD_STATE_SUSPENDED;
pdev->dev_old_state = pdev->dev_state;
pdev->dev_state = USBD_STATE_SUSPENDED;
return USBD_OK;
}
@ -589,7 +643,11 @@ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
{
/* Free Class Resources */
pdev->dev_state = USBD_STATE_DEFAULT;
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
if (pdev->pClass != NULL)
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
}
return USBD_OK;
}

980
Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
View File

File diff suppressed because it is too large Load Diff

24
Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
View File

@ -85,15 +85,15 @@
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
uint8_t *pbuf, uint32_t len)
{
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
pdev->ep_in[0].total_length = len;
pdev->ep_in[0].rem_length = len;
pdev->ep_in[0].rem_length = len;
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
return USBD_OK;
}
@ -107,10 +107,10 @@ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
uint8_t *pbuf, uint32_t len)
{
/* Start the next transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
return USBD_OK;
}
@ -124,15 +124,15 @@ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
uint8_t *pbuf, uint32_t len)
{
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
pdev->ep_out[0].total_length = len;
pdev->ep_out[0].rem_length = len;
pdev->ep_out[0].rem_length = len;
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
return USBD_OK;
}
@ -146,9 +146,9 @@ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
uint8_t *pbuf, uint32_t len)
{
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
return USBD_OK;
}
@ -165,7 +165,7 @@ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
pdev->ep0_state = USBD_EP0_STATUS_IN;
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
return USBD_OK;
}
@ -182,7 +182,7 @@ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
pdev->ep0_state = USBD_EP0_STATUS_OUT;
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
return USBD_OK;
}

2
STM32H750VBTx_FLASH.ld
View File

@ -55,7 +55,7 @@ ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20020000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x1000; /* required amount of heap */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */

480
STM32H750VB_Bootloader.ioc
View File

@ -1,253 +1,265 @@
#MicroXplorer Configuration settings - do not modify
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0x0
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000
CORTEX_M7.CPU_DCache=Disabled
CORTEX_M7.CPU_ICache=Enabled
CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_BUFFERABLE
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
CORTEX_M7.MPU_Control=__NULL
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_8MB
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32H7
Mcu.IP0=CORTEX_M7
Mcu.IP1=DEBUG
Mcu.IP2=NVIC
Mcu.IP3=QUADSPI
NVIC.FLASH_IRQn=true\:0\:0\:false\:false\:true\:true\:true
QUADSPI.ClockMode=QSPI_CLOCK_MODE_3
RCC.DIVQ2Freq_Value=16000000
ProjectManager.MainLocation=Core/Src
USB_DEVICE.CLASS_NAME_FS=DFU
RCC.SAI1Freq_Value=160000000
RCC.CortexFreq_Value=80000000
ProjectManager.KeepUserCode=true
Mcu.UserName=STM32H750VBTx
QUADSPI.ClockPrescaler=2
RCC.HPRE=RCC_HCLK_DIV2
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
USART1.BaudRate=921600
PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_QUADSPI_Init-QUADSPI-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
PA11.Mode=Device_Only
RCC.RTCFreq_Value=32000
RCC.CpuClockFreq_Value=80000000
RCC.VCO2OutputFreq_Value=32000000
NVIC.OTG_FS_EP1_IN_IRQn=true\:1\:0\:true\:false\:true\:true\:true
USART1.IPParameters=VirtualMode-Asynchronous,BaudRate
VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Mode=DFU_FS
PinOutPanel.RotationAngle=0
RCC.MCO1PinFreq_Value=64000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
ProjectManager.StackSize=0x400
RCC.AHB4Freq_Value=40000000
RCC.VCOInput3Freq_Value=320000
RCC.LPTIM1Freq_Value=20000000
PD13.Signal=QUADSPI_BK1_IO3
Mcu.IP4=RCC
Mcu.IP5=SYS
Mcu.IP6=USART1
Mcu.IP7=USB_DEVICE
Mcu.IP8=USB_OTG_FS
PD13.Locked=true
Mcu.IP2=NVIC
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
Mcu.IP3=QUADSPI
Mcu.IP0=CORTEX_M7
PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE
Mcu.IP1=DEBUG
PA12.Signal=USB_OTG_FS_DP
Mcu.UserConstants=
RCC.DIVP3Freq_Value=38400000
RCC.SDMMCFreq_Value=160000000
Mcu.ThirdPartyNb=0
RCC.HCLKFreq_Value=40000000
RCC.I2C4Freq_Value=20000000
PE2.Mode=Single Bank 1
Mcu.IPNb=9
Mcu.Name=STM32H750VBTx
Mcu.Package=LQFP100
ProjectManager.PreviousToolchain=SW4STM32
PB6.Signal=QUADSPI_BK1_NCS
RCC.SPDIFRXFreq_Value=160000000
PB6.Mode=Single Bank 1
RCC.DIVQ3Freq_Value=15360000
Mcu.Pin6=PA1
Mcu.Pin7=PB2
Mcu.Pin8=PD11
Mcu.Pin9=PD12
QUADSPI.FlashSize=24
Mcu.Pin0=PE2
Mcu.Pin1=PE3
Mcu.Pin10=PA9
Mcu.Pin11=PA10
Mcu.Pin12=PA11
Mcu.Pin13=PA12
Mcu.Pin14=PA13 (JTMS/SWDIO)
Mcu.Pin15=PA14 (JTCK/SWCLK)
Mcu.Pin16=PB6
Mcu.Pin17=VP_SYS_VS_Systick
Mcu.Pin18=VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS
GPIO.groupedBy=Group By Peripherals
Mcu.Pin2=PC14-OSC32_IN (OSC32_IN)
RCC.HRTIMFreq_Value=40000000
Mcu.Pin3=PC15-OSC32_OUT (OSC32_OUT)
Mcu.Pin4=PH0-OSC_IN (PH0)
Mcu.Pin5=PH1-OSC_OUT (PH1)
Mcu.Pin6=PB2
Mcu.Pin7=PD11
Mcu.Pin8=PD12
Mcu.Pin9=PD13
Mcu.PinsNb=19
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32H750VBTx
MxCube.Version=5.4.0
MxDb.Version=DB.5.0.40
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.FLASH_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.FPU_IRQn=true\:0\:0\:false\:false\:true\:true\:false
NVIC.ForceEnableDMAVector=true
NVIC.HSEM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.OTG_FS_EP1_IN_IRQn=true\:1\:0\:true\:false\:true\:true\:true
NVIC.OTG_FS_EP1_OUT_IRQn=true\:1\:0\:true\:false\:true\:true\:true
NVIC.OTG_FS_IRQn=true\:2\:0\:true\:false\:true\:false\:true
NVIC.PVD_AVD_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.QUADSPI_IRQn=true\:1\:0\:true\:false\:true\:true\:true
NVIC.RCC_IRQn=true\:0\:0\:false\:false\:true\:true\:false
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.USART1_IRQn=true\:1\:0\:true\:false\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PA10.Locked=true
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
PA11.Mode=Device_Only
PA11.Signal=USB_OTG_FS_DM
PA12.Mode=Device_Only
PA12.Signal=USB_OTG_FS_DP
PA13\ (JTMS/SWDIO).Mode=Serial_Wire
PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
PA14\ (JTCK/SWCLK).Mode=Serial_Wire
PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
PA9.Locked=true
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB2.Mode=Single Bank 1
PB2.Signal=QUADSPI_CLK
PB6.Locked=true
PB6.Mode=Single Bank 1
PB6.Signal=QUADSPI_BK1_NCS
PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT
PCC.Checker=true
PCC.Line=STM32H750 Value line
PCC.MCU=STM32H750VBTx
PCC.PartNumber=STM32H750VBTx
PCC.Seq0=0
PCC.Series=STM32H7
PCC.Temperature=25
PCC.Vdd=3.0
PD11.Mode=Single Bank 1
PD11.Signal=QUADSPI_BK1_IO0
PD12.Mode=Single Bank 1
PD12.Signal=QUADSPI_BK1_IO1
PD13.Locked=true
PD13.Mode=Single Bank 1
PD13.Signal=QUADSPI_BK1_IO3
PE2.Mode=Single Bank 1
PE2.Signal=QUADSPI_BK1_IO2
PE3.GPIOParameters=GPIO_PuPd
PE3.GPIO_PuPd=GPIO_PULLUP
PE3.Locked=true
PE3.Signal=GPIO_Input
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
ProjectManager.ProjectBuild=false
PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
RCC.DIVR3Freq_Value=38400000
RCC.HSE_VALUE=8000000
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PB2.Signal=QUADSPI_CLK
RCC.DIVM3=25
RCC.DIVM2=25
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
RCC.DIVM1=2
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0
MxDb.Version=DB.6.0.10
RCC.DIVP1Freq_Value=80000000
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
RCC.FMCFreq_Value=40000000
RCC.USART16Freq_Value=20000000
File.Version=6
PE3.GPIOParameters=GPIO_PuPd
PE3.Locked=true
PE2.Signal=QUADSPI_BK1_IO2
PA14\ (JTCK/SWCLK).Mode=Serial_Wire
PB6.Locked=true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
RCC.DIVR2Freq_Value=16000000
CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
ProjectManager.HalAssertFull=false
RCC.DIVP2Freq_Value=16000000
ProjectManager.ProjectName=STM32H750VB_Bootloader
RCC.APB3Freq_Value=20000000
RCC.MCO2PinFreq_Value=80000000
Mcu.Package=LQFP100
RCC.PLL3FRACN=0
PD11.Locked=true
RCC.D1PPRE=RCC_APB3_DIV2
USB_DEVICE.USBD_DEBUG_LEVEL-DFU_FS=0
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000
PD12.Signal=QUADSPI_BK1_IO1
NVIC.OTG_FS_IRQn=true\:2\:0\:true\:false\:true\:false\:true
ProjectManager.ToolChainLocation=
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
PA10.Signal=USART1_RX
USB_OTG_FS.VirtualMode=Device_Only
RCC.DFSDMFreq_Value=20000000
RCC.DIVR1Freq_Value=160000000
USB_DEVICE.USBD_DFU_MEDIA-DFU_FS=@QSPI Flash/0x90000000/2048*4Kg
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_8MB
PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
RCC.TraceFreq_Value=160000000
RCC.APB4Freq_Value=20000000
RCC.CECFreq_Value=32000
RCC.SAI23Freq_Value=160000000
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
RCC.LPUART1Freq_Value=20000000
USB_OTG_FS.IPParameters=VirtualMode
NVIC.USART1_IRQn=true\:1\:0\:true\:false\:true\:true\:true
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
ProjectManager.CustomerFirmwarePackage=
RCC.Tim2OutputFreq_Value=40000000
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_BUFFERABLE
NVIC.RCC_IRQn=true\:0\:0\:false\:false\:true\:true\:false
RCC.DFSDMACLkFreq_Value=160000000
RCC.VCO3OutputFreq_Value=76800000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_3_CYCLE
NVIC.QUADSPI_IRQn=true\:1\:0\:true\:false\:true\:true\:true
ProjectManager.ProjectFileName=STM32H750VB_Bootloader.ioc
RCC.DIVQ3=5
CORTEX_M7.CPU_ICache=Disabled
RCC.DIVQ1=1
PA13\ (JTMS/SWDIO).Mode=Serial_Wire
Mcu.PinsNb=20
PA10.Mode=Asynchronous
ProjectManager.NoMain=false
USB_DEVICE.VirtualModeFS=Dfu_FS
RCC.SWPMI1Freq_Value=20000000
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE
RCC.SAI4BFreq_Value=160000000
VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Signal=USB_DEVICE_VS_USB_DEVICE_DFU_FS
RCC.D2PPRE2=RCC_APB2_DIV2
RCC.D2PPRE1=RCC_APB1_DIV2
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32H750VBTx
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.5.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x1000
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=SW4STM32
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32H750VB_Bootloader.ioc
ProjectManager.ProjectName=STM32H750VB_Bootloader
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=SW4STM32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_QUADSPI_Init-QUADSPI-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false
QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_5_CYCLE
QUADSPI.ClockPrescaler=16
QUADSPI.FifoThreshold=4
QUADSPI.FlashSize=23
QUADSPI.IPParameters=FlashSize,ChipSelectHighTime,ClockPrescaler,FifoThreshold
RCC.ADCFreq_Value=50390625
RCC.AHB12Freq_Value=60000000
RCC.AHB4Freq_Value=60000000
RCC.APB1Freq_Value=60000000
RCC.APB2Freq_Value=60000000
RCC.APB3Freq_Value=60000000
RCC.APB4Freq_Value=60000000
RCC.AXIClockFreq_Value=60000000
RCC.CECFreq_Value=32000
RCC.CKPERFreq_Value=64000000
RCC.CortexFreq_Value=120000000
RCC.CpuClockFreq_Value=120000000
RCC.D1CPREFreq_Value=120000000
RCC.DFSDMACLkFreq_Value=48000000
RCC.DFSDMFreq_Value=60000000
RCC.DIVM1=25
RCC.DIVM3=25
RCC.DIVN1=240
RCC.DIVN3=192
RCC.DIVP1Freq_Value=120000000
RCC.DIVP2Freq_Value=50390625
RCC.DIVP3Freq_Value=96000000
RCC.DIVQ1=5
RCC.DIVQ1Freq_Value=48000000
RCC.DIVQ2Freq_Value=50390625
RCC.DIVQ3=4
RCC.DIVQ3Freq_Value=48000000
RCC.DIVR1Freq_Value=120000000
RCC.DIVR2Freq_Value=50390625
RCC.DIVR3Freq_Value=96000000
RCC.EnbaleCSS=true
RCC.FDCANFreq_Value=48000000
RCC.FMCFreq_Value=60000000
RCC.FamilyName=M
RCC.HCLK3ClockFreq_Value=60000000
RCC.HCLKFreq_Value=60000000
RCC.HPRE=RCC_HCLK_DIV2
RCC.HRTIMFreq_Value=60000000
RCC.I2C123Freq_Value=60000000
RCC.I2C4Freq_Value=60000000
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
RCC.LPTIM1Freq_Value=60000000
RCC.LPTIM2Freq_Value=60000000
RCC.LPTIM345Freq_Value=60000000
RCC.LPUART1Freq_Value=60000000
RCC.LTDCFreq_Value=96000000
RCC.MCO1PinFreq_Value=64000000
RCC.MCO2PinFreq_Value=120000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.QSPIFreq_Value=60000000
RCC.RNGFreq_Value=48000000
RCC.RTCFreq_Value=32000
RCC.SAI1Freq_Value=48000000
RCC.SAI23Freq_Value=48000000
RCC.SAI4AFreq_Value=48000000
RCC.SAI4BFreq_Value=48000000
RCC.SDMMCFreq_Value=48000000
RCC.SPDIFRXFreq_Value=48000000
RCC.SPI123Freq_Value=48000000
RCC.SPI45Freq_Value=60000000
RCC.SPI6Freq_Value=60000000
RCC.SWPMI1Freq_Value=60000000
RCC.SYSCLKFreq_VALUE=120000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.Tim1OutputFreq_Value=60000000
RCC.Tim2OutputFreq_Value=60000000
RCC.TraceFreq_Value=120000000
RCC.USART16Freq_Value=60000000
RCC.USART234578Freq_Value=60000000
RCC.USBFreq_Value=48000000
RCC.VCO1OutputFreq_Value=240000000
RCC.VCO2OutputFreq_Value=100781250
RCC.VCO3OutputFreq_Value=192000000
RCC.VCOInput1Freq_Value=1000000
RCC.VCOInput2Freq_Value=781250
RCC.VCOInput3Freq_Value=1000000
USART1.BaudRate=921600
USART1.IPParameters=VirtualMode-Asynchronous,BaudRate
USART1.VirtualMode-Asynchronous=VM_ASYNC
USB_DEVICE.CLASS_NAME_FS=DFU
RCC.QSPIFreq_Value=64000000
USB_DEVICE.IPParameters=VirtualMode-DFU_FS,VirtualModeFS,CLASS_NAME_FS,USBD_DFU_XFER_SIZE-DFU_FS,USBD_DFU_APP_DEFAULT_ADD-DFU_FS,USBD_DFU_MEDIA-DFU_FS,USBD_DEBUG_LEVEL-DFU_FS
USB_DEVICE.USBD_DEBUG_LEVEL-DFU_FS=0
QUADSPI.IPParameters=FlashSize,ChipSelectHighTime,ClockPrescaler,FifoThreshold,ClockMode
RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
RCC.FamilyName=M
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
PD12.Locked=true
RCC.SPI6Freq_Value=20000000
RCC.D1CPREFreq_Value=80000000
USART1.VirtualMode-Asynchronous=VM_ASYNC
CORTEX_M7.MPU_Control=__NULL
RCC.USART234578Freq_Value=20000000
PA9.Mode=Asynchronous
RCC.SPI45Freq_Value=20000000
RCC.Tim1OutputFreq_Value=40000000
RCC.SPI123Freq_Value=160000000
ProjectManager.TargetToolchain=Makefile
PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT
RCC.VCO1OutputFreq_Value=160000000
PA9.Signal=USART1_TX
RCC.DIVN3=240
RCC.HSE_Timout=1000
RCC.DIVN2=100
RCC.AXIClockFreq_Value=40000000
PD13.Mode=Single Bank 1
RCC.DIVN1=40
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0x0
ProjectManager.RegisterCallBack=
RCC.USBFreq_Value=48000000
PA1.Signal=GPIO_Output
RCC.CKPERFreq_Value=64000000
NVIC.PVD_AVD_IRQn=true\:0\:0\:false\:false\:true\:true\:true
RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48
USB_DEVICE.USBD_DFU_APP_DEFAULT_ADD-DFU_FS=0x90000000
USB_DEVICE.USBD_DFU_MEDIA-DFU_FS=@QSPI Flash/0x90000000/2048*4Kg
USB_DEVICE.USBD_DFU_XFER_SIZE-DFU_FS=4096
USB_DEVICE.VirtualMode-DFU_FS=Dfu
USB_DEVICE.VirtualModeFS=Dfu_FS
USB_OTG_FS.IPParameters=VirtualMode
USB_OTG_FS.VirtualMode=Device_Only
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Mode=DFU_FS
VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Signal=USB_DEVICE_VS_USB_DEVICE_DFU_FS
board=custom
ProjectManager.LastFirmware=true
RCC.VCOInput1Freq_Value=4000000
RCC.AHB12Freq_Value=40000000
RCC.APB2Freq_Value=20000000
MxCube.Version=6.1.1
USB_DEVICE.VirtualMode-DFU_FS=Dfu
RCC.FDCANFreq_Value=160000000
RCC.RNGFreq_Value=48000000
RCC.ADCFreq_Value=16000000
VP_SYS_VS_Systick.Mode=SysTick
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS
PE3.GPIO_PuPd=GPIO_PULLUP
PA9.Locked=true
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.HSEM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
QUADSPI.FifoThreshold=4
ProjectManager.FreePins=false
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_Timout,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL3FRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
ProjectManager.AskForMigrate=true
Mcu.Name=STM32H750VBTx
RCC.LPTIM2Freq_Value=20000000
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB
NVIC.OTG_FS_EP1_OUT_IRQn=true\:1\:0\:true\:false\:true\:true\:true
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS
ProjectManager.UnderRoot=false
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings
Mcu.IP8=USB_OTG_FS
Mcu.IP6=USART1
Mcu.IP7=USB_DEVICE
ProjectManager.CoupleFile=false
RCC.SYSCLKFreq_VALUE=80000000
RCC.I2C123Freq_Value=20000000
PA1.Locked=true
PD12.Mode=Single Bank 1
PA12.Mode=Device_Only
PA10.Locked=true
NVIC.ForceEnableDMAVector=true
KeepUserPlacement=false
PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
PD11.Signal=QUADSPI_BK1_IO0
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PB2.Mode=Single Bank 1
ProjectManager.CompilerOptimize=6
RCC.QSPICLockSelection=RCC_QSPICLKSOURCE_CLKP
PA11.Signal=USB_OTG_FS_DM
ProjectManager.HeapSize=0x200
Mcu.Pin15=PA13 (JTMS/SWDIO)
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
Mcu.Pin16=PA14 (JTCK/SWCLK)
Mcu.Pin13=PA11
PD11.Mode=Single Bank 1
Mcu.Pin14=PA12
Mcu.Pin19=VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS
RCC.LPTIM345Freq_Value=20000000
ProjectManager.ComputerToolchain=false
Mcu.Pin17=PB6
Mcu.Pin18=VP_SYS_VS_Systick
RCC.LTDCFreq_Value=38400000
RCC.SAI4AFreq_Value=160000000
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
Mcu.Pin11=PA9
Mcu.Pin12=PA10
Mcu.Pin10=PD13
RCC.DIVQ1Freq_Value=160000000
PE3.Signal=GPIO_Input
USB_DEVICE.USBD_DFU_XFER_SIZE-DFU_FS=4096
RCC.D3PPRE=RCC_APB4_DIV2
NVIC.FPU_IRQn=true\:0\:0\:false\:false\:true\:true\:false
CORTEX_M7.CPU_DCache=Disabled
RCC.HCLK3ClockFreq_Value=40000000
RCC.VCOInput2Freq_Value=320000
RCC.APB1Freq_Value=20000000
RCC.DIVR1=1
ProjectManager.DeviceId=STM32H750VBTx
ProjectManager.LibraryCopy=1
PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO

9
STM32H750VB_Bootloader.xml
View File

@ -1,9 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<targetDefinitions xmlns="http://openstm32.org/stm32TargetDefinitions" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://openstm32.org/stm32TargetDefinitions stm32TargetDefinitions.xsd">
<board id="STM32H750VB_Bootloader">
<name>STM32H750VB_Bootloader</name>
<mcuId>STM32H750VBTx</mcuId> <!-- mcu-->
<dbgIF>SWD</dbgIF>
<dbgDEV>ST-LinkV2-1</dbgDEV>
</board>
</targetDefinitions>

5
USB_DEVICE/App/usb_device.c
View File

@ -30,6 +30,7 @@
/* USER CODE BEGIN Includes */
#include "stm32h7xx_hal.h"
#include "pin_config.h"
/* USER CODE END Includes */
@ -70,11 +71,11 @@ void MX_USB_DEVICE_Init(void)
{
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
if(HAL_GPIO_ReadPin(GPIOE, GPIO_PIN_3) == GPIO_PIN_SET && g_DFU == 0) return;
if(HAL_GPIO_ReadPin(BTN_PORT, BTN_PIN) == BTN_INACTIVE_STATE && g_DFU == 0) return;
g_DFU = 1;
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
{

19
USB_DEVICE/App/usbd_desc.c
View File

@ -95,19 +95,18 @@
/**
* @}
*/
/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
* @brief Private functions declaration.
* @{
*/
static void Get_SerialNum(void);
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
/**
* @}
*/
*/
/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
* @brief Private functions declaration for FS.
@ -199,7 +198,7 @@ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma data_alignment=4
#pragma data_alignment=4
#endif
__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
USB_SIZ_STRING_SERIAL,
@ -332,8 +331,8 @@ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng
}
/**
* @brief Create the serial number string descriptor
* @param None
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
@ -354,9 +353,9 @@ static void Get_SerialNum(void)
}
/**
* @brief Convert Hex 32Bits value into char
* @brief Convert Hex 32Bits value into char
* @param value: value to convert
* @param pbuf: pointer to the buffer
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/

4
USB_DEVICE/App/usbd_desc.h
View File

@ -17,7 +17,7 @@
*
******************************************************************************
*/
/* USER CODE END Header */
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_DESC__C__
#define __USBD_DESC__C__
@ -41,7 +41,7 @@
* @brief Usb device descriptors module.
* @{
*/
/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
* @brief Constants.
* @{

10
USB_DEVICE/App/usbd_dfu_if.c
View File

@ -25,6 +25,8 @@
#include "w25_qspi.h"
#include "printf.h"
#include "pin_config.h"
/* USER CODE END INCLUDE */
/* Private typedef -----------------------------------------------------------*/
@ -64,7 +66,7 @@
* @{
*/
#define FLASH_DESC_STR "@QSPI Flash/0x90000000/2048*4Kg"
#define FLASH_DESC_STR "@QSPI Flash/0x90000000/4096*4Kg"
/* USER CODE BEGIN PRIVATE_DEFINES */
@ -164,6 +166,10 @@ uint16_t MEM_If_Init_FS(void)
w25_flash.mode = W25_MODE_QUAD;
w25_flash.address_size = W25_ADDRESS_24BITS;
#if(USE_QPI_MODE == 1)
W25_QPI_Mode(&w25_flash, 0);
#endif // USE_QPI_MODE
W25_QSPI_Init(&w25_flash);
printf("MEM_If_Init_FS: Mfg: 0x%x\r\n", w25_flash.manufacturer);
return (USBD_OK);
@ -206,6 +212,7 @@ uint16_t MEM_If_Erase_FS(uint32_t Add)
uint16_t MEM_If_Write_FS(uint8_t *src, uint8_t *dest, uint32_t Len)
{
/* USER CODE BEGIN 3 */
HAL_GPIO_TogglePin(LED_PORT, LED_PIN);
printf("Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08x 1St: 0x%02x\r\n", (uint32_t)dest, (uint32_t)src, Len, src[0]);
uint8_t page_count = Len / 256;
if(Len & 0xFFU) page_count++;
@ -230,6 +237,7 @@ uint8_t *MEM_If_Read_FS(uint8_t *src, uint8_t *dest, uint32_t Len)
{
/* Return a valid address to avoid HardFault */
/* USER CODE BEGIN 4 */
HAL_GPIO_TogglePin(LED_PORT, LED_PIN);
printf("Mem_If_Read_FS: Add: 0x%08x\r\n", (uint32_t)src);
W25_QSPI_Read(&w25_flash, (uint32_t)src - 0x90000000, dest, Len);
//HAL_Delay(100);

106
USB_DEVICE/Target/usbd_conf.c
View File

@ -71,11 +71,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USB_OTG_FS GPIO Configuration
/**USB_OTG_FS GPIO Configuration
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@ -109,10 +109,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
/* USER CODE END USB_OTG_FS_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();
/**USB_OTG_FS GPIO Configuration
/**USB_OTG_FS GPIO Configuration
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
PA12 ------> USB_OTG_FS_DP
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
@ -197,7 +197,7 @@ static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
{
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
if ( hpcd->Init.speed == PCD_SPEED_HIGH)
@ -336,7 +336,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
/* Link the driver to the stack. */
hpcd_USB_OTG_FS.pData = pdev;
pdev->pData = &hpcd_USB_OTG_FS;
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
hpcd_USB_OTG_FS.Init.dev_endpoints = 9;
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
@ -388,8 +388,8 @@ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
hal_status = HAL_PCD_DeInit(pdev->pData);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
return usb_status;
}
/**
@ -401,11 +401,11 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_Start(pdev->pData);
usb_status = USBD_Get_USB_Status(hal_status);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
@ -420,9 +420,9 @@ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_Stop(pdev->pData);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
@ -442,7 +442,7 @@ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uin
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
@ -456,12 +456,12 @@ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
/**
@ -474,12 +474,12 @@ USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
/**
@ -492,12 +492,12 @@ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
return usb_status;
}
/**
@ -510,12 +510,12 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
/**
@ -527,14 +527,14 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
if((ep_addr & 0x80) == 0x80)
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
}
}
@ -548,12 +548,12 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
return usb_status;
}
/**
@ -561,19 +561,19 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
/**
@ -584,16 +584,16 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, u
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
HAL_StatusTypeDef hal_status = HAL_OK;
USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
usb_status = USBD_Get_USB_Status(hal_status);
return usb_status;
}
/**

1
USB_DEVICE/Target/usbd_conf.h
View File

@ -42,6 +42,7 @@
/* USER CODE END INCLUDE */
/** @addtogroup USBD_OTG_DRIVER
* @brief Driver for Usb device.
* @{
*/

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build/bootloader_control.d Normal file
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@ -0,0 +1,67 @@
build/bootloader_control.o: Core/Src/bootloader_control.c \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
Core/Inc/stm32h7xx_hal_conf.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \
Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Include/mpu_armv7.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
Core/Inc/stm32h7xx_hal_conf.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h:
Drivers/CMSIS/Include/core_cm7.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Include/mpu_armv7.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h:

354
build/bootloader_control.lst Normal file
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@ -0,0 +1,354 @@
ARM GAS /tmp/cc2CqpQ9.s page 1
1 .cpu cortex-m7
2 .eabi_attribute 28, 1
3 .eabi_attribute 20, 1
4 .eabi_attribute 21, 1
5 .eabi_attribute 23, 3
6 .eabi_attribute 24, 1
7 .eabi_attribute 25, 1
8 .eabi_attribute 26, 1
9 .eabi_attribute 30, 1
10 .eabi_attribute 34, 1
11 .eabi_attribute 18, 4
12 .file "bootloader_control.c"
13 .text
14 .Ltext0:
15 .cfi_sections .debug_frame
16 .section .text.BL_CheckValidImage,"ax",%progbits
17 .align 1
18 .global BL_CheckValidImage
19 .arch armv7e-m
20 .syntax unified
21 .thumb
22 .thumb_func
23 .fpu fpv5-d16
25 BL_CheckValidImage:
26 .LVL0:
27 .LFB141:
28 .file 1 "Core/Src/bootloader_control.c"
1:Core/Src/bootloader_control.c **** //
2:Core/Src/bootloader_control.c **** // Created by imi415 on 2019/12/17.
3:Core/Src/bootloader_control.c **** //
4:Core/Src/bootloader_control.c ****
5:Core/Src/bootloader_control.c **** #include <stm32h7xx_hal.h>
6:Core/Src/bootloader_control.c ****
7:Core/Src/bootloader_control.c **** HAL_StatusTypeDef BL_CheckValidImage(uint32_t base_address) {
29 .loc 1 7 61 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
8:Core/Src/bootloader_control.c **** uint32_t qspi_sp = *(uint32_t *)base_address;
34 .loc 1 8 5 view .LVU1
35 .loc 1 8 14 is_stmt 0 view .LVU2
36 0000 0368 ldr r3, [r0]
37 .LVL1:
9:Core/Src/bootloader_control.c **** if(qspi_sp < 0x40000000) {
38 .loc 1 9 5 is_stmt 1 view .LVU3
39 .loc 1 9 7 is_stmt 0 view .LVU4
40 0002 B3F1804F cmp r3, #1073741824
41 0006 01D2 bcs .L3
10:Core/Src/bootloader_control.c **** return HAL_OK;
42 .loc 1 10 16 view .LVU5
43 0008 0020 movs r0, #0
44 .LVL2:
45 .loc 1 10 16 view .LVU6
46 000a 7047 bx lr
47 .LVL3:
48 .L3:
ARM GAS /tmp/cc2CqpQ9.s page 2
11:Core/Src/bootloader_control.c **** }
12:Core/Src/bootloader_control.c **** else return HAL_ERROR;
49 .loc 1 12 17 view .LVU7
50 000c 0120 movs r0, #1
51 .LVL4:
13:Core/Src/bootloader_control.c **** }
52 .loc 1 13 1 view .LVU8
53 000e 7047 bx lr
54 .cfi_endproc
55 .LFE141:
57 .section .text.BL_GetEntryPoint,"ax",%progbits
58 .align 1
59 .global BL_GetEntryPoint
60 .syntax unified
61 .thumb
62 .thumb_func
63 .fpu fpv5-d16
65 BL_GetEntryPoint:
66 .LVL5:
67 .LFB142:
14:Core/Src/bootloader_control.c ****
15:Core/Src/bootloader_control.c **** uint32_t BL_GetEntryPoint(uint32_t base_address) {
68 .loc 1 15 50 is_stmt 1 view -0
69 .cfi_startproc
70 @ args = 0, pretend = 0, frame = 0
71 @ frame_needed = 0, uses_anonymous_args = 0
72 @ link register save eliminated.
16:Core/Src/bootloader_control.c **** uint32_t target_reset_vector = *(uint32_t *)(base_address + 0x04);
73 .loc 1 16 5 view .LVU10
74 .loc 1 16 14 is_stmt 0 view .LVU11
75 0000 4068 ldr r0, [r0, #4]
76 .LVL6:
17:Core/Src/bootloader_control.c **** if(target_reset_vector > 0x90000000 && target_reset_vector < 0xA0000000) {
77 .loc 1 17 5 is_stmt 1 view .LVU12
78 .loc 1 17 41 is_stmt 0 view .LVU13
79 0002 6FF01043 mvn r3, #-1879048192
80 0006 0344 add r3, r3, r0
81 .loc 1 17 7 view .LVU14
82 0008 6FF07042 mvn r2, #-268435456
83 000c 9342 cmp r3, r2
84 000e 00D3 bcc .L4
18:Core/Src/bootloader_control.c **** return target_reset_vector;
19:Core/Src/bootloader_control.c **** }
20:Core/Src/bootloader_control.c **** else return 0x00000000;
85 .loc 1 20 17 view .LVU15
86 0010 0020 movs r0, #0
87 .LVL7:
88 .L4:
21:Core/Src/bootloader_control.c **** }
89 .loc 1 21 1 view .LVU16
90 0012 7047 bx lr
91 .cfi_endproc
92 .LFE142:
94 .section .text.BL_JumpToXIPStart,"ax",%progbits
95 .align 1
96 .global BL_JumpToXIPStart
97 .syntax unified
ARM GAS /tmp/cc2CqpQ9.s page 3
98 .thumb
99 .thumb_func
100 .fpu fpv5-d16
102 BL_JumpToXIPStart:
103 .LVL8:
104 .LFB143:
22:Core/Src/bootloader_control.c ****
23:Core/Src/bootloader_control.c **** void BL_JumpToXIPStart(uint32_t entry_point, uint32_t vector_base) {
105 .loc 1 23 68 is_stmt 1 view -0
106 .cfi_startproc
107 @ args = 0, pretend = 0, frame = 0
108 @ frame_needed = 0, uses_anonymous_args = 0
109 .loc 1 23 68 is_stmt 0 view .LVU18
110 0000 08B5 push {r3, lr}
111 .LCFI0:
112 .cfi_def_cfa_offset 8
113 .cfi_offset 3, -8
114 .cfi_offset 14, -4
24:Core/Src/bootloader_control.c **** __disable_irq();
115 .loc 1 24 5 is_stmt 1 view .LVU19
116 .LBB4:
117 .LBI4:
118 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
ARM GAS /tmp/cc2CqpQ9.s page 4
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
ARM GAS /tmp/cc2CqpQ9.s page 5
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
119 .loc 2 140 27 view .LVU20
120 .LBB5:
141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
121 .loc 2 142 3 view .LVU21
122 .syntax unified
123 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
124 0002 72B6 cpsid i
ARM GAS /tmp/cc2CqpQ9.s page 6
125 @ 0 "" 2
126 .thumb
127 .syntax unified
128 .LBE5:
129 .LBE4:
25:Core/Src/bootloader_control.c **** SysTick->CTRL = 0;
130 .loc 1 25 5 view .LVU22
131 .loc 1 25 19 is_stmt 0 view .LVU23
132 0004 4FF0E023 mov r3, #-536813568
133 0008 0022 movs r2, #0
134 000a 1A61 str r2, [r3, #16]
26:Core/Src/bootloader_control.c **** SysTick->LOAD = 0;
135 .loc 1 26 5 is_stmt 1 view .LVU24
136 .loc 1 26 19 is_stmt 0 view .LVU25
137 000c 5A61 str r2, [r3, #20]
27:Core/Src/bootloader_control.c **** SysTick->VAL = 0;
138 .loc 1 27 5 is_stmt 1 view .LVU26
139 .loc 1 27 19 is_stmt 0 view .LVU27
140 000e 9A61 str r2, [r3, #24]
28:Core/Src/bootloader_control.c **** void (*entry)(void) = (void *)entry_point;
141 .loc 1 28 5 is_stmt 1 view .LVU28
142 .LVL9:
29:Core/Src/bootloader_control.c **** //__set_MSP(*(uint32_t *)vector_base);
30:Core/Src/bootloader_control.c **** entry();
143 .loc 1 30 5 view .LVU29
144 0010 8047 blx r0
145 .LVL10:
31:Core/Src/bootloader_control.c **** }...
146 .loc 1 31 1 is_stmt 0 view .LVU30
147 0012 08BD pop {r3, pc}
148 .cfi_endproc
149 .LFE143:
151 .text
152 .Letext0:
153 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h"
154 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h"
155 .file 5 "Drivers/CMSIS/Include/core_cm7.h"
156 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
ARM GAS /tmp/cc2CqpQ9.s page 7
DEFINED SYMBOLS
*ABS*:0000000000000000 bootloader_control.c
/tmp/cc2CqpQ9.s:17 .text.BL_CheckValidImage:0000000000000000 $t
/tmp/cc2CqpQ9.s:25 .text.BL_CheckValidImage:0000000000000000 BL_CheckValidImage
/tmp/cc2CqpQ9.s:58 .text.BL_GetEntryPoint:0000000000000000 $t
/tmp/cc2CqpQ9.s:65 .text.BL_GetEntryPoint:0000000000000000 BL_GetEntryPoint
/tmp/cc2CqpQ9.s:95 .text.BL_JumpToXIPStart:0000000000000000 $t
/tmp/cc2CqpQ9.s:102 .text.BL_JumpToXIPStart:0000000000000000 BL_JumpToXIPStart
NO UNDEFINED SYMBOLS

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build/main.o: Core/Src/main.c Core/Inc/main.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
Core/Inc/stm32h7xx_hal_conf.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \
Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Include/mpu_armv7.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \
Core/Inc/pin_config.h Core/Inc/flash_config.h \
USB_DEVICE/App/usb_device.h \
Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \
USB_DEVICE/Target/usbd_conf.h Core/Inc/printf.h \
Core/Inc/bootloader_control.h Core/Inc/w25_qspi.h
Core/Inc/main.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
Core/Inc/stm32h7xx_hal_conf.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h:
Drivers/CMSIS/Include/core_cm7.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Include/mpu_armv7.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h:
Core/Inc/pin_config.h:
Core/Inc/flash_config.h:
USB_DEVICE/App/usb_device.h:
Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:
USB_DEVICE/Target/usbd_conf.h:
Core/Inc/printf.h:
Core/Inc/bootloader_control.h:
Core/Inc/w25_qspi.h:

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build/port_printf.o: Core/Src/port_printf.c \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
Core/Inc/stm32h7xx_hal_conf.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \
Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Include/mpu_armv7.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \
Core/Inc/printf.h
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
Core/Inc/stm32h7xx_hal_conf.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h:
Drivers/CMSIS/Include/core_cm7.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Include/mpu_armv7.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h:
Core/Inc/printf.h:

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ARM GAS /tmp/ccAYJ7K0.s page 1
1 .cpu cortex-m7
2 .eabi_attribute 28, 1
3 .eabi_attribute 20, 1
4 .eabi_attribute 21, 1
5 .eabi_attribute 23, 3
6 .eabi_attribute 24, 1
7 .eabi_attribute 25, 1
8 .eabi_attribute 26, 1
9 .eabi_attribute 30, 1
10 .eabi_attribute 34, 1
11 .eabi_attribute 18, 4
12 .file "port_printf.c"
13 .text
14 .Ltext0:
15 .cfi_sections .debug_frame
16 .section .text._putchar,"ax",%progbits
17 .align 1
18 .global _putchar
19 .arch armv7e-m
20 .syntax unified
21 .thumb
22 .thumb_func
23 .fpu fpv5-d16
25 _putchar:
26 .LVL0:
27 .LFB141:
28 .file 1 "Core/Src/port_printf.c"
1:Core/Src/port_printf.c **** //
2:Core/Src/port_printf.c **** // Created by imi415 on 2019/12/06.
3:Core/Src/port_printf.c **** //
4:Core/Src/port_printf.c **** #include "stm32h7xx_hal.h"
5:Core/Src/port_printf.c **** #include "printf.h"
6:Core/Src/port_printf.c ****
7:Core/Src/port_printf.c **** extern UART_HandleTypeDef huart1;
8:Core/Src/port_printf.c ****
9:Core/Src/port_printf.c **** void _putchar(char character) {
29 .loc 1 9 31 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 8
32 @ frame_needed = 0, uses_anonymous_args = 0
33 .loc 1 9 31 is_stmt 0 view .LVU1
34 0000 00B5 push {lr}
35 .LCFI0:
36 .cfi_def_cfa_offset 4
37 .cfi_offset 14, -4
38 0002 83B0 sub sp, sp, #12
39 .LCFI1:
40 .cfi_def_cfa_offset 16
41 0004 8DF80700 strb r0, [sp, #7]
10:Core/Src/port_printf.c **** HAL_UART_Transmit(&huart1, (uint8_t *)&character, 0x01, 1000);
42 .loc 1 10 5 is_stmt 1 view .LVU2
43 0008 4FF47A73 mov r3, #1000
44 000c 0122 movs r2, #1
45 000e 0DF10701 add r1, sp, #7
46 0012 0348 ldr r0, .L3
47 .LVL1:
48 .loc 1 10 5 is_stmt 0 view .LVU3
ARM GAS /tmp/ccAYJ7K0.s page 2
49 0014 FFF7FEFF bl HAL_UART_Transmit
50 .LVL2:
11:Core/Src/port_printf.c **** }...
51 .loc 1 11 1 view .LVU4
52 0018 03B0 add sp, sp, #12
53 .LCFI2:
54 .cfi_def_cfa_offset 4
55 @ sp needed
56 001a 5DF804FB ldr pc, [sp], #4
57 .L4:
58 001e 00BF .align 2
59 .L3:
60 0020 00000000 .word huart1
61 .cfi_endproc
62 .LFE141:
64 .text
65 .Letext0:
66 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
67 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
68 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h"
69 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
70 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h"
71 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h"
ARM GAS /tmp/ccAYJ7K0.s page 3
DEFINED SYMBOLS
*ABS*:0000000000000000 port_printf.c
/tmp/ccAYJ7K0.s:17 .text._putchar:0000000000000000 $t
/tmp/ccAYJ7K0.s:25 .text._putchar:0000000000000000 _putchar
/tmp/ccAYJ7K0.s:60 .text._putchar:0000000000000020 $d
UNDEFINED SYMBOLS
HAL_UART_Transmit
huart1

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build/printf.o: Core/Src/printf.c Core/Inc/printf.h
Core/Inc/printf.h:

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build/startup_stm32h750xx.o: startup_stm32h750xx.s

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build/stm32h7xx_hal.o: Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
Core/Inc/stm32h7xx_hal_conf.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \
Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Include/mpu_armv7.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
Core/Inc/stm32h7xx_hal_conf.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h:
Drivers/CMSIS/Include/core_cm7.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Include/mpu_armv7.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h:

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build/stm32h7xx_hal_cortex.o: \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
Core/Inc/stm32h7xx_hal_conf.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \
Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
Drivers/CMSIS/Include/mpu_armv7.h \
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
Core/Inc/stm32h7xx_hal_conf.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h:
Drivers/CMSIS/Include/core_cm7.h:
Drivers/CMSIS/Include/cmsis_version.h:
Drivers/CMSIS/Include/cmsis_compiler.h:
Drivers/CMSIS/Include/cmsis_gcc.h:
Drivers/CMSIS/Include/mpu_armv7.h:
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h:
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h:

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