ARM GAS /tmp/ccOSKXvF.s page 1 1 .cpu cortex-m7 2 .eabi_attribute 28, 1 3 .eabi_attribute 20, 1 4 .eabi_attribute 21, 1 5 .eabi_attribute 23, 3 6 .eabi_attribute 24, 1 7 .eabi_attribute 25, 1 8 .eabi_attribute 26, 1 9 .eabi_attribute 30, 1 10 .eabi_attribute 34, 1 11 .eabi_attribute 18, 4 12 .file "main.c" 13 .text 14 .Ltext0: 15 .cfi_sections .debug_frame 16 .section .text.MX_GPIO_Init,"ax",%progbits 17 .align 1 18 .arch armv7e-m 19 .syntax unified 20 .thumb 21 .thumb_func 22 .fpu fpv5-d16 24 MX_GPIO_Init: 25 .LFB149: 26 .file 1 "Core/Src/main.c" 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** *

© Copyright (c) 2019 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved.

11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software component is licensed by ST under BSD 3-Clause license, 13:Core/Src/main.c **** * the "License"; You may not use this file except in compliance with the 14:Core/Src/main.c **** * License. You may obtain a copy of the License at: 15:Core/Src/main.c **** * opensource.org/licenses/BSD-3-Clause 16:Core/Src/main.c **** * 17:Core/Src/main.c **** ****************************************************************************** 18:Core/Src/main.c **** */ 19:Core/Src/main.c **** /* USER CODE END Header */ 20:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 21:Core/Src/main.c **** #include "main.h" 22:Core/Src/main.c **** #include "usb_device.h" 23:Core/Src/main.c **** 24:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 25:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 26:Core/Src/main.c **** 27:Core/Src/main.c **** #include "printf.h" 28:Core/Src/main.c **** #include "bootloader_control.h" 29:Core/Src/main.c **** #include "w25_qspi.h" 30:Core/Src/main.c **** 31:Core/Src/main.c **** /* USER CODE END Includes */ 32:Core/Src/main.c **** ARM GAS /tmp/ccOSKXvF.s page 2 33:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 34:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 35:Core/Src/main.c **** 36:Core/Src/main.c **** /* USER CODE END PTD */ 37:Core/Src/main.c **** 38:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ 39:Core/Src/main.c **** /* USER CODE BEGIN PD */ 40:Core/Src/main.c **** /* USER CODE END PD */ 41:Core/Src/main.c **** 42:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 43:Core/Src/main.c **** /* USER CODE BEGIN PM */ 44:Core/Src/main.c **** 45:Core/Src/main.c **** /* USER CODE END PM */ 46:Core/Src/main.c **** 47:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 48:Core/Src/main.c **** 49:Core/Src/main.c **** QSPI_HandleTypeDef hqspi; 50:Core/Src/main.c **** 51:Core/Src/main.c **** UART_HandleTypeDef huart1; 52:Core/Src/main.c **** 53:Core/Src/main.c **** /* USER CODE BEGIN PV */ 54:Core/Src/main.c **** 55:Core/Src/main.c **** uint8_t g_DFU = 0; 56:Core/Src/main.c **** 57:Core/Src/main.c **** /* USER CODE END PV */ 58:Core/Src/main.c **** 59:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 60:Core/Src/main.c **** void SystemClock_Config(void); 61:Core/Src/main.c **** static void MX_GPIO_Init(void); 62:Core/Src/main.c **** static void MX_QUADSPI_Init(void); 63:Core/Src/main.c **** static void MX_USART1_UART_Init(void); 64:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 65:Core/Src/main.c **** 66:Core/Src/main.c **** /* USER CODE END PFP */ 67:Core/Src/main.c **** 68:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 69:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 70:Core/Src/main.c **** 71:Core/Src/main.c **** /* USER CODE END 0 */ 72:Core/Src/main.c **** 73:Core/Src/main.c **** /** 74:Core/Src/main.c **** * @brief The application entry point. 75:Core/Src/main.c **** * @retval int 76:Core/Src/main.c **** */ 77:Core/Src/main.c **** int main(void) 78:Core/Src/main.c **** { 79:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 80:Core/Src/main.c **** 81:Core/Src/main.c **** /* USER CODE END 1 */ 82:Core/Src/main.c **** 83:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 84:Core/Src/main.c **** 85:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 86:Core/Src/main.c **** HAL_Init(); 87:Core/Src/main.c **** 88:Core/Src/main.c **** /* USER CODE BEGIN Init */ 89:Core/Src/main.c **** ARM GAS /tmp/ccOSKXvF.s page 3 90:Core/Src/main.c **** /* USER CODE END Init */ 91:Core/Src/main.c **** 92:Core/Src/main.c **** /* Configure the system clock */ 93:Core/Src/main.c **** SystemClock_Config(); 94:Core/Src/main.c **** 95:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ 96:Core/Src/main.c **** 97:Core/Src/main.c **** /* USER CODE END SysInit */ 98:Core/Src/main.c **** 99:Core/Src/main.c **** /* Initialize all configured peripherals */ 100:Core/Src/main.c **** MX_GPIO_Init(); 101:Core/Src/main.c **** MX_QUADSPI_Init(); 102:Core/Src/main.c **** MX_USART1_UART_Init(); 103:Core/Src/main.c **** MX_USB_DEVICE_Init(); 104:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 105:Core/Src/main.c **** 106:Core/Src/main.c **** if(!g_DFU) { 107:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; 108:Core/Src/main.c **** QSPI_MemoryMappedTypeDef sMemMappedCfg; 109:Core/Src/main.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; 110:Core/Src/main.c **** sCommand.AddressMode = QSPI_ADDRESS_4_LINES; 111:Core/Src/main.c **** sCommand.AddressSize = QSPI_ADDRESS_24_BITS; 112:Core/Src/main.c **** sCommand.DataMode = QSPI_DATA_4_LINES; 113:Core/Src/main.c **** sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; 114:Core/Src/main.c **** sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; 115:Core/Src/main.c **** sCommand.AlternateBytes = 0xFF; 116:Core/Src/main.c **** sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; 117:Core/Src/main.c **** sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 118:Core/Src/main.c **** sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 119:Core/Src/main.c **** sCommand.Instruction = 0xEB; 120:Core/Src/main.c **** sCommand.DummyCycles = 4; 121:Core/Src/main.c **** sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; 122:Core/Src/main.c **** sMemMappedCfg.TimeOutPeriod = 0; 123:Core/Src/main.c **** 124:Core/Src/main.c **** w25_qspi_t w25_flash; 125:Core/Src/main.c **** w25_flash.interface = &hqspi; 126:Core/Src/main.c **** w25_flash.mode = W25_MODE_QUAD; 127:Core/Src/main.c **** w25_flash.address_size = W25_ADDRESS_24BITS; 128:Core/Src/main.c **** 129:Core/Src/main.c **** #if(USE_QPI_MODE == 1) 130:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 0); // Special use case!! 131:Core/Src/main.c **** #endif // USE_QPI_MODE 132:Core/Src/main.c **** 133:Core/Src/main.c **** W25_QSPI_Init(&w25_flash); 134:Core/Src/main.c **** printf("Main: Mfg: 0x%x\r\n", w25_flash.manufacturer); 135:Core/Src/main.c **** 136:Core/Src/main.c **** W25_QSPI_QuadEnable(&w25_flash, 0); 137:Core/Src/main.c **** 138:Core/Src/main.c **** #if(USE_QPI_MODE == 1) 139:Core/Src/main.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; 140:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 1); 141:Core/Src/main.c **** #if(QPI_HIGH_SPEED == 1) // For 80MHz HIGHHHHHH speed QPI mode(33-80MHz), additional 4 dummy cycles 142:Core/Src/main.c **** sCommand.DummyCycles = 4; // In QPI mode, M7-0 are used as dummy clocks. 143:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_6, W25_QPI_WRAP_LENGTH_8); 144:Core/Src/main.c **** #else 145:Core/Src/main.c **** sCommand.DummyCycles = 0; // In QPI mode, M7-0 are used as dummy clocks. 146:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); ARM GAS /tmp/ccOSKXvF.s page 4 147:Core/Src/main.c **** #endif // QPI_HIGH_SPEED 148:Core/Src/main.c **** #endif // USE_QPI_MODE 149:Core/Src/main.c **** 150:Core/Src/main.c **** if(HAL_QSPI_MemoryMapped(&hqspi, &sCommand, &sMemMappedCfg) == HAL_OK) { 151:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); 152:Core/Src/main.c **** if(BL_CheckValidImage(0x90000000) == HAL_OK) { 153:Core/Src/main.c **** printf("Valid SP found!\r\n"); 154:Core/Src/main.c **** uint32_t entry = BL_GetEntryPoint(0x90000000); 155:Core/Src/main.c **** printf("Entry: 0x%08lx\r\n", entry); 156:Core/Src/main.c **** BL_JumpToXIPStart(entry, 0x90000000); 157:Core/Src/main.c **** } 158:Core/Src/main.c **** else printf("No valid image found!\r\n"); 159:Core/Src/main.c **** } 160:Core/Src/main.c **** } 161:Core/Src/main.c **** 162:Core/Src/main.c **** /* USER CODE END 2 */ 163:Core/Src/main.c **** 164:Core/Src/main.c **** /* Infinite loop */ 165:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 166:Core/Src/main.c **** while (1) 167:Core/Src/main.c **** { 168:Core/Src/main.c **** /* USER CODE END WHILE */ 169:Core/Src/main.c **** 170:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 171:Core/Src/main.c **** } 172:Core/Src/main.c **** /* USER CODE END 3 */ 173:Core/Src/main.c **** } 174:Core/Src/main.c **** 175:Core/Src/main.c **** /** 176:Core/Src/main.c **** * @brief System Clock Configuration 177:Core/Src/main.c **** * @retval None 178:Core/Src/main.c **** */ 179:Core/Src/main.c **** void SystemClock_Config(void) 180:Core/Src/main.c **** { 181:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 182:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 183:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 184:Core/Src/main.c **** 185:Core/Src/main.c **** /** Supply configuration update enable 186:Core/Src/main.c **** */ 187:Core/Src/main.c **** HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 188:Core/Src/main.c **** /** Configure the main internal regulator output voltage 189:Core/Src/main.c **** */ 190:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 191:Core/Src/main.c **** 192:Core/Src/main.c **** while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 193:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 194:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 195:Core/Src/main.c **** */ 196:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI 197:Core/Src/main.c **** |RCC_OSCILLATORTYPE_HSE; 198:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 199:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 200:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 201:Core/Src/main.c **** RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 202:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 203:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; ARM GAS /tmp/ccOSKXvF.s page 5 204:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2; 205:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 40; 206:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; 207:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 1; 208:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 1; 209:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 210:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; 211:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; 212:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 213:Core/Src/main.c **** { 214:Core/Src/main.c **** Error_Handler(); 215:Core/Src/main.c **** } 216:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 217:Core/Src/main.c **** */ 218:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 219:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 220:Core/Src/main.c **** |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; 221:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 222:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 223:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 224:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 225:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 226:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 227:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 228:Core/Src/main.c **** 229:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 230:Core/Src/main.c **** { 231:Core/Src/main.c **** Error_Handler(); 232:Core/Src/main.c **** } 233:Core/Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USB 234:Core/Src/main.c **** |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; 235:Core/Src/main.c **** PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_CLKP; 236:Core/Src/main.c **** PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; 237:Core/Src/main.c **** PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 238:Core/Src/main.c **** PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; 239:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 240:Core/Src/main.c **** { 241:Core/Src/main.c **** Error_Handler(); 242:Core/Src/main.c **** } 243:Core/Src/main.c **** /** Enable USB Voltage detector 244:Core/Src/main.c **** */ 245:Core/Src/main.c **** HAL_PWREx_EnableUSBVoltageDetector(); 246:Core/Src/main.c **** } 247:Core/Src/main.c **** 248:Core/Src/main.c **** /** 249:Core/Src/main.c **** * @brief QUADSPI Initialization Function 250:Core/Src/main.c **** * @param None 251:Core/Src/main.c **** * @retval None 252:Core/Src/main.c **** */ 253:Core/Src/main.c **** static void MX_QUADSPI_Init(void) 254:Core/Src/main.c **** { 255:Core/Src/main.c **** 256:Core/Src/main.c **** /* USER CODE BEGIN QUADSPI_Init 0 */ 257:Core/Src/main.c **** 258:Core/Src/main.c **** /* USER CODE END QUADSPI_Init 0 */ 259:Core/Src/main.c **** 260:Core/Src/main.c **** /* USER CODE BEGIN QUADSPI_Init 1 */ ARM GAS /tmp/ccOSKXvF.s page 6 261:Core/Src/main.c **** 262:Core/Src/main.c **** /* USER CODE END QUADSPI_Init 1 */ 263:Core/Src/main.c **** /* QUADSPI parameter configuration*/ 264:Core/Src/main.c **** hqspi.Instance = QUADSPI; 265:Core/Src/main.c **** hqspi.Init.ClockPrescaler = 2; 266:Core/Src/main.c **** hqspi.Init.FifoThreshold = 4; 267:Core/Src/main.c **** hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; 268:Core/Src/main.c **** hqspi.Init.FlashSize = 24; 269:Core/Src/main.c **** hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; 270:Core/Src/main.c **** hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; 271:Core/Src/main.c **** hqspi.Init.FlashID = QSPI_FLASH_ID_1; 272:Core/Src/main.c **** hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; 273:Core/Src/main.c **** if (HAL_QSPI_Init(&hqspi) != HAL_OK) 274:Core/Src/main.c **** { 275:Core/Src/main.c **** Error_Handler(); 276:Core/Src/main.c **** } 277:Core/Src/main.c **** /* USER CODE BEGIN QUADSPI_Init 2 */ 278:Core/Src/main.c **** 279:Core/Src/main.c **** /* USER CODE END QUADSPI_Init 2 */ 280:Core/Src/main.c **** 281:Core/Src/main.c **** } 282:Core/Src/main.c **** 283:Core/Src/main.c **** /** 284:Core/Src/main.c **** * @brief USART1 Initialization Function 285:Core/Src/main.c **** * @param None 286:Core/Src/main.c **** * @retval None 287:Core/Src/main.c **** */ 288:Core/Src/main.c **** static void MX_USART1_UART_Init(void) 289:Core/Src/main.c **** { 290:Core/Src/main.c **** 291:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ 292:Core/Src/main.c **** 293:Core/Src/main.c **** /* USER CODE END USART1_Init 0 */ 294:Core/Src/main.c **** 295:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ 296:Core/Src/main.c **** 297:Core/Src/main.c **** /* USER CODE END USART1_Init 1 */ 298:Core/Src/main.c **** huart1.Instance = USART1; 299:Core/Src/main.c **** huart1.Init.BaudRate = 921600; 300:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; 301:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; 302:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; 303:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; 304:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 305:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; 306:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 307:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 308:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 309:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) 310:Core/Src/main.c **** { 311:Core/Src/main.c **** Error_Handler(); 312:Core/Src/main.c **** } 313:Core/Src/main.c **** if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 314:Core/Src/main.c **** { 315:Core/Src/main.c **** Error_Handler(); 316:Core/Src/main.c **** } 317:Core/Src/main.c **** if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) ARM GAS /tmp/ccOSKXvF.s page 7 318:Core/Src/main.c **** { 319:Core/Src/main.c **** Error_Handler(); 320:Core/Src/main.c **** } 321:Core/Src/main.c **** if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 322:Core/Src/main.c **** { 323:Core/Src/main.c **** Error_Handler(); 324:Core/Src/main.c **** } 325:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 326:Core/Src/main.c **** 327:Core/Src/main.c **** /* USER CODE END USART1_Init 2 */ 328:Core/Src/main.c **** 329:Core/Src/main.c **** } 330:Core/Src/main.c **** 331:Core/Src/main.c **** /** 332:Core/Src/main.c **** * @brief GPIO Initialization Function 333:Core/Src/main.c **** * @param None 334:Core/Src/main.c **** * @retval None 335:Core/Src/main.c **** */ 336:Core/Src/main.c **** static void MX_GPIO_Init(void) 337:Core/Src/main.c **** { 27 .loc 1 337 1 view -0 28 .cfi_startproc 29 @ args = 0, pretend = 0, frame = 48 30 @ frame_needed = 0, uses_anonymous_args = 0 31 0000 70B5 push {r4, r5, r6, lr} 32 .LCFI0: 33 .cfi_def_cfa_offset 16 34 .cfi_offset 4, -16 35 .cfi_offset 5, -12 36 .cfi_offset 6, -8 37 .cfi_offset 14, -4 38 0002 8CB0 sub sp, sp, #48 39 .LCFI1: 40 .cfi_def_cfa_offset 64 338:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 41 .loc 1 338 3 view .LVU1 42 .loc 1 338 20 is_stmt 0 view .LVU2 43 0004 0024 movs r4, #0 44 0006 0794 str r4, [sp, #28] 45 0008 0894 str r4, [sp, #32] 46 000a 0994 str r4, [sp, #36] 47 000c 0A94 str r4, [sp, #40] 48 000e 0B94 str r4, [sp, #44] 339:Core/Src/main.c **** 340:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 341:Core/Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 49 .loc 1 341 3 is_stmt 1 view .LVU3 50 .LBB2: 51 .loc 1 341 3 view .LVU4 52 .loc 1 341 3 view .LVU5 53 0010 314B ldr r3, .L3 54 0012 D3F8E020 ldr r2, [r3, #224] 55 0016 42F01002 orr r2, r2, #16 56 001a C3F8E020 str r2, [r3, #224] 57 .loc 1 341 3 view .LVU6 58 001e D3F8E020 ldr r2, [r3, #224] 59 0022 02F01002 and r2, r2, #16 ARM GAS /tmp/ccOSKXvF.s page 8 60 0026 0192 str r2, [sp, #4] 61 .loc 1 341 3 view .LVU7 62 0028 019A ldr r2, [sp, #4] 63 .LBE2: 64 .loc 1 341 3 view .LVU8 342:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 65 .loc 1 342 3 view .LVU9 66 .LBB3: 67 .loc 1 342 3 view .LVU10 68 .loc 1 342 3 view .LVU11 69 002a D3F8E020 ldr r2, [r3, #224] 70 002e 42F00402 orr r2, r2, #4 71 0032 C3F8E020 str r2, [r3, #224] 72 .loc 1 342 3 view .LVU12 73 0036 D3F8E020 ldr r2, [r3, #224] 74 003a 02F00402 and r2, r2, #4 75 003e 0292 str r2, [sp, #8] 76 .loc 1 342 3 view .LVU13 77 0040 029A ldr r2, [sp, #8] 78 .LBE3: 79 .loc 1 342 3 view .LVU14 343:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 80 .loc 1 343 3 view .LVU15 81 .LBB4: 82 .loc 1 343 3 view .LVU16 83 .loc 1 343 3 view .LVU17 84 0042 D3F8E020 ldr r2, [r3, #224] 85 0046 42F08002 orr r2, r2, #128 86 004a C3F8E020 str r2, [r3, #224] 87 .loc 1 343 3 view .LVU18 88 004e D3F8E020 ldr r2, [r3, #224] 89 0052 02F08002 and r2, r2, #128 90 0056 0392 str r2, [sp, #12] 91 .loc 1 343 3 view .LVU19 92 0058 039A ldr r2, [sp, #12] 93 .LBE4: 94 .loc 1 343 3 view .LVU20 344:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 95 .loc 1 344 3 view .LVU21 96 .LBB5: 97 .loc 1 344 3 view .LVU22 98 .loc 1 344 3 view .LVU23 99 005a D3F8E020 ldr r2, [r3, #224] 100 005e 42F00102 orr r2, r2, #1 101 0062 C3F8E020 str r2, [r3, #224] 102 .loc 1 344 3 view .LVU24 103 0066 D3F8E020 ldr r2, [r3, #224] 104 006a 02F00102 and r2, r2, #1 105 006e 0492 str r2, [sp, #16] 106 .loc 1 344 3 view .LVU25 107 0070 049A ldr r2, [sp, #16] 108 .LBE5: 109 .loc 1 344 3 view .LVU26 345:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 110 .loc 1 345 3 view .LVU27 111 .LBB6: 112 .loc 1 345 3 view .LVU28 ARM GAS /tmp/ccOSKXvF.s page 9 113 .loc 1 345 3 view .LVU29 114 0072 D3F8E020 ldr r2, [r3, #224] 115 0076 42F00202 orr r2, r2, #2 116 007a C3F8E020 str r2, [r3, #224] 117 .loc 1 345 3 view .LVU30 118 007e D3F8E020 ldr r2, [r3, #224] 119 0082 02F00202 and r2, r2, #2 120 0086 0592 str r2, [sp, #20] 121 .loc 1 345 3 view .LVU31 122 0088 059A ldr r2, [sp, #20] 123 .LBE6: 124 .loc 1 345 3 view .LVU32 346:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 125 .loc 1 346 3 view .LVU33 126 .LBB7: 127 .loc 1 346 3 view .LVU34 128 .loc 1 346 3 view .LVU35 129 008a D3F8E020 ldr r2, [r3, #224] 130 008e 42F00802 orr r2, r2, #8 131 0092 C3F8E020 str r2, [r3, #224] 132 .loc 1 346 3 view .LVU36 133 0096 D3F8E030 ldr r3, [r3, #224] 134 009a 03F00803 and r3, r3, #8 135 009e 0693 str r3, [sp, #24] 136 .loc 1 346 3 view .LVU37 137 00a0 069B ldr r3, [sp, #24] 138 .LBE7: 139 .loc 1 346 3 view .LVU38 347:Core/Src/main.c **** 348:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 349:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); 140 .loc 1 349 3 view .LVU39 141 00a2 0E4D ldr r5, .L3+4 142 00a4 2246 mov r2, r4 143 00a6 0221 movs r1, #2 144 00a8 2846 mov r0, r5 145 00aa FFF7FEFF bl HAL_GPIO_WritePin 146 .LVL0: 350:Core/Src/main.c **** 351:Core/Src/main.c **** /*Configure GPIO pin : PE3 */ 352:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_3; 147 .loc 1 352 3 view .LVU40 148 .loc 1 352 23 is_stmt 0 view .LVU41 149 00ae 0823 movs r3, #8 150 00b0 0793 str r3, [sp, #28] 353:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 151 .loc 1 353 3 is_stmt 1 view .LVU42 152 .loc 1 353 24 is_stmt 0 view .LVU43 153 00b2 0894 str r4, [sp, #32] 354:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; 154 .loc 1 354 3 is_stmt 1 view .LVU44 155 .loc 1 354 24 is_stmt 0 view .LVU45 156 00b4 0126 movs r6, #1 157 00b6 0996 str r6, [sp, #36] 355:Core/Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 158 .loc 1 355 3 is_stmt 1 view .LVU46 159 00b8 07A9 add r1, sp, #28 ARM GAS /tmp/ccOSKXvF.s page 10 160 00ba 0948 ldr r0, .L3+8 161 00bc FFF7FEFF bl HAL_GPIO_Init 162 .LVL1: 356:Core/Src/main.c **** 357:Core/Src/main.c **** /*Configure GPIO pin : PA1 */ 358:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_1; 163 .loc 1 358 3 view .LVU47 164 .loc 1 358 23 is_stmt 0 view .LVU48 165 00c0 0223 movs r3, #2 166 00c2 0793 str r3, [sp, #28] 359:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 167 .loc 1 359 3 is_stmt 1 view .LVU49 168 .loc 1 359 24 is_stmt 0 view .LVU50 169 00c4 0896 str r6, [sp, #32] 360:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 170 .loc 1 360 3 is_stmt 1 view .LVU51 171 .loc 1 360 24 is_stmt 0 view .LVU52 172 00c6 0994 str r4, [sp, #36] 361:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 173 .loc 1 361 3 is_stmt 1 view .LVU53 174 .loc 1 361 25 is_stmt 0 view .LVU54 175 00c8 0A94 str r4, [sp, #40] 362:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 176 .loc 1 362 3 is_stmt 1 view .LVU55 177 00ca 07A9 add r1, sp, #28 178 00cc 2846 mov r0, r5 179 00ce FFF7FEFF bl HAL_GPIO_Init 180 .LVL2: 363:Core/Src/main.c **** 364:Core/Src/main.c **** } 181 .loc 1 364 1 is_stmt 0 view .LVU56 182 00d2 0CB0 add sp, sp, #48 183 .LCFI2: 184 .cfi_def_cfa_offset 16 185 @ sp needed 186 00d4 70BD pop {r4, r5, r6, pc} 187 .L4: 188 00d6 00BF .align 2 189 .L3: 190 00d8 00440258 .word 1476543488 191 00dc 00000258 .word 1476526080 192 00e0 00100258 .word 1476530176 193 .cfi_endproc 194 .LFE149: 196 .section .text.MX_QUADSPI_Init,"ax",%progbits 197 .align 1 198 .syntax unified 199 .thumb 200 .thumb_func 201 .fpu fpv5-d16 203 MX_QUADSPI_Init: 204 .LFB147: 254:Core/Src/main.c **** 205 .loc 1 254 1 is_stmt 1 view -0 206 .cfi_startproc 207 @ args = 0, pretend = 0, frame = 0 208 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccOSKXvF.s page 11 209 0000 08B5 push {r3, lr} 210 .LCFI3: 211 .cfi_def_cfa_offset 8 212 .cfi_offset 3, -8 213 .cfi_offset 14, -4 264:Core/Src/main.c **** hqspi.Init.ClockPrescaler = 2; 214 .loc 1 264 3 view .LVU58 264:Core/Src/main.c **** hqspi.Init.ClockPrescaler = 2; 215 .loc 1 264 18 is_stmt 0 view .LVU59 216 0002 0A48 ldr r0, .L7 217 0004 0A4B ldr r3, .L7+4 218 0006 0360 str r3, [r0] 265:Core/Src/main.c **** hqspi.Init.FifoThreshold = 4; 219 .loc 1 265 3 is_stmt 1 view .LVU60 265:Core/Src/main.c **** hqspi.Init.FifoThreshold = 4; 220 .loc 1 265 29 is_stmt 0 view .LVU61 221 0008 0223 movs r3, #2 222 000a 4360 str r3, [r0, #4] 266:Core/Src/main.c **** hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; 223 .loc 1 266 3 is_stmt 1 view .LVU62 266:Core/Src/main.c **** hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; 224 .loc 1 266 28 is_stmt 0 view .LVU63 225 000c 0423 movs r3, #4 226 000e 8360 str r3, [r0, #8] 267:Core/Src/main.c **** hqspi.Init.FlashSize = 24; 227 .loc 1 267 3 is_stmt 1 view .LVU64 267:Core/Src/main.c **** hqspi.Init.FlashSize = 24; 228 .loc 1 267 29 is_stmt 0 view .LVU65 229 0010 0023 movs r3, #0 230 0012 C360 str r3, [r0, #12] 268:Core/Src/main.c **** hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; 231 .loc 1 268 3 is_stmt 1 view .LVU66 268:Core/Src/main.c **** hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; 232 .loc 1 268 24 is_stmt 0 view .LVU67 233 0014 1822 movs r2, #24 234 0016 0261 str r2, [r0, #16] 269:Core/Src/main.c **** hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; 235 .loc 1 269 3 is_stmt 1 view .LVU68 269:Core/Src/main.c **** hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; 236 .loc 1 269 33 is_stmt 0 view .LVU69 237 0018 4FF40072 mov r2, #512 238 001c 4261 str r2, [r0, #20] 270:Core/Src/main.c **** hqspi.Init.FlashID = QSPI_FLASH_ID_1; 239 .loc 1 270 3 is_stmt 1 view .LVU70 270:Core/Src/main.c **** hqspi.Init.FlashID = QSPI_FLASH_ID_1; 240 .loc 1 270 24 is_stmt 0 view .LVU71 241 001e 0122 movs r2, #1 242 0020 8261 str r2, [r0, #24] 271:Core/Src/main.c **** hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; 243 .loc 1 271 3 is_stmt 1 view .LVU72 271:Core/Src/main.c **** hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; 244 .loc 1 271 22 is_stmt 0 view .LVU73 245 0022 C361 str r3, [r0, #28] 272:Core/Src/main.c **** if (HAL_QSPI_Init(&hqspi) != HAL_OK) 246 .loc 1 272 3 is_stmt 1 view .LVU74 272:Core/Src/main.c **** if (HAL_QSPI_Init(&hqspi) != HAL_OK) 247 .loc 1 272 24 is_stmt 0 view .LVU75 ARM GAS /tmp/ccOSKXvF.s page 12 248 0024 0362 str r3, [r0, #32] 273:Core/Src/main.c **** { 249 .loc 1 273 3 is_stmt 1 view .LVU76 273:Core/Src/main.c **** { 250 .loc 1 273 7 is_stmt 0 view .LVU77 251 0026 FFF7FEFF bl HAL_QSPI_Init 252 .LVL3: 281:Core/Src/main.c **** 253 .loc 1 281 1 view .LVU78 254 002a 08BD pop {r3, pc} 255 .L8: 256 .align 2 257 .L7: 258 002c 00000000 .word .LANCHOR0 259 0030 00500052 .word 1375752192 260 .cfi_endproc 261 .LFE147: 263 .section .text.MX_USART1_UART_Init,"ax",%progbits 264 .align 1 265 .syntax unified 266 .thumb 267 .thumb_func 268 .fpu fpv5-d16 270 MX_USART1_UART_Init: 271 .LFB148: 289:Core/Src/main.c **** 272 .loc 1 289 1 is_stmt 1 view -0 273 .cfi_startproc 274 @ args = 0, pretend = 0, frame = 0 275 @ frame_needed = 0, uses_anonymous_args = 0 276 0000 38B5 push {r3, r4, r5, lr} 277 .LCFI4: 278 .cfi_def_cfa_offset 16 279 .cfi_offset 3, -16 280 .cfi_offset 4, -12 281 .cfi_offset 5, -8 282 .cfi_offset 14, -4 298:Core/Src/main.c **** huart1.Init.BaudRate = 921600; 283 .loc 1 298 3 view .LVU80 298:Core/Src/main.c **** huart1.Init.BaudRate = 921600; 284 .loc 1 298 19 is_stmt 0 view .LVU81 285 0002 104C ldr r4, .L11 286 0004 104B ldr r3, .L11+4 287 0006 2360 str r3, [r4] 299:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; 288 .loc 1 299 3 is_stmt 1 view .LVU82 299:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; 289 .loc 1 299 24 is_stmt 0 view .LVU83 290 0008 4FF46123 mov r3, #921600 291 000c 6360 str r3, [r4, #4] 300:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; 292 .loc 1 300 3 is_stmt 1 view .LVU84 300:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; 293 .loc 1 300 26 is_stmt 0 view .LVU85 294 000e 0025 movs r5, #0 295 0010 A560 str r5, [r4, #8] 301:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; ARM GAS /tmp/ccOSKXvF.s page 13 296 .loc 1 301 3 is_stmt 1 view .LVU86 301:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; 297 .loc 1 301 24 is_stmt 0 view .LVU87 298 0012 E560 str r5, [r4, #12] 302:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; 299 .loc 1 302 3 is_stmt 1 view .LVU88 302:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; 300 .loc 1 302 22 is_stmt 0 view .LVU89 301 0014 2561 str r5, [r4, #16] 303:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 302 .loc 1 303 3 is_stmt 1 view .LVU90 303:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 303 .loc 1 303 20 is_stmt 0 view .LVU91 304 0016 0C23 movs r3, #12 305 0018 6361 str r3, [r4, #20] 304:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; 306 .loc 1 304 3 is_stmt 1 view .LVU92 304:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; 307 .loc 1 304 25 is_stmt 0 view .LVU93 308 001a A561 str r5, [r4, #24] 305:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 309 .loc 1 305 3 is_stmt 1 view .LVU94 305:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 310 .loc 1 305 28 is_stmt 0 view .LVU95 311 001c E561 str r5, [r4, #28] 306:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 312 .loc 1 306 3 is_stmt 1 view .LVU96 306:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 313 .loc 1 306 30 is_stmt 0 view .LVU97 314 001e 2562 str r5, [r4, #32] 307:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 315 .loc 1 307 3 is_stmt 1 view .LVU98 307:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 316 .loc 1 307 30 is_stmt 0 view .LVU99 317 0020 6562 str r5, [r4, #36] 308:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) 318 .loc 1 308 3 is_stmt 1 view .LVU100 308:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) 319 .loc 1 308 38 is_stmt 0 view .LVU101 320 0022 A562 str r5, [r4, #40] 309:Core/Src/main.c **** { 321 .loc 1 309 3 is_stmt 1 view .LVU102 309:Core/Src/main.c **** { 322 .loc 1 309 7 is_stmt 0 view .LVU103 323 0024 2046 mov r0, r4 324 0026 FFF7FEFF bl HAL_UART_Init 325 .LVL4: 313:Core/Src/main.c **** { 326 .loc 1 313 3 is_stmt 1 view .LVU104 313:Core/Src/main.c **** { 327 .loc 1 313 7 is_stmt 0 view .LVU105 328 002a 2946 mov r1, r5 329 002c 2046 mov r0, r4 330 002e FFF7FEFF bl HAL_UARTEx_SetTxFifoThreshold 331 .LVL5: 317:Core/Src/main.c **** { 332 .loc 1 317 3 is_stmt 1 view .LVU106 ARM GAS /tmp/ccOSKXvF.s page 14 317:Core/Src/main.c **** { 333 .loc 1 317 7 is_stmt 0 view .LVU107 334 0032 2946 mov r1, r5 335 0034 2046 mov r0, r4 336 0036 FFF7FEFF bl HAL_UARTEx_SetRxFifoThreshold 337 .LVL6: 321:Core/Src/main.c **** { 338 .loc 1 321 3 is_stmt 1 view .LVU108 321:Core/Src/main.c **** { 339 .loc 1 321 7 is_stmt 0 view .LVU109 340 003a 2046 mov r0, r4 341 003c FFF7FEFF bl HAL_UARTEx_DisableFifoMode 342 .LVL7: 329:Core/Src/main.c **** 343 .loc 1 329 1 view .LVU110 344 0040 38BD pop {r3, r4, r5, pc} 345 .L12: 346 0042 00BF .align 2 347 .L11: 348 0044 00000000 .word .LANCHOR1 349 0048 00100140 .word 1073811456 350 .cfi_endproc 351 .LFE148: 353 .section .text.SystemClock_Config,"ax",%progbits 354 .align 1 355 .global SystemClock_Config 356 .syntax unified 357 .thumb 358 .thumb_func 359 .fpu fpv5-d16 361 SystemClock_Config: 362 .LFB146: 180:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 363 .loc 1 180 1 is_stmt 1 view -0 364 .cfi_startproc 365 @ args = 0, pretend = 0, frame = 304 366 @ frame_needed = 0, uses_anonymous_args = 0 367 0000 70B5 push {r4, r5, r6, lr} 368 .LCFI5: 369 .cfi_def_cfa_offset 16 370 .cfi_offset 4, -16 371 .cfi_offset 5, -12 372 .cfi_offset 6, -8 373 .cfi_offset 14, -4 374 0002 CCB0 sub sp, sp, #304 375 .LCFI6: 376 .cfi_def_cfa_offset 320 181:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 377 .loc 1 181 3 view .LVU112 181:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 378 .loc 1 181 22 is_stmt 0 view .LVU113 379 0004 4C22 movs r2, #76 380 0006 0021 movs r1, #0 381 0008 39A8 add r0, sp, #228 382 000a FFF7FEFF bl memset 383 .LVL8: 182:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; ARM GAS /tmp/ccOSKXvF.s page 15 384 .loc 1 182 3 is_stmt 1 view .LVU114 182:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 385 .loc 1 182 22 is_stmt 0 view .LVU115 386 000e 2022 movs r2, #32 387 0010 0021 movs r1, #0 388 0012 31A8 add r0, sp, #196 389 0014 FFF7FEFF bl memset 390 .LVL9: 183:Core/Src/main.c **** 391 .loc 1 183 3 is_stmt 1 view .LVU116 183:Core/Src/main.c **** 392 .loc 1 183 28 is_stmt 0 view .LVU117 393 0018 BC22 movs r2, #188 394 001a 0021 movs r1, #0 395 001c 02A8 add r0, sp, #8 396 001e FFF7FEFF bl memset 397 .LVL10: 187:Core/Src/main.c **** /** Configure the main internal regulator output voltage 398 .loc 1 187 3 is_stmt 1 view .LVU118 399 0022 0220 movs r0, #2 400 0024 FFF7FEFF bl HAL_PWREx_ConfigSupply 401 .LVL11: 190:Core/Src/main.c **** 402 .loc 1 190 3 view .LVU119 403 .LBB8: 190:Core/Src/main.c **** 404 .loc 1 190 3 view .LVU120 405 0028 0023 movs r3, #0 406 002a 0193 str r3, [sp, #4] 190:Core/Src/main.c **** 407 .loc 1 190 3 view .LVU121 190:Core/Src/main.c **** 408 .loc 1 190 3 view .LVU122 409 002c 294B ldr r3, .L16 410 002e DA6A ldr r2, [r3, #44] 411 0030 22F00102 bic r2, r2, #1 412 0034 DA62 str r2, [r3, #44] 190:Core/Src/main.c **** 413 .loc 1 190 3 view .LVU123 414 0036 DB6A ldr r3, [r3, #44] 415 0038 03F00103 and r3, r3, #1 416 003c 0193 str r3, [sp, #4] 190:Core/Src/main.c **** 417 .loc 1 190 3 view .LVU124 418 003e 264B ldr r3, .L16+4 419 0040 9A69 ldr r2, [r3, #24] 420 0042 42F44042 orr r2, r2, #49152 421 0046 9A61 str r2, [r3, #24] 190:Core/Src/main.c **** 422 .loc 1 190 3 view .LVU125 423 0048 9B69 ldr r3, [r3, #24] 424 004a 03F44043 and r3, r3, #49152 425 004e 0193 str r3, [sp, #4] 190:Core/Src/main.c **** 426 .loc 1 190 3 view .LVU126 427 0050 019B ldr r3, [sp, #4] 428 .LBE8: ARM GAS /tmp/ccOSKXvF.s page 16 190:Core/Src/main.c **** 429 .loc 1 190 3 view .LVU127 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 430 .loc 1 192 3 view .LVU128 431 .L14: 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 432 .loc 1 192 48 discriminator 1 view .LVU129 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 433 .loc 1 192 8 discriminator 1 view .LVU130 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 434 .loc 1 192 10 is_stmt 0 discriminator 1 view .LVU131 435 0052 214B ldr r3, .L16+4 436 0054 9B69 ldr r3, [r3, #24] 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 437 .loc 1 192 8 discriminator 1 view .LVU132 438 0056 13F4005F tst r3, #8192 439 005a FAD0 beq .L14 196:Core/Src/main.c **** |RCC_OSCILLATORTYPE_HSE; 440 .loc 1 196 3 is_stmt 1 view .LVU133 196:Core/Src/main.c **** |RCC_OSCILLATORTYPE_HSE; 441 .loc 1 196 36 is_stmt 0 view .LVU134 442 005c 2323 movs r3, #35 443 005e 3993 str r3, [sp, #228] 198:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 444 .loc 1 198 3 is_stmt 1 view .LVU135 198:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 445 .loc 1 198 30 is_stmt 0 view .LVU136 446 0060 4FF48033 mov r3, #65536 447 0064 3A93 str r3, [sp, #232] 199:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 448 .loc 1 199 3 is_stmt 1 view .LVU137 199:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 449 .loc 1 199 30 is_stmt 0 view .LVU138 450 0066 0122 movs r2, #1 451 0068 3C92 str r2, [sp, #240] 200:Core/Src/main.c **** RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 452 .loc 1 200 3 is_stmt 1 view .LVU139 200:Core/Src/main.c **** RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 453 .loc 1 200 41 is_stmt 0 view .LVU140 454 006a 4025 movs r5, #64 455 006c 3D95 str r5, [sp, #244] 201:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 456 .loc 1 201 3 is_stmt 1 view .LVU141 201:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 457 .loc 1 201 32 is_stmt 0 view .LVU142 458 006e 3F92 str r2, [sp, #252] 202:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 459 .loc 1 202 3 is_stmt 1 view .LVU143 202:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 460 .loc 1 202 34 is_stmt 0 view .LVU144 461 0070 0223 movs r3, #2 462 0072 4293 str r3, [sp, #264] 203:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2; 463 .loc 1 203 3 is_stmt 1 view .LVU145 203:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2; 464 .loc 1 203 35 is_stmt 0 view .LVU146 465 0074 4393 str r3, [sp, #268] ARM GAS /tmp/ccOSKXvF.s page 17 204:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 40; 466 .loc 1 204 3 is_stmt 1 view .LVU147 204:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 40; 467 .loc 1 204 30 is_stmt 0 view .LVU148 468 0076 4493 str r3, [sp, #272] 205:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; 469 .loc 1 205 3 is_stmt 1 view .LVU149 205:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; 470 .loc 1 205 30 is_stmt 0 view .LVU150 471 0078 2821 movs r1, #40 472 007a 4591 str r1, [sp, #276] 206:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 1; 473 .loc 1 206 3 is_stmt 1 view .LVU151 206:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 1; 474 .loc 1 206 30 is_stmt 0 view .LVU152 475 007c 4693 str r3, [sp, #280] 207:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 1; 476 .loc 1 207 3 is_stmt 1 view .LVU153 207:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 1; 477 .loc 1 207 30 is_stmt 0 view .LVU154 478 007e 4792 str r2, [sp, #284] 208:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 479 .loc 1 208 3 is_stmt 1 view .LVU155 208:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 480 .loc 1 208 30 is_stmt 0 view .LVU156 481 0080 4892 str r2, [sp, #288] 209:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; 482 .loc 1 209 3 is_stmt 1 view .LVU157 209:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; 483 .loc 1 209 32 is_stmt 0 view .LVU158 484 0082 0826 movs r6, #8 485 0084 4996 str r6, [sp, #292] 210:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; 486 .loc 1 210 3 is_stmt 1 view .LVU159 210:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; 487 .loc 1 210 35 is_stmt 0 view .LVU160 488 0086 4A93 str r3, [sp, #296] 211:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 489 .loc 1 211 3 is_stmt 1 view .LVU161 211:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 490 .loc 1 211 34 is_stmt 0 view .LVU162 491 0088 0024 movs r4, #0 492 008a 4B94 str r4, [sp, #300] 212:Core/Src/main.c **** { 493 .loc 1 212 3 is_stmt 1 view .LVU163 212:Core/Src/main.c **** { 494 .loc 1 212 7 is_stmt 0 view .LVU164 495 008c 39A8 add r0, sp, #228 496 008e FFF7FEFF bl HAL_RCC_OscConfig 497 .LVL12: 218:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 498 .loc 1 218 3 is_stmt 1 view .LVU165 218:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 499 .loc 1 218 31 is_stmt 0 view .LVU166 500 0092 3F23 movs r3, #63 501 0094 3193 str r3, [sp, #196] 221:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; ARM GAS /tmp/ccOSKXvF.s page 18 502 .loc 1 221 3 is_stmt 1 view .LVU167 221:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 503 .loc 1 221 34 is_stmt 0 view .LVU168 504 0096 0323 movs r3, #3 505 0098 3293 str r3, [sp, #200] 222:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 506 .loc 1 222 3 is_stmt 1 view .LVU169 222:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 507 .loc 1 222 35 is_stmt 0 view .LVU170 508 009a 3394 str r4, [sp, #204] 223:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 509 .loc 1 223 3 is_stmt 1 view .LVU171 223:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 510 .loc 1 223 35 is_stmt 0 view .LVU172 511 009c 3496 str r6, [sp, #208] 224:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 512 .loc 1 224 3 is_stmt 1 view .LVU173 224:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 513 .loc 1 224 36 is_stmt 0 view .LVU174 514 009e 3595 str r5, [sp, #212] 225:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 515 .loc 1 225 3 is_stmt 1 view .LVU175 225:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 516 .loc 1 225 36 is_stmt 0 view .LVU176 517 00a0 3695 str r5, [sp, #216] 226:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 518 .loc 1 226 3 is_stmt 1 view .LVU177 226:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 519 .loc 1 226 36 is_stmt 0 view .LVU178 520 00a2 4FF48063 mov r3, #1024 521 00a6 3793 str r3, [sp, #220] 227:Core/Src/main.c **** 522 .loc 1 227 3 is_stmt 1 view .LVU179 227:Core/Src/main.c **** 523 .loc 1 227 36 is_stmt 0 view .LVU180 524 00a8 3895 str r5, [sp, #224] 229:Core/Src/main.c **** { 525 .loc 1 229 3 is_stmt 1 view .LVU181 229:Core/Src/main.c **** { 526 .loc 1 229 7 is_stmt 0 view .LVU182 527 00aa 2146 mov r1, r4 528 00ac 31A8 add r0, sp, #196 529 00ae FFF7FEFF bl HAL_RCC_ClockConfig 530 .LVL13: 233:Core/Src/main.c **** |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; 531 .loc 1 233 3 is_stmt 1 view .LVU183 233:Core/Src/main.c **** |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; 532 .loc 1 233 44 is_stmt 0 view .LVU184 533 00b2 0A4B ldr r3, .L16+8 534 00b4 0293 str r3, [sp, #8] 235:Core/Src/main.c **** PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; 535 .loc 1 235 3 is_stmt 1 view .LVU185 235:Core/Src/main.c **** PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; 536 .loc 1 235 42 is_stmt 0 view .LVU186 537 00b6 3023 movs r3, #48 538 00b8 1493 str r3, [sp, #80] 236:Core/Src/main.c **** PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; ARM GAS /tmp/ccOSKXvF.s page 19 539 .loc 1 236 3 is_stmt 1 view .LVU187 236:Core/Src/main.c **** PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 540 .loc 1 236 43 is_stmt 0 view .LVU188 541 00ba 1694 str r4, [sp, #88] 237:Core/Src/main.c **** PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; 542 .loc 1 237 3 is_stmt 1 view .LVU189 237:Core/Src/main.c **** PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; 543 .loc 1 237 45 is_stmt 0 view .LVU190 544 00bc 2094 str r4, [sp, #128] 238:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 545 .loc 1 238 3 is_stmt 1 view .LVU191 238:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 546 .loc 1 238 41 is_stmt 0 view .LVU192 547 00be 4FF44013 mov r3, #3145728 548 00c2 2393 str r3, [sp, #140] 239:Core/Src/main.c **** { 549 .loc 1 239 3 is_stmt 1 view .LVU193 239:Core/Src/main.c **** { 550 .loc 1 239 7 is_stmt 0 view .LVU194 551 00c4 0DEB0600 add r0, sp, r6 552 00c8 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 553 .LVL14: 245:Core/Src/main.c **** } 554 .loc 1 245 3 is_stmt 1 view .LVU195 555 00cc FFF7FEFF bl HAL_PWREx_EnableUSBVoltageDetector 556 .LVL15: 246:Core/Src/main.c **** 557 .loc 1 246 1 is_stmt 0 view .LVU196 558 00d0 4CB0 add sp, sp, #304 559 .LCFI7: 560 .cfi_def_cfa_offset 16 561 @ sp needed 562 00d2 70BD pop {r4, r5, r6, pc} 563 .L17: 564 .align 2 565 .L16: 566 00d4 00040058 .word 1476396032 567 00d8 00480258 .word 1476544512 568 00dc 01000482 .word -2113667071 569 .cfi_endproc 570 .LFE146: 572 .section .rodata.main.str1.4,"aMS",%progbits,1 573 .align 2 574 .LC0: 575 0000 4D61696E .ascii "Main: Mfg: 0x%x\015\012\000" 575 3A204D66 575 673A2030 575 7825780D 575 0A00 576 0012 0000 .align 2 577 .LC1: 578 0014 51535049 .ascii "QSPI mapped ok!\015\012\000" 578 206D6170 578 70656420 578 6F6B210D 578 0A00 579 0026 0000 .align 2 ARM GAS /tmp/ccOSKXvF.s page 20 580 .LC2: 581 0028 56616C69 .ascii "Valid SP found!\015\012\000" 581 64205350 581 20666F75 581 6E64210D 581 0A00 582 003a 0000 .align 2 583 .LC3: 584 003c 456E7472 .ascii "Entry: 0x%08lx\015\012\000" 584 793A2030 584 78253038 584 6C780D0A 584 00 585 004d 000000 .align 2 586 .LC4: 587 0050 4E6F2076 .ascii "No valid image found!\015\012\000" 587 616C6964 587 20696D61 587 67652066 587 6F756E64 588 .section .text.main,"ax",%progbits 589 .align 1 590 .global main 591 .syntax unified 592 .thumb 593 .thumb_func 594 .fpu fpv5-d16 596 main: 597 .LFB145: 78:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 598 .loc 1 78 1 is_stmt 1 view -0 599 .cfi_startproc 600 @ args = 0, pretend = 0, frame = 80 601 @ frame_needed = 0, uses_anonymous_args = 0 602 0000 30B5 push {r4, r5, lr} 603 .LCFI8: 604 .cfi_def_cfa_offset 12 605 .cfi_offset 4, -12 606 .cfi_offset 5, -8 607 .cfi_offset 14, -4 608 0002 95B0 sub sp, sp, #84 609 .LCFI9: 610 .cfi_def_cfa_offset 96 86:Core/Src/main.c **** 611 .loc 1 86 3 view .LVU198 612 0004 FFF7FEFF bl HAL_Init 613 .LVL16: 93:Core/Src/main.c **** 614 .loc 1 93 3 view .LVU199 615 0008 FFF7FEFF bl SystemClock_Config 616 .LVL17: 100:Core/Src/main.c **** MX_QUADSPI_Init(); 617 .loc 1 100 3 view .LVU200 618 000c FFF7FEFF bl MX_GPIO_Init 619 .LVL18: 101:Core/Src/main.c **** MX_USART1_UART_Init(); 620 .loc 1 101 3 view .LVU201 ARM GAS /tmp/ccOSKXvF.s page 21 621 0010 FFF7FEFF bl MX_QUADSPI_Init 622 .LVL19: 102:Core/Src/main.c **** MX_USB_DEVICE_Init(); 623 .loc 1 102 3 view .LVU202 624 0014 FFF7FEFF bl MX_USART1_UART_Init 625 .LVL20: 103:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 626 .loc 1 103 3 view .LVU203 627 0018 FFF7FEFF bl MX_USB_DEVICE_Init 628 .LVL21: 106:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; 629 .loc 1 106 3 view .LVU204 106:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; 630 .loc 1 106 6 is_stmt 0 view .LVU205 631 001c 344B ldr r3, .L25 632 001e 1B78 ldrb r3, [r3] @ zero_extendqisi2 106:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; 633 .loc 1 106 5 view .LVU206 634 0020 03B1 cbz r3, .L23 635 .L19: 166:Core/Src/main.c **** { 636 .loc 1 166 3 is_stmt 1 discriminator 2 view .LVU207 171:Core/Src/main.c **** /* USER CODE END 3 */ 637 .loc 1 171 3 discriminator 2 view .LVU208 166:Core/Src/main.c **** { 638 .loc 1 166 9 discriminator 2 view .LVU209 639 0022 FEE7 b .L19 640 .L23: 641 .LBB9: 107:Core/Src/main.c **** QSPI_MemoryMappedTypeDef sMemMappedCfg; 642 .loc 1 107 7 view .LVU210 108:Core/Src/main.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; 643 .loc 1 108 7 view .LVU211 109:Core/Src/main.c **** sCommand.AddressMode = QSPI_ADDRESS_4_LINES; 644 .loc 1 109 7 view .LVU212 109:Core/Src/main.c **** sCommand.AddressMode = QSPI_ADDRESS_4_LINES; 645 .loc 1 109 32 is_stmt 0 view .LVU213 646 0024 4FF48073 mov r3, #256 647 0028 0C93 str r3, [sp, #48] 110:Core/Src/main.c **** sCommand.AddressSize = QSPI_ADDRESS_24_BITS; 648 .loc 1 110 7 is_stmt 1 view .LVU214 110:Core/Src/main.c **** sCommand.AddressSize = QSPI_ADDRESS_24_BITS; 649 .loc 1 110 28 is_stmt 0 view .LVU215 650 002a 4FF44063 mov r3, #3072 651 002e 0D93 str r3, [sp, #52] 111:Core/Src/main.c **** sCommand.DataMode = QSPI_DATA_4_LINES; 652 .loc 1 111 7 is_stmt 1 view .LVU216 111:Core/Src/main.c **** sCommand.DataMode = QSPI_DATA_4_LINES; 653 .loc 1 111 28 is_stmt 0 view .LVU217 654 0030 4FF40053 mov r3, #8192 655 0034 0993 str r3, [sp, #36] 112:Core/Src/main.c **** sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; 656 .loc 1 112 7 is_stmt 1 view .LVU218 112:Core/Src/main.c **** sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; 657 .loc 1 112 25 is_stmt 0 view .LVU219 658 0036 4FF04073 mov r3, #50331648 659 003a 0F93 str r3, [sp, #60] ARM GAS /tmp/ccOSKXvF.s page 22 113:Core/Src/main.c **** sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; 660 .loc 1 113 7 is_stmt 1 view .LVU220 113:Core/Src/main.c **** sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; 661 .loc 1 113 34 is_stmt 0 view .LVU221 662 003c 4FF44043 mov r3, #49152 663 0040 0E93 str r3, [sp, #56] 114:Core/Src/main.c **** sCommand.AlternateBytes = 0xFF; 664 .loc 1 114 7 is_stmt 1 view .LVU222 114:Core/Src/main.c **** sCommand.AlternateBytes = 0xFF; 665 .loc 1 114 35 is_stmt 0 view .LVU223 666 0042 0024 movs r4, #0 667 0044 0A94 str r4, [sp, #40] 115:Core/Src/main.c **** sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; 668 .loc 1 115 7 is_stmt 1 view .LVU224 115:Core/Src/main.c **** sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; 669 .loc 1 115 31 is_stmt 0 view .LVU225 670 0046 FF23 movs r3, #255 671 0048 0893 str r3, [sp, #32] 116:Core/Src/main.c **** sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 672 .loc 1 116 7 is_stmt 1 view .LVU226 116:Core/Src/main.c **** sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 673 .loc 1 116 24 is_stmt 0 view .LVU227 674 004a 1194 str r4, [sp, #68] 117:Core/Src/main.c **** sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 675 .loc 1 117 7 is_stmt 1 view .LVU228 117:Core/Src/main.c **** sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 676 .loc 1 117 33 is_stmt 0 view .LVU229 677 004c 1294 str r4, [sp, #72] 118:Core/Src/main.c **** sCommand.Instruction = 0xEB; 678 .loc 1 118 7 is_stmt 1 view .LVU230 118:Core/Src/main.c **** sCommand.Instruction = 0xEB; 679 .loc 1 118 25 is_stmt 0 view .LVU231 680 004e 1394 str r4, [sp, #76] 119:Core/Src/main.c **** sCommand.DummyCycles = 4; 681 .loc 1 119 7 is_stmt 1 view .LVU232 119:Core/Src/main.c **** sCommand.DummyCycles = 4; 682 .loc 1 119 28 is_stmt 0 view .LVU233 683 0050 EB23 movs r3, #235 684 0052 0693 str r3, [sp, #24] 120:Core/Src/main.c **** sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; 685 .loc 1 120 7 is_stmt 1 view .LVU234 120:Core/Src/main.c **** sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; 686 .loc 1 120 28 is_stmt 0 view .LVU235 687 0054 0423 movs r3, #4 688 0056 0B93 str r3, [sp, #44] 121:Core/Src/main.c **** sMemMappedCfg.TimeOutPeriod = 0; 689 .loc 1 121 7 is_stmt 1 view .LVU236 121:Core/Src/main.c **** sMemMappedCfg.TimeOutPeriod = 0; 690 .loc 1 121 39 is_stmt 0 view .LVU237 691 0058 0194 str r4, [sp, #4] 122:Core/Src/main.c **** 692 .loc 1 122 7 is_stmt 1 view .LVU238 122:Core/Src/main.c **** 693 .loc 1 122 35 is_stmt 0 view .LVU239 694 005a 0094 str r4, [sp] 124:Core/Src/main.c **** w25_flash.interface = &hqspi; 695 .loc 1 124 7 is_stmt 1 view .LVU240 ARM GAS /tmp/ccOSKXvF.s page 23 125:Core/Src/main.c **** w25_flash.mode = W25_MODE_QUAD; 696 .loc 1 125 7 view .LVU241 125:Core/Src/main.c **** w25_flash.mode = W25_MODE_QUAD; 697 .loc 1 125 27 is_stmt 0 view .LVU242 698 005c 254D ldr r5, .L25+4 699 005e 0295 str r5, [sp, #8] 126:Core/Src/main.c **** w25_flash.address_size = W25_ADDRESS_24BITS; 700 .loc 1 126 7 is_stmt 1 view .LVU243 126:Core/Src/main.c **** w25_flash.address_size = W25_ADDRESS_24BITS; 701 .loc 1 126 22 is_stmt 0 view .LVU244 702 0060 0223 movs r3, #2 703 0062 8DF80C30 strb r3, [sp, #12] 127:Core/Src/main.c **** 704 .loc 1 127 7 is_stmt 1 view .LVU245 127:Core/Src/main.c **** 705 .loc 1 127 30 is_stmt 0 view .LVU246 706 0066 8DF80D40 strb r4, [sp, #13] 130:Core/Src/main.c **** #endif // USE_QPI_MODE 707 .loc 1 130 7 is_stmt 1 view .LVU247 708 006a 2146 mov r1, r4 709 006c 02A8 add r0, sp, #8 710 006e FFF7FEFF bl W25_QPI_Mode 711 .LVL22: 133:Core/Src/main.c **** printf("Main: Mfg: 0x%x\r\n", w25_flash.manufacturer); 712 .loc 1 133 7 view .LVU248 713 0072 02A8 add r0, sp, #8 714 0074 FFF7FEFF bl W25_QSPI_Init 715 .LVL23: 134:Core/Src/main.c **** 716 .loc 1 134 7 view .LVU249 717 0078 9DF81410 ldrb r1, [sp, #20] @ zero_extendqisi2 718 007c 1E48 ldr r0, .L25+8 719 007e FFF7FEFF bl printf_ 720 .LVL24: 136:Core/Src/main.c **** 721 .loc 1 136 7 view .LVU250 722 0082 2146 mov r1, r4 723 0084 02A8 add r0, sp, #8 724 0086 FFF7FEFF bl W25_QSPI_QuadEnable 725 .LVL25: 139:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 1); 726 .loc 1 139 7 view .LVU251 139:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 1); 727 .loc 1 139 32 is_stmt 0 view .LVU252 728 008a 4FF44073 mov r3, #768 729 008e 0C93 str r3, [sp, #48] 140:Core/Src/main.c **** #if(QPI_HIGH_SPEED == 1) // For 80MHz HIGHHHHHH speed QPI mode(33-80MHz), additional 4 dummy cycles 730 .loc 1 140 7 is_stmt 1 view .LVU253 731 0090 0121 movs r1, #1 732 0092 02A8 add r0, sp, #8 733 0094 FFF7FEFF bl W25_QPI_Mode 734 .LVL26: 145:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); 735 .loc 1 145 7 view .LVU254 145:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); 736 .loc 1 145 28 is_stmt 0 view .LVU255 737 0098 0B94 str r4, [sp, #44] ARM GAS /tmp/ccOSKXvF.s page 24 146:Core/Src/main.c **** #endif // QPI_HIGH_SPEED 738 .loc 1 146 7 is_stmt 1 view .LVU256 739 009a 2246 mov r2, r4 740 009c 2146 mov r1, r4 741 009e 02A8 add r0, sp, #8 742 00a0 FFF7FEFF bl W25_QPI_ReadParams 743 .LVL27: 150:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); 744 .loc 1 150 7 view .LVU257 150:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); 745 .loc 1 150 10 is_stmt 0 view .LVU258 746 00a4 6A46 mov r2, sp 747 00a6 06A9 add r1, sp, #24 748 00a8 2846 mov r0, r5 749 00aa FFF7FEFF bl HAL_QSPI_MemoryMapped 750 .LVL28: 150:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); 751 .loc 1 150 9 view .LVU259 752 00ae 00B1 cbz r0, .L24 753 .L20: 754 00b0 B7E7 b .L19 755 .L24: 151:Core/Src/main.c **** if(BL_CheckValidImage(0x90000000) == HAL_OK) { 756 .loc 1 151 11 is_stmt 1 view .LVU260 757 00b2 1248 ldr r0, .L25+12 758 00b4 FFF7FEFF bl printf_ 759 .LVL29: 152:Core/Src/main.c **** printf("Valid SP found!\r\n"); 760 .loc 1 152 11 view .LVU261 152:Core/Src/main.c **** printf("Valid SP found!\r\n"); 761 .loc 1 152 14 is_stmt 0 view .LVU262 762 00b8 4FF01040 mov r0, #-1879048192 763 00bc FFF7FEFF bl BL_CheckValidImage 764 .LVL30: 152:Core/Src/main.c **** printf("Valid SP found!\r\n"); 765 .loc 1 152 13 view .LVU263 766 00c0 88B9 cbnz r0, .L21 767 .LBB10: 153:Core/Src/main.c **** uint32_t entry = BL_GetEntryPoint(0x90000000); 768 .loc 1 153 15 is_stmt 1 view .LVU264 769 00c2 0F48 ldr r0, .L25+16 770 00c4 FFF7FEFF bl printf_ 771 .LVL31: 154:Core/Src/main.c **** printf("Entry: 0x%08lx\r\n", entry); 772 .loc 1 154 15 view .LVU265 154:Core/Src/main.c **** printf("Entry: 0x%08lx\r\n", entry); 773 .loc 1 154 32 is_stmt 0 view .LVU266 774 00c8 4FF01040 mov r0, #-1879048192 775 00cc FFF7FEFF bl BL_GetEntryPoint 776 .LVL32: 777 00d0 0446 mov r4, r0 778 .LVL33: 155:Core/Src/main.c **** BL_JumpToXIPStart(entry, 0x90000000); 779 .loc 1 155 15 is_stmt 1 view .LVU267 780 00d2 0146 mov r1, r0 781 00d4 0B48 ldr r0, .L25+20 782 .LVL34: ARM GAS /tmp/ccOSKXvF.s page 25 155:Core/Src/main.c **** BL_JumpToXIPStart(entry, 0x90000000); 783 .loc 1 155 15 is_stmt 0 view .LVU268 784 00d6 FFF7FEFF bl printf_ 785 .LVL35: 156:Core/Src/main.c **** } 786 .loc 1 156 15 is_stmt 1 view .LVU269 787 00da 4FF01041 mov r1, #-1879048192 788 00de 2046 mov r0, r4 789 00e0 FFF7FEFF bl BL_JumpToXIPStart 790 .LVL36: 791 .LBE10: 792 00e4 E4E7 b .L20 793 .LVL37: 794 .L21: 158:Core/Src/main.c **** } 795 .loc 1 158 16 view .LVU270 796 00e6 0848 ldr r0, .L25+24 797 00e8 FFF7FEFF bl printf_ 798 .LVL38: 799 00ec E0E7 b .L20 800 .L26: 801 00ee 00BF .align 2 802 .L25: 803 00f0 00000000 .word .LANCHOR2 804 00f4 00000000 .word .LANCHOR0 805 00f8 00000000 .word .LC0 806 00fc 14000000 .word .LC1 807 0100 28000000 .word .LC2 808 0104 3C000000 .word .LC3 809 0108 50000000 .word .LC4 810 .LBE9: 811 .cfi_endproc 812 .LFE145: 814 .section .text.Error_Handler,"ax",%progbits 815 .align 1 816 .global Error_Handler 817 .syntax unified 818 .thumb 819 .thumb_func 820 .fpu fpv5-d16 822 Error_Handler: 823 .LFB150: 365:Core/Src/main.c **** 366:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 367:Core/Src/main.c **** 368:Core/Src/main.c **** /* USER CODE END 4 */ 369:Core/Src/main.c **** 370:Core/Src/main.c **** /** 371:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 372:Core/Src/main.c **** * @retval None 373:Core/Src/main.c **** */ 374:Core/Src/main.c **** void Error_Handler(void) 375:Core/Src/main.c **** { 824 .loc 1 375 1 view -0 825 .cfi_startproc 826 @ args = 0, pretend = 0, frame = 0 827 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccOSKXvF.s page 26 828 @ link register save eliminated. 376:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 377:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 378:Core/Src/main.c **** 379:Core/Src/main.c **** /* USER CODE END Error_Handler_Debug */ 380:Core/Src/main.c **** } 829 .loc 1 380 1 view .LVU272 830 0000 7047 bx lr 831 .cfi_endproc 832 .LFE150: 834 .global g_DFU 835 .global huart1 836 .global hqspi 837 .section .bss.g_DFU,"aw",%nobits 838 .set .LANCHOR2,. + 0 841 g_DFU: 842 0000 00 .space 1 843 .section .bss.hqspi,"aw",%nobits 844 .align 2 845 .set .LANCHOR0,. + 0 848 hqspi: 849 0000 00000000 .space 76 849 00000000 849 00000000 849 00000000 849 00000000 850 .section .bss.huart1,"aw",%nobits 851 .align 2 852 .set .LANCHOR1,. + 0 855 huart1: 856 0000 00000000 .space 140 856 00000000 856 00000000 856 00000000 856 00000000 857 .text 858 .Letext0: 859 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" 860 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" 861 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" 862 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" 863 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" 864 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h" 865 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" 866 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" 867 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" 868 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" 869 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" 870 .file 13 "Core/Inc/w25_qspi.h" 871 .file 14 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h" 872 .file 15 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h" 873 .file 16 "Core/Inc/printf.h" 874 .file 17 "Core/Inc/bootloader_control.h" 875 .file 18 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" 876 .file 19 "USB_DEVICE/App/usb_device.h" 877 .file 20 "" ARM GAS /tmp/ccOSKXvF.s page 27 DEFINED SYMBOLS *ABS*:0000000000000000 main.c /tmp/ccOSKXvF.s:17 .text.MX_GPIO_Init:0000000000000000 $t /tmp/ccOSKXvF.s:24 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init /tmp/ccOSKXvF.s:190 .text.MX_GPIO_Init:00000000000000d8 $d /tmp/ccOSKXvF.s:197 .text.MX_QUADSPI_Init:0000000000000000 $t /tmp/ccOSKXvF.s:203 .text.MX_QUADSPI_Init:0000000000000000 MX_QUADSPI_Init /tmp/ccOSKXvF.s:258 .text.MX_QUADSPI_Init:000000000000002c $d /tmp/ccOSKXvF.s:264 .text.MX_USART1_UART_Init:0000000000000000 $t /tmp/ccOSKXvF.s:270 .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init /tmp/ccOSKXvF.s:348 .text.MX_USART1_UART_Init:0000000000000044 $d /tmp/ccOSKXvF.s:354 .text.SystemClock_Config:0000000000000000 $t /tmp/ccOSKXvF.s:361 .text.SystemClock_Config:0000000000000000 SystemClock_Config /tmp/ccOSKXvF.s:566 .text.SystemClock_Config:00000000000000d4 $d /tmp/ccOSKXvF.s:573 .rodata.main.str1.4:0000000000000000 $d /tmp/ccOSKXvF.s:589 .text.main:0000000000000000 $t /tmp/ccOSKXvF.s:596 .text.main:0000000000000000 main /tmp/ccOSKXvF.s:803 .text.main:00000000000000f0 $d /tmp/ccOSKXvF.s:815 .text.Error_Handler:0000000000000000 $t /tmp/ccOSKXvF.s:822 .text.Error_Handler:0000000000000000 Error_Handler /tmp/ccOSKXvF.s:841 .bss.g_DFU:0000000000000000 g_DFU /tmp/ccOSKXvF.s:855 .bss.huart1:0000000000000000 huart1 /tmp/ccOSKXvF.s:848 .bss.hqspi:0000000000000000 hqspi /tmp/ccOSKXvF.s:842 .bss.g_DFU:0000000000000000 $d /tmp/ccOSKXvF.s:844 .bss.hqspi:0000000000000000 $d /tmp/ccOSKXvF.s:851 .bss.huart1:0000000000000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_GPIO_Init HAL_QSPI_Init HAL_UART_Init HAL_UARTEx_SetTxFifoThreshold HAL_UARTEx_SetRxFifoThreshold HAL_UARTEx_DisableFifoMode memset HAL_PWREx_ConfigSupply HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_RCCEx_PeriphCLKConfig HAL_PWREx_EnableUSBVoltageDetector HAL_Init MX_USB_DEVICE_Init W25_QPI_Mode W25_QSPI_Init printf_ W25_QSPI_QuadEnable W25_QPI_ReadParams HAL_QSPI_MemoryMapped BL_CheckValidImage BL_GetEntryPoint BL_JumpToXIPStart