5701 lines
412 KiB
Plaintext
5701 lines
412 KiB
Plaintext
ARM GAS /tmp/ccV0GlXv.s page 1
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1 .cpu cortex-m7
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2 .eabi_attribute 28, 1
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3 .eabi_attribute 20, 1
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4 .eabi_attribute 21, 1
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5 .eabi_attribute 23, 3
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6 .eabi_attribute 24, 1
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7 .eabi_attribute 25, 1
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8 .eabi_attribute 26, 1
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9 .eabi_attribute 30, 1
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10 .eabi_attribute 34, 1
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11 .eabi_attribute 18, 4
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12 .file "stm32h7xx_hal_cortex.c"
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13 .text
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14 .Ltext0:
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15 .cfi_sections .debug_frame
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16 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits
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17 .align 1
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18 .global HAL_NVIC_SetPriorityGrouping
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19 .arch armv7e-m
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20 .syntax unified
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21 .thumb
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22 .thumb_func
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23 .fpu fpv5-d16
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25 HAL_NVIC_SetPriorityGrouping:
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26 .LVL0:
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27 .LFB141:
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28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c"
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1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
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2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ******************************************************************************
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3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @file stm32h7xx_hal_cortex.c
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4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @author MCD Application Team
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5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief CORTEX HAL module driver.
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6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This file provides firmware functions to manage the following
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7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * functionalities of the CORTEX:
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8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + Initialization and de-initialization functions
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9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + Peripheral Control functions
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10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *
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11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @verbatim
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12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ==============================================================================
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13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ##### How to use this driver #####
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14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ==============================================================================
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15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..]
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17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver ***
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18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ===========================================================
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19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..]
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20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ).
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21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** The Cortex-M exceptions are managed by CMSIS functions.
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22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
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24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** function according to the following table.
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25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
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26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
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27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) please refer to programming manual for details in how to configure priority.
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28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
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30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority.
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ARM GAS /tmp/ccV0GlXv.s page 2
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31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority):
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33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+@) Lowest preemption priority
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34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+@) Lowest sub priority
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35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number)
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36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..]
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38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver ***
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39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ========================================================
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40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..]
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41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** Setup SysTick Timer for time base.
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42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
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44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** is a CMSIS function that:
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45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter.
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46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
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47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Resets the SysTick Counter register.
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48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
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49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Enables the SysTick Interrupt.
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50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Starts the SysTick Counter.
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51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
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53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
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54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
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55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** inside the stm32h7xx_hal_cortex.h file.
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56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the
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58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
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59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
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60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula:
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62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
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64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
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65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF
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66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @endverbatim
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68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ******************************************************************************
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69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @attention
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70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *
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71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
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72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * All rights reserved.</center></h2>
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73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *
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74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license,
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75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the
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76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * License. You may obtain a copy of the License at:
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77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause
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78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *
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79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ******************************************************************************
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80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
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81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
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83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #include "stm32h7xx_hal.h"
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84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @addtogroup STM32H7xx_HAL_Driver
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86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{
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87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
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ARM GAS /tmp/ccV0GlXv.s page 3
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88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
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90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief CORTEX HAL module driver
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91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{
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92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
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93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
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95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
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97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
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98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
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99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
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100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/
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101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
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102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
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104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{
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105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
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106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
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109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initialization and Configuration functions
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110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *
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111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @verbatim
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112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ==============================================================================
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113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ##### Initialization and de-initialization functions #####
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114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ==============================================================================
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115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..]
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116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts
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117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** Systick functionalities
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118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @endverbatim
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120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{
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121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
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122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
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125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Sets the priority grouping field (preemption priority and subpriority)
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126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * using the required unlock sequence.
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127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length.
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128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values:
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129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
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130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 4 bits for subpriority
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131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
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132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 3 bits for subpriority
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133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
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134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 2 bits for subpriority
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135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
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136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 1 bits for subpriority
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137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
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138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 0 bits for subpriority
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139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
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140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority.
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141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
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142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
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143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
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144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
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ARM GAS /tmp/ccV0GlXv.s page 4
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29 .loc 1 144 1 view -0
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 0
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32 @ frame_needed = 0, uses_anonymous_args = 0
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33 @ link register save eliminated.
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145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
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146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
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34 .loc 1 146 3 view .LVU1
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147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
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148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
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149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup);
|
||
35 .loc 1 149 3 view .LVU2
|
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36 .LBB38:
|
||
37 .LBI38:
|
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38 .file 2 "Drivers/CMSIS/Include/core_cm7.h"
|
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1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//**
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2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h
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3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
|
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4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8
|
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5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018
|
||
6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/
|
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7:Drivers/CMSIS/Include/core_cm7.h **** /*
|
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8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||
9:Drivers/CMSIS/Include/core_cm7.h **** *
|
||
10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0
|
||
11:Drivers/CMSIS/Include/core_cm7.h **** *
|
||
12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
|
||
13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License.
|
||
14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at
|
||
15:Drivers/CMSIS/Include/core_cm7.h **** *
|
||
16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0
|
||
17:Drivers/CMSIS/Include/core_cm7.h **** *
|
||
18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software
|
||
19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||
20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and
|
||
22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License.
|
||
23:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
24:Drivers/CMSIS/Include/core_cm7.h ****
|
||
25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ )
|
||
26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */
|
||
27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__)
|
||
28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */
|
||
29:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
30:Drivers/CMSIS/Include/core_cm7.h ****
|
||
31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC
|
||
32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC
|
||
33:Drivers/CMSIS/Include/core_cm7.h ****
|
||
34:Drivers/CMSIS/Include/core_cm7.h **** #include <stdint.h>
|
||
35:Drivers/CMSIS/Include/core_cm7.h ****
|
||
36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
|
||
37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" {
|
||
38:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
39:Drivers/CMSIS/Include/core_cm7.h ****
|
||
40:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||
42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules:
|
||
ARM GAS /tmp/ccV0GlXv.s page 5
|
||
|
||
|
||
43:Drivers/CMSIS/Include/core_cm7.h ****
|
||
44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.<br>
|
||
45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'.
|
||
46:Drivers/CMSIS/Include/core_cm7.h ****
|
||
47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||
48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers.
|
||
49:Drivers/CMSIS/Include/core_cm7.h ****
|
||
50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.<br>
|
||
51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code.
|
||
52:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
53:Drivers/CMSIS/Include/core_cm7.h ****
|
||
54:Drivers/CMSIS/Include/core_cm7.h ****
|
||
55:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
|
||
56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions
|
||
57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/
|
||
58:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7
|
||
60:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
61:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
62:Drivers/CMSIS/Include/core_cm7.h ****
|
||
63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h"
|
||
64:Drivers/CMSIS/Include/core_cm7.h ****
|
||
65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */
|
||
66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1
|
||
67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0
|
||
68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
|
||
69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS
|
||
70:Drivers/CMSIS/Include/core_cm7.h ****
|
||
71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */
|
||
72:Drivers/CMSIS/Include/core_cm7.h ****
|
||
73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not.
|
||
74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
|
||
75:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
|
||
77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP
|
||
78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
80:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
|
||
82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
83:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
84:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
86:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
87:Drivers/CMSIS/Include/core_cm7.h ****
|
||
88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||
89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP
|
||
90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
92:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
|
||
94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
95:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
96:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
98:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
99:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 6
|
||
|
||
|
||
100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ )
|
||
101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||
102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
104:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
|
||
106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
107:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
108:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
110:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
111:Drivers/CMSIS/Include/core_cm7.h ****
|
||
112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ )
|
||
113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__
|
||
114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
116:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
|
||
118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
119:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
120:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
122:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
123:Drivers/CMSIS/Include/core_cm7.h ****
|
||
124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ )
|
||
125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__
|
||
126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
128:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
|
||
130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
131:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
132:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
134:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
135:Drivers/CMSIS/Include/core_cm7.h ****
|
||
136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ )
|
||
137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__
|
||
138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
140:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
|
||
142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
143:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
144:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
146:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
147:Drivers/CMSIS/Include/core_cm7.h ****
|
||
148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ )
|
||
149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U)
|
||
150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||
151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U
|
||
152:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
|
||
154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
155:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
156:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
ARM GAS /tmp/ccV0GlXv.s page 7
|
||
|
||
|
||
157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
|
||
158:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
159:Drivers/CMSIS/Include/core_cm7.h ****
|
||
160:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
161:Drivers/CMSIS/Include/core_cm7.h ****
|
||
162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||
163:Drivers/CMSIS/Include/core_cm7.h ****
|
||
164:Drivers/CMSIS/Include/core_cm7.h ****
|
||
165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
|
||
166:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
167:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
168:Drivers/CMSIS/Include/core_cm7.h ****
|
||
169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */
|
||
170:Drivers/CMSIS/Include/core_cm7.h ****
|
||
171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC
|
||
172:Drivers/CMSIS/Include/core_cm7.h ****
|
||
173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT
|
||
174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT
|
||
175:Drivers/CMSIS/Include/core_cm7.h ****
|
||
176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
|
||
177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" {
|
||
178:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
179:Drivers/CMSIS/Include/core_cm7.h ****
|
||
180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */
|
||
181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES
|
||
182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV
|
||
183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U
|
||
184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!"
|
||
185:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
186:Drivers/CMSIS/Include/core_cm7.h ****
|
||
187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT
|
||
188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U
|
||
189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!"
|
||
190:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
191:Drivers/CMSIS/Include/core_cm7.h ****
|
||
192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT
|
||
193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U
|
||
194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!"
|
||
195:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
196:Drivers/CMSIS/Include/core_cm7.h ****
|
||
197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT
|
||
198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U
|
||
199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!"
|
||
200:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
201:Drivers/CMSIS/Include/core_cm7.h ****
|
||
202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT
|
||
203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U
|
||
204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!"
|
||
205:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
206:Drivers/CMSIS/Include/core_cm7.h ****
|
||
207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT
|
||
208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U
|
||
209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!"
|
||
210:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
211:Drivers/CMSIS/Include/core_cm7.h ****
|
||
212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS
|
||
213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U
|
||
ARM GAS /tmp/ccV0GlXv.s page 8
|
||
|
||
|
||
214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||
215:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
216:Drivers/CMSIS/Include/core_cm7.h ****
|
||
217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig
|
||
218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U
|
||
219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||
220:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
221:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
222:Drivers/CMSIS/Include/core_cm7.h ****
|
||
223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */
|
||
224:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines
|
||
226:Drivers/CMSIS/Include/core_cm7.h ****
|
||
227:Drivers/CMSIS/Include/core_cm7.h **** <strong>IO Type Qualifiers</strong> are used
|
||
228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables.
|
||
229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information.
|
||
230:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
|
||
232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */
|
||
233:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */
|
||
235:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */
|
||
237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */
|
||
238:Drivers/CMSIS/Include/core_cm7.h ****
|
||
239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */
|
||
240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||
241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */
|
||
242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||
243:Drivers/CMSIS/Include/core_cm7.h ****
|
||
244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */
|
||
245:Drivers/CMSIS/Include/core_cm7.h ****
|
||
246:Drivers/CMSIS/Include/core_cm7.h ****
|
||
247:Drivers/CMSIS/Include/core_cm7.h ****
|
||
248:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
|
||
249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction
|
||
250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain:
|
||
251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register
|
||
252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register
|
||
253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register
|
||
254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register
|
||
255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register
|
||
256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register
|
||
257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register
|
||
258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/
|
||
259:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions
|
||
261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices.
|
||
262:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
263:Drivers/CMSIS/Include/core_cm7.h ****
|
||
264:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers
|
||
267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions.
|
||
268:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
269:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
270:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 9
|
||
|
||
|
||
271:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR).
|
||
273:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
274:Drivers/CMSIS/Include/core_cm7.h **** typedef union
|
||
275:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
276:Drivers/CMSIS/Include/core_cm7.h **** struct
|
||
277:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||
279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||
280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||
281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||
282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||
283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||
284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||
285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||
286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */
|
||
287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */
|
||
288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type;
|
||
289:Drivers/CMSIS/Include/core_cm7.h ****
|
||
290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */
|
||
291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR
|
||
292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR
|
||
293:Drivers/CMSIS/Include/core_cm7.h ****
|
||
294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR
|
||
295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR
|
||
296:Drivers/CMSIS/Include/core_cm7.h ****
|
||
297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR
|
||
298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR
|
||
299:Drivers/CMSIS/Include/core_cm7.h ****
|
||
300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR
|
||
301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR
|
||
302:Drivers/CMSIS/Include/core_cm7.h ****
|
||
303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR
|
||
304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR
|
||
305:Drivers/CMSIS/Include/core_cm7.h ****
|
||
306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR
|
||
307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR
|
||
308:Drivers/CMSIS/Include/core_cm7.h ****
|
||
309:Drivers/CMSIS/Include/core_cm7.h ****
|
||
310:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||
312:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
313:Drivers/CMSIS/Include/core_cm7.h **** typedef union
|
||
314:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
315:Drivers/CMSIS/Include/core_cm7.h **** struct
|
||
316:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||
318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||
319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */
|
||
320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */
|
||
321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type;
|
||
322:Drivers/CMSIS/Include/core_cm7.h ****
|
||
323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */
|
||
324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR
|
||
325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR
|
||
326:Drivers/CMSIS/Include/core_cm7.h ****
|
||
327:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 10
|
||
|
||
|
||
328:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||
330:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
331:Drivers/CMSIS/Include/core_cm7.h **** typedef union
|
||
332:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
333:Drivers/CMSIS/Include/core_cm7.h **** struct
|
||
334:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||
336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||
337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||
338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||
339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||
340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||
341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||
342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||
343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||
344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||
345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||
346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||
347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */
|
||
348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */
|
||
349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type;
|
||
350:Drivers/CMSIS/Include/core_cm7.h ****
|
||
351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */
|
||
352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR
|
||
353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR
|
||
354:Drivers/CMSIS/Include/core_cm7.h ****
|
||
355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR
|
||
356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR
|
||
357:Drivers/CMSIS/Include/core_cm7.h ****
|
||
358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR
|
||
359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR
|
||
360:Drivers/CMSIS/Include/core_cm7.h ****
|
||
361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR
|
||
362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR
|
||
363:Drivers/CMSIS/Include/core_cm7.h ****
|
||
364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR
|
||
365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR
|
||
366:Drivers/CMSIS/Include/core_cm7.h ****
|
||
367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR
|
||
368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR
|
||
369:Drivers/CMSIS/Include/core_cm7.h ****
|
||
370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR
|
||
371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR
|
||
372:Drivers/CMSIS/Include/core_cm7.h ****
|
||
373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR
|
||
374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR
|
||
375:Drivers/CMSIS/Include/core_cm7.h ****
|
||
376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR
|
||
377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR
|
||
378:Drivers/CMSIS/Include/core_cm7.h ****
|
||
379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR
|
||
380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR
|
||
381:Drivers/CMSIS/Include/core_cm7.h ****
|
||
382:Drivers/CMSIS/Include/core_cm7.h ****
|
||
383:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL).
|
||
ARM GAS /tmp/ccV0GlXv.s page 11
|
||
|
||
|
||
385:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
386:Drivers/CMSIS/Include/core_cm7.h **** typedef union
|
||
387:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
388:Drivers/CMSIS/Include/core_cm7.h **** struct
|
||
389:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||
391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||
392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||
393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||
394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */
|
||
395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */
|
||
396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type;
|
||
397:Drivers/CMSIS/Include/core_cm7.h ****
|
||
398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */
|
||
399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT
|
||
400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT
|
||
401:Drivers/CMSIS/Include/core_cm7.h ****
|
||
402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT
|
||
403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT
|
||
404:Drivers/CMSIS/Include/core_cm7.h ****
|
||
405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT
|
||
406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT
|
||
407:Drivers/CMSIS/Include/core_cm7.h ****
|
||
408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */
|
||
409:Drivers/CMSIS/Include/core_cm7.h ****
|
||
410:Drivers/CMSIS/Include/core_cm7.h ****
|
||
411:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||
414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers
|
||
415:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
416:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
417:Drivers/CMSIS/Include/core_cm7.h ****
|
||
418:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||
420:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
422:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||
424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U];
|
||
425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register
|
||
426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U];
|
||
427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *
|
||
428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U];
|
||
429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register
|
||
430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U];
|
||
431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
|
||
432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U];
|
||
433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi
|
||
434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U];
|
||
435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis
|
||
436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type;
|
||
437:Drivers/CMSIS/Include/core_cm7.h ****
|
||
438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */
|
||
439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I
|
||
440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I
|
||
441:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 12
|
||
|
||
|
||
442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */
|
||
443:Drivers/CMSIS/Include/core_cm7.h ****
|
||
444:Drivers/CMSIS/Include/core_cm7.h ****
|
||
445:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB)
|
||
448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers
|
||
449:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
450:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
451:Drivers/CMSIS/Include/core_cm7.h ****
|
||
452:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB).
|
||
454:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
456:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||
458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi
|
||
459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||
460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset
|
||
461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||
462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register *
|
||
463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe
|
||
464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State
|
||
465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist
|
||
466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
|
||
467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
|
||
468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register
|
||
469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
|
||
470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register
|
||
471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
|
||
472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
|
||
473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
|
||
474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
|
||
475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis
|
||
476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U];
|
||
477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
|
||
478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
|
||
479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
|
||
480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
|
||
481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis
|
||
482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U];
|
||
483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg
|
||
484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U];
|
||
485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0
|
||
486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1
|
||
487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2
|
||
488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U];
|
||
489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
|
||
490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U];
|
||
491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU
|
||
492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC
|
||
493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
|
||
494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
|
||
495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
|
||
496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
|
||
497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by
|
||
498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by
|
||
ARM GAS /tmp/ccV0GlXv.s page 13
|
||
|
||
|
||
499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U];
|
||
500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo
|
||
501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont
|
||
502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
|
||
503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
|
||
504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
|
||
505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U];
|
||
506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis
|
||
507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type;
|
||
508:Drivers/CMSIS/Include/core_cm7.h ****
|
||
509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */
|
||
510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB
|
||
511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB
|
||
512:Drivers/CMSIS/Include/core_cm7.h ****
|
||
513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB
|
||
514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB
|
||
515:Drivers/CMSIS/Include/core_cm7.h ****
|
||
516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB
|
||
517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB
|
||
518:Drivers/CMSIS/Include/core_cm7.h ****
|
||
519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB
|
||
520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB
|
||
521:Drivers/CMSIS/Include/core_cm7.h ****
|
||
522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB
|
||
523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB
|
||
524:Drivers/CMSIS/Include/core_cm7.h ****
|
||
525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */
|
||
526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB
|
||
527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
|
||
528:Drivers/CMSIS/Include/core_cm7.h ****
|
||
529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
|
||
530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
|
||
531:Drivers/CMSIS/Include/core_cm7.h ****
|
||
532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB
|
||
533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB
|
||
534:Drivers/CMSIS/Include/core_cm7.h ****
|
||
535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB
|
||
536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB
|
||
537:Drivers/CMSIS/Include/core_cm7.h ****
|
||
538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB
|
||
539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB
|
||
540:Drivers/CMSIS/Include/core_cm7.h ****
|
||
541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB
|
||
542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB
|
||
543:Drivers/CMSIS/Include/core_cm7.h ****
|
||
544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB
|
||
545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB
|
||
546:Drivers/CMSIS/Include/core_cm7.h ****
|
||
547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB
|
||
548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB
|
||
549:Drivers/CMSIS/Include/core_cm7.h ****
|
||
550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB
|
||
551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB
|
||
552:Drivers/CMSIS/Include/core_cm7.h ****
|
||
553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB
|
||
554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB
|
||
555:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 14
|
||
|
||
|
||
556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */
|
||
557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB
|
||
558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB
|
||
559:Drivers/CMSIS/Include/core_cm7.h ****
|
||
560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
|
||
561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB
|
||
562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB
|
||
563:Drivers/CMSIS/Include/core_cm7.h ****
|
||
564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB
|
||
565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB
|
||
566:Drivers/CMSIS/Include/core_cm7.h ****
|
||
567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB
|
||
568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB
|
||
569:Drivers/CMSIS/Include/core_cm7.h ****
|
||
570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB
|
||
571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB
|
||
572:Drivers/CMSIS/Include/core_cm7.h ****
|
||
573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB
|
||
574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB
|
||
575:Drivers/CMSIS/Include/core_cm7.h ****
|
||
576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB
|
||
577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB
|
||
578:Drivers/CMSIS/Include/core_cm7.h ****
|
||
579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB
|
||
580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB
|
||
581:Drivers/CMSIS/Include/core_cm7.h ****
|
||
582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */
|
||
583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB
|
||
584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
|
||
585:Drivers/CMSIS/Include/core_cm7.h ****
|
||
586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
|
||
587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
|
||
588:Drivers/CMSIS/Include/core_cm7.h ****
|
||
589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB
|
||
590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB
|
||
591:Drivers/CMSIS/Include/core_cm7.h ****
|
||
592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */
|
||
593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB
|
||
594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB
|
||
595:Drivers/CMSIS/Include/core_cm7.h ****
|
||
596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB
|
||
597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB
|
||
598:Drivers/CMSIS/Include/core_cm7.h ****
|
||
599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB
|
||
600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB
|
||
601:Drivers/CMSIS/Include/core_cm7.h ****
|
||
602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB
|
||
603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB
|
||
604:Drivers/CMSIS/Include/core_cm7.h ****
|
||
605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB
|
||
606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB
|
||
607:Drivers/CMSIS/Include/core_cm7.h ****
|
||
608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB
|
||
609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB
|
||
610:Drivers/CMSIS/Include/core_cm7.h ****
|
||
611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB
|
||
612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB
|
||
ARM GAS /tmp/ccV0GlXv.s page 15
|
||
|
||
|
||
613:Drivers/CMSIS/Include/core_cm7.h ****
|
||
614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB
|
||
615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB
|
||
616:Drivers/CMSIS/Include/core_cm7.h ****
|
||
617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB
|
||
618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB
|
||
619:Drivers/CMSIS/Include/core_cm7.h ****
|
||
620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */
|
||
621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB
|
||
622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
|
||
623:Drivers/CMSIS/Include/core_cm7.h ****
|
||
624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB
|
||
625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
|
||
626:Drivers/CMSIS/Include/core_cm7.h ****
|
||
627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB
|
||
628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
|
||
629:Drivers/CMSIS/Include/core_cm7.h ****
|
||
630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB
|
||
631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
|
||
632:Drivers/CMSIS/Include/core_cm7.h ****
|
||
633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB
|
||
634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB
|
||
635:Drivers/CMSIS/Include/core_cm7.h ****
|
||
636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB
|
||
637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB
|
||
638:Drivers/CMSIS/Include/core_cm7.h ****
|
||
639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB
|
||
640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB
|
||
641:Drivers/CMSIS/Include/core_cm7.h ****
|
||
642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB
|
||
643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB
|
||
644:Drivers/CMSIS/Include/core_cm7.h ****
|
||
645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB
|
||
646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB
|
||
647:Drivers/CMSIS/Include/core_cm7.h ****
|
||
648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB
|
||
649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB
|
||
650:Drivers/CMSIS/Include/core_cm7.h ****
|
||
651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB
|
||
652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB
|
||
653:Drivers/CMSIS/Include/core_cm7.h ****
|
||
654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB
|
||
655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB
|
||
656:Drivers/CMSIS/Include/core_cm7.h ****
|
||
657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB
|
||
658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB
|
||
659:Drivers/CMSIS/Include/core_cm7.h ****
|
||
660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB
|
||
661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB
|
||
662:Drivers/CMSIS/Include/core_cm7.h ****
|
||
663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */
|
||
664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB
|
||
665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
|
||
666:Drivers/CMSIS/Include/core_cm7.h ****
|
||
667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB
|
||
668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
|
||
669:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 16
|
||
|
||
|
||
670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB
|
||
671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB
|
||
672:Drivers/CMSIS/Include/core_cm7.h ****
|
||
673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||
674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB
|
||
675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB
|
||
676:Drivers/CMSIS/Include/core_cm7.h ****
|
||
677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB
|
||
678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB
|
||
679:Drivers/CMSIS/Include/core_cm7.h ****
|
||
680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB
|
||
681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB
|
||
682:Drivers/CMSIS/Include/core_cm7.h ****
|
||
683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB
|
||
684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB
|
||
685:Drivers/CMSIS/Include/core_cm7.h ****
|
||
686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB
|
||
687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB
|
||
688:Drivers/CMSIS/Include/core_cm7.h ****
|
||
689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB
|
||
690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB
|
||
691:Drivers/CMSIS/Include/core_cm7.h ****
|
||
692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||
693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB
|
||
694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB
|
||
695:Drivers/CMSIS/Include/core_cm7.h ****
|
||
696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB
|
||
697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB
|
||
698:Drivers/CMSIS/Include/core_cm7.h ****
|
||
699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB
|
||
700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB
|
||
701:Drivers/CMSIS/Include/core_cm7.h ****
|
||
702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB
|
||
703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB
|
||
704:Drivers/CMSIS/Include/core_cm7.h ****
|
||
705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB
|
||
706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB
|
||
707:Drivers/CMSIS/Include/core_cm7.h ****
|
||
708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB
|
||
709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB
|
||
710:Drivers/CMSIS/Include/core_cm7.h ****
|
||
711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB
|
||
712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB
|
||
713:Drivers/CMSIS/Include/core_cm7.h ****
|
||
714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||
715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB
|
||
716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB
|
||
717:Drivers/CMSIS/Include/core_cm7.h ****
|
||
718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB
|
||
719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB
|
||
720:Drivers/CMSIS/Include/core_cm7.h ****
|
||
721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB
|
||
722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB
|
||
723:Drivers/CMSIS/Include/core_cm7.h ****
|
||
724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB
|
||
725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB
|
||
726:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 17
|
||
|
||
|
||
727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB
|
||
728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB
|
||
729:Drivers/CMSIS/Include/core_cm7.h ****
|
||
730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB
|
||
731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB
|
||
732:Drivers/CMSIS/Include/core_cm7.h ****
|
||
733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */
|
||
734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB
|
||
735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB
|
||
736:Drivers/CMSIS/Include/core_cm7.h ****
|
||
737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB
|
||
738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB
|
||
739:Drivers/CMSIS/Include/core_cm7.h ****
|
||
740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB
|
||
741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB
|
||
742:Drivers/CMSIS/Include/core_cm7.h ****
|
||
743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */
|
||
744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB
|
||
745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB
|
||
746:Drivers/CMSIS/Include/core_cm7.h ****
|
||
747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB
|
||
748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB
|
||
749:Drivers/CMSIS/Include/core_cm7.h ****
|
||
750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB
|
||
751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB
|
||
752:Drivers/CMSIS/Include/core_cm7.h ****
|
||
753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB
|
||
754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB
|
||
755:Drivers/CMSIS/Include/core_cm7.h ****
|
||
756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB
|
||
757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB
|
||
758:Drivers/CMSIS/Include/core_cm7.h ****
|
||
759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */
|
||
760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB
|
||
761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB
|
||
762:Drivers/CMSIS/Include/core_cm7.h ****
|
||
763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB
|
||
764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB
|
||
765:Drivers/CMSIS/Include/core_cm7.h ****
|
||
766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */
|
||
767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB
|
||
768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB
|
||
769:Drivers/CMSIS/Include/core_cm7.h ****
|
||
770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB
|
||
771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB
|
||
772:Drivers/CMSIS/Include/core_cm7.h ****
|
||
773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB
|
||
774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB
|
||
775:Drivers/CMSIS/Include/core_cm7.h ****
|
||
776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB
|
||
777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB
|
||
778:Drivers/CMSIS/Include/core_cm7.h ****
|
||
779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB
|
||
780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB
|
||
781:Drivers/CMSIS/Include/core_cm7.h ****
|
||
782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */
|
||
783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB
|
||
ARM GAS /tmp/ccV0GlXv.s page 18
|
||
|
||
|
||
784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB
|
||
785:Drivers/CMSIS/Include/core_cm7.h ****
|
||
786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB
|
||
787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB
|
||
788:Drivers/CMSIS/Include/core_cm7.h ****
|
||
789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB
|
||
790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB
|
||
791:Drivers/CMSIS/Include/core_cm7.h ****
|
||
792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB
|
||
793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB
|
||
794:Drivers/CMSIS/Include/core_cm7.h ****
|
||
795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB
|
||
796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB
|
||
797:Drivers/CMSIS/Include/core_cm7.h ****
|
||
798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB
|
||
799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB
|
||
800:Drivers/CMSIS/Include/core_cm7.h ****
|
||
801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB
|
||
802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB
|
||
803:Drivers/CMSIS/Include/core_cm7.h ****
|
||
804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */
|
||
805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB
|
||
806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB
|
||
807:Drivers/CMSIS/Include/core_cm7.h ****
|
||
808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB
|
||
809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB
|
||
810:Drivers/CMSIS/Include/core_cm7.h ****
|
||
811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */
|
||
812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB
|
||
813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB
|
||
814:Drivers/CMSIS/Include/core_cm7.h ****
|
||
815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */
|
||
816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB
|
||
817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB
|
||
818:Drivers/CMSIS/Include/core_cm7.h ****
|
||
819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB
|
||
820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB
|
||
821:Drivers/CMSIS/Include/core_cm7.h ****
|
||
822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */
|
||
823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB
|
||
824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB
|
||
825:Drivers/CMSIS/Include/core_cm7.h ****
|
||
826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB
|
||
827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB
|
||
828:Drivers/CMSIS/Include/core_cm7.h ****
|
||
829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
|
||
830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB
|
||
831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB
|
||
832:Drivers/CMSIS/Include/core_cm7.h ****
|
||
833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB
|
||
834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB
|
||
835:Drivers/CMSIS/Include/core_cm7.h ****
|
||
836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */
|
||
837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB
|
||
838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB
|
||
839:Drivers/CMSIS/Include/core_cm7.h ****
|
||
840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB
|
||
ARM GAS /tmp/ccV0GlXv.s page 19
|
||
|
||
|
||
841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB
|
||
842:Drivers/CMSIS/Include/core_cm7.h ****
|
||
843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB
|
||
844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB
|
||
845:Drivers/CMSIS/Include/core_cm7.h ****
|
||
846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB
|
||
847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB
|
||
848:Drivers/CMSIS/Include/core_cm7.h ****
|
||
849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */
|
||
850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB
|
||
851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB
|
||
852:Drivers/CMSIS/Include/core_cm7.h ****
|
||
853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB
|
||
854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB
|
||
855:Drivers/CMSIS/Include/core_cm7.h ****
|
||
856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB
|
||
857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB
|
||
858:Drivers/CMSIS/Include/core_cm7.h ****
|
||
859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB
|
||
860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB
|
||
861:Drivers/CMSIS/Include/core_cm7.h ****
|
||
862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */
|
||
863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB
|
||
864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB
|
||
865:Drivers/CMSIS/Include/core_cm7.h ****
|
||
866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB
|
||
867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB
|
||
868:Drivers/CMSIS/Include/core_cm7.h ****
|
||
869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */
|
||
870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB
|
||
871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB
|
||
872:Drivers/CMSIS/Include/core_cm7.h ****
|
||
873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB
|
||
874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB
|
||
875:Drivers/CMSIS/Include/core_cm7.h ****
|
||
876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB
|
||
877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB
|
||
878:Drivers/CMSIS/Include/core_cm7.h ****
|
||
879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */
|
||
880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB
|
||
881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB
|
||
882:Drivers/CMSIS/Include/core_cm7.h ****
|
||
883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB
|
||
884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB
|
||
885:Drivers/CMSIS/Include/core_cm7.h ****
|
||
886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB
|
||
887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB
|
||
888:Drivers/CMSIS/Include/core_cm7.h ****
|
||
889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */
|
||
890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB
|
||
891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB
|
||
892:Drivers/CMSIS/Include/core_cm7.h ****
|
||
893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB
|
||
894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB
|
||
895:Drivers/CMSIS/Include/core_cm7.h ****
|
||
896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB
|
||
897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB
|
||
ARM GAS /tmp/ccV0GlXv.s page 20
|
||
|
||
|
||
898:Drivers/CMSIS/Include/core_cm7.h ****
|
||
899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB
|
||
900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB
|
||
901:Drivers/CMSIS/Include/core_cm7.h ****
|
||
902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB
|
||
903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB
|
||
904:Drivers/CMSIS/Include/core_cm7.h ****
|
||
905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB
|
||
906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB
|
||
907:Drivers/CMSIS/Include/core_cm7.h ****
|
||
908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */
|
||
909:Drivers/CMSIS/Include/core_cm7.h ****
|
||
910:Drivers/CMSIS/Include/core_cm7.h ****
|
||
911:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||
914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB
|
||
915:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
916:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
917:Drivers/CMSIS/Include/core_cm7.h ****
|
||
918:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB.
|
||
920:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
922:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U];
|
||
924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist
|
||
925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||
926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type;
|
||
927:Drivers/CMSIS/Include/core_cm7.h ****
|
||
928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */
|
||
929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I
|
||
930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I
|
||
931:Drivers/CMSIS/Include/core_cm7.h ****
|
||
932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */
|
||
933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR:
|
||
934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR:
|
||
935:Drivers/CMSIS/Include/core_cm7.h ****
|
||
936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR:
|
||
937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR:
|
||
938:Drivers/CMSIS/Include/core_cm7.h ****
|
||
939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR:
|
||
940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR:
|
||
941:Drivers/CMSIS/Include/core_cm7.h ****
|
||
942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR:
|
||
943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR:
|
||
944:Drivers/CMSIS/Include/core_cm7.h ****
|
||
945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR:
|
||
946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR:
|
||
947:Drivers/CMSIS/Include/core_cm7.h ****
|
||
948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */
|
||
949:Drivers/CMSIS/Include/core_cm7.h ****
|
||
950:Drivers/CMSIS/Include/core_cm7.h ****
|
||
951:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||
954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers.
|
||
ARM GAS /tmp/ccV0GlXv.s page 21
|
||
|
||
|
||
955:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
956:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
957:Drivers/CMSIS/Include/core_cm7.h ****
|
||
958:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick).
|
||
960:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
962:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis
|
||
964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||
965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register *
|
||
966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||
967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type;
|
||
968:Drivers/CMSIS/Include/core_cm7.h ****
|
||
969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */
|
||
970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
|
||
971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
|
||
972:Drivers/CMSIS/Include/core_cm7.h ****
|
||
973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
|
||
974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT
|
||
975:Drivers/CMSIS/Include/core_cm7.h ****
|
||
976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT
|
||
977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT
|
||
978:Drivers/CMSIS/Include/core_cm7.h ****
|
||
979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT
|
||
980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT
|
||
981:Drivers/CMSIS/Include/core_cm7.h ****
|
||
982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */
|
||
983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT
|
||
984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT
|
||
985:Drivers/CMSIS/Include/core_cm7.h ****
|
||
986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */
|
||
987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT
|
||
988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT
|
||
989:Drivers/CMSIS/Include/core_cm7.h ****
|
||
990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */
|
||
991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT
|
||
992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT
|
||
993:Drivers/CMSIS/Include/core_cm7.h ****
|
||
994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT
|
||
995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT
|
||
996:Drivers/CMSIS/Include/core_cm7.h ****
|
||
997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT
|
||
998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT
|
||
999:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */
|
||
1001:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1002:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1003:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
|
||
1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
|
||
1007:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1008:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1009:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1010:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
|
||
ARM GAS /tmp/ccV0GlXv.s page 22
|
||
|
||
|
||
1012:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
1014:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union
|
||
1016:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
|
||
1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
|
||
1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
|
||
1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
|
||
1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U];
|
||
1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
|
||
1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U];
|
||
1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
|
||
1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U];
|
||
1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
|
||
1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U];
|
||
1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register *
|
||
1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
|
||
1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg
|
||
1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U];
|
||
1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
|
||
1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
|
||
1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U];
|
||
1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re
|
||
1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re
|
||
1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re
|
||
1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re
|
||
1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re
|
||
1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re
|
||
1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re
|
||
1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re
|
||
1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re
|
||
1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re
|
||
1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re
|
||
1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re
|
||
1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type;
|
||
1048:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */
|
||
1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM
|
||
1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM
|
||
1052:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */
|
||
1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM
|
||
1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM
|
||
1056:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM
|
||
1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM
|
||
1059:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM
|
||
1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM
|
||
1062:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM
|
||
1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM
|
||
1065:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM
|
||
1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM
|
||
1068:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 23
|
||
|
||
|
||
1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM
|
||
1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM
|
||
1071:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM
|
||
1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM
|
||
1074:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM
|
||
1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM
|
||
1077:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM
|
||
1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM
|
||
1080:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */
|
||
1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM
|
||
1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM
|
||
1084:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */
|
||
1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM
|
||
1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM
|
||
1088:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */
|
||
1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM
|
||
1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM
|
||
1092:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */
|
||
1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM
|
||
1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM
|
||
1096:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM
|
||
1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM
|
||
1099:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM
|
||
1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM
|
||
1102:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */
|
||
1104:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1105:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1106:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
|
||
1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT)
|
||
1110:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1111:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1112:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1113:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
|
||
1115:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
1117:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
|
||
1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
|
||
1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
|
||
1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe
|
||
1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
|
||
1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
|
||
1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe
|
||
1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register
|
||
ARM GAS /tmp/ccV0GlXv.s page 24
|
||
|
||
|
||
1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
|
||
1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
|
||
1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
|
||
1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U];
|
||
1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
|
||
1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
|
||
1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
|
||
1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U];
|
||
1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
|
||
1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
|
||
1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
|
||
1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U];
|
||
1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
|
||
1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
|
||
1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
|
||
1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U];
|
||
1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
|
||
1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
|
||
1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type;
|
||
1145:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */
|
||
1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR
|
||
1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR
|
||
1149:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR
|
||
1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR
|
||
1152:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR
|
||
1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR
|
||
1155:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR
|
||
1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR
|
||
1158:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR
|
||
1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR
|
||
1161:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR
|
||
1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR
|
||
1164:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR
|
||
1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR
|
||
1167:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR
|
||
1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR
|
||
1170:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR
|
||
1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR
|
||
1173:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR
|
||
1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR
|
||
1176:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR
|
||
1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR
|
||
1179:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR
|
||
1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR
|
||
1182:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 25
|
||
|
||
|
||
1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR
|
||
1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR
|
||
1185:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR
|
||
1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR
|
||
1188:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR
|
||
1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR
|
||
1191:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR
|
||
1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR
|
||
1194:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR
|
||
1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR
|
||
1197:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR
|
||
1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR
|
||
1200:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */
|
||
1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI
|
||
1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI
|
||
1204:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */
|
||
1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC
|
||
1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC
|
||
1208:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */
|
||
1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE
|
||
1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE
|
||
1212:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */
|
||
1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU
|
||
1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU
|
||
1216:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */
|
||
1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL
|
||
1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL
|
||
1220:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */
|
||
1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS
|
||
1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS
|
||
1224:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */
|
||
1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN
|
||
1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN
|
||
1228:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN
|
||
1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN
|
||
1231:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN
|
||
1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN
|
||
1234:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN
|
||
1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN
|
||
1237:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN
|
||
1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN
|
||
ARM GAS /tmp/ccV0GlXv.s page 26
|
||
|
||
|
||
1240:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN
|
||
1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN
|
||
1243:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN
|
||
1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN
|
||
1246:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN
|
||
1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN
|
||
1249:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN
|
||
1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN
|
||
1252:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */
|
||
1254:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1255:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1256:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI)
|
||
1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI)
|
||
1260:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1261:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1262:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1263:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI).
|
||
1265:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
1267:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg
|
||
1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis
|
||
1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U];
|
||
1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg
|
||
1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U];
|
||
1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register *
|
||
1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U];
|
||
1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis
|
||
1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi
|
||
1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte
|
||
1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U];
|
||
1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||
1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||
1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||
1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U];
|
||
1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
|
||
1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
|
||
1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
|
||
1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U];
|
||
1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
|
||
1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
|
||
1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U];
|
||
1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
|
||
1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
|
||
1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type;
|
||
1293:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
|
||
1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP
|
||
1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP
|
||
ARM GAS /tmp/ccV0GlXv.s page 27
|
||
|
||
|
||
1297:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */
|
||
1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP
|
||
1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP
|
||
1301:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */
|
||
1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS
|
||
1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS
|
||
1305:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS
|
||
1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS
|
||
1308:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS
|
||
1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS
|
||
1311:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS
|
||
1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS
|
||
1314:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */
|
||
1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC
|
||
1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC
|
||
1318:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC
|
||
1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC
|
||
1321:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */
|
||
1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI
|
||
1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI
|
||
1325:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
|
||
1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF
|
||
1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF
|
||
1329:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF
|
||
1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF
|
||
1332:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF
|
||
1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF
|
||
1335:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF
|
||
1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF
|
||
1338:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF
|
||
1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF
|
||
1341:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF
|
||
1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF
|
||
1344:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF
|
||
1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF
|
||
1347:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */
|
||
1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA
|
||
1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA
|
||
1351:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA
|
||
1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA
|
||
ARM GAS /tmp/ccV0GlXv.s page 28
|
||
|
||
|
||
1354:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||
1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF
|
||
1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF
|
||
1358:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF
|
||
1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF
|
||
1361:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF
|
||
1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF
|
||
1364:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF
|
||
1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF
|
||
1367:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF
|
||
1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF
|
||
1370:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF
|
||
1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF
|
||
1373:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF
|
||
1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF
|
||
1376:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */
|
||
1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA
|
||
1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA
|
||
1380:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA
|
||
1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA
|
||
1383:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */
|
||
1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC
|
||
1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC
|
||
1387:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */
|
||
1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV
|
||
1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV
|
||
1391:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV
|
||
1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV
|
||
1394:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV
|
||
1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV
|
||
1397:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV
|
||
1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV
|
||
1400:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV
|
||
1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV
|
||
1403:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV
|
||
1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV
|
||
1406:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */
|
||
1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV
|
||
1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV
|
||
1410:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 29
|
||
|
||
|
||
1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV
|
||
1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV
|
||
1413:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */
|
||
1415:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1416:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||
1418:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||
1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU)
|
||
1422:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1423:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1424:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1425:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU).
|
||
1427:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
1429:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||
1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||
1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||
1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register
|
||
1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re
|
||
1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address
|
||
1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and
|
||
1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address
|
||
1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and
|
||
1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address
|
||
1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and
|
||
1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type;
|
||
1442:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U
|
||
1444:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */
|
||
1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU
|
||
1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU
|
||
1448:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU
|
||
1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU
|
||
1451:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU
|
||
1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU
|
||
1454:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */
|
||
1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU
|
||
1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU
|
||
1458:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU
|
||
1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU
|
||
1461:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU
|
||
1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU
|
||
1464:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */
|
||
1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU
|
||
1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU
|
||
ARM GAS /tmp/ccV0GlXv.s page 30
|
||
|
||
|
||
1468:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */
|
||
1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU
|
||
1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU
|
||
1472:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU
|
||
1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU
|
||
1475:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU
|
||
1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU
|
||
1478:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */
|
||
1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU
|
||
1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
|
||
1482:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU
|
||
1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
|
||
1485:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU
|
||
1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
|
||
1488:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU
|
||
1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
|
||
1491:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU
|
||
1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU
|
||
1494:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU
|
||
1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU
|
||
1497:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU
|
||
1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU
|
||
1500:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU
|
||
1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU
|
||
1503:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU
|
||
1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU
|
||
1506:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU
|
||
1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU
|
||
1509:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */
|
||
1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
|
||
1512:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1513:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1514:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU)
|
||
1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU)
|
||
1518:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1519:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1520:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1521:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU).
|
||
1523:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
ARM GAS /tmp/ccV0GlXv.s page 31
|
||
|
||
|
||
1525:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U];
|
||
1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R
|
||
1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R
|
||
1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co
|
||
1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0
|
||
1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1
|
||
1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2
|
||
1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type;
|
||
1534:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */
|
||
1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC
|
||
1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC
|
||
1538:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC
|
||
1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC
|
||
1541:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC
|
||
1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC
|
||
1544:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC
|
||
1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC
|
||
1547:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC
|
||
1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC
|
||
1550:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC
|
||
1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC
|
||
1553:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC
|
||
1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC
|
||
1556:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC
|
||
1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC
|
||
1559:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC
|
||
1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC
|
||
1562:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */
|
||
1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA
|
||
1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA
|
||
1566:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */
|
||
1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS
|
||
1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS
|
||
1570:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS
|
||
1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS
|
||
1573:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS
|
||
1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS
|
||
1576:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS
|
||
1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS
|
||
1579:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */
|
||
1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR
|
||
ARM GAS /tmp/ccV0GlXv.s page 32
|
||
|
||
|
||
1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR
|
||
1583:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR
|
||
1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR
|
||
1586:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR
|
||
1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR
|
||
1589:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR
|
||
1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR
|
||
1592:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR
|
||
1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR
|
||
1595:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR
|
||
1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR
|
||
1598:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR
|
||
1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR
|
||
1601:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR
|
||
1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR
|
||
1604:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */
|
||
1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR
|
||
1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR
|
||
1608:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR
|
||
1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR
|
||
1611:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR
|
||
1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR
|
||
1614:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR
|
||
1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR
|
||
1617:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */
|
||
1619:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */
|
||
1621:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1622:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1623:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||
1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers
|
||
1627:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1628:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1629:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1630:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug).
|
||
1632:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
|
||
1634:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status
|
||
1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg
|
||
1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe
|
||
1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont
|
||
ARM GAS /tmp/ccV0GlXv.s page 33
|
||
|
||
|
||
1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type;
|
||
1640:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */
|
||
1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core
|
||
1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core
|
||
1644:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core
|
||
1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core
|
||
1647:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core
|
||
1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core
|
||
1650:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core
|
||
1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core
|
||
1653:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core
|
||
1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core
|
||
1656:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core
|
||
1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core
|
||
1659:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core
|
||
1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core
|
||
1662:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core
|
||
1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core
|
||
1665:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core
|
||
1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core
|
||
1668:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core
|
||
1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core
|
||
1671:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core
|
||
1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core
|
||
1674:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core
|
||
1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core
|
||
1677:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */
|
||
1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core
|
||
1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core
|
||
1681:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core
|
||
1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core
|
||
1684:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */
|
||
1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core
|
||
1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core
|
||
1688:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core
|
||
1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core
|
||
1691:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core
|
||
1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core
|
||
1694:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core
|
||
ARM GAS /tmp/ccV0GlXv.s page 34
|
||
|
||
|
||
1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core
|
||
1697:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core
|
||
1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core
|
||
1700:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core
|
||
1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core
|
||
1703:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core
|
||
1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core
|
||
1706:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core
|
||
1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core
|
||
1709:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core
|
||
1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core
|
||
1712:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core
|
||
1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core
|
||
1715:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core
|
||
1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core
|
||
1718:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core
|
||
1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core
|
||
1721:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core
|
||
1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core
|
||
1724:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */
|
||
1726:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1727:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1728:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros
|
||
1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||
1732:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1733:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1734:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1735:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range.
|
||
1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field.
|
||
1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||
1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value.
|
||
1740:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||
1742:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1743:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value.
|
||
1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field.
|
||
1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||
1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value.
|
||
1748:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||
1750:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */
|
||
1752:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 35
|
||
|
||
|
||
1753:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1754:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
|
||
1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions
|
||
1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures.
|
||
1758:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1759:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1760:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */
|
||
1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas
|
||
1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||
1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||
1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||
1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address
|
||
1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||
1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||
1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas
|
||
1770:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register
|
||
1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct
|
||
1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st
|
||
1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc
|
||
1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct
|
||
1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct
|
||
1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct
|
||
1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration
|
||
1779:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||
1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit *
|
||
1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit *
|
||
1783:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
1784:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||
1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||
1787:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */
|
||
1789:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1790:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1791:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1792:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
|
||
1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer
|
||
1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains:
|
||
1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions
|
||
1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions
|
||
1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions
|
||
1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions
|
||
1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/
|
||
1800:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||
1802:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1803:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1804:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1805:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */
|
||
1807:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface
|
||
1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||
ARM GAS /tmp/ccV0GlXv.s page 36
|
||
|
||
|
||
1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC.
|
||
1811:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
1812:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1813:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL
|
||
1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||
1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||
1817:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||
1819:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||
1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||
1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||
1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||
1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||
1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||
1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||
1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||
1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive
|
||
1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority
|
||
1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority
|
||
1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset
|
||
1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */
|
||
1833:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL
|
||
1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||
1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||
1837:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||
1839:Drivers/CMSIS/Include/core_cm7.h **** #else
|
||
1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector
|
||
1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector
|
||
1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||
1843:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16
|
||
1845:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1846:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
|
||
1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret
|
||
1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu
|
||
1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu
|
||
1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret
|
||
1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu
|
||
1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu
|
||
1854:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1855:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1856:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping
|
||
1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence.
|
||
1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
|
||
1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used.
|
||
1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available
|
||
1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||
1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field.
|
||
1864:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||
39 .loc 2 1865 22 view .LVU3
|
||
ARM GAS /tmp/ccV0GlXv.s page 37
|
||
|
||
|
||
40 .LBB39:
|
||
1866:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value;
|
||
41 .loc 2 1867 3 view .LVU4
|
||
1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a
|
||
42 .loc 2 1868 3 view .LVU5
|
||
1869:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register
|
||
43 .loc 2 1870 3 view .LVU6
|
||
44 .loc 2 1870 14 is_stmt 0 view .LVU7
|
||
45 0000 0649 ldr r1, .L2
|
||
46 0002 CB68 ldr r3, [r1, #12]
|
||
47 .LVL1:
|
||
1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
|
||
48 .loc 2 1871 3 is_stmt 1 view .LVU8
|
||
49 .loc 2 1871 13 is_stmt 0 view .LVU9
|
||
50 0004 23F4E063 bic r3, r3, #1792
|
||
51 .LVL2:
|
||
52 .loc 2 1871 13 view .LVU10
|
||
53 0008 1B04 lsls r3, r3, #16
|
||
54 000a 1B0C lsrs r3, r3, #16
|
||
55 .LVL3:
|
||
1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value |
|
||
56 .loc 2 1872 3 is_stmt 1 view .LVU11
|
||
1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||
1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a
|
||
57 .loc 2 1874 35 is_stmt 0 view .LVU12
|
||
58 000c 0002 lsls r0, r0, #8
|
||
59 .LVL4:
|
||
60 .loc 2 1874 35 view .LVU13
|
||
61 000e 00F4E060 and r0, r0, #1792
|
||
1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||
62 .loc 2 1873 62 view .LVU14
|
||
63 0012 0343 orrs r3, r3, r0
|
||
64 .LVL5:
|
||
1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value |
|
||
65 .loc 2 1872 14 view .LVU15
|
||
66 0014 024A ldr r2, .L2+4
|
||
67 0016 1A43 orrs r2, r2, r3
|
||
68 .LVL6:
|
||
1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value;
|
||
69 .loc 2 1875 3 is_stmt 1 view .LVU16
|
||
70 .loc 2 1875 14 is_stmt 0 view .LVU17
|
||
71 0018 CA60 str r2, [r1, #12]
|
||
72 .LVL7:
|
||
73 .loc 2 1875 14 view .LVU18
|
||
74 .LBE39:
|
||
75 .LBE38:
|
||
150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
76 .loc 1 150 1 view .LVU19
|
||
77 001a 7047 bx lr
|
||
78 .L3:
|
||
79 .align 2
|
||
80 .L2:
|
||
81 001c 00ED00E0 .word -536810240
|
||
82 0020 0000FA05 .word 100270080
|
||
83 .cfi_endproc
|
||
ARM GAS /tmp/ccV0GlXv.s page 38
|
||
|
||
|
||
84 .LFE141:
|
||
86 .section .text.HAL_NVIC_SetPriority,"ax",%progbits
|
||
87 .align 1
|
||
88 .global HAL_NVIC_SetPriority
|
||
89 .syntax unified
|
||
90 .thumb
|
||
91 .thumb_func
|
||
92 .fpu fpv5-d16
|
||
94 HAL_NVIC_SetPriority:
|
||
95 .LVL8:
|
||
96 .LFB142:
|
||
151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Sets the priority of an interrupt.
|
||
154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number.
|
||
155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param PreemptPriority The preemption priority for the IRQn channel.
|
||
158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be a value between 0 and 15
|
||
159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * A lower priority value indicates a higher priority
|
||
160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel.
|
||
161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be a value between 0 and 15
|
||
162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * A lower priority value indicates a higher priority.
|
||
163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||
166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
97 .loc 1 166 1 is_stmt 1 view -0
|
||
98 .cfi_startproc
|
||
99 @ args = 0, pretend = 0, frame = 0
|
||
100 @ frame_needed = 0, uses_anonymous_args = 0
|
||
101 .loc 1 166 1 is_stmt 0 view .LVU21
|
||
102 0000 00B5 push {lr}
|
||
103 .LCFI0:
|
||
104 .cfi_def_cfa_offset 4
|
||
105 .cfi_offset 14, -4
|
||
167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t prioritygroup;
|
||
106 .loc 1 167 3 is_stmt 1 view .LVU22
|
||
168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||
107 .loc 1 170 3 view .LVU23
|
||
171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||
108 .loc 1 171 3 view .LVU24
|
||
172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping();
|
||
109 .loc 1 173 3 view .LVU25
|
||
110 .LBB46:
|
||
111 .LBI46:
|
||
1876:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1877:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1878:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1879:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping
|
||
1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||
1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||
1883:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
ARM GAS /tmp/ccV0GlXv.s page 39
|
||
|
||
|
||
1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||
112 .loc 2 1884 26 view .LVU26
|
||
113 .LBB47:
|
||
1885:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||
114 .loc 2 1886 3 view .LVU27
|
||
115 .loc 2 1886 26 is_stmt 0 view .LVU28
|
||
116 0002 174B ldr r3, .L10
|
||
117 0004 DB68 ldr r3, [r3, #12]
|
||
118 .loc 2 1886 11 view .LVU29
|
||
119 0006 C3F30223 ubfx r3, r3, #8, #3
|
||
120 .LVL9:
|
||
121 .loc 2 1886 11 view .LVU30
|
||
122 .LBE47:
|
||
123 .LBE46:
|
||
174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||
124 .loc 1 175 3 is_stmt 1 view .LVU31
|
||
125 .LBB48:
|
||
126 .LBI48:
|
||
1887:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1888:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1889:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1890:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt
|
||
1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller.
|
||
1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
1895:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||
1897:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
1899:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
1901:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1902:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1903:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1904:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1905:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status
|
||
1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||
1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled.
|
||
1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled.
|
||
1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
1912:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||
1914:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
1916:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
|
||
1918:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1919:Drivers/CMSIS/Include/core_cm7.h **** else
|
||
1920:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U);
|
||
1922:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1923:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
ARM GAS /tmp/ccV0GlXv.s page 40
|
||
|
||
|
||
1924:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1925:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1926:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt
|
||
1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller.
|
||
1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
1931:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||
1933:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
1935:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
1939:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1940:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1941:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1942:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1943:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt
|
||
1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe
|
||
1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending.
|
||
1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending.
|
||
1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
1950:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||
1952:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
1954:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
|
||
1956:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1957:Drivers/CMSIS/Include/core_cm7.h **** else
|
||
1958:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U);
|
||
1960:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1961:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1962:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1963:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1964:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt
|
||
1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||
1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
1969:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||
1971:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
1973:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
1975:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1976:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1977:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1978:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1979:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt
|
||
ARM GAS /tmp/ccV0GlXv.s page 41
|
||
|
||
|
||
1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||
1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
1984:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||
1986:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
1988:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||
1990:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1991:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1992:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1993:Drivers/CMSIS/Include/core_cm7.h ****
|
||
1994:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt
|
||
1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific
|
||
1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number.
|
||
1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active.
|
||
1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active.
|
||
2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
|
||
2001:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||
2003:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
2005:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
|
||
2007:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2008:Drivers/CMSIS/Include/core_cm7.h **** else
|
||
2009:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U);
|
||
2011:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2012:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2013:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2014:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2015:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority
|
||
2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception.
|
||
2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt,
|
||
2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception.
|
||
2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number.
|
||
2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set.
|
||
2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception.
|
||
2023:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||
2025:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
2027:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (
|
||
2029:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2030:Drivers/CMSIS/Include/core_cm7.h **** else
|
||
2031:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (
|
||
2033:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2034:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2035:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2036:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2037:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
ARM GAS /tmp/ccV0GlXv.s page 42
|
||
|
||
|
||
2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority
|
||
2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception.
|
||
2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt,
|
||
2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception.
|
||
2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number.
|
||
2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority.
|
||
2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc
|
||
2045:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||
2047:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2048:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
|
||
2050:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||
2052:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2053:Drivers/CMSIS/Include/core_cm7.h **** else
|
||
2054:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||
2056:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2057:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2058:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2059:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2060:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority
|
||
2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group,
|
||
2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value.
|
||
2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available
|
||
2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||
2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group.
|
||
2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||
2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0).
|
||
2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP
|
||
2070:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
|
||
127 .loc 2 2071 26 view .LVU32
|
||
128 .LBB49:
|
||
2072:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
|
||
129 .loc 2 2073 3 view .LVU33
|
||
2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits;
|
||
130 .loc 2 2074 3 view .LVU34
|
||
2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits;
|
||
131 .loc 2 2075 3 view .LVU35
|
||
2076:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
|
||
132 .loc 2 2077 3 view .LVU36
|
||
133 .loc 2 2077 31 is_stmt 0 view .LVU37
|
||
134 000a C3F1070C rsb ip, r3, #7
|
||
135 .loc 2 2077 23 view .LVU38
|
||
136 000e BCF1040F cmp ip, #4
|
||
137 0012 28BF it cs
|
||
138 0014 4FF0040C movcs ip, #4
|
||
139 .LVL10:
|
||
2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
|
||
140 .loc 2 2078 3 is_stmt 1 view .LVU39
|
||
141 .loc 2 2078 44 is_stmt 0 view .LVU40
|
||
142 0018 03F1040E add lr, r3, #4
|
||
ARM GAS /tmp/ccV0GlXv.s page 43
|
||
|
||
|
||
143 .loc 2 2078 109 view .LVU41
|
||
144 001c BEF1060F cmp lr, #6
|
||
145 0020 14D9 bls .L8
|
||
146 0022 033B subs r3, r3, #3
|
||
147 .LVL11:
|
||
148 .L5:
|
||
2079:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2080:Drivers/CMSIS/Include/core_cm7.h **** return (
|
||
149 .loc 2 2080 3 is_stmt 1 view .LVU42
|
||
2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
|
||
150 .loc 2 2081 30 is_stmt 0 view .LVU43
|
||
151 0024 4FF0FF3E mov lr, #-1
|
||
152 .LVL12:
|
||
153 .loc 2 2081 30 view .LVU44
|
||
154 0028 0EFA0CFC lsl ip, lr, ip
|
||
155 .LVL13:
|
||
156 .loc 2 2081 30 view .LVU45
|
||
157 002c 21EA0C01 bic r1, r1, ip
|
||
158 .LVL14:
|
||
159 .loc 2 2081 82 view .LVU46
|
||
160 0030 9940 lsls r1, r1, r3
|
||
2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||
161 .loc 2 2082 30 view .LVU47
|
||
162 0032 0EFA03F3 lsl r3, lr, r3
|
||
163 .LVL15:
|
||
164 .loc 2 2082 30 view .LVU48
|
||
165 0036 22EA0303 bic r3, r2, r3
|
||
2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
|
||
166 .loc 2 2081 102 view .LVU49
|
||
167 003a 1943 orrs r1, r1, r3
|
||
168 .LVL16:
|
||
2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
|
||
169 .loc 2 2081 102 view .LVU50
|
||
170 .LBE49:
|
||
171 .LBE48:
|
||
172 .LBB51:
|
||
173 .LBI51:
|
||
2024:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
174 .loc 2 2024 22 is_stmt 1 view .LVU51
|
||
175 .LBB52:
|
||
2026:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
176 .loc 2 2026 3 view .LVU52
|
||
2026:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
177 .loc 2 2026 6 is_stmt 0 view .LVU53
|
||
178 003c 0028 cmp r0, #0
|
||
179 003e 07DB blt .L6
|
||
2028:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
180 .loc 2 2028 5 is_stmt 1 view .LVU54
|
||
2028:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
181 .loc 2 2028 49 is_stmt 0 view .LVU55
|
||
182 0040 0901 lsls r1, r1, #4
|
||
183 .LVL17:
|
||
2028:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
184 .loc 2 2028 49 view .LVU56
|
||
185 0042 C9B2 uxtb r1, r1
|
||
2028:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
186 .loc 2 2028 47 view .LVU57
|
||
ARM GAS /tmp/ccV0GlXv.s page 44
|
||
|
||
|
||
187 0044 074B ldr r3, .L10+4
|
||
188 0046 1954 strb r1, [r3, r0]
|
||
189 .LVL18:
|
||
190 .L4:
|
||
2028:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
191 .loc 2 2028 47 view .LVU58
|
||
192 .LBE52:
|
||
193 .LBE51:
|
||
176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
194 .loc 1 176 1 view .LVU59
|
||
195 0048 5DF804FB ldr pc, [sp], #4
|
||
196 .LVL19:
|
||
197 .L8:
|
||
198 .LBB54:
|
||
199 .LBB50:
|
||
2078:Drivers/CMSIS/Include/core_cm7.h ****
|
||
200 .loc 2 2078 109 view .LVU60
|
||
201 004c 0023 movs r3, #0
|
||
202 .LVL20:
|
||
2078:Drivers/CMSIS/Include/core_cm7.h ****
|
||
203 .loc 2 2078 109 view .LVU61
|
||
204 004e E9E7 b .L5
|
||
205 .LVL21:
|
||
206 .L6:
|
||
2078:Drivers/CMSIS/Include/core_cm7.h ****
|
||
207 .loc 2 2078 109 view .LVU62
|
||
208 .LBE50:
|
||
209 .LBE54:
|
||
210 .LBB55:
|
||
211 .LBB53:
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
212 .loc 2 2032 5 is_stmt 1 view .LVU63
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
213 .loc 2 2032 33 is_stmt 0 view .LVU64
|
||
214 0050 00F00F00 and r0, r0, #15
|
||
215 .LVL22:
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
216 .loc 2 2032 49 view .LVU65
|
||
217 0054 0901 lsls r1, r1, #4
|
||
218 .LVL23:
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
219 .loc 2 2032 49 view .LVU66
|
||
220 0056 C9B2 uxtb r1, r1
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
221 .loc 2 2032 47 view .LVU67
|
||
222 0058 034B ldr r3, .L10+8
|
||
223 005a 1954 strb r1, [r3, r0]
|
||
224 .LVL24:
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
225 .loc 2 2032 47 view .LVU68
|
||
226 .LBE53:
|
||
227 .LBE55:
|
||
228 .loc 1 176 1 view .LVU69
|
||
229 005c F4E7 b .L4
|
||
230 .L11:
|
||
231 005e 00BF .align 2
|
||
232 .L10:
|
||
ARM GAS /tmp/ccV0GlXv.s page 45
|
||
|
||
|
||
233 0060 00ED00E0 .word -536810240
|
||
234 0064 00E400E0 .word -536812544
|
||
235 0068 14ED00E0 .word -536810220
|
||
236 .cfi_endproc
|
||
237 .LFE142:
|
||
239 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits
|
||
240 .align 1
|
||
241 .global HAL_NVIC_EnableIRQ
|
||
242 .syntax unified
|
||
243 .thumb
|
||
244 .thumb_func
|
||
245 .fpu fpv5-d16
|
||
247 HAL_NVIC_EnableIRQ:
|
||
248 .LVL25:
|
||
249 .LFB143:
|
||
177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||
180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||
181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * function should be called before.
|
||
182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number.
|
||
183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||
188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
250 .loc 1 188 1 is_stmt 1 view -0
|
||
251 .cfi_startproc
|
||
252 @ args = 0, pretend = 0, frame = 0
|
||
253 @ frame_needed = 0, uses_anonymous_args = 0
|
||
254 @ link register save eliminated.
|
||
189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
255 .loc 1 190 3 view .LVU71
|
||
191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Enable interrupt */
|
||
193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn);
|
||
256 .loc 1 193 3 view .LVU72
|
||
257 .LBB56:
|
||
258 .LBI56:
|
||
1896:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
259 .loc 2 1896 22 view .LVU73
|
||
260 .LBB57:
|
||
1898:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
261 .loc 2 1898 3 view .LVU74
|
||
1898:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
262 .loc 2 1898 6 is_stmt 0 view .LVU75
|
||
263 0000 0028 cmp r0, #0
|
||
264 .LVL26:
|
||
1898:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
265 .loc 2 1898 6 view .LVU76
|
||
266 0002 07DB blt .L12
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
267 .loc 2 1900 5 is_stmt 1 view .LVU77
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
268 .loc 2 1900 81 is_stmt 0 view .LVU78
|
||
ARM GAS /tmp/ccV0GlXv.s page 46
|
||
|
||
|
||
269 0004 00F01F02 and r2, r0, #31
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
270 .loc 2 1900 34 view .LVU79
|
||
271 0008 4009 lsrs r0, r0, #5
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
272 .loc 2 1900 45 view .LVU80
|
||
273 000a 0123 movs r3, #1
|
||
274 000c 9340 lsls r3, r3, r2
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
275 .loc 2 1900 43 view .LVU81
|
||
276 000e 024A ldr r2, .L14
|
||
277 0010 42F82030 str r3, [r2, r0, lsl #2]
|
||
278 .LVL27:
|
||
279 .L12:
|
||
1900:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
280 .loc 2 1900 43 view .LVU82
|
||
281 .LBE57:
|
||
282 .LBE56:
|
||
194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
283 .loc 1 194 1 view .LVU83
|
||
284 0014 7047 bx lr
|
||
285 .L15:
|
||
286 0016 00BF .align 2
|
||
287 .L14:
|
||
288 0018 00E100E0 .word -536813312
|
||
289 .cfi_endproc
|
||
290 .LFE143:
|
||
292 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits
|
||
293 .align 1
|
||
294 .global HAL_NVIC_DisableIRQ
|
||
295 .syntax unified
|
||
296 .thumb
|
||
297 .thumb_func
|
||
298 .fpu fpv5-d16
|
||
300 HAL_NVIC_DisableIRQ:
|
||
301 .LVL28:
|
||
302 .LFB144:
|
||
195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||
198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number.
|
||
199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||
204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
303 .loc 1 204 1 is_stmt 1 view -0
|
||
304 .cfi_startproc
|
||
305 @ args = 0, pretend = 0, frame = 0
|
||
306 @ frame_needed = 0, uses_anonymous_args = 0
|
||
307 @ link register save eliminated.
|
||
205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
308 .loc 1 206 3 view .LVU85
|
||
207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Disable interrupt */
|
||
ARM GAS /tmp/ccV0GlXv.s page 47
|
||
|
||
|
||
209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn);
|
||
309 .loc 1 209 3 view .LVU86
|
||
310 .LBB64:
|
||
311 .LBI64:
|
||
1932:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
312 .loc 2 1932 22 view .LVU87
|
||
313 .LBB65:
|
||
1934:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
314 .loc 2 1934 3 view .LVU88
|
||
1934:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
315 .loc 2 1934 6 is_stmt 0 view .LVU89
|
||
316 0000 0028 cmp r0, #0
|
||
317 .LVL29:
|
||
1934:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
318 .loc 2 1934 6 view .LVU90
|
||
319 0002 0CDB blt .L16
|
||
1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
320 .loc 2 1936 5 is_stmt 1 view .LVU91
|
||
1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
321 .loc 2 1936 81 is_stmt 0 view .LVU92
|
||
322 0004 00F01F02 and r2, r0, #31
|
||
1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
323 .loc 2 1936 34 view .LVU93
|
||
324 0008 4009 lsrs r0, r0, #5
|
||
1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
325 .loc 2 1936 45 view .LVU94
|
||
326 000a 0123 movs r3, #1
|
||
327 000c 9340 lsls r3, r3, r2
|
||
1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
328 .loc 2 1936 43 view .LVU95
|
||
329 000e 2030 adds r0, r0, #32
|
||
330 0010 034A ldr r2, .L18
|
||
331 0012 42F82030 str r3, [r2, r0, lsl #2]
|
||
1937:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
332 .loc 2 1937 5 is_stmt 1 view .LVU96
|
||
333 .LBB66:
|
||
334 .LBI66:
|
||
335 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
|
||
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
|
||
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
|
||
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
|
||
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
|
||
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
|
||
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
|
||
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
|
||
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
|
||
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
|
||
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
|
||
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
|
||
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
|
||
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
|
||
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||
ARM GAS /tmp/ccV0GlXv.s page 48
|
||
|
||
|
||
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
|
||
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
|
||
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
|
||
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
|
||
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
|
||
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
|
||
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
|
||
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
|
||
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
|
||
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
|
||
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
|
||
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
|
||
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
|
||
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
|
||
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
|
||
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
|
||
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
|
||
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
|
||
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
|
||
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
|
||
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
|
||
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
|
||
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
|
||
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
|
||
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
|
||
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
|
||
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
|
||
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
|
||
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
|
||
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
|
||
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||
ARM GAS /tmp/ccV0GlXv.s page 49
|
||
|
||
|
||
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
|
||
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
|
||
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
|
||
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
|
||
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
|
||
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
|
||
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
|
||
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
|
||
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
|
||
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
|
||
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
|
||
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
|
||
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
|
||
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
|
||
120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||
121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
|
||
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||
127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
|
||
130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
|
||
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 50
|
||
|
||
|
||
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
|
||
137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||
138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
|
||
141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
|
||
143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
144:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
|
||
148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
|
||
149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
|
||
150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
|
||
152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
154:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
|
||
156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
158:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
159:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure)
|
||
163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode.
|
||
164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value
|
||
165:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
|
||
167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
169:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
|
||
171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
174:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
175:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
|
||
178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
|
||
179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
|
||
180:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||
182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||
184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
185:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
186:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
|
||
190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
|
||
ARM GAS /tmp/ccV0GlXv.s page 51
|
||
|
||
|
||
191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
|
||
192:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||
194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
|
||
196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
198:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
199:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
|
||
202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
|
||
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
|
||
204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
|
||
206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
208:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
212:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
213:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
|
||
216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
|
||
217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
|
||
218:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
|
||
220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
222:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||
224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
226:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
227:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
|
||
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
|
||
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
|
||
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
|
||
234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
236:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||
238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
240:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
|
||
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
|
||
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
|
||
246:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
|
||
ARM GAS /tmp/ccV0GlXv.s page 52
|
||
|
||
|
||
248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
250:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) );
|
||
252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
254:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
255:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure)
|
||
259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
|
||
260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
|
||
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
|
||
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
265:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
|
||
267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
270:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
271:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
|
||
274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
|
||
275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
|
||
276:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
|
||
278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
|
||
280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
281:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
282:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
|
||
286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
|
||
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
|
||
288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
|
||
290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
|
||
292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
294:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
295:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
|
||
298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
|
||
299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
|
||
300:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
|
||
302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
304:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 53
|
||
|
||
|
||
305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
|
||
306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
309:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure)
|
||
313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
|
||
314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
|
||
315:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
|
||
317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
|
||
321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
324:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
325:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
|
||
328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
|
||
329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
|
||
330:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
|
||
332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
|
||
334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
335:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
336:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
|
||
340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
|
||
341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
|
||
342:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
|
||
344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
|
||
346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
349:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure)
|
||
353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
|
||
354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value
|
||
355:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
|
||
357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
359:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
|
||
361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
ARM GAS /tmp/ccV0GlXv.s page 54
|
||
|
||
|
||
362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
363:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
364:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure)
|
||
367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
|
||
368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set
|
||
369:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
|
||
371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
|
||
373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
|
||
379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
|
||
381:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
|
||
383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
385:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
||
387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
389:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
390:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
|
||
394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
|
||
395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
|
||
396:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
|
||
398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
400:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
|
||
402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
405:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
406:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
|
||
409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
|
||
410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
|
||
411:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
|
||
413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||
415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
416:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
417:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
ARM GAS /tmp/ccV0GlXv.s page 55
|
||
|
||
|
||
419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure)
|
||
421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
|
||
422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
|
||
423:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
|
||
425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
|
||
427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
429:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
430:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||
434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
|
||
436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||
437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
438:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||
440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
|
||
442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
443:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
444:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
|
||
447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||
448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
449:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||
451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
|
||
453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
454:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
455:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
|
||
458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
|
||
459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
|
||
460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
|
||
462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
464:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
||
466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
468:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
469:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure)
|
||
473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
|
||
474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
|
||
475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
ARM GAS /tmp/ccV0GlXv.s page 56
|
||
|
||
|
||
476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
|
||
477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
479:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
|
||
481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
484:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
485:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
|
||
488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
|
||
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
|
||
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
|
||
494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
495:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure)
|
||
500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state.
|
||
501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
502:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
|
||
504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
|
||
506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
508:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
509:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
|
||
512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
|
||
513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
|
||
514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||
517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
|
||
519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
520:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
521:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
|
||
524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
|
||
525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
|
||
526:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
|
||
528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
530:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||
532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
ARM GAS /tmp/ccV0GlXv.s page 57
|
||
|
||
|
||
533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
534:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
535:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure)
|
||
539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state.
|
||
540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
|
||
541:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
|
||
543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
545:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
|
||
547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
550:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
551:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
|
||
554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
|
||
555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
|
||
556:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
|
||
558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||
560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
561:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
562:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
|
||
566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
|
||
567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
|
||
568:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
|
||
570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
|
||
572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
574:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
|
||
578:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
579:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||
581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||
582:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit
|
||
585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
|
||
587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
588:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
|
||
ARM GAS /tmp/ccV0GlXv.s page 58
|
||
|
||
|
||
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
|
||
591:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
|
||
593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) );
|
||
601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
604:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
|
||
606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure)
|
||
608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
|
||
610:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
|
||
612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
|
||
613:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
|
||
615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
|
||
622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
626:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
627:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
|
||
630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||
632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
633:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
|
||
635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||
636:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
|
||
638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
|
||
643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
|
||
645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
ARM GAS /tmp/ccV0GlXv.s page 59
|
||
|
||
|
||
647:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
648:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
|
||
652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
|
||
654:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
|
||
656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||
657:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
|
||
659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
|
||
663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
|
||
665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
668:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
669:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit
|
||
672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
|
||
674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
675:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
|
||
677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
|
||
678:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
|
||
680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
|
||
688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
691:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
692:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure)
|
||
696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
|
||
698:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
|
||
700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
|
||
701:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
|
||
703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
ARM GAS /tmp/ccV0GlXv.s page 60
|
||
|
||
|
||
704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
|
||
710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
714:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
715:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
|
||
718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||
720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
721:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
|
||
723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
|
||
724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
|
||
726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
|
||
731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
|
||
733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
735:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
736:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure)
|
||
740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
|
||
742:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
|
||
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
|
||
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
||
747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
|
||
751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
|
||
753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
756:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||
758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
|
||
759:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
760:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 61
|
||
|
||
|
||
761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
|
||
763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
|
||
764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
|
||
765:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
||
767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||
769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||
770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr)
|
||
771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
|
||
772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
||
773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
||
774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
|
||
775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
777:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||
779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
|
||
783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
785:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
786:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
|
||
789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
|
||
790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
|
||
791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
||
793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||
795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||
796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
|
||
797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
|
||
798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
||
799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
||
800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
|
||
801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
|
||
803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr;
|
||
806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
808:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
809:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
|
||
811:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
812:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
|
||
814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||
815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
|
||
816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
ARM GAS /tmp/ccV0GlXv.s page 62
|
||
|
||
|
||
818:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
|
||
820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
|
||
821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
|
||
822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
|
||
823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||
824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
|
||
825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||
826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||
828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
|
||
829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||
830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
831:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
|
||
834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||
835:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
|
||
837:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
|
||
840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
|
||
841:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi")
|
||
843:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
844:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
|
||
847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
|
||
848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
|
||
849:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
|
||
851:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
852:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
|
||
855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||
856:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
|
||
858:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
859:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
|
||
862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||
863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
|
||
864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
|
||
865:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
|
||
867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
|
||
869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
870:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
871:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
|
||
874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
|
||
ARM GAS /tmp/ccV0GlXv.s page 63
|
||
|
||
|
||
875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
|
||
876:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
|
||
336 .loc 3 877 27 view .LVU97
|
||
337 .LBB67:
|
||
878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
|
||
338 .loc 3 879 3 view .LVU98
|
||
339 .syntax unified
|
||
340 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
341 0016 BFF34F8F dsb 0xF
|
||
342 @ 0 "" 2
|
||
343 .thumb
|
||
344 .syntax unified
|
||
345 .LBE67:
|
||
346 .LBE66:
|
||
1938:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
347 .loc 2 1938 5 view .LVU99
|
||
348 .LBB68:
|
||
349 .LBI68:
|
||
866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
350 .loc 3 866 27 view .LVU100
|
||
351 .LBB69:
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
352 .loc 3 868 3 view .LVU101
|
||
353 .syntax unified
|
||
354 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
355 001a BFF36F8F isb 0xF
|
||
356 @ 0 "" 2
|
||
357 .LVL30:
|
||
358 .thumb
|
||
359 .syntax unified
|
||
360 .L16:
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
361 .loc 3 868 3 is_stmt 0 view .LVU102
|
||
362 .LBE69:
|
||
363 .LBE68:
|
||
364 .LBE65:
|
||
365 .LBE64:
|
||
210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
366 .loc 1 210 1 view .LVU103
|
||
367 001e 7047 bx lr
|
||
368 .L19:
|
||
369 .align 2
|
||
370 .L18:
|
||
371 0020 00E100E0 .word -536813312
|
||
372 .cfi_endproc
|
||
373 .LFE144:
|
||
375 .section .text.HAL_NVIC_SystemReset,"ax",%progbits
|
||
376 .align 1
|
||
377 .global HAL_NVIC_SystemReset
|
||
378 .syntax unified
|
||
379 .thumb
|
||
380 .thumb_func
|
||
381 .fpu fpv5-d16
|
||
383 HAL_NVIC_SystemReset:
|
||
384 .LFB145:
|
||
ARM GAS /tmp/ccV0GlXv.s page 64
|
||
|
||
|
||
211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU.
|
||
214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
|
||
217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
385 .loc 1 217 1 is_stmt 1 view -0
|
||
386 .cfi_startproc
|
||
387 @ Volatile: function does not return.
|
||
388 @ args = 0, pretend = 0, frame = 0
|
||
389 @ frame_needed = 0, uses_anonymous_args = 0
|
||
390 @ link register save eliminated.
|
||
218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* System Reset */
|
||
219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SystemReset();
|
||
391 .loc 1 219 3 view .LVU105
|
||
392 .LBB76:
|
||
393 .LBI76:
|
||
2083:Drivers/CMSIS/Include/core_cm7.h **** );
|
||
2084:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2085:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2086:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2087:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2088:Drivers/CMSIS/Include/core_cm7.h **** \brief Decode Priority
|
||
2089:Drivers/CMSIS/Include/core_cm7.h **** \details Decodes an interrupt priority value with a given priority group to
|
||
2090:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value and subpriority value.
|
||
2091:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available
|
||
2092:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||
2093:Drivers/CMSIS/Include/core_cm7.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC
|
||
2094:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group.
|
||
2095:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||
2096:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pSubPriority Subpriority value (starting from 0).
|
||
2097:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2098:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
|
||
2099:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
|
||
2101:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits;
|
||
2102:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits;
|
||
2103:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2104:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
|
||
2105:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
|
||
2106:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2107:Drivers/CMSIS/Include/core_cm7.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
|
||
2108:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
|
||
2109:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2110:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2111:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2112:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2113:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Vector
|
||
2114:Drivers/CMSIS/Include/core_cm7.h **** \details Sets an interrupt vector in SRAM based interrupt vector table.
|
||
2115:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt,
|
||
2116:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception.
|
||
2117:Drivers/CMSIS/Include/core_cm7.h **** VTOR must been relocated to SRAM before.
|
||
2118:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number
|
||
2119:Drivers/CMSIS/Include/core_cm7.h **** \param [in] vector Address of interrupt handler function
|
||
2120:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2121:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||
ARM GAS /tmp/ccV0GlXv.s page 65
|
||
|
||
|
||
2122:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2123:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||
2124:Drivers/CMSIS/Include/core_cm7.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||
2125:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2126:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2127:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2128:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2129:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Vector
|
||
2130:Drivers/CMSIS/Include/core_cm7.h **** \details Reads an interrupt vector from interrupt vector table.
|
||
2131:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt,
|
||
2132:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception.
|
||
2133:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number.
|
||
2134:Drivers/CMSIS/Include/core_cm7.h **** \return Address of interrupt handler function
|
||
2135:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2136:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||
2137:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2138:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||
2139:Drivers/CMSIS/Include/core_cm7.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||
2140:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2141:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2142:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2143:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2144:Drivers/CMSIS/Include/core_cm7.h **** \brief System Reset
|
||
2145:Drivers/CMSIS/Include/core_cm7.h **** \details Initiates a system reset request to reset the MCU.
|
||
2146:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2147:Drivers/CMSIS/Include/core_cm7.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||
394 .loc 2 2147 34 view .LVU106
|
||
395 .LBB77:
|
||
2148:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2149:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure all outstanding memor
|
||
396 .loc 2 2149 3 view .LVU107
|
||
397 .LBB78:
|
||
398 .LBI78:
|
||
877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
399 .loc 3 877 27 view .LVU108
|
||
400 .LBB79:
|
||
401 .loc 3 879 3 view .LVU109
|
||
402 .syntax unified
|
||
403 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
404 0000 BFF34F8F dsb 0xF
|
||
405 @ 0 "" 2
|
||
406 .thumb
|
||
407 .syntax unified
|
||
408 .LBE79:
|
||
409 .LBE78:
|
||
2150:Drivers/CMSIS/Include/core_cm7.h **** buffered write are completed
|
||
2151:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||
410 .loc 2 2151 3 view .LVU110
|
||
2152:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||
411 .loc 2 2152 32 is_stmt 0 view .LVU111
|
||
412 0004 0549 ldr r1, .L22
|
||
413 0006 CA68 ldr r2, [r1, #12]
|
||
414 .loc 2 2152 40 view .LVU112
|
||
415 0008 02F4E062 and r2, r2, #1792
|
||
2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||
416 .loc 2 2151 17 view .LVU113
|
||
417 000c 044B ldr r3, .L22+4
|
||
ARM GAS /tmp/ccV0GlXv.s page 66
|
||
|
||
|
||
418 000e 1343 orrs r3, r3, r2
|
||
2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||
419 .loc 2 2151 15 view .LVU114
|
||
420 0010 CB60 str r3, [r1, #12]
|
||
2153:Drivers/CMSIS/Include/core_cm7.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange
|
||
2154:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure completion of memory
|
||
421 .loc 2 2154 3 is_stmt 1 view .LVU115
|
||
422 .LBB80:
|
||
423 .LBI80:
|
||
877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
424 .loc 3 877 27 view .LVU116
|
||
425 .LBB81:
|
||
426 .loc 3 879 3 view .LVU117
|
||
427 .syntax unified
|
||
428 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
429 0012 BFF34F8F dsb 0xF
|
||
430 @ 0 "" 2
|
||
431 .thumb
|
||
432 .syntax unified
|
||
433 .L21:
|
||
434 .LBE81:
|
||
435 .LBE80:
|
||
2155:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2156:Drivers/CMSIS/Include/core_cm7.h **** for(;;) /* wait until reset */
|
||
436 .loc 2 2156 3 view .LVU118
|
||
2157:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2158:Drivers/CMSIS/Include/core_cm7.h **** __NOP();
|
||
437 .loc 2 2158 5 view .LVU119
|
||
438 .syntax unified
|
||
439 @ 2158 "Drivers/CMSIS/Include/core_cm7.h" 1
|
||
440 0016 00BF nop
|
||
441 @ 0 "" 2
|
||
2156:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
442 .loc 2 2156 8 view .LVU120
|
||
443 .thumb
|
||
444 .syntax unified
|
||
445 0018 FDE7 b .L21
|
||
446 .L23:
|
||
447 001a 00BF .align 2
|
||
448 .L22:
|
||
449 001c 00ED00E0 .word -536810240
|
||
450 0020 0400FA05 .word 100270084
|
||
451 .LBE77:
|
||
452 .LBE76:
|
||
453 .cfi_endproc
|
||
454 .LFE145:
|
||
456 .section .text.HAL_SYSTICK_Config,"ax",%progbits
|
||
457 .align 1
|
||
458 .global HAL_SYSTICK_Config
|
||
459 .syntax unified
|
||
460 .thumb
|
||
461 .thumb_func
|
||
462 .fpu fpv5-d16
|
||
464 HAL_SYSTICK_Config:
|
||
465 .LVL31:
|
||
466 .LFB146:
|
||
220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
ARM GAS /tmp/ccV0GlXv.s page 67
|
||
|
||
|
||
221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||
224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts.
|
||
225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||
226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval status - 0 Function succeeded.
|
||
227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * - 1 Function failed.
|
||
228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||
230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
467 .loc 1 230 1 view -0
|
||
468 .cfi_startproc
|
||
469 @ args = 0, pretend = 0, frame = 0
|
||
470 @ frame_needed = 0, uses_anonymous_args = 0
|
||
471 @ link register save eliminated.
|
||
231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return SysTick_Config(TicksNumb);
|
||
472 .loc 1 231 4 view .LVU122
|
||
473 .LBB82:
|
||
474 .LBI82:
|
||
2159:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2160:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2161:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2162:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_NVICFunctions */
|
||
2163:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2164:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## MPU functions #################################### */
|
||
2165:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2166:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||
2167:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2168:Drivers/CMSIS/Include/core_cm7.h **** #include "mpu_armv7.h"
|
||
2169:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2170:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2171:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2172:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## FPU functions #################################### */
|
||
2173:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2174:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface
|
||
2175:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||
2176:Drivers/CMSIS/Include/core_cm7.h **** \brief Function that provides FPU type.
|
||
2177:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
2178:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2179:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2180:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2181:Drivers/CMSIS/Include/core_cm7.h **** \brief get FPU type
|
||
2182:Drivers/CMSIS/Include/core_cm7.h **** \details returns the FPU type
|
||
2183:Drivers/CMSIS/Include/core_cm7.h **** \returns
|
||
2184:Drivers/CMSIS/Include/core_cm7.h **** - \b 0: No FPU
|
||
2185:Drivers/CMSIS/Include/core_cm7.h **** - \b 1: Single precision FPU
|
||
2186:Drivers/CMSIS/Include/core_cm7.h **** - \b 2: Double + Single precision FPU
|
||
2187:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2188:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||
2189:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2190:Drivers/CMSIS/Include/core_cm7.h **** uint32_t mvfr0;
|
||
2191:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2192:Drivers/CMSIS/Include/core_cm7.h **** mvfr0 = SCB->MVFR0;
|
||
2193:Drivers/CMSIS/Include/core_cm7.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
|
||
2194:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2195:Drivers/CMSIS/Include/core_cm7.h **** return 2U; /* Double + Single precision FPU */
|
||
2196:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
ARM GAS /tmp/ccV0GlXv.s page 68
|
||
|
||
|
||
2197:Drivers/CMSIS/Include/core_cm7.h **** else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
|
||
2198:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2199:Drivers/CMSIS/Include/core_cm7.h **** return 1U; /* Single precision FPU */
|
||
2200:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2201:Drivers/CMSIS/Include/core_cm7.h **** else
|
||
2202:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2203:Drivers/CMSIS/Include/core_cm7.h **** return 0U; /* No FPU */
|
||
2204:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2205:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2206:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2207:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2208:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_FpuFunctions */
|
||
2209:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2210:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2211:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2212:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## Cache functions #################################### */
|
||
2213:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2214:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface
|
||
2215:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||
2216:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that configure Instruction and Data cache.
|
||
2217:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
2218:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2219:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2220:Drivers/CMSIS/Include/core_cm7.h **** /* Cache Size ID Register Macros */
|
||
2221:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Po
|
||
2222:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos
|
||
2223:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2224:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2225:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2226:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable I-Cache
|
||
2227:Drivers/CMSIS/Include/core_cm7.h **** \details Turns on I-Cache
|
||
2228:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2229:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableICache (void)
|
||
2230:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2231:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||
2232:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2233:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2234:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||
2235:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2236:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2237:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||
2238:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2239:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2240:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2241:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2242:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2243:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2244:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2245:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable I-Cache
|
||
2246:Drivers/CMSIS/Include/core_cm7.h **** \details Turns off I-Cache
|
||
2247:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2248:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableICache (void)
|
||
2249:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2250:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||
2251:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2252:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2253:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||
ARM GAS /tmp/ccV0GlXv.s page 69
|
||
|
||
|
||
2254:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||
2255:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2256:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2257:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2258:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2259:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2260:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2261:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2262:Drivers/CMSIS/Include/core_cm7.h **** \brief Invalidate I-Cache
|
||
2263:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates I-Cache
|
||
2264:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2265:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateICache (void)
|
||
2266:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2267:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||
2268:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2269:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2270:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL;
|
||
2271:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2272:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2273:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2274:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2275:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2276:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2277:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2278:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable D-Cache
|
||
2279:Drivers/CMSIS/Include/core_cm7.h **** \details Turns on D-Cache
|
||
2280:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2281:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableDCache (void)
|
||
2282:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2283:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr;
|
||
2285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets;
|
||
2286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways;
|
||
2287:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2288:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
||
2289:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2290:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2291:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
|
||
2292:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2293:Drivers/CMSIS/Include/core_cm7.h **** /* invalidate D-Cache */
|
||
2294:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||
2295:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2296:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||
2297:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2298:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||
2299:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||
2300:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
|
||
2301:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier();
|
||
2302:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2303:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U);
|
||
2304:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U);
|
||
2305:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2306:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2307:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||
2308:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2309:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2310:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
ARM GAS /tmp/ccV0GlXv.s page 70
|
||
|
||
|
||
2311:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2312:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2313:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2314:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2315:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2316:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable D-Cache
|
||
2317:Drivers/CMSIS/Include/core_cm7.h **** \details Turns off D-Cache
|
||
2318:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2319:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableDCache (void)
|
||
2320:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2321:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2322:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr;
|
||
2323:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets;
|
||
2324:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways;
|
||
2325:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2326:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
||
2327:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2328:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2329:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||
2330:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2331:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2332:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
|
||
2333:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2334:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */
|
||
2335:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||
2336:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2337:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||
2338:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2339:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||
2340:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||
2341:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
|
||
2342:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier();
|
||
2343:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2344:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U);
|
||
2345:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U);
|
||
2346:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2347:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2348:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2349:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2350:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2351:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2352:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2353:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2354:Drivers/CMSIS/Include/core_cm7.h **** \brief Invalidate D-Cache
|
||
2355:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates D-Cache
|
||
2356:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2357:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache (void)
|
||
2358:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2359:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2360:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr;
|
||
2361:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets;
|
||
2362:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways;
|
||
2363:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2364:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
||
2365:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2366:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2367:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
|
||
ARM GAS /tmp/ccV0GlXv.s page 71
|
||
|
||
|
||
2368:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2369:Drivers/CMSIS/Include/core_cm7.h **** /* invalidate D-Cache */
|
||
2370:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||
2371:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2372:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||
2373:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2374:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||
2375:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||
2376:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
|
||
2377:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier();
|
||
2378:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2379:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U);
|
||
2380:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U);
|
||
2381:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2382:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2383:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2384:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2385:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2386:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2387:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2388:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2389:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean D-Cache
|
||
2390:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans D-Cache
|
||
2391:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2392:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache (void)
|
||
2393:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2394:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr;
|
||
2396:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets;
|
||
2397:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways;
|
||
2398:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2399:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
||
2400:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2401:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2402:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
|
||
2403:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2404:Drivers/CMSIS/Include/core_cm7.h **** /* clean D-Cache */
|
||
2405:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||
2406:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2407:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||
2408:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2409:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||
2410:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||
2411:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
|
||
2412:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier();
|
||
2413:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2414:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U);
|
||
2415:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U);
|
||
2416:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2417:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2418:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2419:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2420:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2421:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2422:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2423:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2424:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean & Invalidate D-Cache
|
||
ARM GAS /tmp/ccV0GlXv.s page 72
|
||
|
||
|
||
2425:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and Invalidates D-Cache
|
||
2426:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2427:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
|
||
2428:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2429:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr;
|
||
2431:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets;
|
||
2432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways;
|
||
2433:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2434:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
|
||
2435:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2436:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2437:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
|
||
2438:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2439:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */
|
||
2440:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||
2441:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2442:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||
2443:Drivers/CMSIS/Include/core_cm7.h **** do {
|
||
2444:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||
2445:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||
2446:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
|
||
2447:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier();
|
||
2448:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2449:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U);
|
||
2450:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U);
|
||
2451:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2452:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2453:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2454:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2455:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2456:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2457:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2458:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2459:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Invalidate by address
|
||
2460:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates D-Cache for the given address
|
||
2461:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary)
|
||
2462:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes)
|
||
2463:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2464:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||
2465:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2466:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2467:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize;
|
||
2468:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t)addr;
|
||
2469:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (
|
||
2470:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2471:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2472:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2473:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) {
|
||
2474:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCIMVAC = op_addr;
|
||
2475:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize;
|
||
2476:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize;
|
||
2477:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2478:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2479:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2480:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2481:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
ARM GAS /tmp/ccV0GlXv.s page 73
|
||
|
||
|
||
2482:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2483:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2484:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2485:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2486:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Clean by address
|
||
2487:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans D-Cache for the given address
|
||
2488:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary)
|
||
2489:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes)
|
||
2490:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2491:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||
2492:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2493:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2494:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize;
|
||
2495:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr;
|
||
2496:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (
|
||
2497:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2498:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2499:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2500:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) {
|
||
2501:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCMVAC = op_addr;
|
||
2502:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize;
|
||
2503:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize;
|
||
2504:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2505:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2506:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2507:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2508:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2509:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2510:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2511:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2512:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2513:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Clean and Invalidate by address
|
||
2514:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and invalidates D_Cache for the given address
|
||
2515:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary)
|
||
2516:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes)
|
||
2517:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2518:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||
2519:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2520:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
2521:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize;
|
||
2522:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr;
|
||
2523:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (
|
||
2524:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2525:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2526:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2527:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) {
|
||
2528:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCIMVAC = op_addr;
|
||
2529:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize;
|
||
2530:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize;
|
||
2531:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2532:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2533:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
|
||
2534:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
|
||
2535:Drivers/CMSIS/Include/core_cm7.h **** #endif
|
||
2536:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2537:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2538:Drivers/CMSIS/Include/core_cm7.h ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 74
|
||
|
||
|
||
2539:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_CacheFunctions */
|
||
2540:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2541:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2542:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2543:Drivers/CMSIS/Include/core_cm7.h **** /* ################################## SysTick function ########################################
|
||
2544:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2545:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface
|
||
2546:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||
2547:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that configure the System.
|
||
2548:Drivers/CMSIS/Include/core_cm7.h **** @{
|
||
2549:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2550:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2551:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||
2552:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2553:Drivers/CMSIS/Include/core_cm7.h **** /**
|
||
2554:Drivers/CMSIS/Include/core_cm7.h **** \brief System Tick Configuration
|
||
2555:Drivers/CMSIS/Include/core_cm7.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||
2556:Drivers/CMSIS/Include/core_cm7.h **** Counter is in free running mode to generate periodic interrupts.
|
||
2557:Drivers/CMSIS/Include/core_cm7.h **** \param [in] ticks Number of ticks between two interrupts.
|
||
2558:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Function succeeded.
|
||
2559:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Function failed.
|
||
2560:Drivers/CMSIS/Include/core_cm7.h **** \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||
2561:Drivers/CMSIS/Include/core_cm7.h **** function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
|
||
2562:Drivers/CMSIS/Include/core_cm7.h **** must contain a vendor-specific implementation of this function.
|
||
2563:Drivers/CMSIS/Include/core_cm7.h **** */
|
||
2564:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||
475 .loc 2 2564 26 view .LVU123
|
||
476 .LBB83:
|
||
2565:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2566:Drivers/CMSIS/Include/core_cm7.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||
477 .loc 2 2566 3 view .LVU124
|
||
478 .loc 2 2566 14 is_stmt 0 view .LVU125
|
||
479 0000 0138 subs r0, r0, #1
|
||
480 .LVL32:
|
||
481 .loc 2 2566 6 view .LVU126
|
||
482 0002 B0F1807F cmp r0, #16777216
|
||
483 0006 0BD2 bcs .L26
|
||
2567:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
2568:Drivers/CMSIS/Include/core_cm7.h **** return (1UL); /* Reload value impossible */
|
||
2569:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
2570:Drivers/CMSIS/Include/core_cm7.h ****
|
||
2571:Drivers/CMSIS/Include/core_cm7.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||
484 .loc 2 2571 3 is_stmt 1 view .LVU127
|
||
485 .loc 2 2571 18 is_stmt 0 view .LVU128
|
||
486 0008 4FF0E023 mov r3, #-536813568
|
||
487 000c 5861 str r0, [r3, #20]
|
||
2572:Drivers/CMSIS/Include/core_cm7.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
|
||
488 .loc 2 2572 3 is_stmt 1 view .LVU129
|
||
489 .LVL33:
|
||
490 .LBB84:
|
||
491 .LBI84:
|
||
2024:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
492 .loc 2 2024 22 view .LVU130
|
||
493 .LBB85:
|
||
2026:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
494 .loc 2 2026 3 view .LVU131
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
ARM GAS /tmp/ccV0GlXv.s page 75
|
||
|
||
|
||
495 .loc 2 2032 5 view .LVU132
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
496 .loc 2 2032 47 is_stmt 0 view .LVU133
|
||
497 000e 054A ldr r2, .L27
|
||
498 0010 F021 movs r1, #240
|
||
499 0012 82F82310 strb r1, [r2, #35]
|
||
500 .LVL34:
|
||
2032:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
501 .loc 2 2032 47 view .LVU134
|
||
502 .LBE85:
|
||
503 .LBE84:
|
||
2573:Drivers/CMSIS/Include/core_cm7.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val
|
||
504 .loc 2 2573 3 is_stmt 1 view .LVU135
|
||
505 .loc 2 2573 18 is_stmt 0 view .LVU136
|
||
506 0016 0020 movs r0, #0
|
||
507 .LVL35:
|
||
508 .loc 2 2573 18 view .LVU137
|
||
509 0018 9861 str r0, [r3, #24]
|
||
2574:Drivers/CMSIS/Include/core_cm7.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||
510 .loc 2 2574 3 is_stmt 1 view .LVU138
|
||
511 .loc 2 2574 18 is_stmt 0 view .LVU139
|
||
512 001a 0722 movs r2, #7
|
||
513 001c 1A61 str r2, [r3, #16]
|
||
2575:Drivers/CMSIS/Include/core_cm7.h **** SysTick_CTRL_TICKINT_Msk |
|
||
2576:Drivers/CMSIS/Include/core_cm7.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi
|
||
2577:Drivers/CMSIS/Include/core_cm7.h **** return (0UL); /* Function successful */
|
||
514 .loc 2 2577 3 is_stmt 1 view .LVU140
|
||
515 .loc 2 2577 10 is_stmt 0 view .LVU141
|
||
516 001e 7047 bx lr
|
||
517 .L26:
|
||
2568:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
518 .loc 2 2568 12 view .LVU142
|
||
519 0020 0120 movs r0, #1
|
||
520 .LVL36:
|
||
2568:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
521 .loc 2 2568 12 view .LVU143
|
||
522 .LBE83:
|
||
523 .LBE82:
|
||
232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
524 .loc 1 232 1 view .LVU144
|
||
525 0022 7047 bx lr
|
||
526 .L28:
|
||
527 .align 2
|
||
528 .L27:
|
||
529 0024 00ED00E0 .word -536810240
|
||
530 .cfi_endproc
|
||
531 .LFE146:
|
||
533 .section .text.HAL_MPU_Disable,"ax",%progbits
|
||
534 .align 1
|
||
535 .global HAL_MPU_Disable
|
||
536 .syntax unified
|
||
537 .thumb
|
||
538 .thumb_func
|
||
539 .fpu fpv5-d16
|
||
541 HAL_MPU_Disable:
|
||
542 .LFB147:
|
||
233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
ARM GAS /tmp/ccV0GlXv.s page 76
|
||
|
||
|
||
234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @}
|
||
235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||
238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Cortex control functions
|
||
239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *
|
||
240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @verbatim
|
||
241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ==============================================================================
|
||
242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ##### Peripheral Control functions #####
|
||
243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ==============================================================================
|
||
244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..]
|
||
245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX
|
||
246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities.
|
||
247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @endverbatim
|
||
250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{
|
||
251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #if (__MPU_PRESENT == 1)
|
||
253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Disables the MPU
|
||
255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_MPU_Disable(void)
|
||
258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
543 .loc 1 258 1 is_stmt 1 view -0
|
||
544 .cfi_startproc
|
||
545 @ args = 0, pretend = 0, frame = 0
|
||
546 @ frame_needed = 0, uses_anonymous_args = 0
|
||
547 @ link register save eliminated.
|
||
259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Make sure outstanding transfers are done */
|
||
260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __DMB();
|
||
548 .loc 1 260 3 view .LVU146
|
||
549 .LBB86:
|
||
550 .LBI86:
|
||
880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
881:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
882:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier
|
||
885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
|
||
886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
|
||
887:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
|
||
551 .loc 3 888 27 view .LVU147
|
||
552 .LBB87:
|
||
889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
|
||
553 .loc 3 890 3 view .LVU148
|
||
554 .syntax unified
|
||
555 @ 890 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
556 0000 BFF35F8F dmb 0xF
|
||
557 @ 0 "" 2
|
||
558 .thumb
|
||
559 .syntax unified
|
||
560 .LBE87:
|
||
561 .LBE86:
|
||
ARM GAS /tmp/ccV0GlXv.s page 77
|
||
|
||
|
||
261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Disable fault exceptions */
|
||
263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||
562 .loc 1 263 3 view .LVU149
|
||
563 .loc 1 263 14 is_stmt 0 view .LVU150
|
||
564 0004 044B ldr r3, .L30
|
||
565 0006 5A6A ldr r2, [r3, #36]
|
||
566 0008 22F48032 bic r2, r2, #65536
|
||
567 000c 5A62 str r2, [r3, #36]
|
||
264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/
|
||
266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->CTRL = 0;
|
||
568 .loc 1 266 3 is_stmt 1 view .LVU151
|
||
569 .loc 1 266 13 is_stmt 0 view .LVU152
|
||
570 000e 0022 movs r2, #0
|
||
571 0010 C3F89420 str r2, [r3, #148]
|
||
267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
572 .loc 1 267 1 view .LVU153
|
||
573 0014 7047 bx lr
|
||
574 .L31:
|
||
575 0016 00BF .align 2
|
||
576 .L30:
|
||
577 0018 00ED00E0 .word -536810240
|
||
578 .cfi_endproc
|
||
579 .LFE147:
|
||
581 .section .text.HAL_MPU_Enable,"ax",%progbits
|
||
582 .align 1
|
||
583 .global HAL_MPU_Enable
|
||
584 .syntax unified
|
||
585 .thumb
|
||
586 .thumb_func
|
||
587 .fpu fpv5-d16
|
||
589 HAL_MPU_Enable:
|
||
590 .LVL37:
|
||
591 .LFB148:
|
||
268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Enables the MPU
|
||
271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault,
|
||
272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory
|
||
273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values:
|
||
274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE
|
||
275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI
|
||
276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT
|
||
277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF
|
||
278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
|
||
281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
592 .loc 1 281 1 is_stmt 1 view -0
|
||
593 .cfi_startproc
|
||
594 @ args = 0, pretend = 0, frame = 0
|
||
595 @ frame_needed = 0, uses_anonymous_args = 0
|
||
596 @ link register save eliminated.
|
||
282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Enable the MPU */
|
||
283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||
597 .loc 1 283 3 view .LVU155
|
||
ARM GAS /tmp/ccV0GlXv.s page 78
|
||
|
||
|
||
598 .loc 1 283 27 is_stmt 0 view .LVU156
|
||
599 0000 40F00100 orr r0, r0, #1
|
||
600 .LVL38:
|
||
601 .loc 1 283 13 view .LVU157
|
||
602 0004 054B ldr r3, .L33
|
||
603 0006 C3F89400 str r0, [r3, #148]
|
||
284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Enable fault exceptions */
|
||
286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||
604 .loc 1 286 3 is_stmt 1 view .LVU158
|
||
605 .loc 1 286 14 is_stmt 0 view .LVU159
|
||
606 000a 5A6A ldr r2, [r3, #36]
|
||
607 000c 42F48032 orr r2, r2, #65536
|
||
608 0010 5A62 str r2, [r3, #36]
|
||
287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Ensure MPU setting take effects */
|
||
289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __DSB();
|
||
609 .loc 1 289 3 is_stmt 1 view .LVU160
|
||
610 .LBB88:
|
||
611 .LBI88:
|
||
877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
612 .loc 3 877 27 view .LVU161
|
||
613 .LBB89:
|
||
879:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
614 .loc 3 879 3 view .LVU162
|
||
615 .syntax unified
|
||
616 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
617 0012 BFF34F8F dsb 0xF
|
||
618 @ 0 "" 2
|
||
619 .thumb
|
||
620 .syntax unified
|
||
621 .LBE89:
|
||
622 .LBE88:
|
||
290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __ISB();
|
||
623 .loc 1 290 3 view .LVU163
|
||
624 .LBB90:
|
||
625 .LBI90:
|
||
866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
626 .loc 3 866 27 view .LVU164
|
||
627 .LBB91:
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
628 .loc 3 868 3 view .LVU165
|
||
629 .syntax unified
|
||
630 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
631 0016 BFF36F8F isb 0xF
|
||
632 @ 0 "" 2
|
||
633 .thumb
|
||
634 .syntax unified
|
||
635 .LBE91:
|
||
636 .LBE90:
|
||
291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
637 .loc 1 291 1 is_stmt 0 view .LVU166
|
||
638 001a 7047 bx lr
|
||
639 .L34:
|
||
640 .align 2
|
||
641 .L33:
|
||
642 001c 00ED00E0 .word -536810240
|
||
ARM GAS /tmp/ccV0GlXv.s page 79
|
||
|
||
|
||
643 .cfi_endproc
|
||
644 .LFE148:
|
||
646 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits
|
||
647 .align 1
|
||
648 .global HAL_MPU_ConfigRegion
|
||
649 .syntax unified
|
||
650 .thumb
|
||
651 .thumb_func
|
||
652 .fpu fpv5-d16
|
||
654 HAL_MPU_ConfigRegion:
|
||
655 .LVL39:
|
||
656 .LFB149:
|
||
292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected.
|
||
294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||
295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * the initialization and configuration information.
|
||
296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||
299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
657 .loc 1 299 1 is_stmt 1 view -0
|
||
658 .cfi_startproc
|
||
659 @ args = 0, pretend = 0, frame = 0
|
||
660 @ frame_needed = 0, uses_anonymous_args = 0
|
||
661 @ link register save eliminated.
|
||
300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||
662 .loc 1 301 3 view .LVU168
|
||
302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||
663 .loc 1 302 3 view .LVU169
|
||
303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Set the Region number */
|
||
305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number;
|
||
664 .loc 1 305 3 view .LVU170
|
||
665 .loc 1 305 22 is_stmt 0 view .LVU171
|
||
666 0000 4278 ldrb r2, [r0, #1] @ zero_extendqisi2
|
||
667 .loc 1 305 12 view .LVU172
|
||
668 0002 164B ldr r3, .L38
|
||
669 0004 C3F89820 str r2, [r3, #152]
|
||
306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** if ((MPU_Init->Enable) != 0UL)
|
||
670 .loc 1 307 3 is_stmt 1 view .LVU173
|
||
671 .loc 1 307 16 is_stmt 0 view .LVU174
|
||
672 0008 0378 ldrb r3, [r0] @ zero_extendqisi2
|
||
673 .loc 1 307 6 view .LVU175
|
||
674 000a FBB1 cbz r3, .L36
|
||
308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||
675 .loc 1 310 5 is_stmt 1 view .LVU176
|
||
311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||
676 .loc 1 311 5 view .LVU177
|
||
312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||
677 .loc 1 312 5 view .LVU178
|
||
313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||
678 .loc 1 313 5 view .LVU179
|
||
314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||
ARM GAS /tmp/ccV0GlXv.s page 80
|
||
|
||
|
||
679 .loc 1 314 5 view .LVU180
|
||
315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||
680 .loc 1 315 5 view .LVU181
|
||
316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||
681 .loc 1 316 5 view .LVU182
|
||
317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||
682 .loc 1 317 5 view .LVU183
|
||
318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress;
|
||
683 .loc 1 319 5 view .LVU184
|
||
684 .loc 1 319 25 is_stmt 0 view .LVU185
|
||
685 000c 4368 ldr r3, [r0, #4]
|
||
686 .loc 1 319 15 view .LVU186
|
||
687 000e 134A ldr r2, .L38
|
||
688 0010 C2F89C30 str r3, [r2, #156]
|
||
320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||
689 .loc 1 320 5 is_stmt 1 view .LVU187
|
||
690 .loc 1 320 36 is_stmt 0 view .LVU188
|
||
691 0014 017B ldrb r1, [r0, #12] @ zero_extendqisi2
|
||
321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||
692 .loc 1 321 36 view .LVU189
|
||
693 0016 C37A ldrb r3, [r0, #11] @ zero_extendqisi2
|
||
694 .loc 1 321 62 view .LVU190
|
||
695 0018 1B06 lsls r3, r3, #24
|
||
320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||
696 .loc 1 320 84 view .LVU191
|
||
697 001a 43EA0173 orr r3, r3, r1, lsl #28
|
||
322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||
698 .loc 1 322 36 view .LVU192
|
||
699 001e 817A ldrb r1, [r0, #10] @ zero_extendqisi2
|
||
321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||
700 .loc 1 321 84 view .LVU193
|
||
701 0020 43EAC143 orr r3, r3, r1, lsl #19
|
||
323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||
702 .loc 1 323 36 view .LVU194
|
||
703 0024 417B ldrb r1, [r0, #13] @ zero_extendqisi2
|
||
322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||
704 .loc 1 322 84 view .LVU195
|
||
705 0026 43EA8143 orr r3, r3, r1, lsl #18
|
||
324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||
706 .loc 1 324 36 view .LVU196
|
||
707 002a 817B ldrb r1, [r0, #14] @ zero_extendqisi2
|
||
323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||
708 .loc 1 323 84 view .LVU197
|
||
709 002c 43EA4143 orr r3, r3, r1, lsl #17
|
||
325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||
710 .loc 1 325 36 view .LVU198
|
||
711 0030 C17B ldrb r1, [r0, #15] @ zero_extendqisi2
|
||
324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||
712 .loc 1 324 84 view .LVU199
|
||
713 0032 43EA0143 orr r3, r3, r1, lsl #16
|
||
326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||
714 .loc 1 326 36 view .LVU200
|
||
715 0036 417A ldrb r1, [r0, #9] @ zero_extendqisi2
|
||
325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||
716 .loc 1 325 84 view .LVU201
|
||
717 0038 43EA0123 orr r3, r3, r1, lsl #8
|
||
ARM GAS /tmp/ccV0GlXv.s page 81
|
||
|
||
|
||
327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||
718 .loc 1 327 36 view .LVU202
|
||
719 003c 017A ldrb r1, [r0, #8] @ zero_extendqisi2
|
||
326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||
720 .loc 1 326 84 view .LVU203
|
||
721 003e 43EA4103 orr r3, r3, r1, lsl #1
|
||
328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||
722 .loc 1 328 36 view .LVU204
|
||
723 0042 0178 ldrb r1, [r0] @ zero_extendqisi2
|
||
327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||
724 .loc 1 327 84 view .LVU205
|
||
725 0044 0B43 orrs r3, r3, r1
|
||
320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||
726 .loc 1 320 15 view .LVU206
|
||
727 0046 C2F8A030 str r3, [r2, #160]
|
||
728 004a 7047 bx lr
|
||
729 .L36:
|
||
329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** else
|
||
331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RBAR = 0x00;
|
||
730 .loc 1 332 5 is_stmt 1 view .LVU207
|
||
731 .loc 1 332 15 is_stmt 0 view .LVU208
|
||
732 004c 034B ldr r3, .L38
|
||
733 004e 0022 movs r2, #0
|
||
734 0050 C3F89C20 str r2, [r3, #156]
|
||
333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RASR = 0x00;
|
||
735 .loc 1 333 5 is_stmt 1 view .LVU209
|
||
736 .loc 1 333 15 is_stmt 0 view .LVU210
|
||
737 0054 C3F8A020 str r2, [r3, #160]
|
||
334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
738 .loc 1 335 1 view .LVU211
|
||
739 0058 7047 bx lr
|
||
740 .L39:
|
||
741 005a 00BF .align 2
|
||
742 .L38:
|
||
743 005c 00ED00E0 .word -536810240
|
||
744 .cfi_endproc
|
||
745 .LFE149:
|
||
747 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits
|
||
748 .align 1
|
||
749 .global HAL_NVIC_GetPriorityGrouping
|
||
750 .syntax unified
|
||
751 .thumb
|
||
752 .thumb_func
|
||
753 .fpu fpv5-d16
|
||
755 HAL_NVIC_GetPriorityGrouping:
|
||
756 .LFB150:
|
||
336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #endif /* __MPU_PRESENT */
|
||
337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||
340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||
341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||
343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
ARM GAS /tmp/ccV0GlXv.s page 82
|
||
|
||
|
||
757 .loc 1 343 1 is_stmt 1 view -0
|
||
758 .cfi_startproc
|
||
759 @ args = 0, pretend = 0, frame = 0
|
||
760 @ frame_needed = 0, uses_anonymous_args = 0
|
||
761 @ link register save eliminated.
|
||
344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */
|
||
345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return NVIC_GetPriorityGrouping();
|
||
762 .loc 1 345 3 view .LVU213
|
||
763 .LBB92:
|
||
764 .LBI92:
|
||
1884:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
765 .loc 2 1884 26 view .LVU214
|
||
766 .LBB93:
|
||
1886:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
767 .loc 2 1886 3 view .LVU215
|
||
1886:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
768 .loc 2 1886 26 is_stmt 0 view .LVU216
|
||
769 0000 024B ldr r3, .L41
|
||
770 0002 D868 ldr r0, [r3, #12]
|
||
771 .LBE93:
|
||
772 .LBE92:
|
||
346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
773 .loc 1 346 1 view .LVU217
|
||
774 0004 C0F30220 ubfx r0, r0, #8, #3
|
||
775 0008 7047 bx lr
|
||
776 .L42:
|
||
777 000a 00BF .align 2
|
||
778 .L41:
|
||
779 000c 00ED00E0 .word -536810240
|
||
780 .cfi_endproc
|
||
781 .LFE150:
|
||
783 .section .text.HAL_NVIC_GetPriority,"ax",%progbits
|
||
784 .align 1
|
||
785 .global HAL_NVIC_GetPriority
|
||
786 .syntax unified
|
||
787 .thumb
|
||
788 .thumb_func
|
||
789 .fpu fpv5-d16
|
||
791 HAL_NVIC_GetPriority:
|
||
792 .LVL40:
|
||
793 .LFB151:
|
||
347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets the priority of an interrupt.
|
||
350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number.
|
||
351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param PriorityGroup the priority grouping bits length.
|
||
354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values:
|
||
355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||
356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 4 bits for subpriority
|
||
357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||
358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 3 bits for subpriority
|
||
359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||
360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 2 bits for subpriority
|
||
361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||
362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 1 bits for subpriority
|
||
ARM GAS /tmp/ccV0GlXv.s page 83
|
||
|
||
|
||
363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||
364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 0 bits for subpriority
|
||
365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
|
||
366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0).
|
||
367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3
|
||
370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
794 .loc 1 370 1 is_stmt 1 view -0
|
||
795 .cfi_startproc
|
||
796 @ args = 0, pretend = 0, frame = 0
|
||
797 @ frame_needed = 0, uses_anonymous_args = 0
|
||
798 .loc 1 370 1 is_stmt 0 view .LVU219
|
||
799 0000 10B5 push {r4, lr}
|
||
800 .LCFI1:
|
||
801 .cfi_def_cfa_offset 8
|
||
802 .cfi_offset 4, -8
|
||
803 .cfi_offset 14, -4
|
||
371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||
804 .loc 1 372 3 is_stmt 1 view .LVU220
|
||
373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */
|
||
374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||
805 .loc 1 374 3 view .LVU221
|
||
806 .LVL41:
|
||
807 .LBB98:
|
||
808 .LBI98:
|
||
2046:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
809 .loc 2 2046 26 view .LVU222
|
||
810 .LBB99:
|
||
2049:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
811 .loc 2 2049 3 view .LVU223
|
||
2049:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
812 .loc 2 2049 6 is_stmt 0 view .LVU224
|
||
813 0002 0028 cmp r0, #0
|
||
814 .LVL42:
|
||
2049:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
815 .loc 2 2049 6 view .LVU225
|
||
816 0004 1EDB blt .L44
|
||
2051:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
817 .loc 2 2051 5 is_stmt 1 view .LVU226
|
||
2051:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
818 .loc 2 2051 31 is_stmt 0 view .LVU227
|
||
819 0006 134C ldr r4, .L49
|
||
820 0008 205C ldrb r0, [r4, r0] @ zero_extendqisi2
|
||
2051:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
821 .loc 2 2051 65 view .LVU228
|
||
822 000a 0009 lsrs r0, r0, #4
|
||
823 .L45:
|
||
824 .LVL43:
|
||
2051:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
825 .loc 2 2051 65 view .LVU229
|
||
826 .LBE99:
|
||
827 .LBE98:
|
||
828 .LBB101:
|
||
829 .LBI101:
|
||
2098:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
ARM GAS /tmp/ccV0GlXv.s page 84
|
||
|
||
|
||
830 .loc 2 2098 22 is_stmt 1 view .LVU230
|
||
831 .LBB102:
|
||
2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits;
|
||
832 .loc 2 2100 3 view .LVU231
|
||
2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits;
|
||
833 .loc 2 2100 12 is_stmt 0 view .LVU232
|
||
834 000c 01F00701 and r1, r1, #7
|
||
835 .LVL44:
|
||
2101:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits;
|
||
836 .loc 2 2101 3 is_stmt 1 view .LVU233
|
||
2102:Drivers/CMSIS/Include/core_cm7.h ****
|
||
837 .loc 2 2102 3 view .LVU234
|
||
2104:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
|
||
838 .loc 2 2104 3 view .LVU235
|
||
2104:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
|
||
839 .loc 2 2104 31 is_stmt 0 view .LVU236
|
||
840 0010 C1F1070C rsb ip, r1, #7
|
||
2104:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
|
||
841 .loc 2 2104 23 view .LVU237
|
||
842 0014 BCF1040F cmp ip, #4
|
||
843 0018 28BF it cs
|
||
844 001a 4FF0040C movcs ip, #4
|
||
845 .LVL45:
|
||
2105:Drivers/CMSIS/Include/core_cm7.h ****
|
||
846 .loc 2 2105 3 is_stmt 1 view .LVU238
|
||
2105:Drivers/CMSIS/Include/core_cm7.h ****
|
||
847 .loc 2 2105 44 is_stmt 0 view .LVU239
|
||
848 001e 0C1D adds r4, r1, #4
|
||
2105:Drivers/CMSIS/Include/core_cm7.h ****
|
||
849 .loc 2 2105 109 view .LVU240
|
||
850 0020 062C cmp r4, #6
|
||
851 0022 15D9 bls .L47
|
||
852 0024 0339 subs r1, r1, #3
|
||
853 .LVL46:
|
||
854 .L46:
|
||
2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
|
||
855 .loc 2 2107 3 is_stmt 1 view .LVU241
|
||
2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
|
||
856 .loc 2 2107 33 is_stmt 0 view .LVU242
|
||
857 0026 20FA01F4 lsr r4, r0, r1
|
||
858 .LVL47:
|
||
2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
|
||
859 .loc 2 2107 53 view .LVU243
|
||
860 002a 4FF0FF3E mov lr, #-1
|
||
861 002e 0EFA0CFC lsl ip, lr, ip
|
||
862 .LVL48:
|
||
2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
|
||
863 .loc 2 2107 53 view .LVU244
|
||
864 0032 24EA0C04 bic r4, r4, ip
|
||
2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
|
||
865 .loc 2 2107 21 view .LVU245
|
||
866 0036 1460 str r4, [r2]
|
||
2108:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
867 .loc 2 2108 3 is_stmt 1 view .LVU246
|
||
2108:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
868 .loc 2 2108 53 is_stmt 0 view .LVU247
|
||
869 0038 0EFA01F1 lsl r1, lr, r1
|
||
ARM GAS /tmp/ccV0GlXv.s page 85
|
||
|
||
|
||
870 .LVL49:
|
||
2108:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
871 .loc 2 2108 53 view .LVU248
|
||
872 003c 20EA0100 bic r0, r0, r1
|
||
873 .LVL50:
|
||
2108:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
874 .loc 2 2108 21 view .LVU249
|
||
875 0040 1860 str r0, [r3]
|
||
876 .LVL51:
|
||
2108:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
877 .loc 2 2108 21 view .LVU250
|
||
878 .LBE102:
|
||
879 .LBE101:
|
||
375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
880 .loc 1 375 1 view .LVU251
|
||
881 0042 10BD pop {r4, pc}
|
||
882 .LVL52:
|
||
883 .L44:
|
||
884 .LBB104:
|
||
885 .LBB100:
|
||
2055:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
886 .loc 2 2055 5 is_stmt 1 view .LVU252
|
||
2055:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
887 .loc 2 2055 51 is_stmt 0 view .LVU253
|
||
888 0044 00F00F00 and r0, r0, #15
|
||
2055:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
889 .loc 2 2055 32 view .LVU254
|
||
890 0048 034C ldr r4, .L49+4
|
||
891 004a 205C ldrb r0, [r4, r0] @ zero_extendqisi2
|
||
2055:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
892 .loc 2 2055 65 view .LVU255
|
||
893 004c 0009 lsrs r0, r0, #4
|
||
894 004e DDE7 b .L45
|
||
895 .LVL53:
|
||
896 .L47:
|
||
2055:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
897 .loc 2 2055 65 view .LVU256
|
||
898 .LBE100:
|
||
899 .LBE104:
|
||
900 .LBB105:
|
||
901 .LBB103:
|
||
2105:Drivers/CMSIS/Include/core_cm7.h ****
|
||
902 .loc 2 2105 109 view .LVU257
|
||
903 0050 0021 movs r1, #0
|
||
904 .LVL54:
|
||
2105:Drivers/CMSIS/Include/core_cm7.h ****
|
||
905 .loc 2 2105 109 view .LVU258
|
||
906 0052 E8E7 b .L46
|
||
907 .L50:
|
||
908 .align 2
|
||
909 .L49:
|
||
910 0054 00E400E0 .word -536812544
|
||
911 0058 14ED00E0 .word -536810220
|
||
912 .LBE103:
|
||
913 .LBE105:
|
||
914 .cfi_endproc
|
||
915 .LFE151:
|
||
ARM GAS /tmp/ccV0GlXv.s page 86
|
||
|
||
|
||
917 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
|
||
918 .align 1
|
||
919 .global HAL_NVIC_SetPendingIRQ
|
||
920 .syntax unified
|
||
921 .thumb
|
||
922 .thumb_func
|
||
923 .fpu fpv5-d16
|
||
925 HAL_NVIC_SetPendingIRQ:
|
||
926 .LVL55:
|
||
927 .LFB152:
|
||
376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt.
|
||
379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number
|
||
380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||
385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
928 .loc 1 385 1 is_stmt 1 view -0
|
||
929 .cfi_startproc
|
||
930 @ args = 0, pretend = 0, frame = 0
|
||
931 @ frame_needed = 0, uses_anonymous_args = 0
|
||
932 @ link register save eliminated.
|
||
386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
933 .loc 1 387 3 view .LVU260
|
||
388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Set interrupt pending */
|
||
390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn);
|
||
934 .loc 1 390 3 view .LVU261
|
||
935 .LBB106:
|
||
936 .LBI106:
|
||
1970:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
937 .loc 2 1970 22 view .LVU262
|
||
938 .LBB107:
|
||
1972:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
939 .loc 2 1972 3 view .LVU263
|
||
1972:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
940 .loc 2 1972 6 is_stmt 0 view .LVU264
|
||
941 0000 0028 cmp r0, #0
|
||
942 .LVL56:
|
||
1972:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
943 .loc 2 1972 6 view .LVU265
|
||
944 0002 08DB blt .L51
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
945 .loc 2 1974 5 is_stmt 1 view .LVU266
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
946 .loc 2 1974 81 is_stmt 0 view .LVU267
|
||
947 0004 00F01F02 and r2, r0, #31
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
948 .loc 2 1974 34 view .LVU268
|
||
949 0008 4009 lsrs r0, r0, #5
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
950 .loc 2 1974 45 view .LVU269
|
||
951 000a 0123 movs r3, #1
|
||
ARM GAS /tmp/ccV0GlXv.s page 87
|
||
|
||
|
||
952 000c 9340 lsls r3, r3, r2
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
953 .loc 2 1974 43 view .LVU270
|
||
954 000e 4030 adds r0, r0, #64
|
||
955 0010 014A ldr r2, .L53
|
||
956 0012 42F82030 str r3, [r2, r0, lsl #2]
|
||
957 .LVL57:
|
||
958 .L51:
|
||
1974:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
959 .loc 2 1974 43 view .LVU271
|
||
960 .LBE107:
|
||
961 .LBE106:
|
||
391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
962 .loc 1 391 1 view .LVU272
|
||
963 0016 7047 bx lr
|
||
964 .L54:
|
||
965 .align 2
|
||
966 .L53:
|
||
967 0018 00E100E0 .word -536813312
|
||
968 .cfi_endproc
|
||
969 .LFE152:
|
||
971 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
|
||
972 .align 1
|
||
973 .global HAL_NVIC_GetPendingIRQ
|
||
974 .syntax unified
|
||
975 .thumb
|
||
976 .thumb_func
|
||
977 .fpu fpv5-d16
|
||
979 HAL_NVIC_GetPendingIRQ:
|
||
980 .LVL58:
|
||
981 .LFB153:
|
||
392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||
395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt).
|
||
396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number.
|
||
397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval status - 0 Interrupt status is not pending.
|
||
400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * - 1 Interrupt status is pending.
|
||
401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||
403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
982 .loc 1 403 1 is_stmt 1 view -0
|
||
983 .cfi_startproc
|
||
984 @ args = 0, pretend = 0, frame = 0
|
||
985 @ frame_needed = 0, uses_anonymous_args = 0
|
||
986 @ link register save eliminated.
|
||
404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
987 .loc 1 405 3 view .LVU274
|
||
406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Return 1 if pending else 0 */
|
||
408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn);
|
||
988 .loc 1 408 3 view .LVU275
|
||
989 .LBB108:
|
||
990 .LBI108:
|
||
ARM GAS /tmp/ccV0GlXv.s page 88
|
||
|
||
|
||
1951:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
991 .loc 2 1951 26 view .LVU276
|
||
992 .LBB109:
|
||
1953:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
993 .loc 2 1953 3 view .LVU277
|
||
1953:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
994 .loc 2 1953 6 is_stmt 0 view .LVU278
|
||
995 0000 0028 cmp r0, #0
|
||
996 .LVL59:
|
||
1953:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
997 .loc 2 1953 6 view .LVU279
|
||
998 0002 0BDB blt .L57
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
999 .loc 2 1955 5 is_stmt 1 view .LVU280
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1000 .loc 2 1955 54 is_stmt 0 view .LVU281
|
||
1001 0004 4309 lsrs r3, r0, #5
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1002 .loc 2 1955 35 view .LVU282
|
||
1003 0006 4033 adds r3, r3, #64
|
||
1004 0008 054A ldr r2, .L58
|
||
1005 000a 52F82330 ldr r3, [r2, r3, lsl #2]
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1006 .loc 2 1955 91 view .LVU283
|
||
1007 000e 00F01F00 and r0, r0, #31
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1008 .loc 2 1955 103 view .LVU284
|
||
1009 0012 23FA00F0 lsr r0, r3, r0
|
||
1955:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1010 .loc 2 1955 12 view .LVU285
|
||
1011 0016 00F00100 and r0, r0, #1
|
||
1012 001a 7047 bx lr
|
||
1013 .L57:
|
||
1959:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1014 .loc 2 1959 11 view .LVU286
|
||
1015 001c 0020 movs r0, #0
|
||
1016 .LVL60:
|
||
1959:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1017 .loc 2 1959 11 view .LVU287
|
||
1018 .LBE109:
|
||
1019 .LBE108:
|
||
409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1020 .loc 1 409 1 view .LVU288
|
||
1021 001e 7047 bx lr
|
||
1022 .L59:
|
||
1023 .align 2
|
||
1024 .L58:
|
||
1025 0020 00E100E0 .word -536813312
|
||
1026 .cfi_endproc
|
||
1027 .LFE153:
|
||
1029 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
|
||
1030 .align 1
|
||
1031 .global HAL_NVIC_ClearPendingIRQ
|
||
1032 .syntax unified
|
||
1033 .thumb
|
||
1034 .thumb_func
|
||
1035 .fpu fpv5-d16
|
||
ARM GAS /tmp/ccV0GlXv.s page 89
|
||
|
||
|
||
1037 HAL_NVIC_ClearPendingIRQ:
|
||
1038 .LVL61:
|
||
1039 .LFB154:
|
||
410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt.
|
||
413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number.
|
||
414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||
419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
1040 .loc 1 419 1 is_stmt 1 view -0
|
||
1041 .cfi_startproc
|
||
1042 @ args = 0, pretend = 0, frame = 0
|
||
1043 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1044 @ link register save eliminated.
|
||
420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
1045 .loc 1 421 3 view .LVU290
|
||
422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Clear pending interrupt */
|
||
424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn);
|
||
1046 .loc 1 424 3 view .LVU291
|
||
1047 .LBB110:
|
||
1048 .LBI110:
|
||
1985:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1049 .loc 2 1985 22 view .LVU292
|
||
1050 .LBB111:
|
||
1987:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1051 .loc 2 1987 3 view .LVU293
|
||
1987:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1052 .loc 2 1987 6 is_stmt 0 view .LVU294
|
||
1053 0000 0028 cmp r0, #0
|
||
1054 .LVL62:
|
||
1987:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1055 .loc 2 1987 6 view .LVU295
|
||
1056 0002 08DB blt .L60
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1057 .loc 2 1989 5 is_stmt 1 view .LVU296
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1058 .loc 2 1989 81 is_stmt 0 view .LVU297
|
||
1059 0004 00F01F02 and r2, r0, #31
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1060 .loc 2 1989 34 view .LVU298
|
||
1061 0008 4009 lsrs r0, r0, #5
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1062 .loc 2 1989 45 view .LVU299
|
||
1063 000a 0123 movs r3, #1
|
||
1064 000c 9340 lsls r3, r3, r2
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1065 .loc 2 1989 43 view .LVU300
|
||
1066 000e 6030 adds r0, r0, #96
|
||
1067 0010 014A ldr r2, .L62
|
||
1068 0012 42F82030 str r3, [r2, r0, lsl #2]
|
||
1069 .LVL63:
|
||
ARM GAS /tmp/ccV0GlXv.s page 90
|
||
|
||
|
||
1070 .L60:
|
||
1989:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1071 .loc 2 1989 43 view .LVU301
|
||
1072 .LBE111:
|
||
1073 .LBE110:
|
||
425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1074 .loc 1 425 1 view .LVU302
|
||
1075 0016 7047 bx lr
|
||
1076 .L63:
|
||
1077 .align 2
|
||
1078 .L62:
|
||
1079 0018 00E100E0 .word -536813312
|
||
1080 .cfi_endproc
|
||
1081 .LFE154:
|
||
1083 .section .text.HAL_NVIC_GetActive,"ax",%progbits
|
||
1084 .align 1
|
||
1085 .global HAL_NVIC_GetActive
|
||
1086 .syntax unified
|
||
1087 .thumb
|
||
1088 .thumb_func
|
||
1089 .fpu fpv5-d16
|
||
1091 HAL_NVIC_GetActive:
|
||
1092 .LVL64:
|
||
1093 .LFB155:
|
||
426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||
429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number
|
||
430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
|
||
431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
|
||
432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval status - 0 Interrupt status is not pending.
|
||
433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * - 1 Interrupt status is pending.
|
||
434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||
436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
1094 .loc 1 436 1 is_stmt 1 view -0
|
||
1095 .cfi_startproc
|
||
1096 @ args = 0, pretend = 0, frame = 0
|
||
1097 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1098 @ link register save eliminated.
|
||
437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||
1099 .loc 1 438 3 view .LVU304
|
||
439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Return 1 if active else 0 */
|
||
441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return NVIC_GetActive(IRQn);
|
||
1100 .loc 1 441 3 view .LVU305
|
||
1101 .LBB112:
|
||
1102 .LBI112:
|
||
2002:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1103 .loc 2 2002 26 view .LVU306
|
||
1104 .LBB113:
|
||
2004:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1105 .loc 2 2004 3 view .LVU307
|
||
2004:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1106 .loc 2 2004 6 is_stmt 0 view .LVU308
|
||
1107 0000 0028 cmp r0, #0
|
||
ARM GAS /tmp/ccV0GlXv.s page 91
|
||
|
||
|
||
1108 .LVL65:
|
||
2004:Drivers/CMSIS/Include/core_cm7.h **** {
|
||
1109 .loc 2 2004 6 view .LVU309
|
||
1110 0002 0BDB blt .L66
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1111 .loc 2 2006 5 is_stmt 1 view .LVU310
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1112 .loc 2 2006 54 is_stmt 0 view .LVU311
|
||
1113 0004 4309 lsrs r3, r0, #5
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1114 .loc 2 2006 35 view .LVU312
|
||
1115 0006 8033 adds r3, r3, #128
|
||
1116 0008 054A ldr r2, .L67
|
||
1117 000a 52F82330 ldr r3, [r2, r3, lsl #2]
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1118 .loc 2 2006 91 view .LVU313
|
||
1119 000e 00F01F00 and r0, r0, #31
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1120 .loc 2 2006 103 view .LVU314
|
||
1121 0012 23FA00F0 lsr r0, r3, r0
|
||
2006:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1122 .loc 2 2006 12 view .LVU315
|
||
1123 0016 00F00100 and r0, r0, #1
|
||
1124 001a 7047 bx lr
|
||
1125 .L66:
|
||
2010:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1126 .loc 2 2010 11 view .LVU316
|
||
1127 001c 0020 movs r0, #0
|
||
1128 .LVL66:
|
||
2010:Drivers/CMSIS/Include/core_cm7.h **** }
|
||
1129 .loc 2 2010 11 view .LVU317
|
||
1130 .LBE113:
|
||
1131 .LBE112:
|
||
442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1132 .loc 1 442 1 view .LVU318
|
||
1133 001e 7047 bx lr
|
||
1134 .L68:
|
||
1135 .align 2
|
||
1136 .L67:
|
||
1137 0020 00E100E0 .word -536813312
|
||
1138 .cfi_endproc
|
||
1139 .LFE155:
|
||
1141 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
|
||
1142 .align 1
|
||
1143 .global HAL_SYSTICK_CLKSourceConfig
|
||
1144 .syntax unified
|
||
1145 .thumb
|
||
1146 .thumb_func
|
||
1147 .fpu fpv5-d16
|
||
1149 HAL_SYSTICK_CLKSourceConfig:
|
||
1150 .LVL67:
|
||
1151 .LFB156:
|
||
443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Configures the SysTick clock source.
|
||
446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source.
|
||
447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values:
|
||
ARM GAS /tmp/ccV0GlXv.s page 92
|
||
|
||
|
||
448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock
|
||
449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||
450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||
453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
1152 .loc 1 453 1 is_stmt 1 view -0
|
||
1153 .cfi_startproc
|
||
1154 @ args = 0, pretend = 0, frame = 0
|
||
1155 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1156 @ link register save eliminated.
|
||
454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */
|
||
455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||
1157 .loc 1 455 3 view .LVU320
|
||
456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||
1158 .loc 1 456 3 view .LVU321
|
||
1159 .loc 1 456 6 is_stmt 0 view .LVU322
|
||
1160 0000 0428 cmp r0, #4
|
||
1161 0002 06D0 beq .L72
|
||
457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||
459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** else
|
||
461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||
1162 .loc 1 462 5 is_stmt 1 view .LVU323
|
||
1163 .loc 1 462 19 is_stmt 0 view .LVU324
|
||
1164 0004 4FF0E022 mov r2, #-536813568
|
||
1165 0008 1369 ldr r3, [r2, #16]
|
||
1166 000a 23F00403 bic r3, r3, #4
|
||
1167 000e 1361 str r3, [r2, #16]
|
||
463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1168 .loc 1 464 1 view .LVU325
|
||
1169 0010 7047 bx lr
|
||
1170 .L72:
|
||
458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1171 .loc 1 458 5 is_stmt 1 view .LVU326
|
||
458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1172 .loc 1 458 19 is_stmt 0 view .LVU327
|
||
1173 0012 4FF0E022 mov r2, #-536813568
|
||
1174 0016 1369 ldr r3, [r2, #16]
|
||
1175 0018 43F00403 orr r3, r3, #4
|
||
1176 001c 1361 str r3, [r2, #16]
|
||
1177 001e 7047 bx lr
|
||
1178 .cfi_endproc
|
||
1179 .LFE156:
|
||
1181 .section .text.HAL_SYSTICK_Callback,"ax",%progbits
|
||
1182 .align 1
|
||
1183 .weak HAL_SYSTICK_Callback
|
||
1184 .syntax unified
|
||
1185 .thumb
|
||
1186 .thumb_func
|
||
1187 .fpu fpv5-d16
|
||
1189 HAL_SYSTICK_Callback:
|
||
1190 .LFB158:
|
||
465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
ARM GAS /tmp/ccV0GlXv.s page 93
|
||
|
||
|
||
466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request.
|
||
468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
|
||
471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_Callback();
|
||
473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief SYSTICK callback.
|
||
477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None
|
||
478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
|
||
480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
1191 .loc 1 480 1 is_stmt 1 view -0
|
||
1192 .cfi_startproc
|
||
1193 @ args = 0, pretend = 0, frame = 0
|
||
1194 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1195 @ link register save eliminated.
|
||
481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed,
|
||
482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file
|
||
483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1196 .loc 1 484 1 view .LVU329
|
||
1197 0000 7047 bx lr
|
||
1198 .cfi_endproc
|
||
1199 .LFE158:
|
||
1201 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits
|
||
1202 .align 1
|
||
1203 .global HAL_SYSTICK_IRQHandler
|
||
1204 .syntax unified
|
||
1205 .thumb
|
||
1206 .thumb_func
|
||
1207 .fpu fpv5-d16
|
||
1209 HAL_SYSTICK_IRQHandler:
|
||
1210 .LFB157:
|
||
471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_Callback();
|
||
1211 .loc 1 471 1 view -0
|
||
1212 .cfi_startproc
|
||
1213 @ args = 0, pretend = 0, frame = 0
|
||
1214 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1215 0000 08B5 push {r3, lr}
|
||
1216 .LCFI2:
|
||
1217 .cfi_def_cfa_offset 8
|
||
1218 .cfi_offset 3, -8
|
||
1219 .cfi_offset 14, -4
|
||
472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1220 .loc 1 472 3 view .LVU331
|
||
1221 0002 FFF7FEFF bl HAL_SYSTICK_Callback
|
||
1222 .LVL68:
|
||
473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
1223 .loc 1 473 1 is_stmt 0 view .LVU332
|
||
1224 0006 08BD pop {r3, pc}
|
||
1225 .cfi_endproc
|
||
1226 .LFE157:
|
||
1228 .section .text.HAL_GetCurrentCPUID,"ax",%progbits
|
||
ARM GAS /tmp/ccV0GlXv.s page 94
|
||
|
||
|
||
1229 .align 1
|
||
1230 .global HAL_GetCurrentCPUID
|
||
1231 .syntax unified
|
||
1232 .thumb
|
||
1233 .thumb_func
|
||
1234 .fpu fpv5-d16
|
||
1236 HAL_GetCurrentCPUID:
|
||
1237 .LFB159:
|
||
485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #if defined(DUAL_CORE)
|
||
487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Returns the current CPU ID.
|
||
490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval CPU identifier
|
||
491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_GetCurrentCPUID(void)
|
||
493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
|
||
495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return CM7_CPUID;
|
||
497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** else
|
||
499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return CM4_CPUID;
|
||
501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #else
|
||
505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c ****
|
||
506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /**
|
||
507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Returns the current CPU ID.
|
||
508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval CPU identifier
|
||
509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */
|
||
510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_GetCurrentCPUID(void)
|
||
511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** {
|
||
1238 .loc 1 511 1 is_stmt 1 view -0
|
||
1239 .cfi_startproc
|
||
1240 @ args = 0, pretend = 0, frame = 0
|
||
1241 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1242 @ link register save eliminated.
|
||
512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return CM7_CPUID;
|
||
1243 .loc 1 512 3 view .LVU334
|
||
513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** }
|
||
1244 .loc 1 513 1 is_stmt 0 view .LVU335
|
||
1245 0000 0320 movs r0, #3
|
||
1246 0002 7047 bx lr
|
||
1247 .cfi_endproc
|
||
1248 .LFE159:
|
||
1250 .text
|
||
1251 .Letext0:
|
||
1252 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h"
|
||
1253 .file 5 "/usr/arm-none-eabi/include/machine/_default_types.h"
|
||
1254 .file 6 "/usr/arm-none-eabi/include/sys/_stdint.h"
|
||
1255 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h"
|
||
ARM GAS /tmp/ccV0GlXv.s page 95
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:0000000000000000 stm32h7xx_hal_cortex.c
|
||
/tmp/ccV0GlXv.s:17 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:25 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping
|
||
/tmp/ccV0GlXv.s:81 .text.HAL_NVIC_SetPriorityGrouping:000000000000001c $d
|
||
/tmp/ccV0GlXv.s:87 .text.HAL_NVIC_SetPriority:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:94 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
|
||
/tmp/ccV0GlXv.s:233 .text.HAL_NVIC_SetPriority:0000000000000060 $d
|
||
/tmp/ccV0GlXv.s:240 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:247 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
|
||
/tmp/ccV0GlXv.s:288 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d
|
||
/tmp/ccV0GlXv.s:293 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:300 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
|
||
/tmp/ccV0GlXv.s:371 .text.HAL_NVIC_DisableIRQ:0000000000000020 $d
|
||
/tmp/ccV0GlXv.s:376 .text.HAL_NVIC_SystemReset:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:383 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
|
||
/tmp/ccV0GlXv.s:449 .text.HAL_NVIC_SystemReset:000000000000001c $d
|
||
/tmp/ccV0GlXv.s:457 .text.HAL_SYSTICK_Config:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:464 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
|
||
/tmp/ccV0GlXv.s:529 .text.HAL_SYSTICK_Config:0000000000000024 $d
|
||
/tmp/ccV0GlXv.s:534 .text.HAL_MPU_Disable:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:541 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable
|
||
/tmp/ccV0GlXv.s:577 .text.HAL_MPU_Disable:0000000000000018 $d
|
||
/tmp/ccV0GlXv.s:582 .text.HAL_MPU_Enable:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:589 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable
|
||
/tmp/ccV0GlXv.s:642 .text.HAL_MPU_Enable:000000000000001c $d
|
||
/tmp/ccV0GlXv.s:647 .text.HAL_MPU_ConfigRegion:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:654 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion
|
||
/tmp/ccV0GlXv.s:743 .text.HAL_MPU_ConfigRegion:000000000000005c $d
|
||
/tmp/ccV0GlXv.s:748 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:755 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping
|
||
/tmp/ccV0GlXv.s:779 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d
|
||
/tmp/ccV0GlXv.s:784 .text.HAL_NVIC_GetPriority:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:791 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
|
||
/tmp/ccV0GlXv.s:910 .text.HAL_NVIC_GetPriority:0000000000000054 $d
|
||
/tmp/ccV0GlXv.s:918 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:925 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
|
||
/tmp/ccV0GlXv.s:967 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d
|
||
/tmp/ccV0GlXv.s:972 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:979 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
|
||
/tmp/ccV0GlXv.s:1025 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d
|
||
/tmp/ccV0GlXv.s:1030 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:1037 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
|
||
/tmp/ccV0GlXv.s:1079 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d
|
||
/tmp/ccV0GlXv.s:1084 .text.HAL_NVIC_GetActive:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:1091 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive
|
||
/tmp/ccV0GlXv.s:1137 .text.HAL_NVIC_GetActive:0000000000000020 $d
|
||
/tmp/ccV0GlXv.s:1142 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:1149 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
|
||
/tmp/ccV0GlXv.s:1182 .text.HAL_SYSTICK_Callback:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:1189 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
|
||
/tmp/ccV0GlXv.s:1202 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:1209 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler
|
||
/tmp/ccV0GlXv.s:1229 .text.HAL_GetCurrentCPUID:0000000000000000 $t
|
||
/tmp/ccV0GlXv.s:1236 .text.HAL_GetCurrentCPUID:0000000000000000 HAL_GetCurrentCPUID
|
||
|
||
NO UNDEFINED SYMBOLS
|
||
ARM GAS /tmp/ccV0GlXv.s page 96
|
||
|
||
|