5672 lines
386 KiB
Plaintext
5672 lines
386 KiB
Plaintext
ARM GAS /tmp/ccMGXY28.s page 1
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1 .cpu cortex-m7
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2 .eabi_attribute 28, 1
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3 .eabi_attribute 20, 1
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4 .eabi_attribute 21, 1
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5 .eabi_attribute 23, 3
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6 .eabi_attribute 24, 1
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7 .eabi_attribute 25, 1
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8 .eabi_attribute 26, 1
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9 .eabi_attribute 30, 1
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10 .eabi_attribute 34, 1
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11 .eabi_attribute 18, 4
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12 .file "stm32h7xx_hal_pwr_ex.c"
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13 .text
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14 .Ltext0:
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15 .cfi_sections .debug_frame
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16 .section .text.HAL_PWREx_ConfigSupply,"ax",%progbits
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17 .align 1
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18 .global HAL_PWREx_ConfigSupply
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19 .arch armv7e-m
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20 .syntax unified
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21 .thumb
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22 .thumb_func
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23 .fpu fpv5-d16
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25 HAL_PWREx_ConfigSupply:
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26 .LVL0:
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27 .LFB141:
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28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c"
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1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
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2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ******************************************************************************
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3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @file stm32h7xx_hal_pwr_ex.c
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4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @author MCD Application Team
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5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver.
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6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following
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7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * functionalities of PWR extension peripheral:
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8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + Peripheral Extended features functions
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9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
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10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ==============================================================================
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11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### How to use this driver #####
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12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ==============================================================================
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13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
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14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
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15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** with the following different setups according to hardware (support SMPS):
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16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_DIRECT_SMPS_SUPPLY
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17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_1V8_SUPPLIES_LDO
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18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_2V5_SUPPLIES_LDO
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19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
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20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
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21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_1V8_SUPPLIES_EXT
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22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_2V5_SUPPLIES_EXT
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23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_LDO_SUPPLY
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24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_EXTERNAL_SOURCE_SUPPLY
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25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
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27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
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29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** internal regulator output voltage. The voltage scaling could be one of
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30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the following scales :
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ARM GAS /tmp/ccMGXY28.s page 2
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31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE0
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32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE1
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33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE2
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34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE3
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35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
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37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** voltage applied to the main regulator.
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38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
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40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** main internal regulator output voltage in STOP mode. The voltage scaling
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41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in STOP mode could be one of the following scales :
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42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_SVOS_SCALE3
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43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_SVOS_SCALE4
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44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_SVOS_SCALE5
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45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
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47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** output voltage applied to the main regulator in STOP mode.
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48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
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50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** with core domain in D2STOP mode. This API is used only for STM32H7Axxx
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51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** and STM32H7Bxxx devices.
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52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Please ensure to clear all CPU pending events by calling
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53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
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54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in DEEP-SLEEP mode with __WFE() entry.
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55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
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57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** DSTOP mode. Call this API with all available power domains to enter the
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58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** system in STOP mode.
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59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Please ensure to clear all CPU pending events by calling
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60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
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61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in DEEP-SLEEP mode with __WFE() entry.
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62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
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64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
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65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
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67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in DSTANDBY mode. Call this API with all available power domains to enter
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68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the system in STANDBY mode.
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69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
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71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (RUN/STOP) when the system enter to low power mode.
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72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
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74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** selected power domain. This API is used only for dual core devices.
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75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
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77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** and release the selected CPU and and their domain peripherals when
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78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** exiting STOP mode. These APIs are used only for dual core devices.
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79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableFlashPowerDown() and
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81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
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82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Flash Power Down in STOP mode.
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83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableMemoryShutOff() and
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85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
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86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** memory block shut-off in DStop or DStop2. These APIs are used only for
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87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** STM32H7Axxx and STM32H7Bxxx lines.
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ARM GAS /tmp/ccMGXY28.s page 3
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88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
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90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to enable and disable the Wake-up pin functionality for
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91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the selected pin.
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92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
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94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to manage wake-up flag for the selected pin.
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95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
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97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** pins interrupts.
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98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
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100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** to enable and disable the backup domain regulator.
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101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
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103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableUSBVoltageDetector() and
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104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
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105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regulation functionnalities.
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106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableBatteryCharging() and
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108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
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109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** battery charging feature with the selected resistor.
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110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableAnalogBooster() and
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112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
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113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** AVD boost feature when the VDD supply voltage is below 2V7.
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114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
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116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to enable and disable the VBAT and Temperature monitoring.
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117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When VBAT and Temperature monitoring feature is enables, use
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118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
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119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** respectively the Temperature level and VBAT level.
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120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
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122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function to get VDDMMC voltage level. This API is used only for
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123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** STM32H7Axxx and STM32H7Bxxx lines
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124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
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126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (event mode and voltage threshold) in order to set up the Analog Voltage
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127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD()
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128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to start and stop the AVD detection.
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129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) AVD level could be one of the following values :
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130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 1V7
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131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 2V1
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132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 2V5
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133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 2V8
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134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
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136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** AVD interrupt request.
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137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
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138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
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139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ******************************************************************************
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140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @attention
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141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
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142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
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143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * All rights reserved.</center></h2>
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144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
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ARM GAS /tmp/ccMGXY28.s page 4
|
||
|
||
|
||
145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This software component is licensed by ST under BSD 3-Clause license,
|
||
146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the "License"; You may not use this file except in compliance with the
|
||
147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * License. You may obtain a copy of the License at:
|
||
148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * opensource.org/licenses/BSD-3-Clause
|
||
149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
|
||
150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ******************************************************************************
|
||
151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/
|
||
154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #include "stm32h7xx_hal.h"
|
||
155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver
|
||
157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx
|
||
161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR Extended HAL module driver
|
||
162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED
|
||
166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/
|
||
168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/
|
||
169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private_Constants
|
||
171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
|
||
175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_MODE_IT (0x00010000U)
|
||
178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_MODE_EVT (0x00020000U)
|
||
179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_RISING_EDGE (0x00000001U)
|
||
180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_FALLING_EDGE (0x00000002U)
|
||
181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_RISING_FALLING_EDGE (0x00000003U)
|
||
182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
|
||
187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_FLAG_SETTING_DELAY (1000U)
|
||
190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
|
||
195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wake-Up Pins EXTI register mask */
|
||
198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (EXTI_IMR2_IM57)
|
||
199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
|
||
200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
|
||
201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
|
||
ARM GAS /tmp/ccMGXY28.s page 5
|
||
|
||
|
||
202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
|
||
203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
|
||
204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EXTI_IMR2_IM58 | EXTI_IMR2_IM60)
|
||
205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (EXTI_IMR2_IM57) */
|
||
206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wake-Up Pins PWR Pin Pull shift offsets */
|
||
208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
|
||
209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/
|
||
218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/
|
||
219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/
|
||
220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private functions ---------------------------------------------------------*/
|
||
221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Exported types ------------------------------------------------------------*/
|
||
222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Exported functions --------------------------------------------------------*/
|
||
223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||
225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
|
||
229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Power supply control functions
|
||
230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
|
||
231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
|
||
232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Power supply control functions #####
|
||
234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
|
||
237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** above the POR threshold level, the voltage regulator is enabled in the
|
||
238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** default supply configuration:
|
||
239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The Voltage converter output level is set at 1V0 in accordance with
|
||
240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the VOS3 level configured in PWR (D3/SRD) domain control register
|
||
241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_D3CR/PWR_SRDCR).
|
||
242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The system is kept in reset mode as long as VCORE is not ok.
|
||
243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Once VCORE is ok, the system is taken out of reset and the HSI
|
||
244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** oscillator is enabled.
|
||
245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Once the oscillator is stable, the system is initialized: Flash memory
|
||
246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** and option bytes are loaded and the CPU starts in Run* mode.
|
||
247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The software shall then initialize the system including supply
|
||
248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** configuration programming using the HAL_PWREx_ConfigSupply().
|
||
249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Once the supply configuration has been configured, the
|
||
250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
|
||
251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** control status register 1 (PWR_CSR1) to guarantee a valid voltage
|
||
252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** levels:
|
||
253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
|
||
254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** system is in limited Run* mode, write accesses to the RAMs are not
|
||
255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** permitted and VOS shall not be changed.
|
||
256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
|
||
257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** is in normal Run mode, write accesses to RAMs are allowed and VOS
|
||
258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** can be changed.
|
||
ARM GAS /tmp/ccMGXY28.s page 6
|
||
|
||
|
||
259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
|
||
261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the system Power Supply.
|
||
266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param SupplySource : Specifies the Power Supply source to set after a
|
||
267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * system startup.
|
||
268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values :
|
||
269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
|
||
270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains. The LDO is Bypassed.
|
||
271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
|
||
272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the LDO. The Vcore Power Domains
|
||
273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the LDO.
|
||
274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
|
||
275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the LDO. The Vcore Power Domains
|
||
276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the LDO.
|
||
277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
|
||
278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * supplies external
|
||
279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * circuits and the LDO.
|
||
280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * The Vcore Power Domains
|
||
281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the
|
||
282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * LDO.
|
||
283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
|
||
284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * supplies external
|
||
285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * circuits and the LDO.
|
||
286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * The Vcore Power Domains
|
||
287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the
|
||
288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * LDO.
|
||
289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
|
||
290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external circuits. The LDO is
|
||
291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Bypassed. The Vcore Power
|
||
292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains are supplied from
|
||
293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external source.
|
||
294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
|
||
295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external circuits. The LDO is
|
||
296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Bypassed. The Vcore Power
|
||
297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains are supplied from
|
||
298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external source.
|
||
299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
|
||
300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains. The SMPS regulator is Bypassed.
|
||
301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
|
||
302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Bypassed. The Vcore Power
|
||
303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains are supplied from
|
||
304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external source.
|
||
305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
|
||
306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * H7 lines.
|
||
307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
|
||
308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
|
||
309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
|
||
310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
|
||
311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator.
|
||
312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
|
||
315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 7
|
||
|
||
|
||
29 .loc 1 315 1 view -0
|
||
30 .cfi_startproc
|
||
31 @ args = 0, pretend = 0, frame = 0
|
||
32 @ frame_needed = 0, uses_anonymous_args = 0
|
||
316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
33 .loc 1 316 3 view .LVU1
|
||
317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_SUPPLY (SupplySource));
|
||
34 .loc 1 319 3 view .LVU2
|
||
320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if supply source was configured */
|
||
322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_FLAG_SCUEN)
|
||
323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
|
||
35 .loc 1 323 3 view .LVU3
|
||
36 .loc 1 323 7 is_stmt 0 view .LVU4
|
||
37 0000 134B ldr r3, .L12
|
||
38 0002 DB68 ldr r3, [r3, #12]
|
||
39 .loc 1 323 6 view .LVU5
|
||
40 0004 13F0040F tst r3, #4
|
||
41 0008 07D1 bne .L2
|
||
324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
|
||
325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_L
|
||
326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_FLAG_SCUEN) */
|
||
327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check supply configuration */
|
||
329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
|
||
42 .loc 1 329 5 is_stmt 1 view .LVU6
|
||
43 .loc 1 329 13 is_stmt 0 view .LVU7
|
||
44 000a 114B ldr r3, .L12
|
||
45 000c DB68 ldr r3, [r3, #12]
|
||
46 .loc 1 329 19 view .LVU8
|
||
47 000e 03F00703 and r3, r3, #7
|
||
48 .loc 1 329 8 view .LVU9
|
||
49 0012 8342 cmp r3, r0
|
||
50 0014 1AD0 beq .L6
|
||
330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Supply configuration update locked, can't apply a new supply config */
|
||
332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
51 .loc 1 332 14 view .LVU10
|
||
52 0016 0120 movs r0, #1
|
||
53 .LVL1:
|
||
54 .loc 1 332 14 view .LVU11
|
||
55 0018 7047 bx lr
|
||
56 .LVL2:
|
||
57 .L2:
|
||
315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
58 .loc 1 315 1 view .LVU12
|
||
59 001a 10B5 push {r4, lr}
|
||
60 .LCFI0:
|
||
61 .cfi_def_cfa_offset 8
|
||
62 .cfi_offset 4, -8
|
||
63 .cfi_offset 14, -4
|
||
333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Supply configuration update locked, but new supply configuration
|
||
ARM GAS /tmp/ccMGXY28.s page 8
|
||
|
||
|
||
337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** matches with old supply configuration : nothing to do
|
||
338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the power supply configuration */
|
||
344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
|
||
64 .loc 1 344 3 is_stmt 1 view .LVU13
|
||
65 001c 0C4A ldr r2, .L12
|
||
66 001e D368 ldr r3, [r2, #12]
|
||
67 0020 23F00703 bic r3, r3, #7
|
||
68 0024 1843 orrs r0, r0, r3
|
||
69 .LVL3:
|
||
70 .loc 1 344 3 is_stmt 0 view .LVU14
|
||
71 0026 D060 str r0, [r2, #12]
|
||
345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
72 .loc 1 347 3 is_stmt 1 view .LVU15
|
||
73 .loc 1 347 15 is_stmt 0 view .LVU16
|
||
74 0028 FFF7FEFF bl HAL_GetTick
|
||
75 .LVL4:
|
||
76 002c 0446 mov r4, r0
|
||
77 .LVL5:
|
||
348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */
|
||
350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
|
||
78 .loc 1 350 3 is_stmt 1 view .LVU17
|
||
79 .L4:
|
||
80 .loc 1 350 9 view .LVU18
|
||
81 .loc 1 350 10 is_stmt 0 view .LVU19
|
||
82 002e 084B ldr r3, .L12
|
||
83 0030 5B68 ldr r3, [r3, #4]
|
||
84 .loc 1 350 9 view .LVU20
|
||
85 0032 13F4005F tst r3, #8192
|
||
86 0036 07D1 bne .L11
|
||
351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
|
||
87 .loc 1 352 5 is_stmt 1 view .LVU21
|
||
88 .loc 1 352 10 is_stmt 0 view .LVU22
|
||
89 0038 FFF7FEFF bl HAL_GetTick
|
||
90 .LVL6:
|
||
91 .loc 1 352 25 view .LVU23
|
||
92 003c 001B subs r0, r0, r4
|
||
93 .loc 1 352 8 view .LVU24
|
||
94 003e B0F57A7F cmp r0, #1000
|
||
95 0042 F4D9 bls .L4
|
||
353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
96 .loc 1 354 14 view .LVU25
|
||
97 0044 0120 movs r0, #1
|
||
98 0046 00E0 b .L3
|
||
99 .L11:
|
||
355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
ARM GAS /tmp/ccMGXY28.s page 9
|
||
|
||
|
||
358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (SMPS)
|
||
359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
|
||
360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
|
||
361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
|
||
362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) ||
|
||
363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
|
||
364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get the current tick number */
|
||
366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till SMPS external supply ready flag is set */
|
||
369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
|
||
370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
|
||
372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (SMPS) */
|
||
378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
100 .loc 1 379 10 view .LVU26
|
||
101 0048 0020 movs r0, #0
|
||
102 .L3:
|
||
380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
103 .loc 1 380 1 view .LVU27
|
||
104 004a 10BD pop {r4, pc}
|
||
105 .LVL7:
|
||
106 .L6:
|
||
107 .LCFI1:
|
||
108 .cfi_def_cfa_offset 0
|
||
109 .cfi_restore 4
|
||
110 .cfi_restore 14
|
||
339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
111 .loc 1 339 14 view .LVU28
|
||
112 004c 0020 movs r0, #0
|
||
113 .LVL8:
|
||
114 .loc 1 380 1 view .LVU29
|
||
115 004e 7047 bx lr
|
||
116 .L13:
|
||
117 .align 2
|
||
118 .L12:
|
||
119 0050 00480258 .word 1476544512
|
||
120 .cfi_endproc
|
||
121 .LFE141:
|
||
123 .section .text.HAL_PWREx_GetSupplyConfig,"ax",%progbits
|
||
124 .align 1
|
||
125 .global HAL_PWREx_GetSupplyConfig
|
||
126 .syntax unified
|
||
127 .thumb
|
||
128 .thumb_func
|
||
129 .fpu fpv5-d16
|
||
131 HAL_PWREx_GetSupplyConfig:
|
||
132 .LFB142:
|
||
381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
ARM GAS /tmp/ccMGXY28.s page 10
|
||
|
||
|
||
383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the power supply configuration.
|
||
384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The supply configuration.
|
||
385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetSupplyConfig (void)
|
||
387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
133 .loc 1 387 1 is_stmt 1 view -0
|
||
134 .cfi_startproc
|
||
135 @ args = 0, pretend = 0, frame = 0
|
||
136 @ frame_needed = 0, uses_anonymous_args = 0
|
||
137 @ link register save eliminated.
|
||
388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
|
||
138 .loc 1 388 3 view .LVU31
|
||
139 .loc 1 388 14 is_stmt 0 view .LVU32
|
||
140 0000 024B ldr r3, .L15
|
||
141 0002 D868 ldr r0, [r3, #12]
|
||
389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
142 .loc 1 389 1 view .LVU33
|
||
143 0004 00F00700 and r0, r0, #7
|
||
144 0008 7047 bx lr
|
||
145 .L16:
|
||
146 000a 00BF .align 2
|
||
147 .L15:
|
||
148 000c 00480258 .word 1476544512
|
||
149 .cfi_endproc
|
||
150 .LFE142:
|
||
152 .section .text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits
|
||
153 .align 1
|
||
154 .global HAL_PWREx_ControlVoltageScaling
|
||
155 .syntax unified
|
||
156 .thumb
|
||
157 .thumb_func
|
||
158 .fpu fpv5-d16
|
||
160 HAL_PWREx_ControlVoltageScaling:
|
||
161 .LVL9:
|
||
162 .LFB143:
|
||
390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the main internal regulator output voltage.
|
||
393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param VoltageScaling : Specifies the regulator output voltage to achieve
|
||
394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * a tradeoff between performance and power
|
||
395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * consumption.
|
||
396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values :
|
||
397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
|
||
398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Scale 0 mode.
|
||
399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
|
||
400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * range 1 mode.
|
||
401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
|
||
402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * range 2 mode.
|
||
403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
|
||
404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * range 3 mode.
|
||
405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
|
||
406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * only possible when Vcore is supplied from LDO (Low DropOut). The
|
||
407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
|
||
408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * macro before configuring Voltage Scale 0.
|
||
409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * To enter low power mode , and if current regulator voltage is
|
||
410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Voltage Scale 0 then first switch to Voltage Scale 1 before entering
|
||
411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * low power mode.
|
||
ARM GAS /tmp/ccMGXY28.s page 11
|
||
|
||
|
||
412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL Status
|
||
413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
|
||
415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
163 .loc 1 415 1 is_stmt 1 view -0
|
||
164 .cfi_startproc
|
||
165 @ args = 0, pretend = 0, frame = 0
|
||
166 @ frame_needed = 0, uses_anonymous_args = 0
|
||
167 .loc 1 415 1 is_stmt 0 view .LVU35
|
||
168 0000 38B5 push {r3, r4, r5, lr}
|
||
169 .LCFI2:
|
||
170 .cfi_def_cfa_offset 16
|
||
171 .cfi_offset 3, -16
|
||
172 .cfi_offset 4, -12
|
||
173 .cfi_offset 5, -8
|
||
174 .cfi_offset 14, -4
|
||
416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
175 .loc 1 416 3 is_stmt 1 view .LVU36
|
||
417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
|
||
176 .loc 1 419 3 view .LVU37
|
||
420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get the voltage scaling */
|
||
422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
|
||
177 .loc 1 422 3 view .LVU38
|
||
178 .loc 1 422 11 is_stmt 0 view .LVU39
|
||
179 0002 324B ldr r3, .L38
|
||
180 0004 5B68 ldr r3, [r3, #4]
|
||
181 .loc 1 422 18 view .LVU40
|
||
182 0006 03F44043 and r3, r3, #49152
|
||
183 .loc 1 422 6 view .LVU41
|
||
184 000a 8342 cmp r3, r0
|
||
185 000c 5CD0 beq .L28
|
||
186 000e 0446 mov r4, r0
|
||
423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Old and new voltage scaling configuration match : nothing to do */
|
||
425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_SRDCR_VOS)
|
||
429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */
|
||
430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
|
||
431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
|
||
432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
|
||
433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
|
||
187 .loc 1 433 3 is_stmt 1 view .LVU42
|
||
188 .loc 1 433 6 is_stmt 0 view .LVU43
|
||
189 0010 08BB cbnz r0, .L19
|
||
434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
|
||
190 .loc 1 435 5 is_stmt 1 view .LVU44
|
||
191 .loc 1 435 13 is_stmt 0 view .LVU45
|
||
192 0012 2E4B ldr r3, .L38
|
||
193 0014 DB68 ldr r3, [r3, #12]
|
||
194 .loc 1 435 8 view .LVU46
|
||
195 0016 13F0020F tst r3, #2
|
||
ARM GAS /tmp/ccMGXY28.s page 12
|
||
|
||
|
||
196 001a 01D1 bne .L34
|
||
436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */
|
||
438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
||
439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */
|
||
444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
|
||
445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
|
||
447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the PWR overdrive */
|
||
453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
|
||
454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* The voltage scale 0 is only possible when LDO regulator is enabled */
|
||
458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
197 .loc 1 458 14 view .LVU47
|
||
198 001c 0120 movs r0, #1
|
||
199 .LVL10:
|
||
200 .loc 1 458 14 view .LVU48
|
||
201 001e 52E0 b .L18
|
||
202 .LVL11:
|
||
203 .L34:
|
||
438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
204 .loc 1 438 7 is_stmt 1 view .LVU49
|
||
205 0020 2A4A ldr r2, .L38
|
||
206 0022 9369 ldr r3, [r2, #24]
|
||
207 0024 43F44043 orr r3, r3, #49152
|
||
208 0028 9361 str r3, [r2, #24]
|
||
441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
209 .loc 1 441 7 view .LVU50
|
||
441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
210 .loc 1 441 19 is_stmt 0 view .LVU51
|
||
211 002a FFF7FEFF bl HAL_GetTick
|
||
212 .LVL12:
|
||
441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
213 .loc 1 441 19 view .LVU52
|
||
214 002e 0446 mov r4, r0
|
||
215 .LVL13:
|
||
444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
216 .loc 1 444 7 is_stmt 1 view .LVU53
|
||
217 .L20:
|
||
444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
218 .loc 1 444 13 view .LVU54
|
||
444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
219 .loc 1 444 14 is_stmt 0 view .LVU55
|
||
220 0030 264B ldr r3, .L38
|
||
221 0032 5B68 ldr r3, [r3, #4]
|
||
444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 13
|
||
|
||
|
||
222 .loc 1 444 13 view .LVU56
|
||
223 0034 13F4005F tst r3, #8192
|
||
224 0038 07D1 bne .L35
|
||
446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
225 .loc 1 446 9 is_stmt 1 view .LVU57
|
||
446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
226 .loc 1 446 14 is_stmt 0 view .LVU58
|
||
227 003a FFF7FEFF bl HAL_GetTick
|
||
228 .LVL14:
|
||
446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
229 .loc 1 446 29 view .LVU59
|
||
230 003e 001B subs r0, r0, r4
|
||
446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
231 .loc 1 446 12 view .LVU60
|
||
232 0040 B0F57A7F cmp r0, #1000
|
||
233 0044 F4D9 bls .L20
|
||
448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
234 .loc 1 448 18 view .LVU61
|
||
235 0046 0120 movs r0, #1
|
||
236 0048 3DE0 b .L18
|
||
237 .L35:
|
||
453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
238 .loc 1 453 7 is_stmt 1 view .LVU62
|
||
239 004a 214A ldr r2, .L38+4
|
||
240 004c D36A ldr r3, [r2, #44]
|
||
241 004e 43F00103 orr r3, r3, #1
|
||
242 0052 D362 str r3, [r2, #44]
|
||
243 0054 0CE0 b .L22
|
||
244 .LVL15:
|
||
245 .L19:
|
||
459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
|
||
246 .loc 1 463 5 view .LVU63
|
||
247 .loc 1 463 13 is_stmt 0 view .LVU64
|
||
248 0056 1D4B ldr r3, .L38
|
||
249 0058 5B68 ldr r3, [r3, #4]
|
||
250 .loc 1 463 20 view .LVU65
|
||
251 005a 03F44043 and r3, r3, #49152
|
||
252 .loc 1 463 8 view .LVU66
|
||
253 005e B3F5404F cmp r3, #49152
|
||
254 0062 15D0 beq .L36
|
||
255 .LVL16:
|
||
256 .L23:
|
||
464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
|
||
466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the PWR overdrive */
|
||
468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
|
||
469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */
|
||
474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
|
||
ARM GAS /tmp/ccMGXY28.s page 14
|
||
|
||
|
||
475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
|
||
477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */
|
||
485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
|
||
257 .loc 1 485 5 is_stmt 1 view .LVU67
|
||
258 0064 194B ldr r3, .L38
|
||
259 0066 9869 ldr r0, [r3, #24]
|
||
260 0068 20F44040 bic r0, r0, #49152
|
||
261 006c 0443 orrs r4, r4, r0
|
||
262 .LVL17:
|
||
263 .loc 1 485 5 is_stmt 0 view .LVU68
|
||
264 006e 9C61 str r4, [r3, #24]
|
||
265 .L22:
|
||
486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else /* STM32H72xxx and STM32H73xxx lines */
|
||
488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */
|
||
489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
|
||
490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (SYSCFG_PWRCR_ODEN) */
|
||
491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_SRDCR_VOS) */
|
||
492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
266 .loc 1 494 3 is_stmt 1 view .LVU69
|
||
267 .loc 1 494 15 is_stmt 0 view .LVU70
|
||
268 0070 FFF7FEFF bl HAL_GetTick
|
||
269 .LVL18:
|
||
270 0074 0446 mov r4, r0
|
||
271 .LVL19:
|
||
495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */
|
||
497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
|
||
272 .loc 1 497 3 is_stmt 1 view .LVU71
|
||
273 .L26:
|
||
274 .loc 1 497 9 view .LVU72
|
||
275 .loc 1 497 10 is_stmt 0 view .LVU73
|
||
276 0076 154B ldr r3, .L38
|
||
277 0078 5B68 ldr r3, [r3, #4]
|
||
278 .loc 1 497 9 view .LVU74
|
||
279 007a 13F4005F tst r3, #8192
|
||
280 007e 21D1 bne .L37
|
||
498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
|
||
281 .loc 1 499 5 is_stmt 1 view .LVU75
|
||
282 .loc 1 499 10 is_stmt 0 view .LVU76
|
||
283 0080 FFF7FEFF bl HAL_GetTick
|
||
284 .LVL20:
|
||
285 .loc 1 499 24 view .LVU77
|
||
286 0084 001B subs r0, r0, r4
|
||
287 .loc 1 499 8 view .LVU78
|
||
288 0086 B0F57A7F cmp r0, #1000
|
||
ARM GAS /tmp/ccMGXY28.s page 15
|
||
|
||
|
||
289 008a F4D9 bls .L26
|
||
500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
290 .loc 1 501 14 view .LVU79
|
||
291 008c 0120 movs r0, #1
|
||
292 008e 1AE0 b .L18
|
||
293 .LVL21:
|
||
294 .L36:
|
||
465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
295 .loc 1 465 7 is_stmt 1 view .LVU80
|
||
465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
296 .loc 1 465 18 is_stmt 0 view .LVU81
|
||
297 0090 0F4B ldr r3, .L38+4
|
||
298 0092 DB6A ldr r3, [r3, #44]
|
||
465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
299 .loc 1 465 10 view .LVU82
|
||
300 0094 13F0010F tst r3, #1
|
||
301 0098 E4D0 beq .L23
|
||
468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
302 .loc 1 468 9 is_stmt 1 view .LVU83
|
||
303 009a 0D4A ldr r2, .L38+4
|
||
304 009c D36A ldr r3, [r2, #44]
|
||
305 009e 23F00103 bic r3, r3, #1
|
||
306 00a2 D362 str r3, [r2, #44]
|
||
471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
307 .loc 1 471 9 view .LVU84
|
||
471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
308 .loc 1 471 21 is_stmt 0 view .LVU85
|
||
309 00a4 FFF7FEFF bl HAL_GetTick
|
||
310 .LVL22:
|
||
471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
311 .loc 1 471 21 view .LVU86
|
||
312 00a8 0546 mov r5, r0
|
||
313 .LVL23:
|
||
474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
314 .loc 1 474 9 is_stmt 1 view .LVU87
|
||
315 .L24:
|
||
474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
316 .loc 1 474 15 view .LVU88
|
||
474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
317 .loc 1 474 16 is_stmt 0 view .LVU89
|
||
318 00aa 084B ldr r3, .L38
|
||
319 00ac 5B68 ldr r3, [r3, #4]
|
||
474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
320 .loc 1 474 15 view .LVU90
|
||
321 00ae 13F4005F tst r3, #8192
|
||
322 00b2 D7D1 bne .L23
|
||
476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
323 .loc 1 476 11 is_stmt 1 view .LVU91
|
||
476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
324 .loc 1 476 16 is_stmt 0 view .LVU92
|
||
325 00b4 FFF7FEFF bl HAL_GetTick
|
||
326 .LVL24:
|
||
476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
327 .loc 1 476 31 view .LVU93
|
||
328 00b8 401B subs r0, r0, r5
|
||
476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 16
|
||
|
||
|
||
329 .loc 1 476 14 view .LVU94
|
||
330 00ba B0F57A7F cmp r0, #1000
|
||
331 00be F4D9 bls .L24
|
||
478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
332 .loc 1 478 20 view .LVU95
|
||
333 00c0 0120 movs r0, #1
|
||
334 00c2 00E0 b .L18
|
||
335 .LVL25:
|
||
336 .L37:
|
||
502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
337 .loc 1 505 10 view .LVU96
|
||
338 00c4 0020 movs r0, #0
|
||
339 .LVL26:
|
||
340 .L18:
|
||
506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
341 .loc 1 506 1 view .LVU97
|
||
342 00c6 38BD pop {r3, r4, r5, pc}
|
||
343 .LVL27:
|
||
344 .L28:
|
||
425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
345 .loc 1 425 12 view .LVU98
|
||
346 00c8 0020 movs r0, #0
|
||
347 .LVL28:
|
||
425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
348 .loc 1 425 12 view .LVU99
|
||
349 00ca FCE7 b .L18
|
||
350 .L39:
|
||
351 .align 2
|
||
352 .L38:
|
||
353 00cc 00480258 .word 1476544512
|
||
354 00d0 00040058 .word 1476396032
|
||
355 .cfi_endproc
|
||
356 .LFE143:
|
||
358 .section .text.HAL_PWREx_GetVoltageRange,"ax",%progbits
|
||
359 .align 1
|
||
360 .global HAL_PWREx_GetVoltageRange
|
||
361 .syntax unified
|
||
362 .thumb
|
||
363 .thumb_func
|
||
364 .fpu fpv5-d16
|
||
366 HAL_PWREx_GetVoltageRange:
|
||
367 .LFB144:
|
||
507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the main internal regulator output voltage. Reflecting the last
|
||
510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * VOS value applied to the PMU.
|
||
511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The current applied VOS selection.
|
||
512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange (void)
|
||
514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
368 .loc 1 514 1 is_stmt 1 view -0
|
||
369 .cfi_startproc
|
||
370 @ args = 0, pretend = 0, frame = 0
|
||
371 @ frame_needed = 0, uses_anonymous_args = 0
|
||
ARM GAS /tmp/ccMGXY28.s page 17
|
||
|
||
|
||
372 @ link register save eliminated.
|
||
515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get the active voltage scaling */
|
||
516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->CSR1 & PWR_CSR1_ACTVOS);
|
||
373 .loc 1 516 3 view .LVU101
|
||
374 .loc 1 516 14 is_stmt 0 view .LVU102
|
||
375 0000 024B ldr r3, .L41
|
||
376 0002 5868 ldr r0, [r3, #4]
|
||
517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
377 .loc 1 517 1 view .LVU103
|
||
378 0004 00F44040 and r0, r0, #49152
|
||
379 0008 7047 bx lr
|
||
380 .L42:
|
||
381 000a 00BF .align 2
|
||
382 .L41:
|
||
383 000c 00480258 .word 1476544512
|
||
384 .cfi_endproc
|
||
385 .LFE144:
|
||
387 .section .text.HAL_PWREx_ControlStopModeVoltageScaling,"ax",%progbits
|
||
388 .align 1
|
||
389 .global HAL_PWREx_ControlStopModeVoltageScaling
|
||
390 .syntax unified
|
||
391 .thumb
|
||
392 .thumb_func
|
||
393 .fpu fpv5-d16
|
||
395 HAL_PWREx_ControlStopModeVoltageScaling:
|
||
396 .LVL29:
|
||
397 .LFB145:
|
||
518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the main internal regulator output voltage in STOP mode.
|
||
521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param VoltageScaling : Specifies the regulator output voltage when the
|
||
522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * system enters Stop mode to achieve a tradeoff between performance
|
||
523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * and power consumption.
|
||
524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
|
||
526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * 3 mode.
|
||
527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
|
||
528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * 4 mode.
|
||
529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
|
||
530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * 5 mode.
|
||
531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
|
||
532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator in Low-power (LP) mode to further reduce power consumption.
|
||
533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * When preselecting SVOS3, the use of the voltage regulator low-power
|
||
534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode (LP) can be selected by LPDS register bit.
|
||
535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The selected SVOS4 and SVOS5 levels add an additional startup delay
|
||
536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * when exiting from system Stop mode.
|
||
537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL Status.
|
||
538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
|
||
540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
398 .loc 1 540 1 is_stmt 1 view -0
|
||
399 .cfi_startproc
|
||
400 @ args = 0, pretend = 0, frame = 0
|
||
401 @ frame_needed = 0, uses_anonymous_args = 0
|
||
402 @ link register save eliminated.
|
||
541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
|
||
ARM GAS /tmp/ccMGXY28.s page 18
|
||
|
||
|
||
403 .loc 1 542 3 view .LVU105
|
||
543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Return the stop mode voltage range */
|
||
545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
|
||
404 .loc 1 545 3 view .LVU106
|
||
405 0000 034A ldr r2, .L44
|
||
406 0002 1368 ldr r3, [r2]
|
||
407 0004 23F44043 bic r3, r3, #49152
|
||
408 0008 0343 orrs r3, r3, r0
|
||
409 000a 1360 str r3, [r2]
|
||
546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
410 .loc 1 547 3 view .LVU107
|
||
548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
411 .loc 1 548 1 is_stmt 0 view .LVU108
|
||
412 000c 0020 movs r0, #0
|
||
413 .LVL30:
|
||
414 .loc 1 548 1 view .LVU109
|
||
415 000e 7047 bx lr
|
||
416 .L45:
|
||
417 .align 2
|
||
418 .L44:
|
||
419 0010 00480258 .word 1476544512
|
||
420 .cfi_endproc
|
||
421 .LFE145:
|
||
423 .section .text.HAL_PWREx_GetStopModeVoltageRange,"ax",%progbits
|
||
424 .align 1
|
||
425 .global HAL_PWREx_GetStopModeVoltageRange
|
||
426 .syntax unified
|
||
427 .thumb
|
||
428 .thumb_func
|
||
429 .fpu fpv5-d16
|
||
431 HAL_PWREx_GetStopModeVoltageRange:
|
||
432 .LFB146:
|
||
549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the main internal regulator output voltage in STOP mode.
|
||
552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The actual applied VOS selection.
|
||
553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
|
||
555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
433 .loc 1 555 1 is_stmt 1 view -0
|
||
434 .cfi_startproc
|
||
435 @ args = 0, pretend = 0, frame = 0
|
||
436 @ frame_needed = 0, uses_anonymous_args = 0
|
||
437 @ link register save eliminated.
|
||
556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Return the stop voltage scaling */
|
||
557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->CR1 & PWR_CR1_SVOS);
|
||
438 .loc 1 557 3 view .LVU111
|
||
439 .loc 1 557 14 is_stmt 0 view .LVU112
|
||
440 0000 024B ldr r3, .L47
|
||
441 0002 1868 ldr r0, [r3]
|
||
558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
442 .loc 1 558 1 view .LVU113
|
||
443 0004 00F44040 and r0, r0, #49152
|
||
444 0008 7047 bx lr
|
||
445 .L48:
|
||
ARM GAS /tmp/ccMGXY28.s page 19
|
||
|
||
|
||
446 000a 00BF .align 2
|
||
447 .L47:
|
||
448 000c 00480258 .word 1476544512
|
||
449 .cfi_endproc
|
||
450 .LFE146:
|
||
452 .section .text.HAL_PWREx_EnterSTOPMode,"ax",%progbits
|
||
453 .align 1
|
||
454 .global HAL_PWREx_EnterSTOPMode
|
||
455 .syntax unified
|
||
456 .thumb
|
||
457 .thumb_func
|
||
458 .fpu fpv5-d16
|
||
460 HAL_PWREx_EnterSTOPMode:
|
||
461 .LVL31:
|
||
462 .LFB147:
|
||
559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
|
||
564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Low power control functions
|
||
565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
|
||
566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
|
||
567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Low power control functions #####
|
||
569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Domains Low Power modes configuration ***
|
||
572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================
|
||
573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** This section provides the extended low power mode control APIs.
|
||
575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The system presents 3 principles domains (D1, D2 and D3) that can be
|
||
576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** operated in low-power modes (DSTOP or DSTANDBY mode):
|
||
577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) DSTOP mode to enters a domain to STOP mode:
|
||
579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
|
||
580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** subsystem is in CSTOP mode and has allocated peripheral in the
|
||
581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** domain.
|
||
582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DSTOP mode the domain bus matrix clock is stopped.
|
||
583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) The system enters STOP mode using one of the following scenarios:
|
||
584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
|
||
585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter DSTOP mode.
|
||
586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
|
||
587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter DSTOP mode.
|
||
588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
|
||
589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter DSTOP mode.
|
||
590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
|
||
591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enters DSTOP mode.
|
||
592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
|
||
593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enters DSTOP mode.
|
||
594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
|
||
595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enters DSTOP mode.
|
||
596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1, D2 and D3 domains enter DSTOP mode.
|
||
597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) When the system enters STOP mode, the clocks are stopped and the
|
||
598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regulator is running in main or low power mode.
|
||
599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) D3 domain can be kept in Run mode regardless of the CPU status when
|
||
600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
|
||
ARM GAS /tmp/ccMGXY28.s page 20
|
||
|
||
|
||
601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) DSTANDBY mode to enters a domain to STANDBY mode:
|
||
603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
|
||
604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** register (PWR_CPUCR) for the Dn domain selects Standby mode.
|
||
605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
|
||
606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** DSTANDBY mode. Consequently the VCORE supply regulator is powered
|
||
607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** off.
|
||
608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** DSTOP mode ***
|
||
610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ==================
|
||
611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DStop mode the domain bus matrix clock is stopped.
|
||
613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The Flash memory can enter low-power Stop mode when it is enabled through
|
||
614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
|
||
615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** restart time and low power consumption.
|
||
616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DStop mode domain peripherals using the LSI or LSE clock and
|
||
618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** peripherals having a kernel clock request are still able to operate.
|
||
619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Before entering DSTOP mode it is recommended to call SCB_CleanDCache
|
||
621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function in order to clean the D-Cache and guarantee the data integrity
|
||
622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** for the SRAM memories.
|
||
623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Entry:
|
||
625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
|
||
626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** STOPEntry, Domain) function with:
|
||
627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Regulator:
|
||
628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_MAINREGULATOR_ON : Main regulator ON.
|
||
629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
|
||
630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) STOPEntry:
|
||
631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
|
||
632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
|
||
633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Domain:
|
||
634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode.
|
||
635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
|
||
636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode.
|
||
637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Exit:
|
||
639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||
640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** DSTANDBY mode ***
|
||
642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =====================
|
||
643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DStandby mode:
|
||
645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The domain bus matrix clock is stopped.
|
||
646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The domain is powered down and the domain RAM and register contents
|
||
647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** are lost.
|
||
648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
|
||
650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function in order to clean the D-Cache and guarantee the data integrity
|
||
651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** for the SRAM memories.
|
||
652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Entry:
|
||
654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
|
||
655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (Domain) function with:
|
||
656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Domain:
|
||
657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode.
|
||
ARM GAS /tmp/ccMGXY28.s page 21
|
||
|
||
|
||
658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
|
||
659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode.
|
||
660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Exit:
|
||
662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
|
||
663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** wakeup, tamper event, time stamp event, external reset in NRST pin,
|
||
664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** IWDG reset.
|
||
665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Keep D3/SRD in RUN mode ***
|
||
667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================
|
||
668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** D3/SRD domain can be kept in Run mode regardless of the CPU status when
|
||
670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
|
||
671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** with :
|
||
672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) D3State:
|
||
673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
|
||
674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode.
|
||
675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
|
||
676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** of CPU subsystem mode.
|
||
677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** FLASH Power Down configuration ****
|
||
679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =======================================
|
||
680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** By setting the FLPS bit in the PWR_CR1 register using the
|
||
682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
|
||
683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** power down mode when the device enters STOP mode. When the Flash memory is
|
||
684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in power down mode, an additional startup delay is incurred when waking up
|
||
685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** from STOP mode.
|
||
686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Wakeup Pins configuration ****
|
||
688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===================================
|
||
689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Wakeup pins allow the system to exit from Standby mode. The configuration
|
||
691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
|
||
692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function with:
|
||
693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) sPinParams: structure to enable and configure a wakeup pin:
|
||
694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) WakeUpPin: Wakeup pin to be enabled.
|
||
695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
|
||
696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
|
||
697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The wakeup pins are internally connected to the EXTI lines [55-60] to
|
||
699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** generate an interrupt if enabled. The EXTI lines configuration is done by
|
||
700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
|
||
701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** file.
|
||
702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
|
||
704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** called and the appropriate flag is set in the PWR_WKUPFR register. Then in
|
||
705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
|
||
706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** cleared and the appropriate user callback will be called. The user can add
|
||
707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
|
||
708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
|
||
710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_RETDS_CD)
|
||
714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
ARM GAS /tmp/ccMGXY28.s page 22
|
||
|
||
|
||
715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enter the system to STOP mode with main domain in DSTOP2.
|
||
716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In STOP mode, the domain bus matrix clock is stalled.
|
||
717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In STOP mode, memories and registers are maintained and peripherals
|
||
718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * in CPU domain are no longer operational.
|
||
719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the
|
||
720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * HSE oscillators are disabled. Only Peripherals that have wakeup
|
||
721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * capability can switch on the HSI to receive a frame, and switch off
|
||
722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the HSI after receiving the frame if it is not a wakeup frame. In
|
||
723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * this case the HSI clock is propagated only to the peripheral
|
||
724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * requesting it.
|
||
725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When exiting STOP mode by issuing an interrupt or a wakeup event,
|
||
726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the HSI RC oscillator is selected as system clock if STOPWUCK bit in
|
||
727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * RCC_CFGR register is set.
|
||
728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Regulator : Specifies the regulator state in STOP mode.
|
||
729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
|
||
731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
|
||
732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator ON.
|
||
733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
|
||
734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * intrinsic instruction.
|
||
735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
|
||
737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
|
||
738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
|
||
741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_REGULATOR (Regulator));
|
||
744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
|
||
745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the regulator state in Stop mode */
|
||
747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
|
||
748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
|
||
750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
|
||
751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
|
||
753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
|
||
754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Ensure that all instructions are done before entering STOP mode */
|
||
759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __ISB ();
|
||
760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __DSB ();
|
||
761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select Stop mode entry */
|
||
763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (STOPEntry == PWR_STOPENTRY_WFI)
|
||
764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */
|
||
766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI ();
|
||
767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Event */
|
||
771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE ();
|
||
ARM GAS /tmp/ccMGXY28.s page 23
|
||
|
||
|
||
772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
|
||
775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_RETDS_CD) */
|
||
778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enter a Domain to DSTOP mode.
|
||
781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API gives flexibility to manage independently each domain STOP
|
||
782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode. For dual core lines, this API should be executed with the
|
||
783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
|
||
784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * executed by all available Cortex-Mx, the system enter to STOP mode.
|
||
785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * For single core lines, calling this API with domain parameter set to
|
||
786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
|
||
787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
|
||
788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * CPUCR_RUN_D3 is cleared.
|
||
789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In DStop mode the domain bus matrix clock is stopped.
|
||
790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem
|
||
791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * is in CStop mode, the EXTI wakeup sources are inactive and at least
|
||
792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
|
||
793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * any domain request Stop.
|
||
794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache
|
||
795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * function in order to clean the D-Cache and guarantee the data
|
||
796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * integrity for the SRAM memories.
|
||
797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In System Stop mode, the domain peripherals that use the LSI or LSE
|
||
798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * clock, and the peripherals that have a kernel clock request to
|
||
799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * select HSI or CSI as source, are still able to operate.
|
||
800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Regulator : Specifies the regulator state in STOP mode.
|
||
801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
|
||
803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
|
||
804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator ON.
|
||
805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
|
||
806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * intrinsic instruction.
|
||
807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
|
||
809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
|
||
810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Domain : Specifies the Domain to enter in DSTOP mode.
|
||
811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
|
||
813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
|
||
814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
|
||
815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
|
||
818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
463 .loc 1 818 1 is_stmt 1 view -0
|
||
464 .cfi_startproc
|
||
465 @ args = 0, pretend = 0, frame = 0
|
||
466 @ frame_needed = 0, uses_anonymous_args = 0
|
||
467 @ link register save eliminated.
|
||
468 .loc 1 818 1 is_stmt 0 view .LVU115
|
||
469 0000 10B4 push {r4}
|
||
470 .LCFI3:
|
||
471 .cfi_def_cfa_offset 4
|
||
472 .cfi_offset 4, -4
|
||
ARM GAS /tmp/ccMGXY28.s page 24
|
||
|
||
|
||
819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_REGULATOR (Regulator));
|
||
473 .loc 1 820 3 is_stmt 1 view .LVU116
|
||
821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
|
||
474 .loc 1 821 3 view .LVU117
|
||
822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_DOMAIN (Domain));
|
||
475 .loc 1 822 3 view .LVU118
|
||
823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the regulator state in Stop mode */
|
||
825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
|
||
476 .loc 1 825 3 view .LVU119
|
||
477 0002 174C ldr r4, .L58
|
||
478 0004 2368 ldr r3, [r4]
|
||
479 0006 23F00103 bic r3, r3, #1
|
||
480 000a 0343 orrs r3, r3, r0
|
||
481 000c 2360 str r3, [r4]
|
||
826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the domain Power Down DeepSleep */
|
||
828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (Domain == PWR_D1_DOMAIN)
|
||
482 .loc 1 828 3 view .LVU120
|
||
483 .loc 1 828 6 is_stmt 0 view .LVU121
|
||
484 000e CAB9 cbnz r2, .L50
|
||
829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */
|
||
832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM7_CPUID)
|
||
833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /*
|
||
835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering stop
|
||
836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode will not be performed
|
||
837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return;
|
||
839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
|
||
843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
|
||
485 .loc 1 843 5 is_stmt 1 view .LVU122
|
||
486 0010 2369 ldr r3, [r4, #16]
|
||
487 0012 23F00103 bic r3, r3, #1
|
||
488 0016 2361 str r3, [r4, #16]
|
||
844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
489 .loc 1 846 5 view .LVU123
|
||
490 0018 124A ldr r2, .L58+4
|
||
491 .LVL32:
|
||
492 .loc 1 846 5 is_stmt 0 view .LVU124
|
||
493 001a 1369 ldr r3, [r2, #16]
|
||
494 001c 43F00403 orr r3, r3, #4
|
||
495 0020 1361 str r3, [r2, #16]
|
||
847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Ensure that all instructions are done before entering STOP mode */
|
||
849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __DSB ();
|
||
496 .loc 1 849 5 is_stmt 1 view .LVU125
|
||
497 .LBB14:
|
||
498 .LBI14:
|
||
ARM GAS /tmp/ccMGXY28.s page 25
|
||
|
||
|
||
499 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
|
||
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
|
||
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
|
||
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
|
||
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
|
||
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
|
||
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
|
||
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
|
||
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
|
||
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
|
||
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
|
||
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
|
||
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
|
||
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
|
||
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
|
||
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
|
||
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
|
||
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
|
||
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
|
||
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
|
||
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
|
||
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
|
||
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
|
||
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
|
||
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
|
||
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
|
||
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
|
||
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
|
||
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
|
||
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
|
||
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
|
||
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
|
||
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
|
||
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
|
||
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
|
||
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
|
||
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
|
||
ARM GAS /tmp/ccMGXY28.s page 26
|
||
|
||
|
||
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
|
||
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
|
||
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
|
||
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
|
||
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
|
||
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
|
||
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
|
||
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
|
||
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
|
||
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
|
||
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
|
||
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
|
||
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
|
||
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
|
||
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
|
||
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
|
||
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
|
||
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
|
||
ARM GAS /tmp/ccMGXY28.s page 27
|
||
|
||
|
||
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
|
||
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
|
||
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
|
||
120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||
121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
|
||
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||
127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
|
||
130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
|
||
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
|
||
137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||
138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
|
||
141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
|
||
143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
144:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
|
||
148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
|
||
149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
|
||
150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
|
||
152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
154:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
|
||
156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
158:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
159:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure)
|
||
163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode.
|
||
164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value
|
||
165:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
|
||
167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
169:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
|
||
ARM GAS /tmp/ccMGXY28.s page 28
|
||
|
||
|
||
171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
174:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
175:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
|
||
178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
|
||
179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
|
||
180:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||
182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||
184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
185:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
186:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
|
||
190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
|
||
191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
|
||
192:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||
194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
|
||
196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
198:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
199:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
|
||
202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
|
||
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
|
||
204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
|
||
206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
208:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
212:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
213:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
|
||
216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
|
||
217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
|
||
218:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
|
||
220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
222:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||
224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
226:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
227:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/ccMGXY28.s page 29
|
||
|
||
|
||
228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
|
||
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
|
||
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
|
||
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
|
||
234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
236:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||
238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
240:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
|
||
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
|
||
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
|
||
246:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
|
||
248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
250:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) );
|
||
252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
254:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
255:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure)
|
||
259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
|
||
260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
|
||
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
|
||
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
265:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
|
||
267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
270:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
271:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
|
||
274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
|
||
275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
|
||
276:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
|
||
278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
|
||
280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
281:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
282:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
ARM GAS /tmp/ccMGXY28.s page 30
|
||
|
||
|
||
285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
|
||
286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
|
||
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
|
||
288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
|
||
290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
|
||
292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
294:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
295:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
|
||
298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
|
||
299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
|
||
300:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
|
||
302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
304:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
|
||
306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
309:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure)
|
||
313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
|
||
314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
|
||
315:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
|
||
317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
|
||
321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
324:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
325:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
|
||
328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
|
||
329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
|
||
330:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
|
||
332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
|
||
334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
335:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
336:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
|
||
340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
|
||
341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
|
||
ARM GAS /tmp/ccMGXY28.s page 31
|
||
|
||
|
||
342:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
|
||
344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
|
||
346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
349:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure)
|
||
353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
|
||
354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value
|
||
355:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
|
||
357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
359:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
|
||
361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
363:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
364:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure)
|
||
367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
|
||
368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set
|
||
369:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
|
||
371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
|
||
373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
|
||
379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
|
||
381:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
|
||
383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
385:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
||
387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
389:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
390:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
|
||
394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
|
||
395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
|
||
396:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
|
||
398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 32
|
||
|
||
|
||
399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
400:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
|
||
402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
405:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
406:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
|
||
409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
|
||
410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
|
||
411:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
|
||
413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||
415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
416:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
417:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure)
|
||
421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
|
||
422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
|
||
423:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
|
||
425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
|
||
427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
429:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
430:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||
434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
|
||
436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||
437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
438:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||
440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
|
||
442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
443:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
444:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
|
||
447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||
448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
449:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||
451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
|
||
453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
454:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
455:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/ccMGXY28.s page 33
|
||
|
||
|
||
456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
|
||
458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
|
||
459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
|
||
460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
|
||
462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
464:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
||
466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
468:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
469:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure)
|
||
473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
|
||
474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
|
||
475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
|
||
477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
479:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
|
||
481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
484:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
485:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
|
||
488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
|
||
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
|
||
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
|
||
494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
495:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure)
|
||
500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state.
|
||
501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
502:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
|
||
504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
|
||
506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
508:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
509:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
|
||
512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
|
||
ARM GAS /tmp/ccMGXY28.s page 34
|
||
|
||
|
||
513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
|
||
514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
|
||
515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||
517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
|
||
519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
520:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
521:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
|
||
524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
|
||
525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
|
||
526:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
|
||
528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
530:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||
532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
534:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
535:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure)
|
||
539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state.
|
||
540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
|
||
541:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
|
||
543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
545:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
|
||
547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
550:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
551:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
|
||
554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
|
||
555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
|
||
556:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
|
||
558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||
560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
561:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
562:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
|
||
566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
|
||
567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
|
||
568:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
|
||
ARM GAS /tmp/ccMGXY28.s page 35
|
||
|
||
|
||
570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
|
||
572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
574:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
|
||
578:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
579:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||
581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||
582:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit
|
||
585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
|
||
587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
588:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
|
||
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
|
||
591:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
|
||
593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) );
|
||
601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
604:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
|
||
606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure)
|
||
608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
|
||
610:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
|
||
612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
|
||
613:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
|
||
615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
|
||
622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
626:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
ARM GAS /tmp/ccMGXY28.s page 36
|
||
|
||
|
||
627:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
|
||
630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||
632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
633:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
|
||
635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||
636:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
|
||
638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
|
||
643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
|
||
645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
647:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
648:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
|
||
652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
|
||
654:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
|
||
656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||
657:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
|
||
659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
|
||
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
|
||
663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
|
||
665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
668:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
669:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit
|
||
672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
|
||
674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
675:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
|
||
677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
|
||
678:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
|
||
680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
ARM GAS /tmp/ccMGXY28.s page 37
|
||
|
||
|
||
684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
|
||
688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
691:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
692:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure)
|
||
696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
|
||
698:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
|
||
700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
|
||
701:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
|
||
703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
|
||
707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
|
||
710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
714:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
715:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
|
||
718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||
720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
|
||
721:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
|
||
723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
|
||
724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
|
||
726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||
728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||
729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
|
||
731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
|
||
733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
735:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
736:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||
738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure)
|
||
740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||
ARM GAS /tmp/ccMGXY28.s page 38
|
||
|
||
|
||
741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
|
||
742:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
|
||
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
|
||
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
||
747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||
749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
|
||
750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
|
||
751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
|
||
753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
756:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||
758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
|
||
759:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
760:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
|
||
763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
|
||
764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
|
||
765:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
||
767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||
769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||
770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr)
|
||
771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
|
||
772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
||
773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
||
774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
|
||
775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
777:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||
779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
|
||
780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
|
||
783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
785:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
786:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
|
||
789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
|
||
790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
|
||
791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
||
793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||
795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||
796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
|
||
797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
|
||
ARM GAS /tmp/ccMGXY28.s page 39
|
||
|
||
|
||
798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
||
799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
||
800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
|
||
801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
|
||
803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr;
|
||
806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
808:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
809:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
|
||
811:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
812:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
|
||
814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||
815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
|
||
816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
818:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
|
||
820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
|
||
821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
|
||
822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
|
||
823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||
824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
|
||
825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||
826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||
828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
|
||
829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||
830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
831:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
|
||
834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||
835:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
|
||
837:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
|
||
840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
|
||
841:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi")
|
||
843:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
844:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
|
||
847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
|
||
848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
|
||
849:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
|
||
851:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
852:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
|
||
ARM GAS /tmp/ccMGXY28.s page 40
|
||
|
||
|
||
855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||
856:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
|
||
858:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
859:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
|
||
862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||
863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
|
||
864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
|
||
865:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
|
||
867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
|
||
869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
870:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
871:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
|
||
874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
|
||
875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
|
||
876:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
|
||
500 .loc 2 877 27 view .LVU126
|
||
501 .LBB15:
|
||
878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
|
||
502 .loc 2 879 3 view .LVU127
|
||
503 .syntax unified
|
||
504 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
505 0022 BFF34F8F dsb 0xF
|
||
506 @ 0 "" 2
|
||
507 .thumb
|
||
508 .syntax unified
|
||
509 .LBE15:
|
||
510 .LBE14:
|
||
850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __ISB ();
|
||
511 .loc 1 850 5 view .LVU128
|
||
512 .LBB16:
|
||
513 .LBI16:
|
||
866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
514 .loc 2 866 27 view .LVU129
|
||
515 .LBB17:
|
||
868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
516 .loc 2 868 3 view .LVU130
|
||
517 .syntax unified
|
||
518 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
519 0026 BFF36F8F isb 0xF
|
||
520 @ 0 "" 2
|
||
521 .thumb
|
||
522 .syntax unified
|
||
523 .LBE17:
|
||
524 .LBE16:
|
||
851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select Stop mode entry */
|
||
853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (STOPEntry == PWR_STOPENTRY_WFI)
|
||
525 .loc 1 853 5 view .LVU131
|
||
ARM GAS /tmp/ccMGXY28.s page 41
|
||
|
||
|
||
526 .loc 1 853 8 is_stmt 0 view .LVU132
|
||
527 002a 0129 cmp r1, #1
|
||
528 002c 08D0 beq .L56
|
||
854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */
|
||
856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI ();
|
||
857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Event */
|
||
861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE ();
|
||
529 .loc 1 861 7 is_stmt 1 view .LVU133
|
||
530 .syntax unified
|
||
531 @ 861 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
|
||
532 002e 20BF wfe
|
||
533 @ 0 "" 2
|
||
534 .thumb
|
||
535 .syntax unified
|
||
536 .L52:
|
||
862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
|
||
865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
537 .loc 1 865 5 view .LVU134
|
||
538 0030 0C4A ldr r2, .L58+4
|
||
539 0032 1369 ldr r3, [r2, #16]
|
||
540 0034 23F00403 bic r3, r3, #4
|
||
541 0038 1361 str r3, [r2, #16]
|
||
542 .L49:
|
||
866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_PDDS_D2)
|
||
868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (Domain == PWR_D2_DOMAIN)
|
||
869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */
|
||
872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM4_CPUID)
|
||
873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /*
|
||
875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering stop
|
||
876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode will not be performed
|
||
877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return;
|
||
879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D2 domain enters Deepsleep */
|
||
882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2);
|
||
883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Ensure that all instructions are done before entering STOP mode */
|
||
888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __DSB ();
|
||
889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __ISB ();
|
||
890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select Stop mode entry */
|
||
892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (STOPEntry == PWR_STOPENTRY_WFI)
|
||
893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 42
|
||
|
||
|
||
894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */
|
||
895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI ();
|
||
896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Event */
|
||
900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE ();
|
||
901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
|
||
904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
|
||
906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D2 domain enters Deepsleep */
|
||
907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
|
||
908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_PDDS_D2) */
|
||
911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */
|
||
915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
||
916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D3 domain enters Deepsleep */
|
||
918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
|
||
919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D3 domain enters Deepsleep */
|
||
923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
|
||
924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
|
||
926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
|
||
927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
|
||
928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
543 .loc 1 930 1 is_stmt 0 view .LVU135
|
||
544 003a 5DF8044B ldr r4, [sp], #4
|
||
545 .LCFI4:
|
||
546 .cfi_remember_state
|
||
547 .cfi_restore 4
|
||
548 .cfi_def_cfa_offset 0
|
||
549 003e 7047 bx lr
|
||
550 .L56:
|
||
551 .LCFI5:
|
||
552 .cfi_restore_state
|
||
856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
553 .loc 1 856 7 is_stmt 1 view .LVU136
|
||
554 .syntax unified
|
||
555 @ 856 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
|
||
556 0040 30BF wfi
|
||
557 @ 0 "" 2
|
||
558 .thumb
|
||
559 .syntax unified
|
||
560 0042 F5E7 b .L52
|
||
561 .LVL33:
|
||
ARM GAS /tmp/ccMGXY28.s page 43
|
||
|
||
|
||
562 .L50:
|
||
868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
563 .loc 1 868 8 view .LVU137
|
||
868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
564 .loc 1 868 11 is_stmt 0 view .LVU138
|
||
565 0044 012A cmp r2, #1
|
||
566 0046 05D0 beq .L57
|
||
927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
567 .loc 1 927 5 is_stmt 1 view .LVU139
|
||
568 0048 054A ldr r2, .L58
|
||
569 .LVL34:
|
||
927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
570 .loc 1 927 5 is_stmt 0 view .LVU140
|
||
571 004a 1369 ldr r3, [r2, #16]
|
||
572 004c 23F00403 bic r3, r3, #4
|
||
573 0050 1361 str r3, [r2, #16]
|
||
574 .loc 1 930 1 view .LVU141
|
||
575 0052 F2E7 b .L49
|
||
576 .LVL35:
|
||
577 .L57:
|
||
907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
578 .loc 1 907 5 is_stmt 1 view .LVU142
|
||
579 0054 024A ldr r2, .L58
|
||
580 .LVL36:
|
||
907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
581 .loc 1 907 5 is_stmt 0 view .LVU143
|
||
582 0056 1369 ldr r3, [r2, #16]
|
||
583 0058 23F00203 bic r3, r3, #2
|
||
584 005c 1361 str r3, [r2, #16]
|
||
585 005e ECE7 b .L49
|
||
586 .L59:
|
||
587 .align 2
|
||
588 .L58:
|
||
589 0060 00480258 .word 1476544512
|
||
590 0064 00ED00E0 .word -536810240
|
||
591 .cfi_endproc
|
||
592 .LFE147:
|
||
594 .section .text.HAL_PWREx_ClearPendingEvent,"ax",%progbits
|
||
595 .align 1
|
||
596 .global HAL_PWREx_ClearPendingEvent
|
||
597 .syntax unified
|
||
598 .thumb
|
||
599 .thumb_func
|
||
600 .fpu fpv5-d16
|
||
602 HAL_PWREx_ClearPendingEvent:
|
||
603 .LFB148:
|
||
931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Clear pending event.
|
||
934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API clears the pending event in order to enter a given CPU
|
||
935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * to CSLEEP or CSTOP. It should be called just before APIs performing
|
||
936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * enter low power mode using Wait For Event request.
|
||
937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4.
|
||
938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ClearPendingEvent (void)
|
||
941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 44
|
||
|
||
|
||
604 .loc 1 941 1 is_stmt 1 view -0
|
||
605 .cfi_startproc
|
||
606 @ args = 0, pretend = 0, frame = 0
|
||
607 @ frame_needed = 0, uses_anonymous_args = 0
|
||
608 @ link register save eliminated.
|
||
942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the current Core */
|
||
944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
||
945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE ();
|
||
947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __SEV ();
|
||
951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE ();
|
||
952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
|
||
954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE ();
|
||
609 .loc 1 954 3 view .LVU145
|
||
610 .syntax unified
|
||
611 @ 954 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
|
||
612 0000 20BF wfe
|
||
613 @ 0 "" 2
|
||
955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
614 .loc 1 956 1 is_stmt 0 view .LVU146
|
||
615 .thumb
|
||
616 .syntax unified
|
||
617 0002 7047 bx lr
|
||
618 .cfi_endproc
|
||
619 .LFE148:
|
||
621 .section .text.HAL_PWREx_EnterSTANDBYMode,"ax",%progbits
|
||
622 .align 1
|
||
623 .global HAL_PWREx_EnterSTANDBYMode
|
||
624 .syntax unified
|
||
625 .thumb
|
||
626 .thumb_func
|
||
627 .fpu fpv5-d16
|
||
629 HAL_PWREx_EnterSTANDBYMode:
|
||
630 .LVL37:
|
||
631 .LFB149:
|
||
957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enter a Domain to DSTANDBY mode.
|
||
960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API gives flexibility to manage independently each domain
|
||
961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * STANDBY mode. For dual core lines, this API should be executed with
|
||
962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
|
||
963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * it is executed by all available Cortex-Mx, the system enter STANDBY
|
||
964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode.
|
||
965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * For single core lines, calling this API with D1/SRD the selected
|
||
966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
|
||
967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
|
||
968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
|
||
969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the Dn domain select Standby mode. When the system enters Standby
|
||
970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode, the voltage regulator is disabled.
|
||
971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When D2 or D3 domain is in DStandby mode and the CPU sets the
|
||
972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * domain PDDS_Dn bit to select Stop mode, the domain remains in
|
||
ARM GAS /tmp/ccMGXY28.s page 45
|
||
|
||
|
||
973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * DStandby mode. The domain will only exit DStandby when the CPU
|
||
974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * allocates a peripheral in the domain.
|
||
975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The system D3/SRD domain enters Standby mode only when the D1 and D2
|
||
976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * domain are in DStandby.
|
||
977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Before entering DSTANDBY mode it is recommended to call
|
||
978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * SCB_CleanDCache function in order to clean the D-Cache and guarantee
|
||
979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the data integrity for the SRAM memories.
|
||
980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Domain : Specifies the Domain to enter to STANDBY mode.
|
||
981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
|
||
983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
|
||
984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
|
||
985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None
|
||
986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
|
||
988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
632 .loc 1 988 1 is_stmt 1 view -0
|
||
633 .cfi_startproc
|
||
634 @ args = 0, pretend = 0, frame = 0
|
||
635 @ frame_needed = 0, uses_anonymous_args = 0
|
||
636 @ link register save eliminated.
|
||
989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_DOMAIN (Domain));
|
||
637 .loc 1 990 3 view .LVU148
|
||
991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the domain Power Down DeepSleep */
|
||
993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (Domain == PWR_D1_DOMAIN)
|
||
638 .loc 1 993 3 view .LVU149
|
||
639 .loc 1 993 6 is_stmt 0 view .LVU150
|
||
640 0000 58B9 cbnz r0, .L62
|
||
994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */
|
||
997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM7_CPUID)
|
||
998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /*
|
||
1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering
|
||
1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** standby mode will not be performed
|
||
1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return;
|
||
1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
|
||
1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
|
||
641 .loc 1 1008 5 is_stmt 1 view .LVU151
|
||
642 0002 0D4A ldr r2, .L66
|
||
643 0004 1369 ldr r3, [r2, #16]
|
||
644 0006 43F00103 orr r3, r3, #1
|
||
645 000a 1361 str r3, [r2, #16]
|
||
1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
|
||
1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
|
||
1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /*DUAL_CORE*/
|
||
1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
ARM GAS /tmp/ccMGXY28.s page 46
|
||
|
||
|
||
1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
646 .loc 1 1016 5 view .LVU152
|
||
647 000c 0B4A ldr r2, .L66+4
|
||
648 000e 1369 ldr r3, [r2, #16]
|
||
649 0010 43F00403 orr r3, r3, #4
|
||
650 0014 1361 str r3, [r2, #16]
|
||
1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* This option is used to ensure that store operations are completed */
|
||
1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (__CC_ARM)
|
||
1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __force_stores ();
|
||
1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (__CC_ARM) */
|
||
1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */
|
||
1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI ();
|
||
651 .loc 1 1024 5 view .LVU153
|
||
652 .syntax unified
|
||
653 @ 1024 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
|
||
654 0016 30BF wfi
|
||
655 @ 0 "" 2
|
||
656 .thumb
|
||
657 .syntax unified
|
||
658 0018 7047 bx lr
|
||
659 .L62:
|
||
1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_PDDS_D2)
|
||
1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (Domain == PWR_D2_DOMAIN)
|
||
660 .loc 1 1027 8 view .LVU154
|
||
661 .loc 1 1027 11 is_stmt 0 view .LVU155
|
||
662 001a 0128 cmp r0, #1
|
||
663 001c 05D0 beq .L65
|
||
1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
|
||
1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
|
||
1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */
|
||
1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM4_CPUID)
|
||
1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /*
|
||
1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering
|
||
1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** standby mode will not be performed
|
||
1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return;
|
||
1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
|
||
1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
|
||
1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||
1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* This option is used to ensure that store operations are completed */
|
||
1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (__CC_ARM)
|
||
1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __force_stores ();
|
||
1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (__CC_ARM) */
|
||
1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */
|
||
ARM GAS /tmp/ccMGXY28.s page 47
|
||
|
||
|
||
1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI ();
|
||
1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_PDDS_D2) */
|
||
1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
|
||
1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
|
||
664 .loc 1 1062 5 is_stmt 1 view .LVU156
|
||
665 001e 064A ldr r2, .L66
|
||
666 0020 1369 ldr r3, [r2, #16]
|
||
667 0022 43F00403 orr r3, r3, #4
|
||
668 0026 1361 str r3, [r2, #16]
|
||
1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
|
||
1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
|
||
1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
669 .loc 1 1069 1 is_stmt 0 view .LVU157
|
||
670 0028 7047 bx lr
|
||
671 .L65:
|
||
1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
672 .loc 1 1030 5 is_stmt 1 view .LVU158
|
||
673 002a 034A ldr r2, .L66
|
||
674 002c 1369 ldr r3, [r2, #16]
|
||
675 002e 43F00203 orr r3, r3, #2
|
||
676 0032 1361 str r3, [r2, #16]
|
||
677 0034 7047 bx lr
|
||
678 .L67:
|
||
679 0036 00BF .align 2
|
||
680 .L66:
|
||
681 0038 00480258 .word 1476544512
|
||
682 003c 00ED00E0 .word -536810240
|
||
683 .cfi_endproc
|
||
684 .LFE149:
|
||
686 .section .text.HAL_PWREx_ConfigD3Domain,"ax",%progbits
|
||
687 .align 1
|
||
688 .global HAL_PWREx_ConfigD3Domain
|
||
689 .syntax unified
|
||
690 .thumb
|
||
691 .thumb_func
|
||
692 .fpu fpv5-d16
|
||
694 HAL_PWREx_ConfigD3Domain:
|
||
695 .LVL38:
|
||
696 .LFB150:
|
||
1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the D3/SRD Domain state when the System in low power mode.
|
||
1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param D3State : Specifies the D3/SRD state.
|
||
1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values :
|
||
1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
|
||
1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * CPU sub-system low power mode.
|
||
1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
|
||
1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regardless of the CPU sub-system low
|
||
1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * power mode.
|
||
ARM GAS /tmp/ccMGXY28.s page 48
|
||
|
||
|
||
1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None
|
||
1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
|
||
1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
697 .loc 1 1083 1 view -0
|
||
698 .cfi_startproc
|
||
699 @ args = 0, pretend = 0, frame = 0
|
||
700 @ frame_needed = 0, uses_anonymous_args = 0
|
||
701 @ link register save eliminated.
|
||
1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_D3_STATE (D3State));
|
||
702 .loc 1 1085 3 view .LVU160
|
||
1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep D3/SRD in run mode */
|
||
1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
|
||
703 .loc 1 1088 3 view .LVU161
|
||
704 0000 034A ldr r2, .L69
|
||
705 0002 1369 ldr r3, [r2, #16]
|
||
706 0004 23F40063 bic r3, r3, #2048
|
||
707 0008 0343 orrs r3, r3, r0
|
||
708 000a 1361 str r3, [r2, #16]
|
||
1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
709 .loc 1 1089 1 is_stmt 0 view .LVU162
|
||
710 000c 7047 bx lr
|
||
711 .L70:
|
||
712 000e 00BF .align 2
|
||
713 .L69:
|
||
714 0010 00480258 .word 1476544512
|
||
715 .cfi_endproc
|
||
716 .LFE150:
|
||
718 .section .text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits
|
||
719 .align 1
|
||
720 .global HAL_PWREx_EnableFlashPowerDown
|
||
721 .syntax unified
|
||
722 .thumb
|
||
723 .thumb_func
|
||
724 .fpu fpv5-d16
|
||
726 HAL_PWREx_EnableFlashPowerDown:
|
||
727 .LFB151:
|
||
1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
|
||
1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * given domain.
|
||
1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param DomainFlags : Specifies the Domain flags to be cleared.
|
||
1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
|
||
1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
|
||
1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
|
||
1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
|
||
1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
|
||
1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* D1 CPU flags */
|
||
ARM GAS /tmp/ccMGXY28.s page 49
|
||
|
||
|
||
1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
|
||
1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
|
||
1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
|
||
1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* D2 CPU flags */
|
||
1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
|
||
1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
|
||
1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
|
||
1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
|
||
1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
|
||
1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
|
||
1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
|
||
1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
|
||
1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param CPU : Specifies the core to be held.
|
||
1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
|
||
1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
|
||
1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status
|
||
1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
|
||
1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK;
|
||
1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_CORE (CPU));
|
||
1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check CPU index */
|
||
1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (CPU == PWR_CORE_CPU2)
|
||
1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* If CPU1 is not held */
|
||
1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
|
||
1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set HOLD2 bit */
|
||
1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
|
||
1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** status = HAL_ERROR;
|
||
1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* If CPU2 is not held */
|
||
1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
|
||
1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set HOLD1 bit */
|
||
1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
|
||
1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
ARM GAS /tmp/ccMGXY28.s page 50
|
||
|
||
|
||
1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** status = HAL_ERROR;
|
||
1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return status;
|
||
1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Release the CPU and their domain peripherals after a wake-up from
|
||
1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * STOP mode.
|
||
1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param CPU: Specifies the core to be released.
|
||
1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU1: Release the CPU1 and their domain
|
||
1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * peripherals from holding.
|
||
1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU2: Release the CPU2 and their domain
|
||
1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * peripherals from holding.
|
||
1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None
|
||
1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ReleaseCore (uint32_t CPU)
|
||
1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_CORE (CPU));
|
||
1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check CPU index */
|
||
1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (CPU == PWR_CORE_CPU2)
|
||
1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Reset HOLD2 bit */
|
||
1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
|
||
1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Reset HOLD1 bit */
|
||
1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
|
||
1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Flash Power Down in Stop mode.
|
||
1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When Flash Power Down is enabled the Flash memory enters low-power
|
||
1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode when D1/SRD domain is in DStop mode. This feature allows to
|
||
1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * obtain the best trade-off between low-power consumption and restart
|
||
1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * time when exiting from DStop mode.
|
||
1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown (void)
|
||
1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
728 .loc 1 1214 1 is_stmt 1 view -0
|
||
729 .cfi_startproc
|
||
730 @ args = 0, pretend = 0, frame = 0
|
||
731 @ frame_needed = 0, uses_anonymous_args = 0
|
||
732 @ link register save eliminated.
|
||
1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Flash Power Down */
|
||
1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_FLPS);
|
||
ARM GAS /tmp/ccMGXY28.s page 51
|
||
|
||
|
||
733 .loc 1 1216 3 view .LVU164
|
||
734 0000 024A ldr r2, .L72
|
||
735 0002 1368 ldr r3, [r2]
|
||
736 0004 43F40073 orr r3, r3, #512
|
||
737 0008 1360 str r3, [r2]
|
||
1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
738 .loc 1 1217 1 is_stmt 0 view .LVU165
|
||
739 000a 7047 bx lr
|
||
740 .L73:
|
||
741 .align 2
|
||
742 .L72:
|
||
743 000c 00480258 .word 1476544512
|
||
744 .cfi_endproc
|
||
745 .LFE151:
|
||
747 .section .text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits
|
||
748 .align 1
|
||
749 .global HAL_PWREx_DisableFlashPowerDown
|
||
750 .syntax unified
|
||
751 .thumb
|
||
752 .thumb_func
|
||
753 .fpu fpv5-d16
|
||
755 HAL_PWREx_DisableFlashPowerDown:
|
||
756 .LFB152:
|
||
1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Flash Power Down in Stop mode.
|
||
1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When Flash Power Down is disabled the Flash memory is kept on
|
||
1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * normal mode when D1/SRD domain is in DStop mode. This feature allows
|
||
1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * to obtain the best trade-off between low-power consumption and
|
||
1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * restart time when exiting from DStop mode.
|
||
1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown (void)
|
||
1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
757 .loc 1 1228 1 is_stmt 1 view -0
|
||
758 .cfi_startproc
|
||
759 @ args = 0, pretend = 0, frame = 0
|
||
760 @ frame_needed = 0, uses_anonymous_args = 0
|
||
761 @ link register save eliminated.
|
||
1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Flash Power Down */
|
||
1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
|
||
762 .loc 1 1230 3 view .LVU167
|
||
763 0000 024A ldr r2, .L75
|
||
764 0002 1368 ldr r3, [r2]
|
||
765 0004 23F40073 bic r3, r3, #512
|
||
766 0008 1360 str r3, [r2]
|
||
1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
767 .loc 1 1231 1 is_stmt 0 view .LVU168
|
||
768 000a 7047 bx lr
|
||
769 .L76:
|
||
770 .align 2
|
||
771 .L75:
|
||
772 000c 00480258 .word 1476544512
|
||
773 .cfi_endproc
|
||
774 .LFE152:
|
||
776 .section .text.HAL_PWREx_EnableWakeUpPin,"ax",%progbits
|
||
777 .align 1
|
||
ARM GAS /tmp/ccMGXY28.s page 52
|
||
|
||
|
||
778 .global HAL_PWREx_EnableWakeUpPin
|
||
779 .syntax unified
|
||
780 .thumb
|
||
781 .thumb_func
|
||
782 .fpu fpv5-d16
|
||
784 HAL_PWREx_EnableWakeUpPin:
|
||
785 .LVL39:
|
||
786 .LFB153:
|
||
1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CR1_SRDRAMSO)
|
||
1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable memory block shut-off in DStop or DStop2 modes
|
||
1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In DStop or DStop2 mode, the content of the memory blocks is
|
||
1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * maintained. Further power optimization can be obtained by switching
|
||
1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * off some memory blocks. This optimization implies loss of the memory
|
||
1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * content. The user can select which memory is discarded during STOP
|
||
1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode by means of xxSO bits.
|
||
1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param MemoryBlock : Specifies the memory block to shut-off during DStop or
|
||
1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * DStop2 mode.
|
||
1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
|
||
1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
|
||
1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * FDCAN memories.
|
||
1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
|
||
1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
|
||
1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
|
||
1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
|
||
1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
|
||
1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
|
||
1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
|
||
1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
|
||
1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
|
||
1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable memory block shut-off */
|
||
1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, MemoryBlock);
|
||
1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable memory block shut-off in DStop or DStop2 modes
|
||
1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param MemoryBlock : Specifies the memory block to keep content during
|
||
1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * DStop or DStop2 mode.
|
||
1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
|
||
1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
|
||
1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * FDCAN memories.
|
||
1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
|
||
1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
|
||
1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
|
||
1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
|
||
1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
|
||
1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
|
||
1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
|
||
1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
ARM GAS /tmp/ccMGXY28.s page 53
|
||
|
||
|
||
1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
|
||
1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
|
||
1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable memory block shut-off */
|
||
1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, MemoryBlock);
|
||
1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CR1_SRDRAMSO) */
|
||
1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Wake-up PINx functionality.
|
||
1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
|
||
1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * contains the configuration information for the wake-up
|
||
1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Pin.
|
||
1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note For dual core devices, please ensure to configure the EXTI lines for
|
||
1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the different Cortex-Mx. All combination are allowed: wake up only
|
||
1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
|
||
1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Cortex-M4.
|
||
1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
|
||
1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
787 .loc 1 1304 1 is_stmt 1 view -0
|
||
788 .cfi_startproc
|
||
789 @ args = 0, pretend = 0, frame = 0
|
||
790 @ frame_needed = 0, uses_anonymous_args = 0
|
||
791 @ link register save eliminated.
|
||
792 .loc 1 1304 1 is_stmt 0 view .LVU170
|
||
793 0000 10B4 push {r4}
|
||
794 .LCFI6:
|
||
795 .cfi_def_cfa_offset 4
|
||
796 .cfi_offset 4, -4
|
||
1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t pinConfig;
|
||
797 .loc 1 1305 3 is_stmt 1 view .LVU171
|
||
1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t regMask;
|
||
798 .loc 1 1306 3 view .LVU172
|
||
1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
|
||
799 .loc 1 1307 3 view .LVU173
|
||
800 .LVL40:
|
||
1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
|
||
801 .loc 1 1310 3 view .LVU174
|
||
1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
|
||
802 .loc 1 1311 3 view .LVU175
|
||
1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
|
||
803 .loc 1 1312 3 view .LVU176
|
||
1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** pinConfig = sPinParams->WakeUpPin | \
|
||
804 .loc 1 1314 3 view .LVU177
|
||
805 .loc 1 1314 25 is_stmt 0 view .LVU178
|
||
806 0002 0368 ldr r3, [r0]
|
||
1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP
|
||
807 .loc 1 1315 26 view .LVU179
|
||
808 0004 4168 ldr r1, [r0, #4]
|
||
ARM GAS /tmp/ccMGXY28.s page 54
|
||
|
||
|
||
809 .LVL41:
|
||
810 .LBB18:
|
||
811 .LBI18:
|
||
880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
881:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
882:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier
|
||
885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
|
||
886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
|
||
887:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
|
||
889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
|
||
891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
892:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
893:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit)
|
||
896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
|
||
897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
899:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
|
||
901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||
903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value);
|
||
904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
906:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
911:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
912:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
|
||
915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes
|
||
916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
918:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
|
||
920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
922:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
926:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
927:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
|
||
930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
|
||
931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
933:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
ARM GAS /tmp/ccMGXY28.s page 55
|
||
|
||
|
||
934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
|
||
935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||
937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value);
|
||
938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result;
|
||
940:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
945:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
946:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
|
||
949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
|
||
950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate
|
||
951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate
|
||
952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value
|
||
953:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||
955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U;
|
||
957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U)
|
||
958:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1;
|
||
960:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2));
|
||
962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
963:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
964:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint
|
||
967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state.
|
||
968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula
|
||
969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor.
|
||
970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break
|
||
971:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||
973:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
974:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value
|
||
977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value.
|
||
978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
|
||
979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
|
||
980:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
|
||
812 .loc 2 981 31 is_stmt 1 view .LVU180
|
||
813 .LBB19:
|
||
982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
|
||
814 .loc 2 983 3 view .LVU181
|
||
984:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||
986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||
987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||
ARM GAS /tmp/ccMGXY28.s page 56
|
||
|
||
|
||
988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||
815 .loc 2 988 4 view .LVU182
|
||
816 .syntax unified
|
||
817 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
818 0006 93FAA3F2 rbit r2, r3
|
||
819 @ 0 "" 2
|
||
820 .LVL42:
|
||
989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||
991:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
|
||
993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
|
||
994:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
|
||
996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U;
|
||
997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--;
|
||
998:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */
|
||
1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
|
||
821 .loc 2 1001 3 view .LVU183
|
||
822 .loc 2 1001 3 is_stmt 0 view .LVU184
|
||
823 .thumb
|
||
824 .syntax unified
|
||
825 .LBE19:
|
||
826 .LBE18:
|
||
827 .loc 1 1315 45 view .LVU185
|
||
828 000a B2FA82F2 clz r2, r2
|
||
829 .loc 1 1315 81 view .LVU186
|
||
830 000e 0832 adds r2, r2, #8
|
||
831 .loc 1 1315 107 view .LVU187
|
||
832 0010 02F01F02 and r2, r2, #31
|
||
833 .loc 1 1315 40 view .LVU188
|
||
834 0014 01FA02F2 lsl r2, r1, r2
|
||
1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP
|
||
835 .loc 1 1314 37 view .LVU189
|
||
836 0018 43EA0201 orr r1, r3, r2
|
||
837 .LVL43:
|
||
838 .LBB20:
|
||
839 .LBI20:
|
||
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
840 .loc 2 981 31 is_stmt 1 view .LVU190
|
||
841 .LBB21:
|
||
983:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
842 .loc 2 983 3 view .LVU191
|
||
988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
843 .loc 2 988 4 view .LVU192
|
||
844 .syntax unified
|
||
845 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
846 001c 93FAA3F2 rbit r2, r3
|
||
847 @ 0 "" 2
|
||
848 .LVL44:
|
||
849 .loc 2 1001 3 view .LVU193
|
||
850 .loc 2 1001 3 is_stmt 0 view .LVU194
|
||
851 .thumb
|
||
852 .syntax unified
|
||
853 .LBE21:
|
||
ARM GAS /tmp/ccMGXY28.s page 57
|
||
|
||
|
||
854 .LBE20:
|
||
1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL
|
||
855 .loc 1 1316 42 view .LVU195
|
||
856 0020 B2FA82F2 clz r2, r2
|
||
857 .loc 1 1316 115 view .LVU196
|
||
858 0024 0832 adds r2, r2, #8
|
||
859 0026 5200 lsls r2, r2, #1
|
||
860 .loc 1 1316 144 view .LVU197
|
||
861 0028 02F01E02 and r2, r2, #30
|
||
862 .loc 1 1316 36 view .LVU198
|
||
863 002c 8468 ldr r4, [r0, #8]
|
||
864 002e 04FA02F2 lsl r2, r4, r2
|
||
1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP
|
||
865 .loc 1 1314 13 view .LVU199
|
||
866 0032 0A43 orrs r2, r2, r1
|
||
867 .LVL45:
|
||
1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regMask = sPinParams->WakeUpPin | \
|
||
868 .loc 1 1318 3 is_stmt 1 view .LVU200
|
||
869 .LBB22:
|
||
870 .LBI22:
|
||
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
871 .loc 2 981 31 view .LVU201
|
||
872 .LBB23:
|
||
983:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
873 .loc 2 983 3 view .LVU202
|
||
988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
874 .loc 2 988 4 view .LVU203
|
||
875 .syntax unified
|
||
876 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
877 0034 93FAA3F1 rbit r1, r3
|
||
878 @ 0 "" 2
|
||
879 .LVL46:
|
||
880 .loc 2 1001 3 view .LVU204
|
||
881 .loc 2 1001 3 is_stmt 0 view .LVU205
|
||
882 .thumb
|
||
883 .syntax unified
|
||
884 .LBE23:
|
||
885 .LBE22:
|
||
1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
|
||
886 .loc 1 1319 75 view .LVU206
|
||
887 0038 B1FA81F1 clz r1, r1
|
||
888 003c 01F01F0C and ip, r1, #31
|
||
889 .loc 1 1319 35 view .LVU207
|
||
890 0040 4FF48071 mov r1, #256
|
||
891 0044 01FA0CF1 lsl r1, r1, ip
|
||
1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
|
||
892 .loc 1 1318 37 view .LVU208
|
||
893 0048 1943 orrs r1, r1, r3
|
||
894 .LVL47:
|
||
895 .LBB24:
|
||
896 .LBI24:
|
||
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
897 .loc 2 981 31 is_stmt 1 view .LVU209
|
||
898 .LBB25:
|
||
983:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
899 .loc 2 983 3 view .LVU210
|
||
ARM GAS /tmp/ccMGXY28.s page 58
|
||
|
||
|
||
988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
|
||
900 .loc 2 988 4 view .LVU211
|
||
901 .syntax unified
|
||
902 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
903 004a 93FAA3F3 rbit r3, r3
|
||
904 @ 0 "" 2
|
||
905 .LVL48:
|
||
906 .loc 2 1001 3 view .LVU212
|
||
907 .loc 2 1001 3 is_stmt 0 view .LVU213
|
||
908 .thumb
|
||
909 .syntax unified
|
||
910 .LBE25:
|
||
911 .LBE24:
|
||
1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSE
|
||
912 .loc 1 1320 30 view .LVU214
|
||
913 004e B3FA83F3 clz r3, r3
|
||
914 .loc 1 1320 66 view .LVU215
|
||
915 0052 5B00 lsls r3, r3, #1
|
||
916 .loc 1 1320 103 view .LVU216
|
||
917 0054 03F01E03 and r3, r3, #30
|
||
918 .loc 1 1320 25 view .LVU217
|
||
919 0058 4FF4403C mov ip, #196608
|
||
920 005c 0CFA03F3 lsl r3, ip, r3
|
||
1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
|
||
921 .loc 1 1318 13 view .LVU218
|
||
922 0060 0B43 orrs r3, r3, r1
|
||
923 .LVL49:
|
||
1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable and Specify the Wake-Up pin polarity and the pull configuration
|
||
1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** for the event detection (rising or falling edge) */
|
||
1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
|
||
924 .loc 1 1324 3 is_stmt 1 view .LVU219
|
||
925 0062 0A4C ldr r4, .L79
|
||
926 0064 A16A ldr r1, [r4, #40]
|
||
927 0066 21EA0303 bic r3, r1, r3
|
||
928 .LVL50:
|
||
929 .loc 1 1324 3 is_stmt 0 view .LVU220
|
||
930 006a 1A43 orrs r2, r2, r3
|
||
931 .LVL51:
|
||
932 .loc 1 1324 3 view .LVU221
|
||
933 006c A262 str r2, [r4, #40]
|
||
1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #ifndef DUAL_CORE
|
||
1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Configure the Wakeup Pin EXTI Line */
|
||
1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos))
|
||
934 .loc 1 1327 3 is_stmt 1 view .LVU222
|
||
935 006e 4FF0B042 mov r2, #1476395008
|
||
936 0072 D2F89030 ldr r3, [r2, #144]
|
||
937 0076 23F0FC53 bic r3, r3, #528482304
|
||
938 007a 0168 ldr r1, [r0]
|
||
939 007c 43EAC153 orr r3, r3, r1, lsl #23
|
||
940 0080 C2F89030 str r3, [r2, #144]
|
||
1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !DUAL_CORE */
|
||
1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
941 .loc 1 1329 1 is_stmt 0 view .LVU223
|
||
942 0084 5DF8044B ldr r4, [sp], #4
|
||
943 .LCFI7:
|
||
944 .cfi_restore 4
|
||
ARM GAS /tmp/ccMGXY28.s page 59
|
||
|
||
|
||
945 .cfi_def_cfa_offset 0
|
||
946 0088 7047 bx lr
|
||
947 .L80:
|
||
948 008a 00BF .align 2
|
||
949 .L79:
|
||
950 008c 00480258 .word 1476544512
|
||
951 .cfi_endproc
|
||
952 .LFE153:
|
||
954 .section .text.HAL_PWREx_DisableWakeUpPin,"ax",%progbits
|
||
955 .align 1
|
||
956 .global HAL_PWREx_DisableWakeUpPin
|
||
957 .syntax unified
|
||
958 .thumb
|
||
959 .thumb_func
|
||
960 .fpu fpv5-d16
|
||
962 HAL_PWREx_DisableWakeUpPin:
|
||
963 .LVL52:
|
||
964 .LFB154:
|
||
1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Wake-up PINx functionality.
|
||
1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param WakeUpPin : Specifies the Wake-Up pin to be disabled.
|
||
1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN.
|
||
1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN.
|
||
1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN.
|
||
1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
|
||
1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
|
||
1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN.
|
||
1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for
|
||
1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * devices that support GPIOI port.
|
||
1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None
|
||
1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
|
||
1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
965 .loc 1 1346 1 is_stmt 1 view -0
|
||
966 .cfi_startproc
|
||
967 @ args = 0, pretend = 0, frame = 0
|
||
968 @ frame_needed = 0, uses_anonymous_args = 0
|
||
969 @ link register save eliminated.
|
||
1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
|
||
970 .loc 1 1348 3 view .LVU225
|
||
1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the WakeUpPin */
|
||
1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
|
||
971 .loc 1 1351 3 view .LVU226
|
||
972 0000 024A ldr r2, .L82
|
||
973 0002 936A ldr r3, [r2, #40]
|
||
974 0004 23EA0003 bic r3, r3, r0
|
||
975 0008 9362 str r3, [r2, #40]
|
||
1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
976 .loc 1 1352 1 is_stmt 0 view .LVU227
|
||
977 000a 7047 bx lr
|
||
978 .L83:
|
||
979 .align 2
|
||
980 .L82:
|
||
ARM GAS /tmp/ccMGXY28.s page 60
|
||
|
||
|
||
981 000c 00480258 .word 1476544512
|
||
982 .cfi_endproc
|
||
983 .LFE154:
|
||
985 .section .text.HAL_PWREx_GetWakeupFlag,"ax",%progbits
|
||
986 .align 1
|
||
987 .global HAL_PWREx_GetWakeupFlag
|
||
988 .syntax unified
|
||
989 .thumb
|
||
990 .thumb_func
|
||
991 .fpu fpv5-d16
|
||
993 HAL_PWREx_GetWakeupFlag:
|
||
994 .LVL53:
|
||
995 .LFB155:
|
||
1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the Wake-Up Pin pending flags.
|
||
1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
|
||
1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0.
|
||
1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2.
|
||
1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8.
|
||
1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13.
|
||
1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11.
|
||
1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1.
|
||
1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
|
||
1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * wake up pins.
|
||
1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
|
||
1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * devices that support GPIOI port.
|
||
1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The Wake-Up pin flag.
|
||
1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
|
||
1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
996 .loc 1 1371 1 is_stmt 1 view -0
|
||
997 .cfi_startproc
|
||
998 @ args = 0, pretend = 0, frame = 0
|
||
999 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1000 @ link register save eliminated.
|
||
1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
|
||
1001 .loc 1 1373 3 view .LVU229
|
||
1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Return the wake up pin flag */
|
||
1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->WKUPFR & WakeUpFlag);
|
||
1002 .loc 1 1376 3 view .LVU230
|
||
1003 .loc 1 1376 14 is_stmt 0 view .LVU231
|
||
1004 0000 014B ldr r3, .L85
|
||
1005 0002 5B6A ldr r3, [r3, #36]
|
||
1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1006 .loc 1 1377 1 view .LVU232
|
||
1007 0004 1840 ands r0, r0, r3
|
||
1008 .LVL54:
|
||
1009 .loc 1 1377 1 view .LVU233
|
||
1010 0006 7047 bx lr
|
||
1011 .L86:
|
||
1012 .align 2
|
||
1013 .L85:
|
||
1014 0008 00480258 .word 1476544512
|
||
ARM GAS /tmp/ccMGXY28.s page 61
|
||
|
||
|
||
1015 .cfi_endproc
|
||
1016 .LFE155:
|
||
1018 .section .text.HAL_PWREx_ClearWakeupFlag,"ax",%progbits
|
||
1019 .align 1
|
||
1020 .global HAL_PWREx_ClearWakeupFlag
|
||
1021 .syntax unified
|
||
1022 .thumb
|
||
1023 .thumb_func
|
||
1024 .fpu fpv5-d16
|
||
1026 HAL_PWREx_ClearWakeupFlag:
|
||
1027 .LVL55:
|
||
1028 .LFB156:
|
||
1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Clear the Wake-Up pin pending flag.
|
||
1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
|
||
1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values:
|
||
1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
|
||
1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
|
||
1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
|
||
1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
|
||
1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
|
||
1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
|
||
1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
|
||
1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * all wake up pins.
|
||
1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
|
||
1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * devices that support GPIOI port.
|
||
1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
|
||
1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1029 .loc 1 1396 1 is_stmt 1 view -0
|
||
1030 .cfi_startproc
|
||
1031 @ args = 0, pretend = 0, frame = 0
|
||
1032 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1033 @ link register save eliminated.
|
||
1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
|
||
1034 .loc 1 1398 3 view .LVU235
|
||
1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear the wake up event received from wake up pin x */
|
||
1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->WKUPCR, WakeUpFlag);
|
||
1035 .loc 1 1401 3 view .LVU236
|
||
1036 0000 054B ldr r3, .L90
|
||
1037 0002 1A6A ldr r2, [r3, #32]
|
||
1038 0004 0243 orrs r2, r2, r0
|
||
1039 0006 1A62 str r2, [r3, #32]
|
||
1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the wake up event is well cleared */
|
||
1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->WKUPFR & WakeUpFlag) != 0U)
|
||
1040 .loc 1 1404 3 view .LVU237
|
||
1041 .loc 1 1404 11 is_stmt 0 view .LVU238
|
||
1042 0008 5B6A ldr r3, [r3, #36]
|
||
1043 .loc 1 1404 6 view .LVU239
|
||
1044 000a 0342 tst r3, r0
|
||
1045 000c 01D1 bne .L89
|
||
1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 62
|
||
|
||
|
||
1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
1046 .loc 1 1409 10 view .LVU240
|
||
1047 000e 0020 movs r0, #0
|
||
1048 .LVL56:
|
||
1049 .loc 1 1409 10 view .LVU241
|
||
1050 0010 7047 bx lr
|
||
1051 .LVL57:
|
||
1052 .L89:
|
||
1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1053 .loc 1 1406 12 view .LVU242
|
||
1054 0012 0120 movs r0, #1
|
||
1055 .LVL58:
|
||
1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1056 .loc 1 1410 1 view .LVU243
|
||
1057 0014 7047 bx lr
|
||
1058 .L91:
|
||
1059 0016 00BF .align 2
|
||
1060 .L90:
|
||
1061 0018 00480258 .word 1476544512
|
||
1062 .cfi_endproc
|
||
1063 .LFE156:
|
||
1065 .section .text.HAL_PWREx_WKUP1_Callback,"ax",%progbits
|
||
1066 .align 1
|
||
1067 .weak HAL_PWREx_WKUP1_Callback
|
||
1068 .syntax unified
|
||
1069 .thumb
|
||
1070 .thumb_func
|
||
1071 .fpu fpv5-d16
|
||
1073 HAL_PWREx_WKUP1_Callback:
|
||
1074 .LFB158:
|
||
1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief This function handles the PWR WAKEUP PIN interrupt request.
|
||
1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API should be called under the WAKEUP_PIN_IRQHandler().
|
||
1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
|
||
1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wakeup pin EXTI line interrupt detected */
|
||
1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
|
||
1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF1 flag */
|
||
1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
|
||
1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP1 interrupt user callback */
|
||
1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP1_Callback ();
|
||
1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
|
||
1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF2 flag */
|
||
1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
|
||
1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP2 interrupt user callback */
|
||
1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP2_Callback ();
|
||
ARM GAS /tmp/ccMGXY28.s page 63
|
||
|
||
|
||
1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF3)
|
||
1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
|
||
1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF3 flag */
|
||
1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
|
||
1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP3 interrupt user callback */
|
||
1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP3_Callback ();
|
||
1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF3) */
|
||
1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
|
||
1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF4 flag */
|
||
1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
|
||
1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP4 interrupt user callback */
|
||
1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP4_Callback ();
|
||
1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF5)
|
||
1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
|
||
1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF5 flag */
|
||
1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
|
||
1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP5 interrupt user callback */
|
||
1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP5_Callback ();
|
||
1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF5) */
|
||
1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF6 flag */
|
||
1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
|
||
1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP6 interrupt user callback */
|
||
1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP6_Callback ();
|
||
1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP1 interrupt callback.
|
||
1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP1_Callback (void)
|
||
1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1075 .loc 1 1479 1 is_stmt 1 view -0
|
||
1076 .cfi_startproc
|
||
1077 @ args = 0, pretend = 0, frame = 0
|
||
1078 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1079 @ link register save eliminated.
|
||
1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP1Callback can be implemented in the user file
|
||
1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1080 .loc 1 1483 1 view .LVU245
|
||
1081 0000 7047 bx lr
|
||
1082 .cfi_endproc
|
||
ARM GAS /tmp/ccMGXY28.s page 64
|
||
|
||
|
||
1083 .LFE158:
|
||
1085 .section .text.HAL_PWREx_WKUP2_Callback,"ax",%progbits
|
||
1086 .align 1
|
||
1087 .weak HAL_PWREx_WKUP2_Callback
|
||
1088 .syntax unified
|
||
1089 .thumb
|
||
1090 .thumb_func
|
||
1091 .fpu fpv5-d16
|
||
1093 HAL_PWREx_WKUP2_Callback:
|
||
1094 .LFB159:
|
||
1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP2 interrupt callback.
|
||
1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP2_Callback (void)
|
||
1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1095 .loc 1 1490 1 view -0
|
||
1096 .cfi_startproc
|
||
1097 @ args = 0, pretend = 0, frame = 0
|
||
1098 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1099 @ link register save eliminated.
|
||
1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP2Callback can be implemented in the user file
|
||
1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1100 .loc 1 1494 1 view .LVU247
|
||
1101 0000 7047 bx lr
|
||
1102 .cfi_endproc
|
||
1103 .LFE159:
|
||
1105 .section .text.HAL_PWREx_WKUP3_Callback,"ax",%progbits
|
||
1106 .align 1
|
||
1107 .weak HAL_PWREx_WKUP3_Callback
|
||
1108 .syntax unified
|
||
1109 .thumb
|
||
1110 .thumb_func
|
||
1111 .fpu fpv5-d16
|
||
1113 HAL_PWREx_WKUP3_Callback:
|
||
1114 .LFB160:
|
||
1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF3)
|
||
1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP3 interrupt callback.
|
||
1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP3_Callback (void)
|
||
1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1115 .loc 1 1502 1 view -0
|
||
1116 .cfi_startproc
|
||
1117 @ args = 0, pretend = 0, frame = 0
|
||
1118 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1119 @ link register save eliminated.
|
||
1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP3Callback can be implemented in the user file
|
||
1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1120 .loc 1 1506 1 view .LVU249
|
||
ARM GAS /tmp/ccMGXY28.s page 65
|
||
|
||
|
||
1121 0000 7047 bx lr
|
||
1122 .cfi_endproc
|
||
1123 .LFE160:
|
||
1125 .section .text.HAL_PWREx_WKUP4_Callback,"ax",%progbits
|
||
1126 .align 1
|
||
1127 .weak HAL_PWREx_WKUP4_Callback
|
||
1128 .syntax unified
|
||
1129 .thumb
|
||
1130 .thumb_func
|
||
1131 .fpu fpv5-d16
|
||
1133 HAL_PWREx_WKUP4_Callback:
|
||
1134 .LFB161:
|
||
1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF3) */
|
||
1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP4 interrupt callback.
|
||
1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP4_Callback (void)
|
||
1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1135 .loc 1 1514 1 view -0
|
||
1136 .cfi_startproc
|
||
1137 @ args = 0, pretend = 0, frame = 0
|
||
1138 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1139 @ link register save eliminated.
|
||
1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP4Callback can be implemented in the user file
|
||
1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1140 .loc 1 1518 1 view .LVU251
|
||
1141 0000 7047 bx lr
|
||
1142 .cfi_endproc
|
||
1143 .LFE161:
|
||
1145 .section .text.HAL_PWREx_WKUP5_Callback,"ax",%progbits
|
||
1146 .align 1
|
||
1147 .weak HAL_PWREx_WKUP5_Callback
|
||
1148 .syntax unified
|
||
1149 .thumb
|
||
1150 .thumb_func
|
||
1151 .fpu fpv5-d16
|
||
1153 HAL_PWREx_WKUP5_Callback:
|
||
1154 .LFB162:
|
||
1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF5)
|
||
1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP5 interrupt callback.
|
||
1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP5_Callback (void)
|
||
1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1155 .loc 1 1526 1 view -0
|
||
1156 .cfi_startproc
|
||
1157 @ args = 0, pretend = 0, frame = 0
|
||
1158 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1159 @ link register save eliminated.
|
||
1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP5Callback can be implemented in the user file
|
||
ARM GAS /tmp/ccMGXY28.s page 66
|
||
|
||
|
||
1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1160 .loc 1 1530 1 view .LVU253
|
||
1161 0000 7047 bx lr
|
||
1162 .cfi_endproc
|
||
1163 .LFE162:
|
||
1165 .section .text.HAL_PWREx_WKUP6_Callback,"ax",%progbits
|
||
1166 .align 1
|
||
1167 .weak HAL_PWREx_WKUP6_Callback
|
||
1168 .syntax unified
|
||
1169 .thumb
|
||
1170 .thumb_func
|
||
1171 .fpu fpv5-d16
|
||
1173 HAL_PWREx_WKUP6_Callback:
|
||
1174 .LFB163:
|
||
1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF5) */
|
||
1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP6 interrupt callback.
|
||
1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP6_Callback (void)
|
||
1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1175 .loc 1 1538 1 view -0
|
||
1176 .cfi_startproc
|
||
1177 @ args = 0, pretend = 0, frame = 0
|
||
1178 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1179 @ link register save eliminated.
|
||
1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP6Callback can be implemented in the user file
|
||
1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1180 .loc 1 1542 1 view .LVU255
|
||
1181 0000 7047 bx lr
|
||
1182 .cfi_endproc
|
||
1183 .LFE163:
|
||
1185 .section .text.HAL_PWREx_WAKEUP_PIN_IRQHandler,"ax",%progbits
|
||
1186 .align 1
|
||
1187 .global HAL_PWREx_WAKEUP_PIN_IRQHandler
|
||
1188 .syntax unified
|
||
1189 .thumb
|
||
1190 .thumb_func
|
||
1191 .fpu fpv5-d16
|
||
1193 HAL_PWREx_WAKEUP_PIN_IRQHandler:
|
||
1194 .LFB157:
|
||
1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wakeup pin EXTI line interrupt detected */
|
||
1195 .loc 1 1418 1 view -0
|
||
1196 .cfi_startproc
|
||
1197 @ args = 0, pretend = 0, frame = 0
|
||
1198 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1199 0000 08B5 push {r3, lr}
|
||
1200 .LCFI8:
|
||
1201 .cfi_def_cfa_offset 8
|
||
1202 .cfi_offset 3, -8
|
||
1203 .cfi_offset 14, -4
|
||
1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1204 .loc 1 1420 3 view .LVU257
|
||
ARM GAS /tmp/ccMGXY28.s page 67
|
||
|
||
|
||
1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1205 .loc 1 1420 7 is_stmt 0 view .LVU258
|
||
1206 0002 244B ldr r3, .L110
|
||
1207 0004 5B6A ldr r3, [r3, #36]
|
||
1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1208 .loc 1 1420 6 view .LVU259
|
||
1209 0006 13F0010F tst r3, #1
|
||
1210 000a 1BD1 bne .L106
|
||
1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1211 .loc 1 1428 8 is_stmt 1 view .LVU260
|
||
1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1212 .loc 1 1428 12 is_stmt 0 view .LVU261
|
||
1213 000c 214B ldr r3, .L110
|
||
1214 000e 5B6A ldr r3, [r3, #36]
|
||
1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1215 .loc 1 1428 11 view .LVU262
|
||
1216 0010 13F0020F tst r3, #2
|
||
1217 0014 1ED1 bne .L107
|
||
1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1218 .loc 1 1437 8 is_stmt 1 view .LVU263
|
||
1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1219 .loc 1 1437 12 is_stmt 0 view .LVU264
|
||
1220 0016 1F4B ldr r3, .L110
|
||
1221 0018 5B6A ldr r3, [r3, #36]
|
||
1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1222 .loc 1 1437 11 view .LVU265
|
||
1223 001a 13F0040F tst r3, #4
|
||
1224 001e 21D1 bne .L108
|
||
1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1225 .loc 1 1446 8 is_stmt 1 view .LVU266
|
||
1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1226 .loc 1 1446 12 is_stmt 0 view .LVU267
|
||
1227 0020 1C4B ldr r3, .L110
|
||
1228 0022 5B6A ldr r3, [r3, #36]
|
||
1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1229 .loc 1 1446 11 view .LVU268
|
||
1230 0024 13F0080F tst r3, #8
|
||
1231 0028 24D1 bne .L109
|
||
1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1232 .loc 1 1455 8 is_stmt 1 view .LVU269
|
||
1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1233 .loc 1 1455 12 is_stmt 0 view .LVU270
|
||
1234 002a 1A4B ldr r3, .L110
|
||
1235 002c 5B6A ldr r3, [r3, #36]
|
||
1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1236 .loc 1 1455 11 view .LVU271
|
||
1237 002e 13F0100F tst r3, #16
|
||
1238 0032 27D0 beq .L104
|
||
1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1239 .loc 1 1458 5 is_stmt 1 view .LVU272
|
||
1240 0034 174A ldr r2, .L110
|
||
1241 0036 136A ldr r3, [r2, #32]
|
||
1242 0038 43F01003 orr r3, r3, #16
|
||
1243 003c 1362 str r3, [r2, #32]
|
||
1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1244 .loc 1 1461 5 view .LVU273
|
||
1245 003e FFF7FEFF bl HAL_PWREx_WKUP5_Callback
|
||
ARM GAS /tmp/ccMGXY28.s page 68
|
||
|
||
|
||
1246 .LVL59:
|
||
1247 0042 06E0 b .L98
|
||
1248 .L106:
|
||
1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1249 .loc 1 1423 5 view .LVU274
|
||
1250 0044 134A ldr r2, .L110
|
||
1251 0046 136A ldr r3, [r2, #32]
|
||
1252 0048 43F00103 orr r3, r3, #1
|
||
1253 004c 1362 str r3, [r2, #32]
|
||
1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1254 .loc 1 1426 5 view .LVU275
|
||
1255 004e FFF7FEFF bl HAL_PWREx_WKUP1_Callback
|
||
1256 .LVL60:
|
||
1257 .L98:
|
||
1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1258 .loc 1 1472 1 is_stmt 0 view .LVU276
|
||
1259 0052 08BD pop {r3, pc}
|
||
1260 .L107:
|
||
1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1261 .loc 1 1431 5 is_stmt 1 view .LVU277
|
||
1262 0054 0F4A ldr r2, .L110
|
||
1263 0056 136A ldr r3, [r2, #32]
|
||
1264 0058 43F00203 orr r3, r3, #2
|
||
1265 005c 1362 str r3, [r2, #32]
|
||
1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1266 .loc 1 1434 5 view .LVU278
|
||
1267 005e FFF7FEFF bl HAL_PWREx_WKUP2_Callback
|
||
1268 .LVL61:
|
||
1269 0062 F6E7 b .L98
|
||
1270 .L108:
|
||
1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1271 .loc 1 1440 5 view .LVU279
|
||
1272 0064 0B4A ldr r2, .L110
|
||
1273 0066 136A ldr r3, [r2, #32]
|
||
1274 0068 43F00403 orr r3, r3, #4
|
||
1275 006c 1362 str r3, [r2, #32]
|
||
1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1276 .loc 1 1443 5 view .LVU280
|
||
1277 006e FFF7FEFF bl HAL_PWREx_WKUP3_Callback
|
||
1278 .LVL62:
|
||
1279 0072 EEE7 b .L98
|
||
1280 .L109:
|
||
1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1281 .loc 1 1449 5 view .LVU281
|
||
1282 0074 074A ldr r2, .L110
|
||
1283 0076 136A ldr r3, [r2, #32]
|
||
1284 0078 43F00803 orr r3, r3, #8
|
||
1285 007c 1362 str r3, [r2, #32]
|
||
1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1286 .loc 1 1452 5 view .LVU282
|
||
1287 007e FFF7FEFF bl HAL_PWREx_WKUP4_Callback
|
||
1288 .LVL63:
|
||
1289 0082 E6E7 b .L98
|
||
1290 .L104:
|
||
1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1291 .loc 1 1467 5 view .LVU283
|
||
1292 0084 034A ldr r2, .L110
|
||
ARM GAS /tmp/ccMGXY28.s page 69
|
||
|
||
|
||
1293 0086 136A ldr r3, [r2, #32]
|
||
1294 0088 43F02003 orr r3, r3, #32
|
||
1295 008c 1362 str r3, [r2, #32]
|
||
1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1296 .loc 1 1470 5 view .LVU284
|
||
1297 008e FFF7FEFF bl HAL_PWREx_WKUP6_Callback
|
||
1298 .LVL64:
|
||
1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1299 .loc 1 1472 1 is_stmt 0 view .LVU285
|
||
1300 0092 DEE7 b .L98
|
||
1301 .L111:
|
||
1302 .align 2
|
||
1303 .L110:
|
||
1304 0094 00480258 .word 1476544512
|
||
1305 .cfi_endproc
|
||
1306 .LFE157:
|
||
1308 .section .text.HAL_PWREx_EnableBkUpReg,"ax",%progbits
|
||
1309 .align 1
|
||
1310 .global HAL_PWREx_EnableBkUpReg
|
||
1311 .syntax unified
|
||
1312 .thumb
|
||
1313 .thumb_func
|
||
1314 .fpu fpv5-d16
|
||
1316 HAL_PWREx_EnableBkUpReg:
|
||
1317 .LFB164:
|
||
1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
|
||
1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Peripherals control functions
|
||
1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
|
||
1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
|
||
1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Peripherals control functions #####
|
||
1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Main and Backup Regulators configuration ***
|
||
1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ================================================
|
||
1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
|
||
1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
|
||
1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** content is retained even in Standby or VBAT mode when the low power
|
||
1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** backup regulator is enabled. It can be considered as an internal
|
||
1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EEPROM when VBAT is always present. You can use the
|
||
1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableBkUpReg() function to enable the low power backup
|
||
1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regulator.
|
||
1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) When the backup domain is supplied by VDD (analog switch connected to
|
||
1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VDD) the backup SRAM is powered from VDD which replaces the VBAT power
|
||
1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** supply to save battery life.
|
||
1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
|
||
1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** protected to prevent confidential data, such as cryptographic private
|
||
1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** key, from being accessed. The backup SRAM can be erased only through
|
||
1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the Flash interface when a protection level change from level 1 to
|
||
1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** level 0 is requested.
|
||
1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** -@- Refer to the description of Read protection (RDP) in the Flash
|
||
1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** programming manual.
|
||
ARM GAS /tmp/ccMGXY28.s page 70
|
||
|
||
|
||
1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The main internal regulator can be configured to have a tradeoff
|
||
1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** between performance and power consumption when the device does not
|
||
1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** operate at the maximum frequency. This is done through
|
||
1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
|
||
1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** bit in PWR_D3CR register.
|
||
1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The main internal regulator can be configured to operate in Low Power
|
||
1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode when the system enters STOP mode to further reduce power
|
||
1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** consumption.
|
||
1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
|
||
1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function which configure the SVOS bit in PWR_CR1 register.
|
||
1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The selected SVOS4 and SVOS5 levels add an additional startup delay
|
||
1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** when exiting from system Stop mode.
|
||
1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** -@- Refer to the product datasheets for more details.
|
||
1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** USB Regulator configuration ***
|
||
1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===================================
|
||
1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The USB transceivers are supplied from a dedicated VDD33USB supply
|
||
1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** that can be provided either by the integrated USB regulator, or by an
|
||
1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** external USB supply.
|
||
1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
|
||
1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VDD33USB is then provided from the USB regulator.
|
||
1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) When the USB regulator is enabled, the VDD33USB supply level detector
|
||
1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** shall be enabled through HAL_PWREx_EnableUSBVoltageDetector()
|
||
1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function.
|
||
1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
|
||
1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function and VDD33USB can be provided from an external supply. In this
|
||
1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** case VDD33USB and VDD50USB shall be connected together.
|
||
1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** VBAT battery charging ***
|
||
1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================
|
||
1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) When VDD is present, the external battery connected to VBAT can be
|
||
1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** charged through an internal resistance. VBAT charging can be performed
|
||
1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
|
||
1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
|
||
1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (ResistorValue) function with:
|
||
1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) ResistorValue:
|
||
1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
|
||
1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
|
||
1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
|
||
1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function.
|
||
1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
|
||
1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Backup Regulator.
|
||
1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
|
||
1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1318 .loc 1 1627 1 is_stmt 1 view -0
|
||
1319 .cfi_startproc
|
||
1320 @ args = 0, pretend = 0, frame = 0
|
||
1321 @ frame_needed = 0, uses_anonymous_args = 0
|
||
ARM GAS /tmp/ccMGXY28.s page 71
|
||
|
||
|
||
1322 0000 10B5 push {r4, lr}
|
||
1323 .LCFI9:
|
||
1324 .cfi_def_cfa_offset 8
|
||
1325 .cfi_offset 4, -8
|
||
1326 .cfi_offset 14, -4
|
||
1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
1327 .loc 1 1628 3 view .LVU287
|
||
1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Backup regulator */
|
||
1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR2, PWR_CR2_BREN);
|
||
1328 .loc 1 1631 3 view .LVU288
|
||
1329 0002 0B4A ldr r2, .L119
|
||
1330 0004 9368 ldr r3, [r2, #8]
|
||
1331 0006 43F00103 orr r3, r3, #1
|
||
1332 000a 9360 str r3, [r2, #8]
|
||
1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
1333 .loc 1 1634 3 view .LVU289
|
||
1334 .loc 1 1634 15 is_stmt 0 view .LVU290
|
||
1335 000c FFF7FEFF bl HAL_GetTick
|
||
1336 .LVL65:
|
||
1337 0010 0446 mov r4, r0
|
||
1338 .LVL66:
|
||
1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is set */
|
||
1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
|
||
1339 .loc 1 1637 3 is_stmt 1 view .LVU291
|
||
1340 .L113:
|
||
1341 .loc 1 1637 9 view .LVU292
|
||
1342 .loc 1 1637 10 is_stmt 0 view .LVU293
|
||
1343 0012 074B ldr r3, .L119
|
||
1344 0014 9B68 ldr r3, [r3, #8]
|
||
1345 .loc 1 1637 9 view .LVU294
|
||
1346 0016 13F4803F tst r3, #65536
|
||
1347 001a 07D1 bne .L118
|
||
1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
|
||
1348 .loc 1 1639 5 is_stmt 1 view .LVU295
|
||
1349 .loc 1 1639 10 is_stmt 0 view .LVU296
|
||
1350 001c FFF7FEFF bl HAL_GetTick
|
||
1351 .LVL67:
|
||
1352 .loc 1 1639 24 view .LVU297
|
||
1353 0020 001B subs r0, r0, r4
|
||
1354 .loc 1 1639 8 view .LVU298
|
||
1355 0022 B0F57A7F cmp r0, #1000
|
||
1356 0026 F4D9 bls .L113
|
||
1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
1357 .loc 1 1641 14 view .LVU299
|
||
1358 0028 0120 movs r0, #1
|
||
1359 002a 00E0 b .L114
|
||
1360 .L118:
|
||
1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
ARM GAS /tmp/ccMGXY28.s page 72
|
||
|
||
|
||
1361 .loc 1 1645 10 view .LVU300
|
||
1362 002c 0020 movs r0, #0
|
||
1363 .L114:
|
||
1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1364 .loc 1 1646 1 view .LVU301
|
||
1365 002e 10BD pop {r4, pc}
|
||
1366 .LVL68:
|
||
1367 .L120:
|
||
1368 .loc 1 1646 1 view .LVU302
|
||
1369 .align 2
|
||
1370 .L119:
|
||
1371 0030 00480258 .word 1476544512
|
||
1372 .cfi_endproc
|
||
1373 .LFE164:
|
||
1375 .section .text.HAL_PWREx_DisableBkUpReg,"ax",%progbits
|
||
1376 .align 1
|
||
1377 .global HAL_PWREx_DisableBkUpReg
|
||
1378 .syntax unified
|
||
1379 .thumb
|
||
1380 .thumb_func
|
||
1381 .fpu fpv5-d16
|
||
1383 HAL_PWREx_DisableBkUpReg:
|
||
1384 .LFB165:
|
||
1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Backup Regulator.
|
||
1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
|
||
1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1385 .loc 1 1653 1 is_stmt 1 view -0
|
||
1386 .cfi_startproc
|
||
1387 @ args = 0, pretend = 0, frame = 0
|
||
1388 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1389 0000 10B5 push {r4, lr}
|
||
1390 .LCFI10:
|
||
1391 .cfi_def_cfa_offset 8
|
||
1392 .cfi_offset 4, -8
|
||
1393 .cfi_offset 14, -4
|
||
1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
1394 .loc 1 1654 3 view .LVU304
|
||
1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Backup regulator */
|
||
1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
|
||
1395 .loc 1 1657 3 view .LVU305
|
||
1396 0002 0B4A ldr r2, .L128
|
||
1397 0004 9368 ldr r3, [r2, #8]
|
||
1398 0006 23F00103 bic r3, r3, #1
|
||
1399 000a 9360 str r3, [r2, #8]
|
||
1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
1400 .loc 1 1660 3 view .LVU306
|
||
1401 .loc 1 1660 15 is_stmt 0 view .LVU307
|
||
1402 000c FFF7FEFF bl HAL_GetTick
|
||
1403 .LVL69:
|
||
1404 0010 0446 mov r4, r0
|
||
ARM GAS /tmp/ccMGXY28.s page 73
|
||
|
||
|
||
1405 .LVL70:
|
||
1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is reset */
|
||
1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
|
||
1406 .loc 1 1663 3 is_stmt 1 view .LVU308
|
||
1407 .L122:
|
||
1408 .loc 1 1663 9 view .LVU309
|
||
1409 .loc 1 1663 10 is_stmt 0 view .LVU310
|
||
1410 0012 074B ldr r3, .L128
|
||
1411 0014 9B68 ldr r3, [r3, #8]
|
||
1412 .loc 1 1663 9 view .LVU311
|
||
1413 0016 13F4803F tst r3, #65536
|
||
1414 001a 07D0 beq .L127
|
||
1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
|
||
1415 .loc 1 1665 5 is_stmt 1 view .LVU312
|
||
1416 .loc 1 1665 10 is_stmt 0 view .LVU313
|
||
1417 001c FFF7FEFF bl HAL_GetTick
|
||
1418 .LVL71:
|
||
1419 .loc 1 1665 24 view .LVU314
|
||
1420 0020 001B subs r0, r0, r4
|
||
1421 .loc 1 1665 8 view .LVU315
|
||
1422 0022 B0F57A7F cmp r0, #1000
|
||
1423 0026 F4D9 bls .L122
|
||
1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
1424 .loc 1 1667 14 view .LVU316
|
||
1425 0028 0120 movs r0, #1
|
||
1426 002a 00E0 b .L123
|
||
1427 .L127:
|
||
1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
1428 .loc 1 1671 10 view .LVU317
|
||
1429 002c 0020 movs r0, #0
|
||
1430 .L123:
|
||
1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1431 .loc 1 1672 1 view .LVU318
|
||
1432 002e 10BD pop {r4, pc}
|
||
1433 .LVL72:
|
||
1434 .L129:
|
||
1435 .loc 1 1672 1 view .LVU319
|
||
1436 .align 2
|
||
1437 .L128:
|
||
1438 0030 00480258 .word 1476544512
|
||
1439 .cfi_endproc
|
||
1440 .LFE165:
|
||
1442 .section .text.HAL_PWREx_EnableUSBReg,"ax",%progbits
|
||
1443 .align 1
|
||
1444 .global HAL_PWREx_EnableUSBReg
|
||
1445 .syntax unified
|
||
1446 .thumb
|
||
1447 .thumb_func
|
||
1448 .fpu fpv5-d16
|
||
1450 HAL_PWREx_EnableUSBReg:
|
||
1451 .LFB166:
|
||
ARM GAS /tmp/ccMGXY28.s page 74
|
||
|
||
|
||
1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the USB Regulator.
|
||
1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
|
||
1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1452 .loc 1 1679 1 is_stmt 1 view -0
|
||
1453 .cfi_startproc
|
||
1454 @ args = 0, pretend = 0, frame = 0
|
||
1455 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1456 0000 10B5 push {r4, lr}
|
||
1457 .LCFI11:
|
||
1458 .cfi_def_cfa_offset 8
|
||
1459 .cfi_offset 4, -8
|
||
1460 .cfi_offset 14, -4
|
||
1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
1461 .loc 1 1680 3 view .LVU321
|
||
1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the USB regulator */
|
||
1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
|
||
1462 .loc 1 1683 3 view .LVU322
|
||
1463 0002 0B4A ldr r2, .L137
|
||
1464 0004 D368 ldr r3, [r2, #12]
|
||
1465 0006 43F00073 orr r3, r3, #33554432
|
||
1466 000a D360 str r3, [r2, #12]
|
||
1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
1467 .loc 1 1686 3 view .LVU323
|
||
1468 .loc 1 1686 15 is_stmt 0 view .LVU324
|
||
1469 000c FFF7FEFF bl HAL_GetTick
|
||
1470 .LVL73:
|
||
1471 0010 0446 mov r4, r0
|
||
1472 .LVL74:
|
||
1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till the USB regulator ready flag is set */
|
||
1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
|
||
1473 .loc 1 1689 3 is_stmt 1 view .LVU325
|
||
1474 .L131:
|
||
1475 .loc 1 1689 9 view .LVU326
|
||
1476 .loc 1 1689 10 is_stmt 0 view .LVU327
|
||
1477 0012 074B ldr r3, .L137
|
||
1478 0014 DB68 ldr r3, [r3, #12]
|
||
1479 .loc 1 1689 9 view .LVU328
|
||
1480 0016 13F0806F tst r3, #67108864
|
||
1481 001a 07D1 bne .L136
|
||
1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
|
||
1482 .loc 1 1691 5 is_stmt 1 view .LVU329
|
||
1483 .loc 1 1691 10 is_stmt 0 view .LVU330
|
||
1484 001c FFF7FEFF bl HAL_GetTick
|
||
1485 .LVL75:
|
||
1486 .loc 1 1691 24 view .LVU331
|
||
1487 0020 001B subs r0, r0, r4
|
||
1488 .loc 1 1691 8 view .LVU332
|
||
1489 0022 B0F57A7F cmp r0, #1000
|
||
ARM GAS /tmp/ccMGXY28.s page 75
|
||
|
||
|
||
1490 0026 F4D9 bls .L131
|
||
1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
1491 .loc 1 1693 14 view .LVU333
|
||
1492 0028 0120 movs r0, #1
|
||
1493 002a 00E0 b .L132
|
||
1494 .L136:
|
||
1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
1495 .loc 1 1697 10 view .LVU334
|
||
1496 002c 0020 movs r0, #0
|
||
1497 .L132:
|
||
1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1498 .loc 1 1698 1 view .LVU335
|
||
1499 002e 10BD pop {r4, pc}
|
||
1500 .LVL76:
|
||
1501 .L138:
|
||
1502 .loc 1 1698 1 view .LVU336
|
||
1503 .align 2
|
||
1504 .L137:
|
||
1505 0030 00480258 .word 1476544512
|
||
1506 .cfi_endproc
|
||
1507 .LFE166:
|
||
1509 .section .text.HAL_PWREx_DisableUSBReg,"ax",%progbits
|
||
1510 .align 1
|
||
1511 .global HAL_PWREx_DisableUSBReg
|
||
1512 .syntax unified
|
||
1513 .thumb
|
||
1514 .thumb_func
|
||
1515 .fpu fpv5-d16
|
||
1517 HAL_PWREx_DisableUSBReg:
|
||
1518 .LFB167:
|
||
1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the USB Regulator.
|
||
1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
|
||
1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1519 .loc 1 1705 1 is_stmt 1 view -0
|
||
1520 .cfi_startproc
|
||
1521 @ args = 0, pretend = 0, frame = 0
|
||
1522 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1523 0000 10B5 push {r4, lr}
|
||
1524 .LCFI12:
|
||
1525 .cfi_def_cfa_offset 8
|
||
1526 .cfi_offset 4, -8
|
||
1527 .cfi_offset 14, -4
|
||
1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart;
|
||
1528 .loc 1 1706 3 view .LVU338
|
||
1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the USB regulator */
|
||
1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
|
||
1529 .loc 1 1709 3 view .LVU339
|
||
1530 0002 0B4A ldr r2, .L146
|
||
ARM GAS /tmp/ccMGXY28.s page 76
|
||
|
||
|
||
1531 0004 D368 ldr r3, [r2, #12]
|
||
1532 0006 23F00073 bic r3, r3, #33554432
|
||
1533 000a D360 str r3, [r2, #12]
|
||
1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */
|
||
1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick ();
|
||
1534 .loc 1 1712 3 view .LVU340
|
||
1535 .loc 1 1712 15 is_stmt 0 view .LVU341
|
||
1536 000c FFF7FEFF bl HAL_GetTick
|
||
1537 .LVL77:
|
||
1538 0010 0446 mov r4, r0
|
||
1539 .LVL78:
|
||
1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till the USB regulator ready flag is reset */
|
||
1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
|
||
1540 .loc 1 1715 3 is_stmt 1 view .LVU342
|
||
1541 .L140:
|
||
1542 .loc 1 1715 8 view .LVU343
|
||
1543 .loc 1 1715 9 is_stmt 0 view .LVU344
|
||
1544 0012 074B ldr r3, .L146
|
||
1545 0014 DB68 ldr r3, [r3, #12]
|
||
1546 .loc 1 1715 8 view .LVU345
|
||
1547 0016 13F0806F tst r3, #67108864
|
||
1548 001a 07D0 beq .L145
|
||
1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
|
||
1549 .loc 1 1717 5 is_stmt 1 view .LVU346
|
||
1550 .loc 1 1717 10 is_stmt 0 view .LVU347
|
||
1551 001c FFF7FEFF bl HAL_GetTick
|
||
1552 .LVL79:
|
||
1553 .loc 1 1717 24 view .LVU348
|
||
1554 0020 001B subs r0, r0, r4
|
||
1555 .loc 1 1717 8 view .LVU349
|
||
1556 0022 B0F57A7F cmp r0, #1000
|
||
1557 0026 F4D9 bls .L140
|
||
1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR;
|
||
1558 .loc 1 1719 14 view .LVU350
|
||
1559 0028 0120 movs r0, #1
|
||
1560 002a 00E0 b .L141
|
||
1561 .L145:
|
||
1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK;
|
||
1562 .loc 1 1723 10 view .LVU351
|
||
1563 002c 0020 movs r0, #0
|
||
1564 .L141:
|
||
1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1565 .loc 1 1724 1 view .LVU352
|
||
1566 002e 10BD pop {r4, pc}
|
||
1567 .LVL80:
|
||
1568 .L147:
|
||
1569 .loc 1 1724 1 view .LVU353
|
||
1570 .align 2
|
||
1571 .L146:
|
||
1572 0030 00480258 .word 1476544512
|
||
ARM GAS /tmp/ccMGXY28.s page 77
|
||
|
||
|
||
1573 .cfi_endproc
|
||
1574 .LFE167:
|
||
1576 .section .text.HAL_PWREx_EnableUSBVoltageDetector,"ax",%progbits
|
||
1577 .align 1
|
||
1578 .global HAL_PWREx_EnableUSBVoltageDetector
|
||
1579 .syntax unified
|
||
1580 .thumb
|
||
1581 .thumb_func
|
||
1582 .fpu fpv5-d16
|
||
1584 HAL_PWREx_EnableUSBVoltageDetector:
|
||
1585 .LFB168:
|
||
1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the USB voltage level detector.
|
||
1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableUSBVoltageDetector (void)
|
||
1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1586 .loc 1 1731 1 is_stmt 1 view -0
|
||
1587 .cfi_startproc
|
||
1588 @ args = 0, pretend = 0, frame = 0
|
||
1589 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1590 @ link register save eliminated.
|
||
1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the USB voltage detector */
|
||
1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
|
||
1591 .loc 1 1733 3 view .LVU355
|
||
1592 0000 024A ldr r2, .L149
|
||
1593 0002 D368 ldr r3, [r2, #12]
|
||
1594 0004 43F08073 orr r3, r3, #16777216
|
||
1595 0008 D360 str r3, [r2, #12]
|
||
1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1596 .loc 1 1734 1 is_stmt 0 view .LVU356
|
||
1597 000a 7047 bx lr
|
||
1598 .L150:
|
||
1599 .align 2
|
||
1600 .L149:
|
||
1601 000c 00480258 .word 1476544512
|
||
1602 .cfi_endproc
|
||
1603 .LFE168:
|
||
1605 .section .text.HAL_PWREx_DisableUSBVoltageDetector,"ax",%progbits
|
||
1606 .align 1
|
||
1607 .global HAL_PWREx_DisableUSBVoltageDetector
|
||
1608 .syntax unified
|
||
1609 .thumb
|
||
1610 .thumb_func
|
||
1611 .fpu fpv5-d16
|
||
1613 HAL_PWREx_DisableUSBVoltageDetector:
|
||
1614 .LFB169:
|
||
1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the USB voltage level detector.
|
||
1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableUSBVoltageDetector (void)
|
||
1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1615 .loc 1 1741 1 is_stmt 1 view -0
|
||
1616 .cfi_startproc
|
||
ARM GAS /tmp/ccMGXY28.s page 78
|
||
|
||
|
||
1617 @ args = 0, pretend = 0, frame = 0
|
||
1618 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1619 @ link register save eliminated.
|
||
1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the USB voltage detector */
|
||
1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
|
||
1620 .loc 1 1743 3 view .LVU358
|
||
1621 0000 024A ldr r2, .L152
|
||
1622 0002 D368 ldr r3, [r2, #12]
|
||
1623 0004 23F08073 bic r3, r3, #16777216
|
||
1624 0008 D360 str r3, [r2, #12]
|
||
1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1625 .loc 1 1744 1 is_stmt 0 view .LVU359
|
||
1626 000a 7047 bx lr
|
||
1627 .L153:
|
||
1628 .align 2
|
||
1629 .L152:
|
||
1630 000c 00480258 .word 1476544512
|
||
1631 .cfi_endproc
|
||
1632 .LFE169:
|
||
1634 .section .text.HAL_PWREx_EnableBatteryCharging,"ax",%progbits
|
||
1635 .align 1
|
||
1636 .global HAL_PWREx_EnableBatteryCharging
|
||
1637 .syntax unified
|
||
1638 .thumb
|
||
1639 .thumb_func
|
||
1640 .fpu fpv5-d16
|
||
1642 HAL_PWREx_EnableBatteryCharging:
|
||
1643 .LVL81:
|
||
1644 .LFB170:
|
||
1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Battery charging.
|
||
1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When VDD is present, charge the external battery through an internal
|
||
1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * resistor.
|
||
1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param ResistorValue : Specifies the charging resistor.
|
||
1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values :
|
||
1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
|
||
1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
|
||
1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
|
||
1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1645 .loc 1 1757 1 is_stmt 1 view -0
|
||
1646 .cfi_startproc
|
||
1647 @ args = 0, pretend = 0, frame = 0
|
||
1648 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1649 @ link register save eliminated.
|
||
1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */
|
||
1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
|
||
1650 .loc 1 1759 3 view .LVU361
|
||
1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Specify the charging resistor */
|
||
1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
|
||
1651 .loc 1 1762 3 view .LVU362
|
||
1652 0000 054A ldr r2, .L155
|
||
1653 0002 D368 ldr r3, [r2, #12]
|
||
1654 0004 23F40073 bic r3, r3, #512
|
||
ARM GAS /tmp/ccMGXY28.s page 79
|
||
|
||
|
||
1655 0008 0343 orrs r3, r3, r0
|
||
1656 000a D360 str r3, [r2, #12]
|
||
1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Battery charging */
|
||
1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR3, PWR_CR3_VBE);
|
||
1657 .loc 1 1765 3 view .LVU363
|
||
1658 000c D368 ldr r3, [r2, #12]
|
||
1659 000e 43F48073 orr r3, r3, #256
|
||
1660 0012 D360 str r3, [r2, #12]
|
||
1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1661 .loc 1 1766 1 is_stmt 0 view .LVU364
|
||
1662 0014 7047 bx lr
|
||
1663 .L156:
|
||
1664 0016 00BF .align 2
|
||
1665 .L155:
|
||
1666 0018 00480258 .word 1476544512
|
||
1667 .cfi_endproc
|
||
1668 .LFE170:
|
||
1670 .section .text.HAL_PWREx_DisableBatteryCharging,"ax",%progbits
|
||
1671 .align 1
|
||
1672 .global HAL_PWREx_DisableBatteryCharging
|
||
1673 .syntax unified
|
||
1674 .thumb
|
||
1675 .thumb_func
|
||
1676 .fpu fpv5-d16
|
||
1678 HAL_PWREx_DisableBatteryCharging:
|
||
1679 .LFB171:
|
||
1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Battery charging.
|
||
1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableBatteryCharging (void)
|
||
1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1680 .loc 1 1773 1 is_stmt 1 view -0
|
||
1681 .cfi_startproc
|
||
1682 @ args = 0, pretend = 0, frame = 0
|
||
1683 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1684 @ link register save eliminated.
|
||
1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Battery charging */
|
||
1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
|
||
1685 .loc 1 1775 3 view .LVU366
|
||
1686 0000 024A ldr r2, .L158
|
||
1687 0002 D368 ldr r3, [r2, #12]
|
||
1688 0004 23F48073 bic r3, r3, #256
|
||
1689 0008 D360 str r3, [r2, #12]
|
||
1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1690 .loc 1 1776 1 is_stmt 0 view .LVU367
|
||
1691 000a 7047 bx lr
|
||
1692 .L159:
|
||
1693 .align 2
|
||
1694 .L158:
|
||
1695 000c 00480258 .word 1476544512
|
||
1696 .cfi_endproc
|
||
1697 .LFE171:
|
||
1699 .section .text.HAL_PWREx_EnableMonitoring,"ax",%progbits
|
||
1700 .align 1
|
||
ARM GAS /tmp/ccMGXY28.s page 80
|
||
|
||
|
||
1701 .global HAL_PWREx_EnableMonitoring
|
||
1702 .syntax unified
|
||
1703 .thumb
|
||
1704 .thumb_func
|
||
1705 .fpu fpv5-d16
|
||
1707 HAL_PWREx_EnableMonitoring:
|
||
1708 .LFB172:
|
||
1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CR1_BOOSTE)
|
||
1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the booster to guarantee the analog switch AC performance when
|
||
1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the VDD supply voltage is below 2V7.
|
||
1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The VDD supply voltage can be monitored through the PVD and the PLS
|
||
1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * field bits.
|
||
1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableAnalogBooster (void)
|
||
1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Analog voltage */
|
||
1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
|
||
1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable VDDA booster */
|
||
1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
|
||
1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the analog booster.
|
||
1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableAnalogBooster (void)
|
||
1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable VDDA booster */
|
||
1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
|
||
1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Analog voltage */
|
||
1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
|
||
1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CR1_BOOSTE) */
|
||
1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @}
|
||
1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
|
||
1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Power Monitoring functions
|
||
1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *
|
||
1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
|
||
1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Power Monitoring functions #####
|
||
1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===============================================================================
|
||
1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** VBAT and Temperature supervision ***
|
||
1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ========================================
|
||
1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The VBAT battery voltage supply can be monitored by comparing it with
|
||
1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
|
||
1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
|
||
1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** lower than the threshold.
|
||
ARM GAS /tmp/ccMGXY28.s page 81
|
||
|
||
|
||
1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The temperature can be monitored by comparing it with two threshold
|
||
1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
|
||
1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** control register 2 (PWR_CR2), indicate whether the device temperature
|
||
1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** is higher or lower than the threshold.
|
||
1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The VBAT and the temperature monitoring is enabled by
|
||
1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableMonitoring() function and disabled by
|
||
1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableMonitoring() function.
|
||
1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
|
||
1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
|
||
1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
|
||
1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
|
||
1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** level which can be :
|
||
1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
|
||
1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
|
||
1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** AVD configuration ***
|
||
1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =========================
|
||
1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..]
|
||
1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The AVD is used to monitor the VDDA power supply by comparing it to a
|
||
1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
|
||
1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** register).
|
||
1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) A AVDO flag is available to indicate if VDDA is higher or lower
|
||
1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** than the AVD threshold. This event is internally connected to the EXTI
|
||
1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** line 16 to generate an interrupt if enabled.
|
||
1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
|
||
1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The AVD is stopped in System Standby mode.
|
||
1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
|
||
1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{
|
||
1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the VBAT and temperature monitoring.
|
||
1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMonitoring (void)
|
||
1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1709 .loc 1 1863 1 is_stmt 1 view -0
|
||
1710 .cfi_startproc
|
||
1711 @ args = 0, pretend = 0, frame = 0
|
||
1712 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1713 @ link register save eliminated.
|
||
1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the VBAT and Temperature monitoring */
|
||
1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR2, PWR_CR2_MONEN);
|
||
1714 .loc 1 1865 3 view .LVU369
|
||
1715 0000 024A ldr r2, .L161
|
||
1716 0002 9368 ldr r3, [r2, #8]
|
||
1717 0004 43F01003 orr r3, r3, #16
|
||
1718 0008 9360 str r3, [r2, #8]
|
||
1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1719 .loc 1 1866 1 is_stmt 0 view .LVU370
|
||
1720 000a 7047 bx lr
|
||
1721 .L162:
|
||
1722 .align 2
|
||
1723 .L161:
|
||
1724 000c 00480258 .word 1476544512
|
||
1725 .cfi_endproc
|
||
ARM GAS /tmp/ccMGXY28.s page 82
|
||
|
||
|
||
1726 .LFE172:
|
||
1728 .section .text.HAL_PWREx_DisableMonitoring,"ax",%progbits
|
||
1729 .align 1
|
||
1730 .global HAL_PWREx_DisableMonitoring
|
||
1731 .syntax unified
|
||
1732 .thumb
|
||
1733 .thumb_func
|
||
1734 .fpu fpv5-d16
|
||
1736 HAL_PWREx_DisableMonitoring:
|
||
1737 .LFB173:
|
||
1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the VBAT and temperature monitoring.
|
||
1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status.
|
||
1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMonitoring (void)
|
||
1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1738 .loc 1 1873 1 is_stmt 1 view -0
|
||
1739 .cfi_startproc
|
||
1740 @ args = 0, pretend = 0, frame = 0
|
||
1741 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1742 @ link register save eliminated.
|
||
1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the VBAT and Temperature monitoring */
|
||
1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
|
||
1743 .loc 1 1875 3 view .LVU372
|
||
1744 0000 024A ldr r2, .L164
|
||
1745 0002 9368 ldr r3, [r2, #8]
|
||
1746 0004 23F01003 bic r3, r3, #16
|
||
1747 0008 9360 str r3, [r2, #8]
|
||
1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1748 .loc 1 1876 1 is_stmt 0 view .LVU373
|
||
1749 000a 7047 bx lr
|
||
1750 .L165:
|
||
1751 .align 2
|
||
1752 .L164:
|
||
1753 000c 00480258 .word 1476544512
|
||
1754 .cfi_endproc
|
||
1755 .LFE173:
|
||
1757 .section .text.HAL_PWREx_GetTemperatureLevel,"ax",%progbits
|
||
1758 .align 1
|
||
1759 .global HAL_PWREx_GetTemperatureLevel
|
||
1760 .syntax unified
|
||
1761 .thumb
|
||
1762 .thumb_func
|
||
1763 .fpu fpv5-d16
|
||
1765 HAL_PWREx_GetTemperatureLevel:
|
||
1766 .LFB174:
|
||
1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Indicate whether the junction temperature is between, above or below
|
||
1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the thresholds.
|
||
1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval Temperature level.
|
||
1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetTemperatureLevel (void)
|
||
1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1767 .loc 1 1884 1 is_stmt 1 view -0
|
||
1768 .cfi_startproc
|
||
ARM GAS /tmp/ccMGXY28.s page 83
|
||
|
||
|
||
1769 @ args = 0, pretend = 0, frame = 0
|
||
1770 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1771 @ link register save eliminated.
|
||
1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tempLevel, regValue;
|
||
1772 .loc 1 1885 3 view .LVU375
|
||
1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Read the temperature flags */
|
||
1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
|
||
1773 .loc 1 1888 3 view .LVU376
|
||
1774 .loc 1 1888 14 is_stmt 0 view .LVU377
|
||
1775 0000 054B ldr r3, .L169
|
||
1776 0002 9868 ldr r0, [r3, #8]
|
||
1777 .loc 1 1888 12 view .LVU378
|
||
1778 0004 00F44000 and r0, r0, #12582912
|
||
1779 .LVL82:
|
||
1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the temperature is below the threshold */
|
||
1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (regValue == PWR_CR2_TEMPL)
|
||
1780 .loc 1 1891 3 is_stmt 1 view .LVU379
|
||
1781 .loc 1 1891 6 is_stmt 0 view .LVU380
|
||
1782 0008 B0F5800F cmp r0, #4194304
|
||
1783 000c 03D0 beq .L166
|
||
1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
|
||
1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the temperature is above the threshold */
|
||
1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (regValue == PWR_CR2_TEMPH)
|
||
1784 .loc 1 1896 8 is_stmt 1 view .LVU381
|
||
1785 .loc 1 1896 11 is_stmt 0 view .LVU382
|
||
1786 000e B0F5000F cmp r0, #8388608
|
||
1787 0012 00D0 beq .L166
|
||
1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
|
||
1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* The temperature is between the thresholds */
|
||
1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
|
||
1788 .loc 1 1903 15 view .LVU383
|
||
1789 0014 0020 movs r0, #0
|
||
1790 .LVL83:
|
||
1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return tempLevel;
|
||
1791 .loc 1 1906 3 is_stmt 1 view .LVU384
|
||
1792 .L166:
|
||
1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1793 .loc 1 1907 1 is_stmt 0 view .LVU385
|
||
1794 0016 7047 bx lr
|
||
1795 .L170:
|
||
1796 .align 2
|
||
1797 .L169:
|
||
1798 0018 00480258 .word 1476544512
|
||
1799 .cfi_endproc
|
||
1800 .LFE174:
|
||
1802 .section .text.HAL_PWREx_GetVBATLevel,"ax",%progbits
|
||
1803 .align 1
|
||
ARM GAS /tmp/ccMGXY28.s page 84
|
||
|
||
|
||
1804 .global HAL_PWREx_GetVBATLevel
|
||
1805 .syntax unified
|
||
1806 .thumb
|
||
1807 .thumb_func
|
||
1808 .fpu fpv5-d16
|
||
1810 HAL_PWREx_GetVBATLevel:
|
||
1811 .LFB175:
|
||
1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Indicate whether the Battery voltage level is between, above or below
|
||
1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the thresholds.
|
||
1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval VBAT level.
|
||
1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVBATLevel (void)
|
||
1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1812 .loc 1 1915 1 is_stmt 1 view -0
|
||
1813 .cfi_startproc
|
||
1814 @ args = 0, pretend = 0, frame = 0
|
||
1815 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1816 @ link register save eliminated.
|
||
1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t VBATLevel, regValue;
|
||
1817 .loc 1 1916 3 view .LVU387
|
||
1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Read the VBAT flags */
|
||
1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
|
||
1818 .loc 1 1919 3 view .LVU388
|
||
1819 .loc 1 1919 14 is_stmt 0 view .LVU389
|
||
1820 0000 054B ldr r3, .L174
|
||
1821 0002 9868 ldr r0, [r3, #8]
|
||
1822 .loc 1 1919 12 view .LVU390
|
||
1823 0004 00F44010 and r0, r0, #3145728
|
||
1824 .LVL84:
|
||
1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the VBAT is below the threshold */
|
||
1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (regValue == PWR_CR2_VBATL)
|
||
1825 .loc 1 1922 3 is_stmt 1 view .LVU391
|
||
1826 .loc 1 1922 6 is_stmt 0 view .LVU392
|
||
1827 0008 B0F5801F cmp r0, #1048576
|
||
1828 000c 03D0 beq .L171
|
||
1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
|
||
1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the VBAT is above the threshold */
|
||
1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (regValue == PWR_CR2_VBATH)
|
||
1829 .loc 1 1927 8 is_stmt 1 view .LVU393
|
||
1830 .loc 1 1927 11 is_stmt 0 view .LVU394
|
||
1831 000e B0F5001F cmp r0, #2097152
|
||
1832 0012 00D0 beq .L171
|
||
1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
|
||
1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* The VBAT is between the thresholds */
|
||
1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
|
||
1833 .loc 1 1934 15 view .LVU395
|
||
1834 0014 0020 movs r0, #0
|
||
ARM GAS /tmp/ccMGXY28.s page 85
|
||
|
||
|
||
1835 .LVL85:
|
||
1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return VBATLevel;
|
||
1836 .loc 1 1937 3 is_stmt 1 view .LVU396
|
||
1837 .L171:
|
||
1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1838 .loc 1 1938 1 is_stmt 0 view .LVU397
|
||
1839 0016 7047 bx lr
|
||
1840 .L175:
|
||
1841 .align 2
|
||
1842 .L174:
|
||
1843 0018 00480258 .word 1476544512
|
||
1844 .cfi_endproc
|
||
1845 .LFE175:
|
||
1847 .section .text.HAL_PWREx_ConfigAVD,"ax",%progbits
|
||
1848 .align 1
|
||
1849 .global HAL_PWREx_ConfigAVD
|
||
1850 .syntax unified
|
||
1851 .thumb
|
||
1852 .thumb_func
|
||
1853 .fpu fpv5-d16
|
||
1855 HAL_PWREx_ConfigAVD:
|
||
1856 .LVL86:
|
||
1857 .LFB176:
|
||
1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CSR1_MMCVDO)
|
||
1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the VDDMMC voltage level.
|
||
1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The VDDMMC voltage level.
|
||
1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
|
||
1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWREx_MMC_VoltageLevel mmc_voltage;
|
||
1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check voltage detector output on VDDMMC value */
|
||
1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
|
||
1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
|
||
1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
|
||
1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return mmc_voltage;
|
||
1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CSR1_MMCVDO) */
|
||
1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the event mode and the voltage threshold detected by the
|
||
1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Analog Voltage Detector (AVD).
|
||
1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
|
||
1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the configuration information for the AVD.
|
||
1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for
|
||
1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * more details about the voltage threshold corresponding to each
|
||
1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * detection level.
|
||
ARM GAS /tmp/ccMGXY28.s page 86
|
||
|
||
|
||
1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note For dual core devices, please ensure to configure the EXTI lines for
|
||
1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the different Cortex-Mx through PWR_Exported_Macro provided by this
|
||
1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * driver. All combination are allowed: wake up only Cortex-M7, wake up
|
||
1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
|
||
1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
|
||
1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1858 .loc 1 1978 1 is_stmt 1 view -0
|
||
1859 .cfi_startproc
|
||
1860 @ args = 0, pretend = 0, frame = 0
|
||
1861 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1862 @ link register save eliminated.
|
||
1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */
|
||
1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
|
||
1863 .loc 1 1980 3 view .LVU399
|
||
1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
|
||
1864 .loc 1 1981 3 view .LVU400
|
||
1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the ALS[18:17] bits according to AVDLevel value */
|
||
1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
|
||
1865 .loc 1 1984 3 view .LVU401
|
||
1866 0000 244A ldr r2, .L181
|
||
1867 0002 1368 ldr r3, [r2]
|
||
1868 0004 23F4C023 bic r3, r3, #393216
|
||
1869 0008 0168 ldr r1, [r0]
|
||
1870 000a 0B43 orrs r3, r3, r1
|
||
1871 000c 1360 str r3, [r2]
|
||
1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear any previous config */
|
||
1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if !defined (DUAL_CORE)
|
||
1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
|
||
1872 .loc 1 1988 3 view .LVU402
|
||
1873 000e 4FF0B043 mov r3, #1476395008
|
||
1874 0012 D3F88420 ldr r2, [r3, #132]
|
||
1875 0016 22F48032 bic r2, r2, #65536
|
||
1876 001a C3F88420 str r2, [r3, #132]
|
||
1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_IT ();
|
||
1877 .loc 1 1989 3 view .LVU403
|
||
1878 001e D3F88020 ldr r2, [r3, #128]
|
||
1879 0022 22F48032 bic r2, r2, #65536
|
||
1880 0026 C3F88020 str r2, [r3, #128]
|
||
1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !defined (DUAL_CORE) */
|
||
1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
|
||
1881 .loc 1 1992 3 view .LVU404
|
||
1882 002a 1A68 ldr r2, [r3]
|
||
1883 002c 22F48032 bic r2, r2, #65536
|
||
1884 0030 1A60 str r2, [r3]
|
||
1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
|
||
1885 .loc 1 1993 3 view .LVU405
|
||
1886 0032 5A68 ldr r2, [r3, #4]
|
||
1887 0034 22F48032 bic r2, r2, #65536
|
||
1888 0038 5A60 str r2, [r3, #4]
|
||
1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if !defined (DUAL_CORE)
|
||
1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Configure the interrupt mode */
|
||
ARM GAS /tmp/ccMGXY28.s page 87
|
||
|
||
|
||
1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
|
||
1889 .loc 1 1997 3 view .LVU406
|
||
1890 .loc 1 1997 18 is_stmt 0 view .LVU407
|
||
1891 003a 4368 ldr r3, [r0, #4]
|
||
1892 .loc 1 1997 6 view .LVU408
|
||
1893 003c 13F4803F tst r3, #65536
|
||
1894 0040 07D0 beq .L177
|
||
1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_IT ();
|
||
1895 .loc 1 1999 5 is_stmt 1 view .LVU409
|
||
1896 0042 4FF0B042 mov r2, #1476395008
|
||
1897 0046 D2F88030 ldr r3, [r2, #128]
|
||
1898 004a 43F48033 orr r3, r3, #65536
|
||
1899 004e C2F88030 str r3, [r2, #128]
|
||
1900 .L177:
|
||
2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Configure the event mode */
|
||
2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
|
||
1901 .loc 1 2003 3 view .LVU410
|
||
1902 .loc 1 2003 18 is_stmt 0 view .LVU411
|
||
1903 0052 4368 ldr r3, [r0, #4]
|
||
1904 .loc 1 2003 6 view .LVU412
|
||
1905 0054 13F4003F tst r3, #131072
|
||
1906 0058 07D0 beq .L178
|
||
2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
|
||
1907 .loc 1 2005 5 is_stmt 1 view .LVU413
|
||
1908 005a 4FF0B042 mov r2, #1476395008
|
||
1909 005e D2F88430 ldr r3, [r2, #132]
|
||
1910 0062 43F48033 orr r3, r3, #65536
|
||
1911 0066 C2F88430 str r3, [r2, #132]
|
||
1912 .L178:
|
||
2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !defined (DUAL_CORE) */
|
||
2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Rising edge configuration */
|
||
2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
|
||
1913 .loc 1 2010 3 view .LVU414
|
||
1914 .loc 1 2010 18 is_stmt 0 view .LVU415
|
||
1915 006a 4368 ldr r3, [r0, #4]
|
||
1916 .loc 1 2010 6 view .LVU416
|
||
1917 006c 13F0010F tst r3, #1
|
||
1918 0070 05D0 beq .L179
|
||
2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
|
||
1919 .loc 1 2012 5 is_stmt 1 view .LVU417
|
||
1920 0072 4FF0B042 mov r2, #1476395008
|
||
1921 0076 1368 ldr r3, [r2]
|
||
1922 0078 43F48033 orr r3, r3, #65536
|
||
1923 007c 1360 str r3, [r2]
|
||
1924 .L179:
|
||
2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Falling edge configuration */
|
||
2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
|
||
1925 .loc 1 2016 3 view .LVU418
|
||
ARM GAS /tmp/ccMGXY28.s page 88
|
||
|
||
|
||
1926 .loc 1 2016 18 is_stmt 0 view .LVU419
|
||
1927 007e 4368 ldr r3, [r0, #4]
|
||
1928 .loc 1 2016 6 view .LVU420
|
||
1929 0080 13F0020F tst r3, #2
|
||
1930 0084 05D0 beq .L176
|
||
2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
|
||
1931 .loc 1 2018 5 is_stmt 1 view .LVU421
|
||
1932 0086 4FF0B042 mov r2, #1476395008
|
||
1933 008a 5368 ldr r3, [r2, #4]
|
||
1934 008c 43F48033 orr r3, r3, #65536
|
||
1935 0090 5360 str r3, [r2, #4]
|
||
1936 .L176:
|
||
2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1937 .loc 1 2020 1 is_stmt 0 view .LVU422
|
||
1938 0092 7047 bx lr
|
||
1939 .L182:
|
||
1940 .align 2
|
||
1941 .L181:
|
||
1942 0094 00480258 .word 1476544512
|
||
1943 .cfi_endproc
|
||
1944 .LFE176:
|
||
1946 .section .text.HAL_PWREx_EnableAVD,"ax",%progbits
|
||
1947 .align 1
|
||
1948 .global HAL_PWREx_EnableAVD
|
||
1949 .syntax unified
|
||
1950 .thumb
|
||
1951 .thumb_func
|
||
1952 .fpu fpv5-d16
|
||
1954 HAL_PWREx_EnableAVD:
|
||
1955 .LFB177:
|
||
2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Analog Voltage Detector (AVD).
|
||
2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableAVD (void)
|
||
2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1956 .loc 1 2027 1 is_stmt 1 view -0
|
||
1957 .cfi_startproc
|
||
1958 @ args = 0, pretend = 0, frame = 0
|
||
1959 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1960 @ link register save eliminated.
|
||
2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Analog Voltage Detector */
|
||
2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
|
||
1961 .loc 1 2029 3 view .LVU424
|
||
1962 0000 024A ldr r2, .L184
|
||
1963 0002 1368 ldr r3, [r2]
|
||
1964 0004 43F48033 orr r3, r3, #65536
|
||
1965 0008 1360 str r3, [r2]
|
||
2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1966 .loc 1 2030 1 is_stmt 0 view .LVU425
|
||
1967 000a 7047 bx lr
|
||
1968 .L185:
|
||
1969 .align 2
|
||
1970 .L184:
|
||
ARM GAS /tmp/ccMGXY28.s page 89
|
||
|
||
|
||
1971 000c 00480258 .word 1476544512
|
||
1972 .cfi_endproc
|
||
1973 .LFE177:
|
||
1975 .section .text.HAL_PWREx_DisableAVD,"ax",%progbits
|
||
1976 .align 1
|
||
1977 .global HAL_PWREx_DisableAVD
|
||
1978 .syntax unified
|
||
1979 .thumb
|
||
1980 .thumb_func
|
||
1981 .fpu fpv5-d16
|
||
1983 HAL_PWREx_DisableAVD:
|
||
1984 .LFB178:
|
||
2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Analog Voltage Detector(AVD).
|
||
2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableAVD (void)
|
||
2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
1985 .loc 1 2037 1 is_stmt 1 view -0
|
||
1986 .cfi_startproc
|
||
1987 @ args = 0, pretend = 0, frame = 0
|
||
1988 @ frame_needed = 0, uses_anonymous_args = 0
|
||
1989 @ link register save eliminated.
|
||
2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Analog Voltage Detector */
|
||
2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
|
||
1990 .loc 1 2039 3 view .LVU427
|
||
1991 0000 024A ldr r2, .L187
|
||
1992 0002 1368 ldr r3, [r2]
|
||
1993 0004 23F48033 bic r3, r3, #65536
|
||
1994 0008 1360 str r3, [r2]
|
||
2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
1995 .loc 1 2040 1 is_stmt 0 view .LVU428
|
||
1996 000a 7047 bx lr
|
||
1997 .L188:
|
||
1998 .align 2
|
||
1999 .L187:
|
||
2000 000c 00480258 .word 1476544512
|
||
2001 .cfi_endproc
|
||
2002 .LFE178:
|
||
2004 .section .text.HAL_PWREx_AVDCallback,"ax",%progbits
|
||
2005 .align 1
|
||
2006 .weak HAL_PWREx_AVDCallback
|
||
2007 .syntax unified
|
||
2008 .thumb
|
||
2009 .thumb_func
|
||
2010 .fpu fpv5-d16
|
||
2012 HAL_PWREx_AVDCallback:
|
||
2013 .LFB180:
|
||
2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD/AVD interrupt request.
|
||
2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_AVD_IRQHandler().
|
||
2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None
|
||
2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_PVD_AVD_IRQHandler (void)
|
||
2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
ARM GAS /tmp/ccMGXY28.s page 90
|
||
|
||
|
||
2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the Programmable Voltage Detector is enabled (PVD) */
|
||
2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
|
||
2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
||
2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR D1/CD EXTI flag */
|
||
2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
|
||
2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */
|
||
2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback ();
|
||
2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D1/CD pending bit */
|
||
2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
|
||
2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR EXTI D2 flag */
|
||
2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
|
||
2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */
|
||
2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback ();
|
||
2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D2 pending bit */
|
||
2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
|
||
2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the Analog Voltage Detector is enabled (AVD) */
|
||
2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
|
||
2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
||
2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR EXTI D1/CD flag */
|
||
2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
|
||
2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR AVD interrupt user callback */
|
||
2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_AVDCallback ();
|
||
2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D1/CD pending bit */
|
||
2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
|
||
2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
|
||
2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else
|
||
2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR EXTI D2 flag */
|
||
2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
|
||
2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR AVD interrupt user callback */
|
||
ARM GAS /tmp/ccMGXY28.s page 91
|
||
|
||
|
||
2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_AVDCallback ();
|
||
2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D2 pending bit */
|
||
2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
|
||
2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
|
||
2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
|
||
2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR AVD interrupt callback.
|
||
2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None.
|
||
2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_AVDCallback (void)
|
||
2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2014 .loc 1 2121 1 is_stmt 1 view -0
|
||
2015 .cfi_startproc
|
||
2016 @ args = 0, pretend = 0, frame = 0
|
||
2017 @ frame_needed = 0, uses_anonymous_args = 0
|
||
2018 @ link register save eliminated.
|
||
2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
|
||
2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWR_AVDCallback can be implemented in the user file
|
||
2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */
|
||
2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2019 .loc 1 2125 1 view .LVU430
|
||
2020 0000 7047 bx lr
|
||
2021 .cfi_endproc
|
||
2022 .LFE180:
|
||
2024 .section .text.HAL_PWREx_PVD_AVD_IRQHandler,"ax",%progbits
|
||
2025 .align 1
|
||
2026 .global HAL_PWREx_PVD_AVD_IRQHandler
|
||
2027 .syntax unified
|
||
2028 .thumb
|
||
2029 .thumb_func
|
||
2030 .fpu fpv5-d16
|
||
2032 HAL_PWREx_PVD_AVD_IRQHandler:
|
||
2033 .LFB179:
|
||
2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the Programmable Voltage Detector is enabled (PVD) */
|
||
2034 .loc 1 2048 1 view -0
|
||
2035 .cfi_startproc
|
||
2036 @ args = 0, pretend = 0, frame = 0
|
||
2037 @ frame_needed = 0, uses_anonymous_args = 0
|
||
2038 0000 08B5 push {r3, lr}
|
||
2039 .LCFI13:
|
||
2040 .cfi_def_cfa_offset 8
|
||
2041 .cfi_offset 3, -8
|
||
2042 .cfi_offset 14, -4
|
||
2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2043 .loc 1 2050 3 view .LVU432
|
||
2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2044 .loc 1 2050 7 is_stmt 0 view .LVU433
|
||
2045 0002 174B ldr r3, .L196
|
||
2046 0004 1B68 ldr r3, [r3]
|
||
2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2047 .loc 1 2050 6 view .LVU434
|
||
2048 0006 13F0100F tst r3, #16
|
||
ARM GAS /tmp/ccMGXY28.s page 92
|
||
|
||
|
||
2049 000a 06D0 beq .L191
|
||
2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2050 .loc 1 2057 7 is_stmt 1 view .LVU435
|
||
2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2051 .loc 1 2057 11 is_stmt 0 view .LVU436
|
||
2052 000c 4FF0B043 mov r3, #1476395008
|
||
2053 0010 D3F88830 ldr r3, [r3, #136]
|
||
2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2054 .loc 1 2057 10 view .LVU437
|
||
2055 0014 13F4803F tst r3, #65536
|
||
2056 0018 0CD1 bne .L194
|
||
2057 .L191:
|
||
2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2058 .loc 1 2083 3 is_stmt 1 view .LVU438
|
||
2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2059 .loc 1 2083 7 is_stmt 0 view .LVU439
|
||
2060 001a 114B ldr r3, .L196
|
||
2061 001c 1B68 ldr r3, [r3]
|
||
2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2062 .loc 1 2083 6 view .LVU440
|
||
2063 001e 13F4803F tst r3, #65536
|
||
2064 0022 06D0 beq .L190
|
||
2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2065 .loc 1 2090 7 is_stmt 1 view .LVU441
|
||
2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2066 .loc 1 2090 11 is_stmt 0 view .LVU442
|
||
2067 0024 4FF0B043 mov r3, #1476395008
|
||
2068 0028 D3F88830 ldr r3, [r3, #136]
|
||
2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
|
||
2069 .loc 1 2090 10 view .LVU443
|
||
2070 002c 13F4803F tst r3, #65536
|
||
2071 0030 0BD1 bne .L195
|
||
2072 .L190:
|
||
2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2073 .loc 1 2114 1 view .LVU444
|
||
2074 0032 08BD pop {r3, pc}
|
||
2075 .L194:
|
||
2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2076 .loc 1 2060 9 is_stmt 1 view .LVU445
|
||
2077 0034 FFF7FEFF bl HAL_PWR_PVDCallback
|
||
2078 .LVL87:
|
||
2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2079 .loc 1 2063 9 view .LVU446
|
||
2080 0038 4FF0B042 mov r2, #1476395008
|
||
2081 003c D2F88830 ldr r3, [r2, #136]
|
||
2082 0040 43F48033 orr r3, r3, #65536
|
||
2083 0044 C2F88830 str r3, [r2, #136]
|
||
2084 0048 E7E7 b .L191
|
||
2085 .L195:
|
||
2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2086 .loc 1 2093 9 view .LVU447
|
||
2087 004a FFF7FEFF bl HAL_PWREx_AVDCallback
|
||
2088 .LVL88:
|
||
2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
|
||
2089 .loc 1 2096 9 view .LVU448
|
||
2090 004e 4FF0B042 mov r2, #1476395008
|
||
2091 0052 D2F88830 ldr r3, [r2, #136]
|
||
ARM GAS /tmp/ccMGXY28.s page 93
|
||
|
||
|
||
2092 0056 43F48033 orr r3, r3, #65536
|
||
2093 005a C2F88830 str r3, [r2, #136]
|
||
2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****
|
||
2094 .loc 1 2114 1 is_stmt 0 view .LVU449
|
||
2095 005e E8E7 b .L190
|
||
2096 .L197:
|
||
2097 .align 2
|
||
2098 .L196:
|
||
2099 0060 00480258 .word 1476544512
|
||
2100 .cfi_endproc
|
||
2101 .LFE179:
|
||
2103 .text
|
||
2104 .Letext0:
|
||
2105 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h"
|
||
2106 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h"
|
||
2107 .file 5 "Drivers/CMSIS/Include/core_cm7.h"
|
||
2108 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h"
|
||
2109 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
|
||
2110 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h"
|
||
2111 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h"
|
||
2112 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h"
|
||
ARM GAS /tmp/ccMGXY28.s page 94
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:0000000000000000 stm32h7xx_hal_pwr_ex.c
|
||
/tmp/ccMGXY28.s:17 .text.HAL_PWREx_ConfigSupply:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:25 .text.HAL_PWREx_ConfigSupply:0000000000000000 HAL_PWREx_ConfigSupply
|
||
/tmp/ccMGXY28.s:119 .text.HAL_PWREx_ConfigSupply:0000000000000050 $d
|
||
/tmp/ccMGXY28.s:124 .text.HAL_PWREx_GetSupplyConfig:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:131 .text.HAL_PWREx_GetSupplyConfig:0000000000000000 HAL_PWREx_GetSupplyConfig
|
||
/tmp/ccMGXY28.s:148 .text.HAL_PWREx_GetSupplyConfig:000000000000000c $d
|
||
/tmp/ccMGXY28.s:153 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:160 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 HAL_PWREx_ControlVoltageScaling
|
||
/tmp/ccMGXY28.s:353 .text.HAL_PWREx_ControlVoltageScaling:00000000000000cc $d
|
||
/tmp/ccMGXY28.s:359 .text.HAL_PWREx_GetVoltageRange:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:366 .text.HAL_PWREx_GetVoltageRange:0000000000000000 HAL_PWREx_GetVoltageRange
|
||
/tmp/ccMGXY28.s:383 .text.HAL_PWREx_GetVoltageRange:000000000000000c $d
|
||
/tmp/ccMGXY28.s:388 .text.HAL_PWREx_ControlStopModeVoltageScaling:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:395 .text.HAL_PWREx_ControlStopModeVoltageScaling:0000000000000000 HAL_PWREx_ControlStopModeVoltageScaling
|
||
/tmp/ccMGXY28.s:419 .text.HAL_PWREx_ControlStopModeVoltageScaling:0000000000000010 $d
|
||
/tmp/ccMGXY28.s:424 .text.HAL_PWREx_GetStopModeVoltageRange:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:431 .text.HAL_PWREx_GetStopModeVoltageRange:0000000000000000 HAL_PWREx_GetStopModeVoltageRange
|
||
/tmp/ccMGXY28.s:448 .text.HAL_PWREx_GetStopModeVoltageRange:000000000000000c $d
|
||
/tmp/ccMGXY28.s:453 .text.HAL_PWREx_EnterSTOPMode:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:460 .text.HAL_PWREx_EnterSTOPMode:0000000000000000 HAL_PWREx_EnterSTOPMode
|
||
/tmp/ccMGXY28.s:589 .text.HAL_PWREx_EnterSTOPMode:0000000000000060 $d
|
||
/tmp/ccMGXY28.s:595 .text.HAL_PWREx_ClearPendingEvent:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:602 .text.HAL_PWREx_ClearPendingEvent:0000000000000000 HAL_PWREx_ClearPendingEvent
|
||
/tmp/ccMGXY28.s:622 .text.HAL_PWREx_EnterSTANDBYMode:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:629 .text.HAL_PWREx_EnterSTANDBYMode:0000000000000000 HAL_PWREx_EnterSTANDBYMode
|
||
/tmp/ccMGXY28.s:681 .text.HAL_PWREx_EnterSTANDBYMode:0000000000000038 $d
|
||
/tmp/ccMGXY28.s:687 .text.HAL_PWREx_ConfigD3Domain:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:694 .text.HAL_PWREx_ConfigD3Domain:0000000000000000 HAL_PWREx_ConfigD3Domain
|
||
/tmp/ccMGXY28.s:714 .text.HAL_PWREx_ConfigD3Domain:0000000000000010 $d
|
||
/tmp/ccMGXY28.s:719 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:726 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 HAL_PWREx_EnableFlashPowerDown
|
||
/tmp/ccMGXY28.s:743 .text.HAL_PWREx_EnableFlashPowerDown:000000000000000c $d
|
||
/tmp/ccMGXY28.s:748 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:755 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 HAL_PWREx_DisableFlashPowerDown
|
||
/tmp/ccMGXY28.s:772 .text.HAL_PWREx_DisableFlashPowerDown:000000000000000c $d
|
||
/tmp/ccMGXY28.s:777 .text.HAL_PWREx_EnableWakeUpPin:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:784 .text.HAL_PWREx_EnableWakeUpPin:0000000000000000 HAL_PWREx_EnableWakeUpPin
|
||
/tmp/ccMGXY28.s:950 .text.HAL_PWREx_EnableWakeUpPin:000000000000008c $d
|
||
/tmp/ccMGXY28.s:955 .text.HAL_PWREx_DisableWakeUpPin:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:962 .text.HAL_PWREx_DisableWakeUpPin:0000000000000000 HAL_PWREx_DisableWakeUpPin
|
||
/tmp/ccMGXY28.s:981 .text.HAL_PWREx_DisableWakeUpPin:000000000000000c $d
|
||
/tmp/ccMGXY28.s:986 .text.HAL_PWREx_GetWakeupFlag:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:993 .text.HAL_PWREx_GetWakeupFlag:0000000000000000 HAL_PWREx_GetWakeupFlag
|
||
/tmp/ccMGXY28.s:1014 .text.HAL_PWREx_GetWakeupFlag:0000000000000008 $d
|
||
/tmp/ccMGXY28.s:1019 .text.HAL_PWREx_ClearWakeupFlag:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1026 .text.HAL_PWREx_ClearWakeupFlag:0000000000000000 HAL_PWREx_ClearWakeupFlag
|
||
/tmp/ccMGXY28.s:1061 .text.HAL_PWREx_ClearWakeupFlag:0000000000000018 $d
|
||
/tmp/ccMGXY28.s:1066 .text.HAL_PWREx_WKUP1_Callback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1073 .text.HAL_PWREx_WKUP1_Callback:0000000000000000 HAL_PWREx_WKUP1_Callback
|
||
/tmp/ccMGXY28.s:1086 .text.HAL_PWREx_WKUP2_Callback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1093 .text.HAL_PWREx_WKUP2_Callback:0000000000000000 HAL_PWREx_WKUP2_Callback
|
||
/tmp/ccMGXY28.s:1106 .text.HAL_PWREx_WKUP3_Callback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1113 .text.HAL_PWREx_WKUP3_Callback:0000000000000000 HAL_PWREx_WKUP3_Callback
|
||
/tmp/ccMGXY28.s:1126 .text.HAL_PWREx_WKUP4_Callback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1133 .text.HAL_PWREx_WKUP4_Callback:0000000000000000 HAL_PWREx_WKUP4_Callback
|
||
ARM GAS /tmp/ccMGXY28.s page 95
|
||
|
||
|
||
/tmp/ccMGXY28.s:1146 .text.HAL_PWREx_WKUP5_Callback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1153 .text.HAL_PWREx_WKUP5_Callback:0000000000000000 HAL_PWREx_WKUP5_Callback
|
||
/tmp/ccMGXY28.s:1166 .text.HAL_PWREx_WKUP6_Callback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1173 .text.HAL_PWREx_WKUP6_Callback:0000000000000000 HAL_PWREx_WKUP6_Callback
|
||
/tmp/ccMGXY28.s:1186 .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1193 .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:0000000000000000 HAL_PWREx_WAKEUP_PIN_IRQHandler
|
||
/tmp/ccMGXY28.s:1304 .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:0000000000000094 $d
|
||
/tmp/ccMGXY28.s:1309 .text.HAL_PWREx_EnableBkUpReg:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1316 .text.HAL_PWREx_EnableBkUpReg:0000000000000000 HAL_PWREx_EnableBkUpReg
|
||
/tmp/ccMGXY28.s:1371 .text.HAL_PWREx_EnableBkUpReg:0000000000000030 $d
|
||
/tmp/ccMGXY28.s:1376 .text.HAL_PWREx_DisableBkUpReg:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1383 .text.HAL_PWREx_DisableBkUpReg:0000000000000000 HAL_PWREx_DisableBkUpReg
|
||
/tmp/ccMGXY28.s:1438 .text.HAL_PWREx_DisableBkUpReg:0000000000000030 $d
|
||
/tmp/ccMGXY28.s:1443 .text.HAL_PWREx_EnableUSBReg:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1450 .text.HAL_PWREx_EnableUSBReg:0000000000000000 HAL_PWREx_EnableUSBReg
|
||
/tmp/ccMGXY28.s:1505 .text.HAL_PWREx_EnableUSBReg:0000000000000030 $d
|
||
/tmp/ccMGXY28.s:1510 .text.HAL_PWREx_DisableUSBReg:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1517 .text.HAL_PWREx_DisableUSBReg:0000000000000000 HAL_PWREx_DisableUSBReg
|
||
/tmp/ccMGXY28.s:1572 .text.HAL_PWREx_DisableUSBReg:0000000000000030 $d
|
||
/tmp/ccMGXY28.s:1577 .text.HAL_PWREx_EnableUSBVoltageDetector:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1584 .text.HAL_PWREx_EnableUSBVoltageDetector:0000000000000000 HAL_PWREx_EnableUSBVoltageDetector
|
||
/tmp/ccMGXY28.s:1601 .text.HAL_PWREx_EnableUSBVoltageDetector:000000000000000c $d
|
||
/tmp/ccMGXY28.s:1606 .text.HAL_PWREx_DisableUSBVoltageDetector:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1613 .text.HAL_PWREx_DisableUSBVoltageDetector:0000000000000000 HAL_PWREx_DisableUSBVoltageDetector
|
||
/tmp/ccMGXY28.s:1630 .text.HAL_PWREx_DisableUSBVoltageDetector:000000000000000c $d
|
||
/tmp/ccMGXY28.s:1635 .text.HAL_PWREx_EnableBatteryCharging:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1642 .text.HAL_PWREx_EnableBatteryCharging:0000000000000000 HAL_PWREx_EnableBatteryCharging
|
||
/tmp/ccMGXY28.s:1666 .text.HAL_PWREx_EnableBatteryCharging:0000000000000018 $d
|
||
/tmp/ccMGXY28.s:1671 .text.HAL_PWREx_DisableBatteryCharging:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1678 .text.HAL_PWREx_DisableBatteryCharging:0000000000000000 HAL_PWREx_DisableBatteryCharging
|
||
/tmp/ccMGXY28.s:1695 .text.HAL_PWREx_DisableBatteryCharging:000000000000000c $d
|
||
/tmp/ccMGXY28.s:1700 .text.HAL_PWREx_EnableMonitoring:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1707 .text.HAL_PWREx_EnableMonitoring:0000000000000000 HAL_PWREx_EnableMonitoring
|
||
/tmp/ccMGXY28.s:1724 .text.HAL_PWREx_EnableMonitoring:000000000000000c $d
|
||
/tmp/ccMGXY28.s:1729 .text.HAL_PWREx_DisableMonitoring:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1736 .text.HAL_PWREx_DisableMonitoring:0000000000000000 HAL_PWREx_DisableMonitoring
|
||
/tmp/ccMGXY28.s:1753 .text.HAL_PWREx_DisableMonitoring:000000000000000c $d
|
||
/tmp/ccMGXY28.s:1758 .text.HAL_PWREx_GetTemperatureLevel:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1765 .text.HAL_PWREx_GetTemperatureLevel:0000000000000000 HAL_PWREx_GetTemperatureLevel
|
||
/tmp/ccMGXY28.s:1798 .text.HAL_PWREx_GetTemperatureLevel:0000000000000018 $d
|
||
/tmp/ccMGXY28.s:1803 .text.HAL_PWREx_GetVBATLevel:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1810 .text.HAL_PWREx_GetVBATLevel:0000000000000000 HAL_PWREx_GetVBATLevel
|
||
/tmp/ccMGXY28.s:1843 .text.HAL_PWREx_GetVBATLevel:0000000000000018 $d
|
||
/tmp/ccMGXY28.s:1848 .text.HAL_PWREx_ConfigAVD:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1855 .text.HAL_PWREx_ConfigAVD:0000000000000000 HAL_PWREx_ConfigAVD
|
||
/tmp/ccMGXY28.s:1942 .text.HAL_PWREx_ConfigAVD:0000000000000094 $d
|
||
/tmp/ccMGXY28.s:1947 .text.HAL_PWREx_EnableAVD:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1954 .text.HAL_PWREx_EnableAVD:0000000000000000 HAL_PWREx_EnableAVD
|
||
/tmp/ccMGXY28.s:1971 .text.HAL_PWREx_EnableAVD:000000000000000c $d
|
||
/tmp/ccMGXY28.s:1976 .text.HAL_PWREx_DisableAVD:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:1983 .text.HAL_PWREx_DisableAVD:0000000000000000 HAL_PWREx_DisableAVD
|
||
/tmp/ccMGXY28.s:2000 .text.HAL_PWREx_DisableAVD:000000000000000c $d
|
||
/tmp/ccMGXY28.s:2005 .text.HAL_PWREx_AVDCallback:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:2012 .text.HAL_PWREx_AVDCallback:0000000000000000 HAL_PWREx_AVDCallback
|
||
/tmp/ccMGXY28.s:2025 .text.HAL_PWREx_PVD_AVD_IRQHandler:0000000000000000 $t
|
||
/tmp/ccMGXY28.s:2032 .text.HAL_PWREx_PVD_AVD_IRQHandler:0000000000000000 HAL_PWREx_PVD_AVD_IRQHandler
|
||
/tmp/ccMGXY28.s:2099 .text.HAL_PWREx_PVD_AVD_IRQHandler:0000000000000060 $d
|
||
ARM GAS /tmp/ccMGXY28.s page 96
|
||
|
||
|
||
|
||
UNDEFINED SYMBOLS
|
||
HAL_GetTick
|
||
HAL_PWR_PVDCallback
|