233 lines
10 KiB
ArmAsm
233 lines
10 KiB
ArmAsm
@/**************************************************************************/
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@/* */
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@/* Copyright (c) Microsoft Corporation. All rights reserved. */
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@/* */
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@/* This software is licensed under the Microsoft Software License */
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@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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@/* and in the root directory of this software. */
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@/* */
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@/**************************************************************************/
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@
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@
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@/**************************************************************************/
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@/**************************************************************************/
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@/** */
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@/** ThreadX Component */
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@/** */
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@/** Initialize */
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@/** */
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@/**************************************************************************/
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@/**************************************************************************/
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@
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@
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.global _tx_thread_system_stack_ptr
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.global _tx_initialize_unused_memory
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.global __RAM_segment_used_end__
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.global _tx_timer_interrupt
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.global __main
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.global __tx_SVCallHandler
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.global __tx_PendSVHandler
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.global _vectors
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.global __tx_NMIHandler @ NMI
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.global __tx_BadHandler @ HardFault
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.global __tx_SVCallHandler @ SVCall
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.global __tx_DBGHandler @ Monitor
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.global __tx_PendSVHandler @ PendSV
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.global __tx_SysTickHandler @ SysTick
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.global __tx_IntHandler @ Int 0
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@
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@
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SYSTEM_CLOCK = 6000000
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SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
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.text 32
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.align 4
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.syntax unified
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@/**************************************************************************/
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@/* */
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@/* FUNCTION RELEASE */
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@/* */
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@/* _tx_initialize_low_level Cortex-M7/GNU */
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@/* 6.1 */
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@/* AUTHOR */
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@/* */
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@/* William E. Lamie, Microsoft Corporation */
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@/* */
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@/* DESCRIPTION */
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@/* */
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@/* This function is responsible for any low-level processor */
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@/* initialization, including setting up interrupt vectors, setting */
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@/* up a periodic timer interrupt source, saving the system stack */
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@/* pointer for use in ISR processing later, and finding the first */
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@/* available RAM memory address for tx_application_define. */
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@/* */
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@/* INPUT */
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@/* */
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@/* None */
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@/* */
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@/* OUTPUT */
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@/* */
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@/* None */
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@/* */
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@/* CALLS */
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@/* */
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@/* None */
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@/* */
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@/* CALLED BY */
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@/* */
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@/* _tx_initialize_kernel_enter ThreadX entry function */
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@/* */
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@/* RELEASE HISTORY */
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@/* */
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@/* DATE NAME DESCRIPTION */
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@/* */
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@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
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@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */
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@/* GNU assembly comment, clean */
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@/* up whitespace, resulting */
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@/* in version 6.1 */
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@/* */
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@/**************************************************************************/
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@VOID _tx_initialize_low_level(VOID)
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@{
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.global _tx_initialize_low_level
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.thumb_func
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_tx_initialize_low_level:
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@
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@ /* Disable interrupts during ThreadX initialization. */
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@
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CPSID i
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@
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@ /* Set base of available memory to end of non-initialised RAM area. */
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@
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LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
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LDR r1, =__RAM_segment_used_end__ @ Build first free address
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ADD r1, r1, #4 @
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STR r1, [r0] @ Setup first unused memory pointer
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@
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@ /* Setup Vector Table Offset Register. */
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@
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MOV r0, #0xE000E000 @ Build address of NVIC registers
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LDR r1, =_vectors @ Pickup address of vector table
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STR r1, [r0, #0xD08] @ Set vector table address
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@
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@ /* Set system stack pointer from vector value. */
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@
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LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
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LDR r1, =_vectors @ Pickup address of vector table
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LDR r1, [r1] @ Pickup reset stack pointer
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STR r1, [r0] @ Save system stack pointer
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@
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@ /* Enable the cycle count register. */
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@
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LDR r0, =0xE0001000 @ Build address of DWT register
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LDR r1, [r0] @ Pickup the current value
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ORR r1, r1, #1 @ Set the CYCCNTENA bit
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STR r1, [r0] @ Enable the cycle count register
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@
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@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
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@
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MOV r0, #0xE000E000 @ Build address of NVIC registers
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LDR r1, =SYSTICK_CYCLES
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STR r1, [r0, #0x14] @ Setup SysTick Reload Value
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MOV r1, #0x7 @ Build SysTick Control Enable Value
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STR r1, [r0, #0x10] @ Setup SysTick Control
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@
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@ /* Configure handler priorities. */
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@
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LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM
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STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers
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LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv
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STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers
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@ Note: SVC must be lowest priority, which is 0xFF
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LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
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STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers
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@ Note: PnSV must be lowest priority, which is 0xFF
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@
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@ /* Return to caller. */
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@
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BX lr
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@}
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@
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@/* Define shells for each of the unused vectors. */
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@
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.global __tx_BadHandler
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.thumb_func
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__tx_BadHandler:
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B __tx_BadHandler
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@ /* added to catch the hardfault */
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.global __tx_HardfaultHandler
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.thumb_func
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__tx_HardfaultHandler:
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B __tx_HardfaultHandler
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@ /* added to catch the SVC */
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.global __tx_SVCallHandler
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.thumb_func
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__tx_SVCallHandler:
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B __tx_SVCallHandler
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@ /* Generic interrupt handler template */
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.global __tx_IntHandler
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.thumb_func
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__tx_IntHandler:
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@ VOID InterruptHandler (VOID)
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@ {
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PUSH {r0, lr}
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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BL _tx_execution_isr_enter @ Call the ISR enter function
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#endif
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@ /* Do interrupt handler work here */
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@ /* BL <your C Function>.... */
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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BL _tx_execution_isr_exit @ Call the ISR exit function
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#endif
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POP {r0, lr}
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BX LR
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@ }
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@ /* System Tick timer interrupt handler */
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.global __tx_SysTickHandler
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.global SysTick_Handler
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.thumb_func
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__tx_SysTickHandler:
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.thumb_func
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SysTick_Handler:
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@ VOID TimerInterruptHandler (VOID)
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@ {
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@
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PUSH {r0, lr}
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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BL _tx_execution_isr_enter @ Call the ISR enter function
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#endif
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BL _tx_timer_interrupt
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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BL _tx_execution_isr_exit @ Call the ISR exit function
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#endif
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POP {r0, lr}
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BX LR
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@ }
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@ /* NMI, DBG handlers */
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.global __tx_NMIHandler
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.thumb_func
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__tx_NMIHandler:
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B __tx_NMIHandler
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.global __tx_DBGHandler
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.thumb_func
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__tx_DBGHandler:
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B __tx_DBGHandler
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