210 lines
6.8 KiB
Plaintext
210 lines
6.8 KiB
Plaintext
Microsoft's Azure RTOS ThreadX for ARMv7-M
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(Cortex-M3, Cortex-M4, Cortex-M7)
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Using the GNU Tools
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1. Building the ThreadX run-time Library
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Navigate to the "example_build" directory. Ensure that
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you have setup your path and other environment variables necessary for the ARM
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GNU compiler. At this point you may run the build_threadx.bat batch file.
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This will build the ThreadX run-time environment in the "example_build"
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directory.
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You should observe assembly and compilation of a series of ThreadX source
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files. At the end of the batch file, they are all combined into the
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run-time library file: tx.a. This file must be linked with your
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application in order to use ThreadX.
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2. Demonstration System
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The ThreadX demonstration is designed to execute on Cortex-M evaluation boards
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or on a dedicated simulator.
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Building the demonstration is easy, simply execute the build_threadx_sample.bat
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batch file while inside the "example_build" directory.
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You should observe the compilation of sample_threadx.c (which is the demonstration
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application) and linking with tx.a. The resulting file sample_threadx.out is a binary
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file that can be downloaded and executed on the a simulator, or downloaded to a board.
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3. System Initialization
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The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU
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Cortex-M reset sequence. From the reset vector the C runtime will be initialized.
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The ThreadX tx_initialize_low_level.S file is responsible for setting up
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various system data structures, the vector area, and a periodic timer interrupt
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source.
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In addition, _tx_initialize_low_level determines the first available
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address for use by the application, which is supplied as the sole input
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parameter to your application definition function, tx_application_define.
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4. Register Usage and Stack Frames
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The following defines the saved context stack frames for context switches
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that occur as a result of interrupt handling or from thread-level API calls.
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All suspended threads have the same stack frame in the Cortex-M version of
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ThreadX. The top of the suspended thread's stack is pointed to by
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tx_thread_stack_ptr in the associated thread control block TX_THREAD.
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Non-FPU Stack Frame:
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Stack Offset Stack Contents
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0x00 lr Interrupted lr (lr at time of PENDSV)
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0x04 r4 Software stacked GP registers
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0x08 r5
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0x0C r6
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0x10 r7
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0x14 r8
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0x18 r9
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0x1C r10
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0x20 r11
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0x24 r0 Hardware stacked registers
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0x28 r1
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0x2C r2
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0x30 r3
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0x34 r12
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0x38 lr
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0x3C pc
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0x40 xPSR
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FPU Stack Frame (only interrupted thread with FPU enabled):
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Stack Offset Stack Contents
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0x00 lr Interrupted lr (lr at time of PENDSV)
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0x04 s16 Software stacked FPU registers
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0x08 s17
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0x0C s18
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0x10 s19
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0x14 s20
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0x18 s21
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0x1C s22
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0x20 s23
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0x24 s24
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0x28 s25
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0x2C s26
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0x30 s27
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0x34 s28
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0x38 s29
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0x3C s30
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0x40 s31
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0x44 r4 Software stacked registers
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0x48 r5
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0x4C r6
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0x50 r7
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0x54 r8
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0x58 r9
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0x5C r10
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0x60 r11
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0x64 r0 Hardware stacked registers
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0x68 r1
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0x6C r2
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0x70 r3
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0x74 r12
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0x78 lr
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0x7C pc
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0x80 xPSR
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0x84 s0 Hardware stacked FPU registers
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0x88 s1
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0x8C s2
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0x90 s3
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0x94 s4
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0x98 s5
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0x9C s6
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0xA0 s7
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0xA4 s8
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0xA8 s9
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0xAC s10
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0xB0 s11
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0xB4 s12
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0xB8 s13
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0xBC s14
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0xC0 s15
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0xC4 fpscr
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5. Improving Performance
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The distribution version of ThreadX is built without any compiler optimizations.
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This makes it easy to debug because you can trace or set breakpoints inside of
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ThreadX itself. Of course, this costs some performance. To make it run faster,
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you can change the build_threadx.bat file to remove the -g option and enable
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all compiler optimizations.
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In addition, you can eliminate the ThreadX basic API error checking by
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compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
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defined.
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6. Interrupt Handling
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ThreadX provides complete and high-performance interrupt handling for Cortex-M
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targets. There are a certain set of requirements that are defined in the
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following sub-sections:
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6.1 Vector Area
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The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify
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the vector area according to its needs. There is code in tx_initialize_low_level() that will
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configure the vector base register.
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6.2 Managed Interrupts
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A ThreadX managed interrupt is defined below. By following these conventions, the
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application ISR is then allowed access to various ThreadX services from the ISR.
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Here is the standard template for managed ISRs in ThreadX:
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.global __tx_IntHandler
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.thumb_func
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__tx_IntHandler:
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; VOID InterruptHandler (VOID)
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; {
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PUSH {r0, lr}
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; /* Do interrupt handler work here */
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; /* BL <your interrupt routine in C> */
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POP {r0, lr}
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BX lr
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; }
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Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set.
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To accomplish this, the declaration of the label has to be preceded by the assembler directive
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.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to
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be inserted in the correct location in the interrupt vector table. This table is typically
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located in either your runtime startup file or in the tx_initialize_low_level.S file.
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7. FPU Support
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ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads
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can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread
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context - no additional setup by the application.
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8. Revision History
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For generic code revision information, please refer to the readme_threadx_generic.txt
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file, which is included in your distribution. The following details the revision
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information associated with this specific port of ThreadX:
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06-02-2021 Initial ThreadX version 6.1.7 for Cortex-M using GNU tools.
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Copyright(c) 1996-2021 Microsoft Corporation
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https://azure.com/rtos
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