134 lines
8.0 KiB
ArmAsm
134 lines
8.0 KiB
ArmAsm
/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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.text
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.align 4
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.syntax unified
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_thread_stack_build Cortex-M7/GNU */
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/* 6.1.7 */
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/* AUTHOR */
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/* */
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/* Scott Larson, Microsoft Corporation */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function builds a stack frame on the supplied thread's stack. */
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/* The stack frame results in a fake interrupt return to the supplied */
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/* function pointer. */
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/* */
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/* INPUT */
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/* */
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/* thread_ptr Pointer to thread control blk */
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/* function_ptr Pointer to return function */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* _tx_thread_create Create thread service */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 06-02-2021 Scott Larson Initial Version 6.1.7 */
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/* */
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/**************************************************************************/
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// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
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// {
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.global _tx_thread_stack_build
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.thumb_func
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_tx_thread_stack_build:
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/* Build a fake interrupt frame. The form of the fake interrupt stack
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on the Cortex-M should look like the following after it is built:
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Stack Top:
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LR Interrupted LR (LR at time of PENDSV)
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r4 Initial value for r4
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r5 Initial value for r5
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r6 Initial value for r6
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r7 Initial value for r7
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r8 Initial value for r8
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r9 Initial value for r9
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r10 Initial value for r10
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r11 Initial value for r11
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r0 Initial value for r0 (Hardware stack starts here!!)
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r1 Initial value for r1
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r2 Initial value for r2
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r3 Initial value for r3
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r12 Initial value for r12
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lr Initial value for lr
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pc Initial value for pc
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xPSR Initial value for xPSR
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Stack Bottom: (higher memory address) */
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LDR r2, [r0, #16] // Pickup end of stack area
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BIC r2, r2, #0x7 // Align frame for 8-byte alignment
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SUB r2, r2, #68 // Subtract frame size
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LDR r3, =0xFFFFFFFD // Build initial LR value
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STR r3, [r2, #0] // Save on the stack
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/* Actually build the stack frame. */
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MOV r3, #0 // Build initial register value
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STR r3, [r2, #4] // Store initial r4
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STR r3, [r2, #8] // Store initial r5
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STR r3, [r2, #12] // Store initial r6
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STR r3, [r2, #16] // Store initial r7
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STR r3, [r2, #20] // Store initial r8
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STR r3, [r2, #24] // Store initial r9
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STR r3, [r2, #28] // Store initial r10
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STR r3, [r2, #32] // Store initial r11
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/* Hardware stack follows. */
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STR r3, [r2, #36] // Store initial r0
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STR r3, [r2, #40] // Store initial r1
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STR r3, [r2, #44] // Store initial r2
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STR r3, [r2, #48] // Store initial r3
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STR r3, [r2, #52] // Store initial r12
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MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value
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STR r3, [r2, #56] // Store initial lr
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STR r1, [r2, #60] // Store initial pc
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MOV r3, #0x01000000 // Only T-bit need be set
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STR r3, [r2, #64] // Store initial xPSR
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/* Setup stack pointer. */
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// thread_ptr -> tx_thread_stack_ptr = r2;
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STR r2, [r0, #8] // Save stack pointer in thread's
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// control block
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BX lr // Return to caller
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// }
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