Fixed MPU configuration for code in AXI SRAM.
This commit is contained in:
parent
9d2eaeed00
commit
3cbe1fd375
GPG Key ID:
17F01E106F9F5E0A
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@ -31,20 +31,11 @@ set(C_SOURCES
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"Core/Src/kururin_pa.c"
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"Core/Src/system_stm32h7xx.c"
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"Core/Src/freertos.c"
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"Middlewares/Third_Party/FreeRTOS/Source/croutine.c"
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"Middlewares/Third_Party/FreeRTOS/Source/event_groups.c"
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"Middlewares/Third_Party/FreeRTOS/Source/list.c"
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"Middlewares/Third_Party/FreeRTOS/Source/queue.c"
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"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c"
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"Middlewares/Third_Party/FreeRTOS/Source/tasks.c"
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"Middlewares/Third_Party/FreeRTOS/Source/timers.c"
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"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c"
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"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c"
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"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c"
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"Core/Src/stm32h7xx_hal_timebase_tim.c"
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"FATFS/App/fatfs.c"
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"FATFS/Target/bsp_driver_sd.c"
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"FATFS/Target/sd_diskio.c"
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"FATFS/Target/fatfs_platform.c"
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"Middlewares/Third_Party/FatFs/src/diskio.c"
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"Middlewares/Third_Party/FatFs/src/ff.c"
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"Middlewares/Third_Party/FatFs/src/ff_gen_drv.c"
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@ -59,6 +50,7 @@ set(ASM_SOURCES
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set(C_LIBRARIES
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"lvgl"
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"rtos"
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"stm32_hal_driver"
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)
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@ -139,6 +131,7 @@ target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf"
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# Additional defines
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target_compile_definitions("${CMAKE_PROJECT_NAME}_RAM.elf"
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PRIVATE "VECT_TAB_SRAM"
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PRIVATE "DATA_IN_D2_SRAM"
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)
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add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex"
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@ -166,7 +159,7 @@ target_link_options("${CMAKE_PROJECT_NAME}_QSPI_FLASH.elf"
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# Additional defines
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target_compile_definitions("${CMAKE_PROJECT_NAME}_QSPI_FLASH.elf"
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PRIVATE "VECT_TAB_SRAM"
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PRIVATE "FLASH_XIP_BASE=0x90000000"
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)
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add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_QSPI_FLASH.hex"
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@ -58,6 +58,8 @@ void Error_Handler(void);
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/* USER CODE END EFP */
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/* Private defines -----------------------------------------------------------*/
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#define SDMMC_CD_Pin GPIO_PIN_13
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#define SDMMC_CD_GPIO_Port GPIOC
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#define LCD_BL_Pin GPIO_PIN_1
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#define LCD_BL_GPIO_Port GPIOB
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#define LED2_Pin GPIO_PIN_15
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@ -94,8 +94,10 @@ int main(void)
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{
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/* USER CODE BEGIN 1 */
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SCB->VTOR = 0x90000000;
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#ifndef VECT_TAB_SRAM
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SCB->VTOR = FLASH_XIP_BASE;
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__enable_irq();
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#endif
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/* USER CODE END 1 */
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@ -510,6 +512,12 @@ static void MX_GPIO_Init(void)
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/*Configure GPIO pin Output Level */
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HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
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/*Configure GPIO pin : SDMMC_CD_Pin */
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GPIO_InitStruct.Pin = SDMMC_CD_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_PULLUP;
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HAL_GPIO_Init(SDMMC_CD_GPIO_Port, &GPIO_InitStruct);
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/*Configure GPIO pin : LCD_BL_Pin */
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GPIO_InitStruct.Pin = LCD_BL_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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@ -605,15 +613,24 @@ void MPU_Config(void)
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MPU_InitStruct.Number = MPU_REGION_NUMBER3;
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MPU_InitStruct.BaseAddress = 0x24000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/** Initializes and configures the Region and the memory to be protected
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*/
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MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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MPU_InitStruct.BaseAddress = 0x60000000;
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MPU_InitStruct.BaseAddress = 0x30000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_256MB;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/** Initializes and configures the Region and the memory to be protected
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*/
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MPU_InitStruct.Number = MPU_REGION_NUMBER5;
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MPU_InitStruct.BaseAddress = 0x60000000;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Enables the MPU */
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@ -295,9 +295,10 @@ __weak uint8_t BSP_SD_IsDetected(void)
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{
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__IO uint8_t status = SD_PRESENT;
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/* USER CODE BEGIN IsDetectedSection */
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/* user code can be inserted here */
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/* USER CODE END IsDetectedSection */
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if (BSP_PlatformIsDetected() == 0x0)
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{
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status = SD_NOT_PRESENT;
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}
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return status;
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}
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@ -27,6 +27,7 @@
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal.h"
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#include "fatfs_platform.h"
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/* Exported types --------------------------------------------------------*/
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/**
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@ -0,0 +1,31 @@
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/**
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******************************************************************************
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* @file : fatfs_platform.c
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* @brief : fatfs_platform source file
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under Ultimate Liberty license
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* SLA0044, the "License"; You may not use this file except in compliance with
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* the License. You may obtain a copy of the License at:
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* www.st.com/SLA0044
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*
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******************************************************************************
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*/
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#include "fatfs_platform.h"
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uint8_t BSP_PlatformIsDetected(void) {
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uint8_t status = SD_PRESENT;
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/* Check SD card detect pin */
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if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
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{
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status = SD_NOT_PRESENT;
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}
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/* USER CODE BEGIN 1 */
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/* user code can be inserted here */
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/* USER CODE END 1 */
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return status;
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}
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@ -0,0 +1,26 @@
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/**
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******************************************************************************
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* @file : fatfs_platform.h
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* @brief : fatfs_platform header file
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under Ultimate Liberty license
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* SLA0044, the "License"; You may not use this file except in compliance with
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* the License. You may obtain a copy of the License at:
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* www.st.com/SLA0044
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal.h"
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/* Defines ------------------------------------------------------------------*/
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#define SD_PRESENT ((uint8_t)0x01) /* also in bsp_driver_sd.h */
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#define SD_NOT_PRESENT ((uint8_t)0x00) /* also in bsp_driver_sd.h */
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#define SD_DETECT_PIN GPIO_PIN_13
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#define SD_DETECT_GPIO_PORT GPIOC
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/* Prototypes ---------------------------------------------------------------*/
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uint8_t BSP_PlatformIsDetected(void);
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5
Makefile
5
Makefile
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@ -1,5 +1,5 @@
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##########################################################################################################################
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# File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Sat Apr 17 14:57:59 CST 2021]
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# File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Sat Apr 17 23:48:08 CST 2021]
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##########################################################################################################################
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# ------------------------------------------------
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@ -204,7 +204,8 @@ Middlewares/Third_Party/FatFs/src/diskio.c \
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Middlewares/Third_Party/FatFs/src/ff.c \
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Middlewares/Third_Party/FatFs/src/ff_gen_drv.c \
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Middlewares/Third_Party/FatFs/src/option/syscall.c \
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Middlewares/Third_Party/FatFs/src/option/cc932.c
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Middlewares/Third_Party/FatFs/src/option/cc932.c \
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FATFS/Target/fatfs_platform.c
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# ASM sources
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ASM_SOURCES = \
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@ -12,4 +12,38 @@ set(LVGL_DEFINES
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add_library(lvgl STATIC ${LVGL_SOURCES})
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target_include_directories(lvgl PRIVATE ${LVGL_INCLUDES})
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target_compile_definitions(lvgl PRIVATE ${LVGL_DEFINES})
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target_compile_definitions(lvgl PRIVATE ${LVGL_DEFINES})
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set(RTOS_SOURCES
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"Third_Party/FreeRTOS/Source/croutine.c"
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"Third_Party/FreeRTOS/Source/event_groups.c"
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"Third_Party/FreeRTOS/Source/list.c"
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"Third_Party/FreeRTOS/Source/queue.c"
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"Third_Party/FreeRTOS/Source/stream_buffer.c"
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"Third_Party/FreeRTOS/Source/tasks.c"
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"Third_Party/FreeRTOS/Source/timers.c"
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"Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c"
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"Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c"
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"Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c"
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)
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set(RTOS_INCLUDES
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"../Core/Inc"
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"../Drivers/CMSIS/Include"
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"../Drivers/CMSIS/Device/ST/STM32H7xx/Include"
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"../Drivers/STM32H7xx_HAL_Driver/Inc"
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"../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"
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"Third_Party/FreeRTOS/Source/include"
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"Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"
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"Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
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)
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set(RTOS_DEFINES
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"STM32H750xx"
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"USE_HAL_DRIVER"
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"USE_FULL_LL_DRIVER"
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)
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add_library(rtos STATIC ${RTOS_SOURCES})
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target_include_directories(rtos PRIVATE ${RTOS_INCLUDES})
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target_compile_definitions(rtos PRIVATE ${RTOS_DEFINES})
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@ -4,42 +4,52 @@ CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_RE
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CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_FULL_ACCESS
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CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_FULL_ACCESS
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CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_FULL_ACCESS
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CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_REGION_FULL_ACCESS
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CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000
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CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings=0x20000000
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CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings=0x24000000
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CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings=0x60000000
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CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings=0x30000000
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CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region5_Settings=0x60000000
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CORTEX_M7.CPU_DCache=Enabled
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CORTEX_M7.CPU_ICache=Enabled
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_ENABLE
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
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CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE
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CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE
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CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_ENABLE
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CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_ENABLE
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CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_ENABLE
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CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region4_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings,Size-Cortex_Memory_Protection_Unit_Region4_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings
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CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_REGION_ENABLE
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CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region4_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings,Size-Cortex_Memory_Protection_Unit_Region4_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings,Enable-Cortex_Memory_Protection_Unit_Region5_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region5_Settings,Size-Cortex_Memory_Protection_Unit_Region5_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region5_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region5_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region5_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region5_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region5_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region4_Settings
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CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_BUFFERABLE
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CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_BUFFERABLE
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CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_BUFFERABLE
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CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_BUFFERABLE
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CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_ACCESS_NOT_BUFFERABLE
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_CACHEABLE
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_CACHEABLE
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_CACHEABLE
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_ACCESS_NOT_CACHEABLE
|
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CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.MPU_Control=MPU_HFNMI_PRIVDEF_NONE
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_16MB
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_SIZE_128KB
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_SIZE_512KB
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_SIZE_256MB
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_REGION_SIZE_256MB
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LEVEL1
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL1
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_TEX_LEVEL1
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_TEX_LEVEL1
|
||||
Dma.MEMTOMEM.0.Direction=DMA_MEMORY_TO_MEMORY
|
||||
Dma.MEMTOMEM.0.EventEnable=DISABLE
|
||||
Dma.MEMTOMEM.0.FIFOMode=DMA_FIFOMODE_ENABLE
|
||||
|
|
@ -63,6 +73,7 @@ Dma.MEMTOMEM.0.SyncRequestNumber=1
|
|||
Dma.MEMTOMEM.0.SyncSignalID=NONE
|
||||
Dma.Request0=MEMTOMEM
|
||||
Dma.RequestsNb=1
|
||||
FATFS.BSP.number=1
|
||||
FATFS.IPParameters=_USE_LFN,_CODE_PAGE,_LFN_UNICODE,_FS_EXFAT,_USE_MUTEX,_USE_FIND,_STRF_ENCODE
|
||||
FATFS._CODE_PAGE=932
|
||||
FATFS._FS_EXFAT=1
|
||||
|
|
@ -71,6 +82,18 @@ FATFS._STRF_ENCODE=0
|
|||
FATFS._USE_FIND=1
|
||||
FATFS._USE_LFN=3
|
||||
FATFS._USE_MUTEX=1
|
||||
FATFS0.BSP.STBoard=false
|
||||
FATFS0.BSP.api=Unknown
|
||||
FATFS0.BSP.component=
|
||||
FATFS0.BSP.condition=
|
||||
FATFS0.BSP.i2caddr=0
|
||||
FATFS0.BSP.i2creg=
|
||||
FATFS0.BSP.instance=PC13
|
||||
FATFS0.BSP.ip=GPIO
|
||||
FATFS0.BSP.mode=Input
|
||||
FATFS0.BSP.name=Detect_SDIO
|
||||
FATFS0.BSP.semaphore=
|
||||
FATFS0.BSP.solution=PC13
|
||||
FMC.AddressSetupTime1=5
|
||||
FMC.BusTurnAroundDuration1=5
|
||||
FMC.DataSetupTime1=5
|
||||
|
|
@ -98,52 +121,53 @@ Mcu.IPNb=12
|
|||
Mcu.Name=STM32H750VBTx
|
||||
Mcu.Package=LQFP100
|
||||
Mcu.Pin0=PE2
|
||||
Mcu.Pin1=PC14-OSC32_IN (OSC32_IN)
|
||||
Mcu.Pin10=PE9
|
||||
Mcu.Pin11=PE10
|
||||
Mcu.Pin12=PE11
|
||||
Mcu.Pin13=PE12
|
||||
Mcu.Pin14=PE13
|
||||
Mcu.Pin15=PE14
|
||||
Mcu.Pin16=PE15
|
||||
Mcu.Pin17=PB10
|
||||
Mcu.Pin18=PB14
|
||||
Mcu.Pin19=PB15
|
||||
Mcu.Pin2=PC15-OSC32_OUT (OSC32_OUT)
|
||||
Mcu.Pin20=PD8
|
||||
Mcu.Pin21=PD9
|
||||
Mcu.Pin22=PD10
|
||||
Mcu.Pin23=PD11
|
||||
Mcu.Pin24=PD14
|
||||
Mcu.Pin25=PD15
|
||||
Mcu.Pin26=PC7
|
||||
Mcu.Pin27=PC9
|
||||
Mcu.Pin28=PA13 (JTMS/SWDIO)
|
||||
Mcu.Pin29=PA14 (JTCK/SWCLK)
|
||||
Mcu.Pin3=PH0-OSC_IN (PH0)
|
||||
Mcu.Pin30=PA15 (JTDI)
|
||||
Mcu.Pin31=PC10
|
||||
Mcu.Pin32=PC11
|
||||
Mcu.Pin33=PD0
|
||||
Mcu.Pin34=PD1
|
||||
Mcu.Pin35=PD4
|
||||
Mcu.Pin36=PD5
|
||||
Mcu.Pin37=PD6
|
||||
Mcu.Pin38=PD7
|
||||
Mcu.Pin39=PB3 (JTDO/TRACESWO)
|
||||
Mcu.Pin4=PH1-OSC_OUT (PH1)
|
||||
Mcu.Pin40=PB4 (NJTRST)
|
||||
Mcu.Pin41=VP_FATFS_VS_SDIO
|
||||
Mcu.Pin42=VP_FREERTOS_VS_CMSIS_V2
|
||||
Mcu.Pin43=VP_RTC_VS_RTC_Activate
|
||||
Mcu.Pin44=VP_RTC_VS_RTC_Calendar
|
||||
Mcu.Pin45=VP_SYS_VS_tim6
|
||||
Mcu.Pin5=PA1
|
||||
Mcu.Pin6=PB1
|
||||
Mcu.Pin7=PB2
|
||||
Mcu.Pin8=PE7
|
||||
Mcu.Pin9=PE8
|
||||
Mcu.PinsNb=46
|
||||
Mcu.Pin1=PC13
|
||||
Mcu.Pin10=PE8
|
||||
Mcu.Pin11=PE9
|
||||
Mcu.Pin12=PE10
|
||||
Mcu.Pin13=PE11
|
||||
Mcu.Pin14=PE12
|
||||
Mcu.Pin15=PE13
|
||||
Mcu.Pin16=PE14
|
||||
Mcu.Pin17=PE15
|
||||
Mcu.Pin18=PB10
|
||||
Mcu.Pin19=PB14
|
||||
Mcu.Pin2=PC14-OSC32_IN (OSC32_IN)
|
||||
Mcu.Pin20=PB15
|
||||
Mcu.Pin21=PD8
|
||||
Mcu.Pin22=PD9
|
||||
Mcu.Pin23=PD10
|
||||
Mcu.Pin24=PD11
|
||||
Mcu.Pin25=PD14
|
||||
Mcu.Pin26=PD15
|
||||
Mcu.Pin27=PC7
|
||||
Mcu.Pin28=PC9
|
||||
Mcu.Pin29=PA13 (JTMS/SWDIO)
|
||||
Mcu.Pin3=PC15-OSC32_OUT (OSC32_OUT)
|
||||
Mcu.Pin30=PA14 (JTCK/SWCLK)
|
||||
Mcu.Pin31=PA15 (JTDI)
|
||||
Mcu.Pin32=PC10
|
||||
Mcu.Pin33=PC11
|
||||
Mcu.Pin34=PD0
|
||||
Mcu.Pin35=PD1
|
||||
Mcu.Pin36=PD4
|
||||
Mcu.Pin37=PD5
|
||||
Mcu.Pin38=PD6
|
||||
Mcu.Pin39=PD7
|
||||
Mcu.Pin4=PH0-OSC_IN (PH0)
|
||||
Mcu.Pin40=PB3 (JTDO/TRACESWO)
|
||||
Mcu.Pin41=PB4 (NJTRST)
|
||||
Mcu.Pin42=VP_FATFS_VS_SDIO
|
||||
Mcu.Pin43=VP_FREERTOS_VS_CMSIS_V2
|
||||
Mcu.Pin44=VP_RTC_VS_RTC_Activate
|
||||
Mcu.Pin45=VP_RTC_VS_RTC_Calendar
|
||||
Mcu.Pin46=VP_SYS_VS_tim6
|
||||
Mcu.Pin5=PH1-OSC_OUT (PH1)
|
||||
Mcu.Pin6=PA1
|
||||
Mcu.Pin7=PB1
|
||||
Mcu.Pin8=PB2
|
||||
Mcu.Pin9=PE7
|
||||
Mcu.PinsNb=47
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32H750VBTx
|
||||
|
|
@ -208,6 +232,11 @@ PC11.GPIOParameters=GPIO_Label
|
|||
PC11.GPIO_Label=LED1
|
||||
PC11.Locked=true
|
||||
PC11.Signal=GPIO_Output
|
||||
PC13.GPIOParameters=GPIO_PuPd,GPIO_Label
|
||||
PC13.GPIO_Label=SDMMC_CD
|
||||
PC13.GPIO_PuPd=GPIO_PULLUP
|
||||
PC13.Locked=true
|
||||
PC13.Signal=GPIO_Input
|
||||
PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
|
||||
PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
|
||||
PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
|
||||
|
|
|
|||
Loading…
Reference in New Issue