diff --git a/CMakeLists.txt b/CMakeLists.txt
index 09e7cfe..161fef9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -31,20 +31,11 @@ set(C_SOURCES
"Core/Src/kururin_pa.c"
"Core/Src/system_stm32h7xx.c"
"Core/Src/freertos.c"
- "Middlewares/Third_Party/FreeRTOS/Source/croutine.c"
- "Middlewares/Third_Party/FreeRTOS/Source/event_groups.c"
- "Middlewares/Third_Party/FreeRTOS/Source/list.c"
- "Middlewares/Third_Party/FreeRTOS/Source/queue.c"
- "Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c"
- "Middlewares/Third_Party/FreeRTOS/Source/tasks.c"
- "Middlewares/Third_Party/FreeRTOS/Source/timers.c"
- "Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c"
- "Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c"
- "Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c"
"Core/Src/stm32h7xx_hal_timebase_tim.c"
"FATFS/App/fatfs.c"
"FATFS/Target/bsp_driver_sd.c"
"FATFS/Target/sd_diskio.c"
+ "FATFS/Target/fatfs_platform.c"
"Middlewares/Third_Party/FatFs/src/diskio.c"
"Middlewares/Third_Party/FatFs/src/ff.c"
"Middlewares/Third_Party/FatFs/src/ff_gen_drv.c"
@@ -59,6 +50,7 @@ set(ASM_SOURCES
set(C_LIBRARIES
"lvgl"
+ "rtos"
"stm32_hal_driver"
)
@@ -139,6 +131,7 @@ target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf"
# Additional defines
target_compile_definitions("${CMAKE_PROJECT_NAME}_RAM.elf"
PRIVATE "VECT_TAB_SRAM"
+ PRIVATE "DATA_IN_D2_SRAM"
)
add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex"
@@ -166,7 +159,7 @@ target_link_options("${CMAKE_PROJECT_NAME}_QSPI_FLASH.elf"
# Additional defines
target_compile_definitions("${CMAKE_PROJECT_NAME}_QSPI_FLASH.elf"
- PRIVATE "VECT_TAB_SRAM"
+ PRIVATE "FLASH_XIP_BASE=0x90000000"
)
add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_QSPI_FLASH.hex"
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 48ad626..64b03d2 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -58,6 +58,8 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
+#define SDMMC_CD_Pin GPIO_PIN_13
+#define SDMMC_CD_GPIO_Port GPIOC
#define LCD_BL_Pin GPIO_PIN_1
#define LCD_BL_GPIO_Port GPIOB
#define LED2_Pin GPIO_PIN_15
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 8521ce4..ebb2ddb 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -94,8 +94,10 @@ int main(void)
{
/* USER CODE BEGIN 1 */
- SCB->VTOR = 0x90000000;
+#ifndef VECT_TAB_SRAM
+ SCB->VTOR = FLASH_XIP_BASE;
__enable_irq();
+#endif
/* USER CODE END 1 */
@@ -510,6 +512,12 @@ static void MX_GPIO_Init(void)
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
+ /*Configure GPIO pin : SDMMC_CD_Pin */
+ GPIO_InitStruct.Pin = SDMMC_CD_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(SDMMC_CD_GPIO_Port, &GPIO_InitStruct);
+
/*Configure GPIO pin : LCD_BL_Pin */
GPIO_InitStruct.Pin = LCD_BL_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -605,15 +613,24 @@ void MPU_Config(void)
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
MPU_InitStruct.BaseAddress = 0x24000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
+ MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER4;
- MPU_InitStruct.BaseAddress = 0x60000000;
+ MPU_InitStruct.BaseAddress = 0x30000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_256MB;
+ MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+
+ HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ /** Initializes and configures the Region and the memory to be protected
+ */
+ MPU_InitStruct.Number = MPU_REGION_NUMBER5;
+ MPU_InitStruct.BaseAddress = 0x60000000;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enables the MPU */
diff --git a/FATFS/Target/bsp_driver_sd.c b/FATFS/Target/bsp_driver_sd.c
index 281ede3..4975807 100644
--- a/FATFS/Target/bsp_driver_sd.c
+++ b/FATFS/Target/bsp_driver_sd.c
@@ -295,9 +295,10 @@ __weak uint8_t BSP_SD_IsDetected(void)
{
__IO uint8_t status = SD_PRESENT;
- /* USER CODE BEGIN IsDetectedSection */
- /* user code can be inserted here */
- /* USER CODE END IsDetectedSection */
+ if (BSP_PlatformIsDetected() == 0x0)
+ {
+ status = SD_NOT_PRESENT;
+ }
return status;
}
diff --git a/FATFS/Target/bsp_driver_sd.h b/FATFS/Target/bsp_driver_sd.h
index c599366..9390e36 100644
--- a/FATFS/Target/bsp_driver_sd.h
+++ b/FATFS/Target/bsp_driver_sd.h
@@ -27,6 +27,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
+#include "fatfs_platform.h"
/* Exported types --------------------------------------------------------*/
/**
diff --git a/FATFS/Target/fatfs_platform.c b/FATFS/Target/fatfs_platform.c
new file mode 100644
index 0000000..354bca9
--- /dev/null
+++ b/FATFS/Target/fatfs_platform.c
@@ -0,0 +1,31 @@
+/**
+ ******************************************************************************
+ * @file : fatfs_platform.c
+ * @brief : fatfs_platform source file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+*/
+#include "fatfs_platform.h"
+
+uint8_t BSP_PlatformIsDetected(void) {
+ uint8_t status = SD_PRESENT;
+ /* Check SD card detect pin */
+ if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
+ {
+ status = SD_NOT_PRESENT;
+ }
+ /* USER CODE BEGIN 1 */
+ /* user code can be inserted here */
+ /* USER CODE END 1 */
+ return status;
+}
diff --git a/FATFS/Target/fatfs_platform.h b/FATFS/Target/fatfs_platform.h
new file mode 100644
index 0000000..cee9650
--- /dev/null
+++ b/FATFS/Target/fatfs_platform.h
@@ -0,0 +1,26 @@
+/**
+ ******************************************************************************
+ * @file : fatfs_platform.h
+ * @brief : fatfs_platform header file
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+*/
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+/* Defines ------------------------------------------------------------------*/
+#define SD_PRESENT ((uint8_t)0x01) /* also in bsp_driver_sd.h */
+#define SD_NOT_PRESENT ((uint8_t)0x00) /* also in bsp_driver_sd.h */
+#define SD_DETECT_PIN GPIO_PIN_13
+#define SD_DETECT_GPIO_PORT GPIOC
+/* Prototypes ---------------------------------------------------------------*/
+uint8_t BSP_PlatformIsDetected(void);
diff --git a/Makefile b/Makefile
index ccd39cd..74e330b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
##########################################################################################################################
-# File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Sat Apr 17 14:57:59 CST 2021]
+# File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Sat Apr 17 23:48:08 CST 2021]
##########################################################################################################################
# ------------------------------------------------
@@ -204,7 +204,8 @@ Middlewares/Third_Party/FatFs/src/diskio.c \
Middlewares/Third_Party/FatFs/src/ff.c \
Middlewares/Third_Party/FatFs/src/ff_gen_drv.c \
Middlewares/Third_Party/FatFs/src/option/syscall.c \
-Middlewares/Third_Party/FatFs/src/option/cc932.c
+Middlewares/Third_Party/FatFs/src/option/cc932.c \
+FATFS/Target/fatfs_platform.c
# ASM sources
ASM_SOURCES = \
diff --git a/Middlewares/CMakeLists.txt b/Middlewares/CMakeLists.txt
index 2d9bee8..3141f00 100644
--- a/Middlewares/CMakeLists.txt
+++ b/Middlewares/CMakeLists.txt
@@ -12,4 +12,38 @@ set(LVGL_DEFINES
add_library(lvgl STATIC ${LVGL_SOURCES})
target_include_directories(lvgl PRIVATE ${LVGL_INCLUDES})
-target_compile_definitions(lvgl PRIVATE ${LVGL_DEFINES})
\ No newline at end of file
+target_compile_definitions(lvgl PRIVATE ${LVGL_DEFINES})
+
+set(RTOS_SOURCES
+ "Third_Party/FreeRTOS/Source/croutine.c"
+ "Third_Party/FreeRTOS/Source/event_groups.c"
+ "Third_Party/FreeRTOS/Source/list.c"
+ "Third_Party/FreeRTOS/Source/queue.c"
+ "Third_Party/FreeRTOS/Source/stream_buffer.c"
+ "Third_Party/FreeRTOS/Source/tasks.c"
+ "Third_Party/FreeRTOS/Source/timers.c"
+ "Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c"
+ "Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c"
+ "Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c"
+)
+
+set(RTOS_INCLUDES
+ "../Core/Inc"
+ "../Drivers/CMSIS/Include"
+ "../Drivers/CMSIS/Device/ST/STM32H7xx/Include"
+ "../Drivers/STM32H7xx_HAL_Driver/Inc"
+ "../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"
+ "Third_Party/FreeRTOS/Source/include"
+ "Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"
+ "Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
+)
+
+set(RTOS_DEFINES
+ "STM32H750xx"
+ "USE_HAL_DRIVER"
+ "USE_FULL_LL_DRIVER"
+)
+
+add_library(rtos STATIC ${RTOS_SOURCES})
+target_include_directories(rtos PRIVATE ${RTOS_INCLUDES})
+target_compile_definitions(rtos PRIVATE ${RTOS_DEFINES})
\ No newline at end of file
diff --git a/STM32H750_LCD.ioc b/STM32H750_LCD.ioc
index 79483cd..799000f 100644
--- a/STM32H750_LCD.ioc
+++ b/STM32H750_LCD.ioc
@@ -4,42 +4,52 @@ CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_RE
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_FULL_ACCESS
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_FULL_ACCESS
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_FULL_ACCESS
+CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_REGION_FULL_ACCESS
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings=0x20000000
CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings=0x24000000
-CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings=0x60000000
+CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings=0x30000000
+CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region5_Settings=0x60000000
CORTEX_M7.CPU_DCache=Enabled
CORTEX_M7.CPU_ICache=Enabled
CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
-CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
+CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_ENABLE
CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
+CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_ENABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_ENABLE
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_ENABLE
-CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region4_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings,Size-Cortex_Memory_Protection_Unit_Region4_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings
+CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_REGION_ENABLE
+CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region4_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings,Size-Cortex_Memory_Protection_Unit_Region4_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings,Enable-Cortex_Memory_Protection_Unit_Region5_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region5_Settings,Size-Cortex_Memory_Protection_Unit_Region5_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region5_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region5_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region5_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region5_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region5_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region4_Settings
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_BUFFERABLE
+CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_ACCESS_NOT_BUFFERABLE
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_CACHEABLE
+CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_CACHEABLE
+CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_ACCESS_NOT_CACHEABLE
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_SHAREABLE
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_SHAREABLE
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_SHAREABLE
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_SHAREABLE
+CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_ACCESS_SHAREABLE
CORTEX_M7.MPU_Control=MPU_HFNMI_PRIVDEF_NONE
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_16MB
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_SIZE_128KB
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_SIZE_512KB
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_SIZE_256MB
+CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region5_Settings=MPU_REGION_SIZE_256MB
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LEVEL1
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL1
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_TEX_LEVEL1
+CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_TEX_LEVEL1
Dma.MEMTOMEM.0.Direction=DMA_MEMORY_TO_MEMORY
Dma.MEMTOMEM.0.EventEnable=DISABLE
Dma.MEMTOMEM.0.FIFOMode=DMA_FIFOMODE_ENABLE
@@ -63,6 +73,7 @@ Dma.MEMTOMEM.0.SyncRequestNumber=1
Dma.MEMTOMEM.0.SyncSignalID=NONE
Dma.Request0=MEMTOMEM
Dma.RequestsNb=1
+FATFS.BSP.number=1
FATFS.IPParameters=_USE_LFN,_CODE_PAGE,_LFN_UNICODE,_FS_EXFAT,_USE_MUTEX,_USE_FIND,_STRF_ENCODE
FATFS._CODE_PAGE=932
FATFS._FS_EXFAT=1
@@ -71,6 +82,18 @@ FATFS._STRF_ENCODE=0
FATFS._USE_FIND=1
FATFS._USE_LFN=3
FATFS._USE_MUTEX=1
+FATFS0.BSP.STBoard=false
+FATFS0.BSP.api=Unknown
+FATFS0.BSP.component=
+FATFS0.BSP.condition=
+FATFS0.BSP.i2caddr=0
+FATFS0.BSP.i2creg=
+FATFS0.BSP.instance=PC13
+FATFS0.BSP.ip=GPIO
+FATFS0.BSP.mode=Input
+FATFS0.BSP.name=Detect_SDIO
+FATFS0.BSP.semaphore=
+FATFS0.BSP.solution=PC13
FMC.AddressSetupTime1=5
FMC.BusTurnAroundDuration1=5
FMC.DataSetupTime1=5
@@ -98,52 +121,53 @@ Mcu.IPNb=12
Mcu.Name=STM32H750VBTx
Mcu.Package=LQFP100
Mcu.Pin0=PE2
-Mcu.Pin1=PC14-OSC32_IN (OSC32_IN)
-Mcu.Pin10=PE9
-Mcu.Pin11=PE10
-Mcu.Pin12=PE11
-Mcu.Pin13=PE12
-Mcu.Pin14=PE13
-Mcu.Pin15=PE14
-Mcu.Pin16=PE15
-Mcu.Pin17=PB10
-Mcu.Pin18=PB14
-Mcu.Pin19=PB15
-Mcu.Pin2=PC15-OSC32_OUT (OSC32_OUT)
-Mcu.Pin20=PD8
-Mcu.Pin21=PD9
-Mcu.Pin22=PD10
-Mcu.Pin23=PD11
-Mcu.Pin24=PD14
-Mcu.Pin25=PD15
-Mcu.Pin26=PC7
-Mcu.Pin27=PC9
-Mcu.Pin28=PA13 (JTMS/SWDIO)
-Mcu.Pin29=PA14 (JTCK/SWCLK)
-Mcu.Pin3=PH0-OSC_IN (PH0)
-Mcu.Pin30=PA15 (JTDI)
-Mcu.Pin31=PC10
-Mcu.Pin32=PC11
-Mcu.Pin33=PD0
-Mcu.Pin34=PD1
-Mcu.Pin35=PD4
-Mcu.Pin36=PD5
-Mcu.Pin37=PD6
-Mcu.Pin38=PD7
-Mcu.Pin39=PB3 (JTDO/TRACESWO)
-Mcu.Pin4=PH1-OSC_OUT (PH1)
-Mcu.Pin40=PB4 (NJTRST)
-Mcu.Pin41=VP_FATFS_VS_SDIO
-Mcu.Pin42=VP_FREERTOS_VS_CMSIS_V2
-Mcu.Pin43=VP_RTC_VS_RTC_Activate
-Mcu.Pin44=VP_RTC_VS_RTC_Calendar
-Mcu.Pin45=VP_SYS_VS_tim6
-Mcu.Pin5=PA1
-Mcu.Pin6=PB1
-Mcu.Pin7=PB2
-Mcu.Pin8=PE7
-Mcu.Pin9=PE8
-Mcu.PinsNb=46
+Mcu.Pin1=PC13
+Mcu.Pin10=PE8
+Mcu.Pin11=PE9
+Mcu.Pin12=PE10
+Mcu.Pin13=PE11
+Mcu.Pin14=PE12
+Mcu.Pin15=PE13
+Mcu.Pin16=PE14
+Mcu.Pin17=PE15
+Mcu.Pin18=PB10
+Mcu.Pin19=PB14
+Mcu.Pin2=PC14-OSC32_IN (OSC32_IN)
+Mcu.Pin20=PB15
+Mcu.Pin21=PD8
+Mcu.Pin22=PD9
+Mcu.Pin23=PD10
+Mcu.Pin24=PD11
+Mcu.Pin25=PD14
+Mcu.Pin26=PD15
+Mcu.Pin27=PC7
+Mcu.Pin28=PC9
+Mcu.Pin29=PA13 (JTMS/SWDIO)
+Mcu.Pin3=PC15-OSC32_OUT (OSC32_OUT)
+Mcu.Pin30=PA14 (JTCK/SWCLK)
+Mcu.Pin31=PA15 (JTDI)
+Mcu.Pin32=PC10
+Mcu.Pin33=PC11
+Mcu.Pin34=PD0
+Mcu.Pin35=PD1
+Mcu.Pin36=PD4
+Mcu.Pin37=PD5
+Mcu.Pin38=PD6
+Mcu.Pin39=PD7
+Mcu.Pin4=PH0-OSC_IN (PH0)
+Mcu.Pin40=PB3 (JTDO/TRACESWO)
+Mcu.Pin41=PB4 (NJTRST)
+Mcu.Pin42=VP_FATFS_VS_SDIO
+Mcu.Pin43=VP_FREERTOS_VS_CMSIS_V2
+Mcu.Pin44=VP_RTC_VS_RTC_Activate
+Mcu.Pin45=VP_RTC_VS_RTC_Calendar
+Mcu.Pin46=VP_SYS_VS_tim6
+Mcu.Pin5=PH1-OSC_OUT (PH1)
+Mcu.Pin6=PA1
+Mcu.Pin7=PB1
+Mcu.Pin8=PB2
+Mcu.Pin9=PE7
+Mcu.PinsNb=47
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32H750VBTx
@@ -208,6 +232,11 @@ PC11.GPIOParameters=GPIO_Label
PC11.GPIO_Label=LED1
PC11.Locked=true
PC11.Signal=GPIO_Output
+PC13.GPIOParameters=GPIO_PuPd,GPIO_Label
+PC13.GPIO_Label=SDMMC_CD
+PC13.GPIO_PuPd=GPIO_PULLUP
+PC13.Locked=true
+PC13.Signal=GPIO_Input
PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator