From 9488499f5d762acd3fe85fa5e1f46e14587fb4ba Mon Sep 17 00:00:00 2001 From: imi415 Date: Fri, 29 Jan 2021 00:38:33 +0800 Subject: [PATCH] More driver related changes. --- Core/Inc/main.h | 2 + Core/Inc/otm8009a_lcd.h | 18 +++++- Core/Inc/otm_lcd_impl.h | 10 ++++ Core/Inc/stm32h7xx_it.h | 6 ++ Core/Src/main.c | 54 +++++++++++++++++- Core/Src/otm8009a_lcd.c | 74 +++++++++++++++++++++++- Core/Src/otm_lcd_impl.c | 29 ++++++++++ Core/Src/stm32h7xx_hal_msp.c | 22 +++++++ Core/Src/stm32h7xx_it.c | 84 ++++++++++++++++++++++++++- Makefile | 8 ++- STM32H750_LCD.ioc | 107 +++++++++++++++++++++-------------- generic_stm32h7.cfg | 7 +++ 12 files changed, 369 insertions(+), 52 deletions(-) create mode 100644 Core/Inc/otm_lcd_impl.h create mode 100644 Core/Src/otm_lcd_impl.c create mode 100644 generic_stm32h7.cfg diff --git a/Core/Inc/main.h b/Core/Inc/main.h index 7e18ee0..8cc7353 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -58,6 +58,8 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ +#define LCD_BL_Pin GPIO_PIN_1 +#define LCD_BL_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/Core/Inc/otm8009a_lcd.h b/Core/Inc/otm8009a_lcd.h index 35a5497..ec3744d 100644 --- a/Core/Inc/otm8009a_lcd.h +++ b/Core/Inc/otm8009a_lcd.h @@ -24,14 +24,30 @@ typedef enum { OTM_ERROR } otm_ret_t; +typedef enum { + OTM_HORIZONTAL, + OTM_HORIZONTAL_INV, + OTM_VERTICAL, + OTM_VERTICAL_INV +} otm_direction_t; + typedef struct { - otm_ret_t (*write_cmd_cb)(void *handle, otm_data_t reg, otm_data_t val); + otm_ret_t (*write_reg_cb)(void *handle, otm_data_t *reg, uint8_t len); otm_ret_t (*write_data_cb)(void *handle, otm_data_t *data, uint32_t len); + otm_ret_t (*delay_cb)(void *handle, uint32_t usec); } otm_cb_t; typedef struct { + otm_direction_t direction; void *user_data; otm_cb_t cb; } otm_t; +#define OTM_ERROR_CHECK(x) if(x != OTM_OK) return OTM_ERROR + +otm_ret_t otm_lcd_init(otm_t *lcd); +otm_ret_t otm_lcd_display(otm_t *lcd, uint8_t on); +otm_ret_t otm_lcd_upload(otm_t *lcd, uint16_t x1, uint16_t x2, uint16_t y1, uint16_t y2, uint16_t *data); +otm_ret_t otm_lcd_direction(otm_t *lcd, otm_direction_t direction); + #endif \ No newline at end of file diff --git a/Core/Inc/otm_lcd_impl.h b/Core/Inc/otm_lcd_impl.h new file mode 100644 index 0000000..06e8e87 --- /dev/null +++ b/Core/Inc/otm_lcd_impl.h @@ -0,0 +1,10 @@ +#ifndef __OTM_LCD_IMPL_H +#define __OTM_LCD_IMPL_H + +#include "otm8009a_lcd.h" + +otm_ret_t _otm_impl_write_reg(void *handle, otm_data_t *reg, uint8_t len); +otm_ret_t _otm_impl_write_data(void *handle, otm_data_t *data, uint32_t len); +otm_ret_t _otm_impl_delay(void *handle, uint32_t usec); + +#endif \ No newline at end of file diff --git a/Core/Inc/stm32h7xx_it.h b/Core/Inc/stm32h7xx_it.h index f69e0dd..3d4f2e3 100644 --- a/Core/Inc/stm32h7xx_it.h +++ b/Core/Inc/stm32h7xx_it.h @@ -56,6 +56,12 @@ void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); +void PVD_AVD_IRQHandler(void); +void FLASH_IRQHandler(void); +void RCC_IRQHandler(void); +void FPU_IRQHandler(void); +void QUADSPI_IRQHandler(void); +void HSEM1_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/main.c b/Core/Src/main.c index 4d123e2..b3771af 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -23,6 +23,10 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include +#include "otm8009a_lcd.h" +#include "otm_lcd_impl.h" + /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -49,6 +53,15 @@ SRAM_HandleTypeDef hsram1; /* USER CODE BEGIN PV */ +otm_t g_lcd = { + .cb = { + .delay_cb = _otm_impl_delay, + .write_data_cb = _otm_impl_write_data, + .write_reg_cb = _otm_impl_write_reg + }, + .user_data = NULL +}; + /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ @@ -75,6 +88,9 @@ int main(void) { /* USER CODE BEGIN 1 */ + SCB->VTOR = 0x90000000; + __enable_irq(); + /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ @@ -109,6 +125,12 @@ int main(void) MX_RTC_Init(); /* USER CODE BEGIN 2 */ + otm_lcd_init(&g_lcd); + otm_lcd_direction(&g_lcd, OTM_HORIZONTAL_INV); + uint32_t color[1024]; + memset(color, 0xFF, 1024 * 4); + otm_lcd_upload(&g_lcd, 0, 99, 0, 9, (uint16_t *)color); + /* USER CODE END 2 */ /* Infinite loop */ @@ -154,7 +176,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 8; RCC_OscInitStruct.PLL.PLLN = 336; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; @@ -182,7 +204,7 @@ void SystemClock_Config(void) } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_QSPI |RCC_PERIPHCLK_FMC|RCC_PERIPHCLK_CKPER; - PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK; + PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL; PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_CLKP; PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; @@ -205,6 +227,8 @@ static void MX_QUADSPI_Init(void) /* USER CODE BEGIN QUADSPI_Init 0 */ + return; + /* USER CODE END QUADSPI_Init 0 */ /* USER CODE BEGIN QUADSPI_Init 1 */ @@ -354,6 +378,7 @@ static void MX_FMC_Init(void) */ static void MX_GPIO_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); @@ -363,6 +388,16 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin : LCD_BL_Pin */ + GPIO_InitStruct.Pin = LCD_BL_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ @@ -436,6 +471,21 @@ void MPU_Config(void) MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER4; + MPU_InitStruct.BaseAddress = 0x60000000; + MPU_InitStruct.Size = MPU_REGION_SIZE_256MB; + MPU_InitStruct.SubRegionDisable = 0x0; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + HAL_MPU_ConfigRegion(&MPU_InitStruct); /* Enables the MPU */ HAL_MPU_Enable(MPU_HFNMI_PRIVDEF_NONE); diff --git a/Core/Src/otm8009a_lcd.c b/Core/Src/otm8009a_lcd.c index bfc2418..cb4915b 100644 --- a/Core/Src/otm8009a_lcd.c +++ b/Core/Src/otm8009a_lcd.c @@ -50,17 +50,87 @@ uint16_t otm8009a_800480_16b_init_sequence[] = { 0x0001, 0xcca1, 0x0000, 0x0001, 0xcca2, 0x0000, 0x0001, 0xcca3, 0x0000, 0x0001, 0xcca4, 0x0000, 0x0001, 0xcca5, 0x0000, 0x0001, 0xcca6, 0x0000, 0x0001, 0xcca7, 0x0000, 0x0001, 0xcca8, 0x0000, 0x0001, 0xcca9, 0x0000, +0x0001, 0x3a00, 0x0057 }; otm_ret_t _otm_lcd_init_seq(otm_t *lcd) { uint16_t i = 0; while(i < (sizeof(OTM_PANEL_SELECTION) / sizeof(otm_data_t))) { - OLED_ERROR_CHECK(lcd->cb.write_cmd_cb(lcd->user_data, &OTM_PANEL_SELECTION[i + 1], OTM_PANEL_SELECTION[i] + 1)); + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, &OTM_PANEL_SELECTION[i + 1], OTM_PANEL_SELECTION[i] + 1)); i += OTM_PANEL_SELECTION[i] + 2; } return OTM_OK; } -otm_ret_t otm_lcd_init(otm_t *lcd) { +otm_ret_t _otm_lcd_sleep(otm_t *lcd, uint8_t sleep) { + uint16_t reg = sleep ? 0x1000 : 0x1100; // SLPIN : SLPOUT + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, ®, 0x01)); + OTM_ERROR_CHECK(lcd->cb.delay_cb(lcd->user_data, 10000)); // 5ms delay. + return OTM_OK; +} + +otm_ret_t _otm_lcd_window(otm_t *lcd, uint16_t x_start, uint16_t x_end, uint16_t y_start, uint16_t y_end) { + uint16_t reg[] = { 0x2A00, x_start >> 0x08U }; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2A01; reg[1] = x_start & 0xFFU; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2A02; reg[1] = x_end >> 0x08U; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2A03; reg[1] = x_end & 0xFFU; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2B00; reg[1] = y_start >> 0x08U; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2B01; reg[1] = y_start & 0xFFU; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2B02; reg[1] = y_end >> 0x08U; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + reg[0] = 0x2B03; reg[1] = y_end & 0xFFU; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + + return OTM_OK; +} + +otm_ret_t otm_lcd_init(otm_t *lcd) { + OTM_ERROR_CHECK(lcd->cb.delay_cb(lcd, 100000)); //50ms + OTM_ERROR_CHECK(_otm_lcd_init_seq(lcd)); + OTM_ERROR_CHECK(_otm_lcd_sleep(lcd, 0)); + OTM_ERROR_CHECK(otm_lcd_display(lcd, 1)); + + return OTM_OK; +} + +otm_ret_t otm_lcd_display(otm_t *lcd, uint8_t on) { + uint16_t reg = on ? 0x2900 : 0x2800; // DISPON : DISPOFF + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, ®, 0x01)); + + return OTM_OK; +} + +otm_ret_t otm_lcd_upload(otm_t *lcd, uint16_t x1, uint16_t x2, uint16_t y1, uint16_t y2, uint16_t *data) { + OTM_ERROR_CHECK(_otm_lcd_window(lcd, x1, x2, y1, y2)); + + uint32_t pixels = (y2 - y1 + 1) * (x2 - x1 + 1); + + uint16_t reg = 0x2C00; + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, ®, 0x01)); + OTM_ERROR_CHECK(lcd->cb.write_data_cb(lcd->user_data, data, pixels * 2)); + + return OTM_OK; +} + +otm_ret_t otm_lcd_direction(otm_t *lcd, otm_direction_t direction) { + uint16_t reg[] = { 0x3600, (1U << 5U) | (1U << 6U) }; + switch(direction) { + case OTM_HORIZONTAL_INV: + reg[1] = (1U << 7U) | (1U << 5U); + break; + case OTM_HORIZONTAL: + default: + break; + } + OTM_ERROR_CHECK(lcd->cb.write_reg_cb(lcd->user_data, reg, 0x02)); + lcd->direction = direction; + + return OTM_OK; } \ No newline at end of file diff --git a/Core/Src/otm_lcd_impl.c b/Core/Src/otm_lcd_impl.c new file mode 100644 index 0000000..f7b7c94 --- /dev/null +++ b/Core/Src/otm_lcd_impl.c @@ -0,0 +1,29 @@ +#include "stm32h7xx_hal.h" + +#include "otm_lcd_impl.h" + +#define LCD_REGISTER_ADDR 0x60000000 +#define LCD_DATA_ADDR 0x60020000 + +otm_ret_t _otm_impl_write_reg(void *handle, otm_data_t *reg, uint8_t len) { + *(uint16_t *)LCD_REGISTER_ADDR = *reg; + for(uint8_t i = 1; i < len; i++) { + *(uint16_t *)LCD_DATA_ADDR = reg[i]; + } + + return OTM_OK; +} + +otm_ret_t _otm_impl_write_data(void *handle, otm_data_t *data, uint32_t len) { + for(uint32_t i = 0; i < len; i++){ + *(uint16_t *)LCD_DATA_ADDR = data[i]; + } + + return OTM_OK; +} + +otm_ret_t _otm_impl_delay(void *handle, uint32_t usec) { + HAL_Delay(usec / 1000); + + return OTM_OK; +} \ No newline at end of file diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c index 4b69c8e..376c3b8 100644 --- a/Core/Src/stm32h7xx_hal_msp.c +++ b/Core/Src/stm32h7xx_hal_msp.c @@ -71,6 +71,23 @@ void HAL_MspInit(void) /* System interrupt init*/ + /* Peripheral interrupt init */ + /* PVD_AVD_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PVD_AVD_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(PVD_AVD_IRQn); + /* FLASH_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(FLASH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FLASH_IRQn); + /* RCC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(RCC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(RCC_IRQn); + /* FPU_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(FPU_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FPU_IRQn); + /* HSEM1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(HSEM1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(HSEM1_IRQn); + /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ @@ -133,6 +150,9 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + /* QUADSPI interrupt Init */ + HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(QUADSPI_IRQn); /* USER CODE BEGIN QUADSPI_MspInit 1 */ /* USER CODE END QUADSPI_MspInit 1 */ @@ -172,6 +192,8 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) HAL_GPIO_DeInit(GPIOC, GPIO_PIN_9|GPIO_PIN_10); + /* QUADSPI interrupt DeInit */ + HAL_NVIC_DisableIRQ(QUADSPI_IRQn); /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ /* USER CODE END QUADSPI_MspDeInit 1 */ diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c index 900df9a..b9ff546 100644 --- a/Core/Src/stm32h7xx_it.c +++ b/Core/Src/stm32h7xx_it.c @@ -56,7 +56,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ - +extern QSPI_HandleTypeDef hqspi; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -200,6 +200,88 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32h7xx.s). */ /******************************************************************************/ +/** + * @brief This function handles PVD and AVD interrupts through EXTI line 16. + */ +void PVD_AVD_IRQHandler(void) +{ + /* USER CODE BEGIN PVD_AVD_IRQn 0 */ + + /* USER CODE END PVD_AVD_IRQn 0 */ + HAL_PWREx_PVD_AVD_IRQHandler(); + /* USER CODE BEGIN PVD_AVD_IRQn 1 */ + + /* USER CODE END PVD_AVD_IRQn 1 */ +} + +/** + * @brief This function handles Flash global interrupt. + */ +void FLASH_IRQHandler(void) +{ + /* USER CODE BEGIN FLASH_IRQn 0 */ + + /* USER CODE END FLASH_IRQn 0 */ + HAL_FLASH_IRQHandler(); + /* USER CODE BEGIN FLASH_IRQn 1 */ + + /* USER CODE END FLASH_IRQn 1 */ +} + +/** + * @brief This function handles RCC global interrupt. + */ +void RCC_IRQHandler(void) +{ + /* USER CODE BEGIN RCC_IRQn 0 */ + + /* USER CODE END RCC_IRQn 0 */ + /* USER CODE BEGIN RCC_IRQn 1 */ + + /* USER CODE END RCC_IRQn 1 */ +} + +/** + * @brief This function handles FPU global interrupt. + */ +void FPU_IRQHandler(void) +{ + /* USER CODE BEGIN FPU_IRQn 0 */ + + /* USER CODE END FPU_IRQn 0 */ + /* USER CODE BEGIN FPU_IRQn 1 */ + + /* USER CODE END FPU_IRQn 1 */ +} + +/** + * @brief This function handles QUADSPI global interrupt. + */ +void QUADSPI_IRQHandler(void) +{ + /* USER CODE BEGIN QUADSPI_IRQn 0 */ + + /* USER CODE END QUADSPI_IRQn 0 */ + HAL_QSPI_IRQHandler(&hqspi); + /* USER CODE BEGIN QUADSPI_IRQn 1 */ + + /* USER CODE END QUADSPI_IRQn 1 */ +} + +/** + * @brief This function handles HSEM1 global interrupt. + */ +void HSEM1_IRQHandler(void) +{ + /* USER CODE BEGIN HSEM1_IRQn 0 */ + + /* USER CODE END HSEM1_IRQn 0 */ + HAL_HSEM_IRQHandler(); + /* USER CODE BEGIN HSEM1_IRQn 1 */ + + /* USER CODE END HSEM1_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Makefile b/Makefile index 2306dd8..10035f4 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Thu Jan 28 01:56:49 CST 2021] +# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Thu Jan 28 22:34:22 CST 2021] ########################################################################################################################## # ------------------------------------------------ @@ -39,6 +39,8 @@ C_SOURCES = \ Core/Src/main.c \ Core/Src/stm32h7xx_it.c \ Core/Src/stm32h7xx_hal_msp.c \ +Core/Src/otm8009a_lcd.c \ +Core/Src/otm_lcd_impl.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ @@ -62,7 +64,7 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \ -Core/Src/system_stm32h7xx.c +Core/Src/system_stm32h7xx.c # ASM sources ASM_SOURCES = \ @@ -195,4 +197,4 @@ clean: ####################################### -include $(wildcard $(BUILD_DIR)/*.d) -# *** EOF *** \ No newline at end of file +# *** EOF *** diff --git a/STM32H750_LCD.ioc b/STM32H750_LCD.ioc index 9d9f247..6c79110 100644 --- a/STM32H750_LCD.ioc +++ b/STM32H750_LCD.ioc @@ -1,10 +1,12 @@ #MicroXplorer Configuration settings - do not modify Mcu.Family=STM32H7 +NVIC.FLASH_IRQn=true\:0\:0\:false\:false\:true\:true\:true RCC.DIVQ2Freq_Value=16125000 ProjectManager.MainLocation=Core/Src SH.FMC_D7_DA7.0=FMC_D7,16b-d1 SH.FMC_D0_DA0.ConfNb=1 -RCC.SAI1Freq_Value=168000000 +CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_INSTRUCTION_ACCESS_DISABLE +RCC.SAI1Freq_Value=84000000 RCC.CortexFreq_Value=168000000 SH.FMC_D6_DA6.ConfNb=1 SH.FMC_D9_DA9.ConfNb=1 @@ -18,7 +20,7 @@ PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN PC10.Locked=true PC10.Signal=QUADSPI_BK1_IO1 PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_FMC_Init-FMC-false-HAL-true,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true SH.FMC_D6_DA6.0=FMC_D6,16b-d1 VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled RCC.RTCFreq_Value=32000 @@ -27,6 +29,7 @@ CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_RE VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar RCC.CpuClockFreq_Value=168000000 RCC.VCO2OutputFreq_Value=32250000 +CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_SHAREABLE SH.FMC_D5_DA5.0=FMC_D5,16b-d1 SH.FMC_NOE.ConfNb=1 PinOutPanel.RotationAngle=0 @@ -51,7 +54,7 @@ Mcu.IP1=FMC CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_BUFFERABLE Mcu.UserConstants= RCC.DIVP3Freq_Value=16125000 -RCC.SDMMCFreq_Value=168000000 +RCC.SDMMCFreq_Value=84000000 Mcu.ThirdPartyNb=0 SH.FMC_D11_DA11.0=FMC_D11,16b-d1 RCC.HCLKFreq_Value=84000000 @@ -61,17 +64,17 @@ Mcu.IPNb=7 ProjectManager.PreviousToolchain= PD4.Signal=FMC_NOE SH.FMC_NWE.ConfNb=1 -RCC.SPDIFRXFreq_Value=168000000 +RCC.SPDIFRXFreq_Value=84000000 SH.FMC_D10_DA10.ConfNb=1 PC7.Signal=FMC_NE1 CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_TEX_LEVEL1 RCC.DIVQ3Freq_Value=16125000 -Mcu.Pin6=PB2 +Mcu.Pin6=PB1 PD0.Signal=FMC_D2_DA2 -Mcu.Pin7=PE7 +Mcu.Pin7=PB2 PD8.Signal=FMC_D13_DA13 -Mcu.Pin8=PE8 -Mcu.Pin9=PE9 +Mcu.Pin8=PE7 +Mcu.Pin9=PE8 Mcu.Pin0=PE2 Mcu.Pin1=PC14-OSC32_IN (OSC32_IN) GPIO.groupedBy= @@ -101,6 +104,7 @@ PE13.Signal=FMC_D10_DA10 ProjectManager.BackupPrevious=false RCC.FMCFreq_Value=84000000 PE9.Signal=FMC_D6_DA6 +PB1.GPIO_Label=LCD_BL SH.FMC_D15_DA15.ConfNb=1 RCC.USART16Freq_Value=84000000 File.Version=6 @@ -110,6 +114,7 @@ PE2.Signal=QUADSPI_BK1_IO2 SH.FMC_D2_DA2.ConfNb=1 SH.FMC_D1_DA1.0=FMC_D1,16b-d1 NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_SIZE_256MB RCC.DIVR2Freq_Value=16125000 PE10.Signal=FMC_D7_DA7 CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE @@ -117,8 +122,10 @@ ProjectManager.HalAssertFull=false RCC.DIVP2Freq_Value=16125000 ProjectManager.ProjectName=STM32H750_LCD RCC.APB3Freq_Value=84000000 +PB1.PinState=GPIO_PIN_SET RCC.MCO2PinFreq_Value=168000000 Mcu.Package=LQFP100 +PB1.Signal=GPIO_Output SH.FMC_D0_DA0.0=FMC_D0,16b-d1 CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000 RCC.EnbaleCSS=true @@ -126,6 +133,7 @@ SH.FMC_D4_DA4.ConfNb=1 ProjectManager.ToolChainLocation= VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar +CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings=0x60000000 SH.FMC_D4_DA4.0=FMC_D4,16b-d1 RCC.DFSDMFreq_Value=84000000 RCC.DIVR1Freq_Value=168000000 @@ -134,7 +142,7 @@ PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator RCC.TraceFreq_Value=64000000 RCC.APB4Freq_Value=84000000 RCC.CECFreq_Value=32000 -RCC.SAI23Freq_Value=168000000 +RCC.SAI23Freq_Value=84000000 CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false RCC.LPUART1Freq_Value=84000000 @@ -145,21 +153,25 @@ PD15.Signal=FMC_D1_DA1 SH.FMC_D3_DA3.0=FMC_D3,16b-d1 ProjectManager.CustomerFirmwarePackage= RCC.Tim2OutputFreq_Value=84000000 -RCC.DFSDMACLkFreq_Value=168000000 +NVIC.RCC_IRQn=true\:0\:0\:false\:false\:true\:true\:false +RCC.DFSDMACLkFreq_Value=84000000 RCC.VCO3OutputFreq_Value=32250000 SH.FMC_D3_DA3.ConfNb=1 VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_FULL_ACCESS +NVIC.QUADSPI_IRQn=true\:0\:0\:false\:false\:true\:true\:true ProjectManager.ProjectFileName=STM32H750_LCD.ioc CORTEX_M7.CPU_ICache=Enabled -Mcu.PinsNb=33 +RCC.DIVQ1=4 +Mcu.PinsNb=34 ProjectManager.NoMain=false CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_SHAREABLE SH.FMC_D10_DA10.0=FMC_D10,16b-d1 CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_BUFFERABLE RCC.SWPMI1Freq_Value=84000000 -RCC.SAI4BFreq_Value=168000000 +CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_ENABLE +RCC.SAI4BFreq_Value=84000000 PC10.Mode=Single Bank 1 PD1.Signal=FMC_D3_DA3 ProjectManager.DefaultFWLocation=true @@ -177,9 +189,10 @@ PD10.Signal=FMC_D15_DA15 RCC.D1CPREFreq_Value=168000000 CORTEX_M7.MPU_Control=MPU_HFNMI_PRIVDEF_NONE RCC.USART234578Freq_Value=84000000 -RCC.Tim1OutputFreq_Value=84000000 RCC.SPI45Freq_Value=84000000 -RCC.SPI123Freq_Value=168000000 +RCC.Tim1OutputFreq_Value=84000000 +RCC.SPI123Freq_Value=84000000 +CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_ACCESS_BUFFERABLE ProjectManager.TargetToolchain=Makefile PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LEVEL1 @@ -193,11 +206,13 @@ CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_ RCC.DIVN1=336 CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_DISABLE ProjectManager.RegisterCallBack= -RCC.USBFreq_Value=168000000 +RCC.USBFreq_Value=84000000 PE11.Signal=FMC_D8_DA8 PA1.Signal=QUADSPI_BK1_IO3 RCC.CKPERFreq_Value=64000000 +PB1.Locked=true PB10.Signal=QUADSPI_BK1_NCS +NVIC.PVD_AVD_IRQn=true\:0\:0\:false\:false\:true\:true\:true CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_ENABLE board=custom ProjectManager.LastFirmware=true @@ -210,45 +225,48 @@ PE15.Signal=FMC_D12_DA12 MxCube.Version=6.1.1 SH.FMC_D13_DA13.ConfNb=1 PE8.Signal=FMC_D5_DA5 -RCC.FDCANFreq_Value=168000000 +RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_PLL +RCC.FDCANFreq_Value=84000000 SH.FMC_D14_DA14.ConfNb=1 RCC.RNGFreq_Value=48000000 -Mcu.Pin30=VP_RTC_VS_RTC_Activate +Mcu.Pin30=PD5 RCC.ADCFreq_Value=16125000 VP_SYS_VS_Systick.Mode=SysTick +Mcu.Pin33=VP_SYS_VS_Systick CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS SH.FMC_D12_DA12.0=FMC_D12,16b-d1 -Mcu.Pin31=VP_RTC_VS_RTC_Calendar -Mcu.Pin32=VP_SYS_VS_Systick +Mcu.Pin31=VP_RTC_VS_RTC_Activate +Mcu.Pin32=VP_RTC_VS_RTC_Calendar NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.HSEM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true SH.FMC_D11_DA11.ConfNb=1 ProjectManager.FreePins=false -RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value ProjectManager.AskForMigrate=true Mcu.Name=STM32H750VBTx RCC.LPTIM2Freq_Value=84000000 CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB PE12.Signal=FMC_D9_DA9 -Mcu.Pin26=PD0 -Mcu.Pin27=PD1 -Mcu.Pin24=PC9 +Mcu.Pin26=PC10 +Mcu.Pin27=PD0 +Mcu.Pin24=PC7 CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS ProjectManager.UnderRoot=false -Mcu.Pin25=PC10 +Mcu.Pin25=PC9 CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE -CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings +CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region4_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region4_Settings,Size-Cortex_Memory_Protection_Unit_Region4_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region4_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region4_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region4_Settings PD14.Signal=FMC_D0_DA0 -Mcu.Pin28=PD4 +Mcu.Pin28=PD1 Mcu.IP6=SYS -Mcu.Pin29=PD5 +Mcu.Pin29=PD4 ProjectManager.CoupleFile=false SH.FMC_D7_DA7.ConfNb=1 RCC.SYSCLKFreq_VALUE=168000000 -Mcu.Pin22=PD15 +Mcu.Pin22=PD14 RCC.I2C123Freq_Value=84000000 -Mcu.Pin23=PC7 -Mcu.Pin20=PD11 -Mcu.Pin21=PD14 +Mcu.Pin23=PD15 +Mcu.Pin20=PD10 +Mcu.Pin21=PD11 NVIC.ForceEnableDMAVector=true KeepUserPlacement=false PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN @@ -258,26 +276,27 @@ PB2.Mode=Single Bank 1 ProjectManager.CompilerOptimize=6 RCC.QSPICLockSelection=RCC_QSPICLKSOURCE_CLKP ProjectManager.HeapSize=0x200 -Mcu.Pin15=PE15 +Mcu.Pin15=PE14 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -Mcu.Pin16=PB10 -Mcu.Pin13=PE13 -Mcu.Pin14=PE14 +Mcu.Pin16=PE15 +Mcu.Pin13=PE12 +Mcu.Pin14=PE13 CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_ENABLE -Mcu.Pin19=PD10 +Mcu.Pin19=PD9 CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_SIZE_512KB RCC.LPTIM345Freq_Value=84000000 ProjectManager.ComputerToolchain=false -Mcu.Pin17=PD8 -Mcu.Pin18=PD9 +Mcu.Pin17=PB10 +Mcu.Pin18=PD8 CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_INSTRUCTION_ACCESS_DISABLE RCC.LTDCFreq_Value=16125000 -RCC.SAI4AFreq_Value=168000000 +RCC.SAI4AFreq_Value=84000000 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -Mcu.Pin11=PE11 -Mcu.Pin12=PE12 -Mcu.Pin10=PE10 -RCC.DIVQ1Freq_Value=168000000 +Mcu.Pin11=PE10 +Mcu.Pin12=PE11 +Mcu.Pin10=PE9 +RCC.DIVQ1Freq_Value=84000000 +NVIC.FPU_IRQn=true\:0\:0\:false\:false\:true\:true\:false PC9.Signal=QUADSPI_BK1_IO0 CORTEX_M7.CPU_DCache=Enabled PC7.Mode=NorPsramChipSelect1_1 @@ -286,5 +305,7 @@ RCC.HCLK3ClockFreq_Value=84000000 SH.FMC_D8_DA8.ConfNb=1 RCC.VCOInput2Freq_Value=250000 RCC.APB1Freq_Value=84000000 +CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region4_Settings=MPU_REGION_FULL_ACCESS ProjectManager.DeviceId=STM32H750VBTx ProjectManager.LibraryCopy=0 +PB1.GPIOParameters=PinState,GPIO_Label diff --git a/generic_stm32h7.cfg b/generic_stm32h7.cfg new file mode 100644 index 0000000..4694a60 --- /dev/null +++ b/generic_stm32h7.cfg @@ -0,0 +1,7 @@ +source /home/imi415/Documents/Conf/OpenOCD/interface/ft232-swd.cfg + +source [find target/stm32h7x.cfg] + +reset_config none +cortex_m reset_config sysresetreq +gdb_breakpoint_override hw