Updated SDK to 1.9.1
This commit is contained in:
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45f486b172
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GPG Key ID:
17F01E106F9F5E0A
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@ -12,13 +12,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -50,7 +49,7 @@ typedef enum
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{
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/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
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@ -213,12 +212,12 @@ typedef enum
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1U /*!< FPU present */
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#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
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#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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/**
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@ -248,10 +247,10 @@ typedef struct
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__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
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__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
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__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
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__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
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__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
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__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
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__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
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__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
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__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
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uint32_t RESERVED2; /*!< Reserved, 0x02C */
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__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
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__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
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@ -928,8 +927,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
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* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
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* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
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* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
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* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
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* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
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* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
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* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
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* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
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*/
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@ -2700,6 +2699,15 @@ typedef struct
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* @{
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*/
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/** @addtogroup Hardware_Constant_Definition
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* @{
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*/
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#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
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/**
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* @}
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*/
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/** @addtogroup Peripheral_Registers_Bits_Definition
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* @{
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*/
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@ -10803,7 +10811,7 @@ typedef struct
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/******************* Bits definition for FLASH_ACR register **********************/
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#define FLASH_ACR_LATENCY_Pos (0U)
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#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
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#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
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#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
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#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
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#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
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@ -10813,6 +10821,14 @@ typedef struct
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#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
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#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
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#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
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#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
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#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
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#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
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#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
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#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
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/* Legacy FLASH Latency defines */
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#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
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#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
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#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
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@ -10821,12 +10837,6 @@ typedef struct
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#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
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#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
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#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
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#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
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#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
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#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
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#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
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#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
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/******************* Bits definition for FLASH_CR register ***********************/
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#define FLASH_CR_LOCK_Pos (0U)
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#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
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@ -19268,8 +19278,8 @@ typedef struct
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#define TIM_CR2_OIS5_Pos (16U)
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#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
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#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
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#define TIM_CR2_OIS6_Pos (17U)
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#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
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#define TIM_CR2_OIS6_Pos (18U)
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#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
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#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
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#define TIM_CR2_MMS2_Pos (20U)
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@ -19546,8 +19556,8 @@ typedef struct
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#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
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#define TIM_CCMR2_OC3M_Pos (4U)
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#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
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#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
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#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
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#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
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#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
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#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
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#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
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@ -19571,12 +19581,12 @@ typedef struct
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#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
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#define TIM_CCMR2_OC4M_Pos (12U)
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#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
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#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
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#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
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#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
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#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
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#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
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#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
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#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
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#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
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#define TIM_CCMR2_OC4CE_Pos (15U)
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#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
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@ -19782,6 +19792,18 @@ typedef struct
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#define TIM_BDTR_BK2P_Pos (25U)
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#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
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#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
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#define TIM_BDTR_BKDSRM_Pos (26U)
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#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
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#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
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#define TIM_BDTR_BK2DSRM_Pos (27U)
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#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
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#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
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#define TIM_BDTR_BKBID_Pos (28U)
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#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
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#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
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#define TIM_BDTR_BK2BID_Pos (29U)
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#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
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#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
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/******************* Bit definition for TIM_DCR register ********************/
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#define TIM_DCR_DBA_Pos (0U)
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#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
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#define TIM_CCMR3_OC5M_Pos (4U)
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#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
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#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
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#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
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#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
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#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
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#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
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#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
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#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
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#define TIM_CCMR3_OC6M_Pos (12U)
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#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
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#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
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#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
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#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
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#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
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#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
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#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
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#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
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#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
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#define TIM_CCMR3_OC6CE_Pos (15U)
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#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
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@ -23968,6 +23990,7 @@ typedef struct
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((INSTANCE) == TIM4) || \
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((INSTANCE) == TIM5) || \
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((INSTANCE) == TIM8) || \
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((INSTANCE) == TIM12) || \
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((INSTANCE) == TIM15) || \
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((INSTANCE) == TIM23) || \
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((INSTANCE) == TIM24))
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@ -23980,6 +24003,7 @@ typedef struct
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((INSTANCE) == TIM4) || \
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((INSTANCE) == TIM5) || \
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((INSTANCE) == TIM8) || \
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((INSTANCE) == TIM12) || \
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((INSTANCE) == TIM15) || \
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((INSTANCE) == TIM23) || \
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((INSTANCE) == TIM24))
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@ -24231,4 +24255,3 @@ typedef struct
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#endif /* STM32H723xx_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -12,13 +12,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -50,7 +49,7 @@ typedef enum
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{
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/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
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@ -214,12 +213,12 @@ typedef enum
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1U /*!< FPU present */
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#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
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#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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/**
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@ -249,10 +248,10 @@ typedef struct
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__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
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__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
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__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
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__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
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__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
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__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
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__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
|
||||
__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x02C */
|
||||
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
|
||||
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
|
||||
|
|
@ -929,8 +928,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2701,6 +2700,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10804,7 +10812,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10814,6 +10822,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10822,12 +10838,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19280,8 +19290,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -19558,8 +19568,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19583,12 +19593,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19794,6 +19804,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -19828,8 +19850,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19847,12 +19869,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -23980,6 +24002,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -23992,6 +24015,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24243,4 +24267,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H725xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -216,12 +215,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -251,10 +250,10 @@ typedef struct
|
|||
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
|
||||
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
|
||||
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
|
||||
__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
|
||||
__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x02C */
|
||||
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
|
||||
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
|
||||
|
|
@ -931,8 +930,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2835,6 +2834,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -11057,7 +11065,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -11067,6 +11075,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -11075,12 +11091,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19755,8 +19765,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -20033,8 +20043,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20058,12 +20068,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20269,6 +20279,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -20303,8 +20325,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20322,12 +20344,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -24459,6 +24481,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24471,6 +24494,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24722,4 +24746,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H730xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -217,12 +216,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -252,10 +251,10 @@ typedef struct
|
|||
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
|
||||
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
|
||||
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
|
||||
__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
|
||||
__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x02C */
|
||||
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
|
||||
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
|
||||
|
|
@ -932,8 +931,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2836,6 +2835,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -11058,7 +11066,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -11068,6 +11076,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -11076,12 +11092,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19767,8 +19777,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -20045,8 +20055,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20070,12 +20080,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20281,6 +20291,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -20315,8 +20337,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20334,12 +20356,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -24471,6 +24493,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24483,6 +24506,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24734,4 +24758,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H730xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -216,12 +215,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -251,10 +250,10 @@ typedef struct
|
|||
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
|
||||
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
|
||||
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
|
||||
__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
|
||||
__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x02C */
|
||||
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
|
||||
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
|
||||
|
|
@ -931,8 +930,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2835,6 +2834,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -11057,7 +11065,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -11067,6 +11075,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -11075,12 +11091,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19755,8 +19765,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -20033,8 +20043,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20058,12 +20068,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20269,6 +20279,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -20303,8 +20325,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20322,12 +20344,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -24459,6 +24481,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24471,6 +24494,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24722,4 +24746,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H733xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -217,12 +216,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -252,10 +251,10 @@ typedef struct
|
|||
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
|
||||
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
|
||||
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
|
||||
__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
|
||||
__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
|
||||
__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x02C */
|
||||
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
|
||||
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
|
||||
|
|
@ -932,8 +931,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2836,6 +2835,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -11058,7 +11066,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -11068,6 +11076,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -11076,12 +11092,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19767,8 +19777,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -20045,8 +20055,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20070,12 +20080,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20281,6 +20291,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -20315,8 +20337,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20334,12 +20356,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -24471,6 +24493,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24483,6 +24506,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM23) || \
|
||||
((INSTANCE) == TIM24))
|
||||
|
|
@ -24734,4 +24758,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H735xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -212,12 +211,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -885,8 +884,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1638,7 +1637,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2618,6 +2617,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10568,7 +10576,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10578,6 +10586,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10586,12 +10602,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -18698,8 +18708,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18976,8 +18986,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19001,12 +19011,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19246,8 +19256,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19265,12 +19275,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -21742,6 +21752,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -21782,6 +21793,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -25293,7 +25468,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -25490,6 +25666,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -25500,6 +25677,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -25730,4 +25908,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H742xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -215,12 +214,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -888,8 +887,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1725,7 +1724,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2713,6 +2712,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10663,7 +10671,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10673,6 +10681,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10681,12 +10697,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19346,8 +19356,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -19624,8 +19634,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19649,12 +19659,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19894,8 +19904,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19913,12 +19923,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22390,6 +22400,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -22430,6 +22441,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -25943,7 +26118,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -26140,6 +26316,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -26150,6 +26327,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -26380,4 +26558,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H743xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -222,22 +221,22 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#ifdef CORE_CM4
|
||||
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
#else /* UNKNOWN_CORE */
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
|
@ -933,8 +932,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1800,7 +1799,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2807,6 +2806,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10757,11 +10765,15 @@ typedef struct
|
|||
/*
|
||||
* @brief FLASH Global Defines
|
||||
*/
|
||||
#if defined(CORE_CM4)
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#else
|
||||
#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
|
||||
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
|
||||
(((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
|
||||
#endif /* CORE_CM4 */
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
|
|
@ -10770,7 +10782,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10780,6 +10792,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10788,12 +10808,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -20004,8 +20018,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -20282,8 +20296,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20307,12 +20321,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20552,8 +20566,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20571,12 +20585,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -23159,6 +23173,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -23199,6 +23214,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -26719,7 +26898,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -26916,6 +27096,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -26926,6 +27107,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -27157,4 +27339,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H745xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -223,22 +222,22 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#ifdef CORE_CM4
|
||||
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
#else /* UNKNOWN_CORE */
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
|
@ -1014,8 +1013,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1881,7 +1880,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2890,6 +2889,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -13914,11 +13922,15 @@ typedef struct
|
|||
/*
|
||||
* @brief FLASH Global Defines
|
||||
*/
|
||||
#if defined(CORE_CM4)
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#else
|
||||
#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
|
||||
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
|
||||
(((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
|
||||
#endif /* CORE_CM4 */
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
|
|
@ -13927,7 +13939,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -13937,6 +13949,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -13945,12 +13965,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -23177,8 +23191,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -23455,8 +23469,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -23480,12 +23494,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -23725,8 +23739,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -23744,12 +23758,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -26332,6 +26346,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -26372,6 +26387,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -29892,7 +30071,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -30089,6 +30269,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -30099,6 +30280,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -30330,4 +30512,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H747xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -216,12 +215,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -889,8 +888,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1795,7 +1794,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2789,6 +2788,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10856,7 +10864,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10866,6 +10874,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10874,12 +10890,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19627,8 +19637,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -19905,8 +19915,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19930,12 +19940,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20175,8 +20185,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20194,12 +20204,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22671,6 +22681,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -22711,6 +22722,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -26224,7 +26399,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -26421,6 +26597,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -26431,6 +26608,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -26661,4 +26839,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H750xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -216,12 +215,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -889,8 +888,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1795,7 +1794,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2789,6 +2788,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10856,7 +10864,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10866,6 +10874,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10874,12 +10890,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19633,8 +19643,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -19911,8 +19921,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -19936,12 +19946,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20181,8 +20191,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20200,12 +20210,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22677,6 +22687,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -22717,6 +22728,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -26230,7 +26405,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -26427,6 +26603,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -26437,6 +26614,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -26667,4 +26845,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H753xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -223,22 +222,22 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#ifdef CORE_CM4
|
||||
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
#else /* UNKNOWN_CORE */
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
|
@ -934,8 +933,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1870,7 +1869,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2883,6 +2882,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -10950,11 +10958,15 @@ typedef struct
|
|||
/*
|
||||
* @brief FLASH Global Defines
|
||||
*/
|
||||
#if defined(CORE_CM4)
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#else
|
||||
#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
|
||||
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
|
||||
(((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
|
||||
#endif /* CORE_CM4 */
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
|
|
@ -10963,7 +10975,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -10973,6 +10985,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -10981,12 +11001,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -20291,8 +20305,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -20569,8 +20583,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20594,12 +20608,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -20839,8 +20853,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20858,12 +20872,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -23446,6 +23460,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -23486,6 +23501,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -27006,7 +27185,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -27203,6 +27383,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -27213,6 +27394,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -27444,4 +27626,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H755xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -224,22 +223,22 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#ifdef CORE_CM4
|
||||
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
#else /* UNKNOWN_CORE */
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
|
@ -1015,8 +1014,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -1951,7 +1950,7 @@ typedef struct
|
|||
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
|
||||
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
|
||||
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */
|
||||
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
|
||||
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
|
||||
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
|
||||
|
|
@ -2966,6 +2965,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -14107,11 +14115,15 @@ typedef struct
|
|||
/*
|
||||
* @brief FLASH Global Defines
|
||||
*/
|
||||
#if defined(CORE_CM4)
|
||||
#define FLASH_SIZE 0x200000UL /* 2 MB */
|
||||
#else
|
||||
#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
|
||||
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
|
||||
(((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
|
||||
#endif /* CORE_CM4 */
|
||||
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
|
||||
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
|
||||
|
|
@ -14120,7 +14132,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -14130,6 +14142,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -14138,12 +14158,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -23464,8 +23478,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -23742,8 +23756,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -23767,12 +23781,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -24012,8 +24026,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -24031,12 +24045,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -26619,6 +26633,7 @@ typedef struct
|
|||
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
|
||||
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
|
||||
|
||||
/* Slave Timer A reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
|
||||
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
|
|
@ -26659,6 +26674,170 @@ typedef struct
|
|||
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer B reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
|
||||
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
|
||||
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
|
||||
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer C reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
|
||||
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
|
||||
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
|
||||
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer D reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
|
||||
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
|
||||
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
|
||||
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
|
||||
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
|
||||
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
|
||||
|
||||
/* Slave Timer E reset enable bits upon other slave timers events */
|
||||
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
|
||||
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
|
||||
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
|
||||
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
|
||||
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
|
||||
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
|
||||
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
|
||||
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
|
||||
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
|
||||
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
|
||||
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
|
||||
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
|
||||
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
|
||||
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
|
||||
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
|
||||
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
|
||||
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
|
||||
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
|
||||
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
|
||||
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
|
||||
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
|
||||
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
|
||||
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
|
||||
|
||||
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
|
||||
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
|
||||
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
|
||||
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
|
||||
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
|
||||
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
|
||||
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
|
||||
|
||||
/**** Bit definition for Slave Timer Chopper register *************************/
|
||||
#define HRTIM_CHPR_CARFRQ_Pos (0U)
|
||||
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -30179,7 +30358,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -30376,6 +30556,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -30386,6 +30567,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -30617,4 +30799,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H757xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -210,12 +209,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -732,8 +731,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2596,6 +2595,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -8472,7 +8480,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8619,7 +8627,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8629,6 +8637,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8637,12 +8653,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -17597,8 +17607,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -17875,8 +17885,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -17900,12 +17910,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18111,6 +18121,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18145,8 +18167,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18164,12 +18186,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22019,7 +22041,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22216,6 +22239,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22226,6 +22250,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -22529,4 +22554,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7A3xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -211,12 +210,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -733,8 +732,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2597,6 +2596,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -8473,7 +8481,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8620,7 +8628,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8630,6 +8638,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8638,12 +8654,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -17609,8 +17619,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -17887,8 +17897,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -17912,12 +17922,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18123,6 +18133,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18157,8 +18179,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18176,12 +18198,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22031,7 +22053,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22228,6 +22251,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22238,6 +22262,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -22541,4 +22566,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7A3xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -213,12 +212,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -735,8 +734,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2731,6 +2730,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -8726,7 +8734,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8872,7 +8880,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8882,6 +8890,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8890,12 +8906,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -18077,8 +18087,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18355,8 +18365,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18380,12 +18390,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18591,6 +18601,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18625,8 +18647,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18644,12 +18666,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22503,7 +22525,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22700,6 +22723,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22710,6 +22734,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23013,4 +23038,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B0xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -214,12 +213,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -736,8 +735,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2732,6 +2731,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -8727,7 +8735,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8873,7 +8881,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8883,6 +8891,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8891,12 +8907,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -18089,8 +18099,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18367,8 +18377,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18392,12 +18402,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18603,6 +18613,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18637,8 +18659,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18656,12 +18678,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22515,7 +22537,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22712,6 +22735,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22722,6 +22746,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23025,4 +23050,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B0xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -213,12 +212,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -735,8 +734,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2731,6 +2730,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -8726,7 +8734,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8873,7 +8881,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8883,6 +8891,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8891,12 +8907,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -18084,8 +18094,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18362,8 +18372,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18387,12 +18397,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18598,6 +18608,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18632,8 +18654,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18651,12 +18673,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22510,7 +22532,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22707,6 +22730,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22717,6 +22741,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23020,4 +23045,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B3xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -214,12 +213,12 @@ typedef enum
|
|||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -736,8 +735,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2732,6 +2731,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -8727,7 +8735,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8874,7 +8882,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8884,6 +8892,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8892,12 +8908,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -18096,8 +18106,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18374,8 +18384,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18399,12 +18409,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18610,6 +18620,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18644,8 +18666,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18663,12 +18685,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -22522,7 +22544,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22719,6 +22742,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22729,6 +22753,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23032,4 +23057,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B3xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -8,21 +8,20 @@
|
|||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32H7xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* - To use or not the peripheral's drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral's registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -59,7 +58,7 @@
|
|||
*/
|
||||
|
||||
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
|
||||
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
|
||||
!defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
|
||||
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
|
||||
|
|
@ -67,8 +66,10 @@
|
|||
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
||||
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
|
||||
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
|
||||
/* #define STM32H747xG */ /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */
|
||||
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
|
||||
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
|
||||
/* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */
|
||||
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
|
||||
/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
|
||||
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
|
||||
|
|
@ -101,11 +102,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.10.0
|
||||
* @brief CMSIS Device version number V1.10.1
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
@ -130,10 +131,14 @@
|
|||
#include "stm32h742xx.h"
|
||||
#elif defined(STM32H745xx)
|
||||
#include "stm32h745xx.h"
|
||||
#elif defined(STM32H745xG)
|
||||
#include "stm32h745xg.h"
|
||||
#elif defined(STM32H755xx)
|
||||
#include "stm32h755xx.h"
|
||||
#elif defined(STM32H747xx)
|
||||
#include "stm32h747xx.h"
|
||||
#elif defined(STM32H747xG)
|
||||
#include "stm32h747xg.h"
|
||||
#elif defined(STM32H757xx)
|
||||
#include "stm32h757xx.h"
|
||||
#elif defined(STM32H7B0xx)
|
||||
|
|
@ -214,6 +219,60 @@ typedef enum
|
|||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
/* Use of CMSIS compiler intrinsics for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -240,4 +299,3 @@ typedef enum
|
|||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -102,4 +101,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the Apache-2.0 license shall apply.
|
||||
You may obtain a copy of the Apache-2.0 at:
|
||||
https://opensource.org/licenses/Apache-2.0
|
||||
|
|
@ -1,83 +1 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
|
||||
|
||||
"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
|
||||
|
||||
"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
|
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
|
||||
|
||||
"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
|
||||
|
||||
"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
|
||||
|
||||
"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
|
||||
|
||||
2. Grant of Copyright License.
|
||||
|
||||
Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form.
|
||||
|
||||
3. Grant of Patent License.
|
||||
|
||||
Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.
|
||||
|
||||
4. Redistribution.
|
||||
|
||||
You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions:
|
||||
1.You must give any other recipients of the Work or Derivative Works a copy of this License; and
|
||||
2.You must cause any modified files to carry prominent notices stating that You changed the files; and
|
||||
3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and
|
||||
4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.
|
||||
|
||||
You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License.
|
||||
|
||||
5. Submission of Contributions.
|
||||
|
||||
Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions.
|
||||
|
||||
6. Trademarks.
|
||||
|
||||
This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
|
||||
|
||||
7. Disclaimer of Warranty.
|
||||
|
||||
Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
|
||||
|
||||
8. Limitation of Liability.
|
||||
|
||||
In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
|
||||
|
||||
9. Accepting Warranty or Additional Liability.
|
||||
|
||||
While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
APPENDIX:
|
||||
|
||||
Copyright [2019] [STMicroelectronics]
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
License.md file kept for legacy purpose
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h723xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -615,4 +614,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h725xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -615,4 +614,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h730xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -621,4 +620,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h730xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -621,4 +620,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h733xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -621,4 +620,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h735xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -621,4 +620,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h742xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -602,4 +601,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h743xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -608,4 +607,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -0,0 +1,619 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h745xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
|
||||
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD 0 ; Reserved
|
||||
DCD RNG_IRQHandler ; Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD SAI2_IRQHandler ; SAI2
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||
DCD JPEG_IRQHandler ; JPEG global Interrupt
|
||||
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
|
||||
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
|
||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
|
||||
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||
EXPORT CM7_SEV_IRQHandler [WEAK]
|
||||
EXPORT CM4_SEV_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||
EXPORT SAI3_IRQHandler [WEAK]
|
||||
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_IRQHandler [WEAK]
|
||||
EXPORT JPEG_IRQHandler [WEAK]
|
||||
EXPORT MDMA_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT HSEM1_IRQHandler [WEAK]
|
||||
EXPORT HSEM2_IRQHandler [WEAK]
|
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||
EXPORT COMP1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT WWDG_RST_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT ECC_IRQHandler [WEAK]
|
||||
EXPORT SAI4_IRQHandler [WEAK]
|
||||
EXPORT HOLD_CORE_IRQHandler [WEAK]
|
||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_AVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
FDCAN_CAL_IRQHandler
|
||||
CM7_SEV_IRQHandler
|
||||
CM4_SEV_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
OTG_FS_EP1_OUT_IRQHandler
|
||||
OTG_FS_EP1_IN_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
HRTIM1_Master_IRQHandler
|
||||
HRTIM1_TIMA_IRQHandler
|
||||
HRTIM1_TIMB_IRQHandler
|
||||
HRTIM1_TIMC_IRQHandler
|
||||
HRTIM1_TIMD_IRQHandler
|
||||
HRTIM1_TIME_IRQHandler
|
||||
HRTIM1_FLT_IRQHandler
|
||||
DFSDM1_FLT0_IRQHandler
|
||||
DFSDM1_FLT1_IRQHandler
|
||||
DFSDM1_FLT2_IRQHandler
|
||||
DFSDM1_FLT3_IRQHandler
|
||||
SAI3_IRQHandler
|
||||
SWPMI1_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
MDIOS_WKUP_IRQHandler
|
||||
MDIOS_IRQHandler
|
||||
JPEG_IRQHandler
|
||||
MDMA_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
HSEM1_IRQHandler
|
||||
HSEM2_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
DMAMUX2_OVR_IRQHandler
|
||||
BDMA_Channel0_IRQHandler
|
||||
BDMA_Channel1_IRQHandler
|
||||
BDMA_Channel2_IRQHandler
|
||||
BDMA_Channel3_IRQHandler
|
||||
BDMA_Channel4_IRQHandler
|
||||
BDMA_Channel5_IRQHandler
|
||||
BDMA_Channel6_IRQHandler
|
||||
BDMA_Channel7_IRQHandler
|
||||
COMP1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
WWDG_RST_IRQHandler
|
||||
CRS_IRQHandler
|
||||
ECC_IRQHandler
|
||||
SAI4_IRQHandler
|
||||
HOLD_CORE_IRQHandler
|
||||
WAKEUP_PIN_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h745xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -618,4 +617,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -0,0 +1,621 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h747xg.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xg devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
|
||||
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD 0 ; Reserved
|
||||
DCD RNG_IRQHandler ; Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD SAI2_IRQHandler ; SAI2
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||
DCD JPEG_IRQHandler ; JPEG global Interrupt
|
||||
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||
DCD DSI_IRQHandler ; DSI global Interrupt
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
|
||||
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
|
||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
|
||||
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||
EXPORT CM7_SEV_IRQHandler [WEAK]
|
||||
EXPORT CM4_SEV_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||
EXPORT SAI3_IRQHandler [WEAK]
|
||||
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_IRQHandler [WEAK]
|
||||
EXPORT JPEG_IRQHandler [WEAK]
|
||||
EXPORT MDMA_IRQHandler [WEAK]
|
||||
EXPORT DSI_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT HSEM1_IRQHandler [WEAK]
|
||||
EXPORT HSEM2_IRQHandler [WEAK]
|
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||
EXPORT COMP1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT WWDG_RST_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT ECC_IRQHandler [WEAK]
|
||||
EXPORT SAI4_IRQHandler [WEAK]
|
||||
EXPORT HOLD_CORE_IRQHandler [WEAK]
|
||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_AVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
FDCAN_CAL_IRQHandler
|
||||
CM7_SEV_IRQHandler
|
||||
CM4_SEV_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
OTG_FS_EP1_OUT_IRQHandler
|
||||
OTG_FS_EP1_IN_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
HRTIM1_Master_IRQHandler
|
||||
HRTIM1_TIMA_IRQHandler
|
||||
HRTIM1_TIMB_IRQHandler
|
||||
HRTIM1_TIMC_IRQHandler
|
||||
HRTIM1_TIMD_IRQHandler
|
||||
HRTIM1_TIME_IRQHandler
|
||||
HRTIM1_FLT_IRQHandler
|
||||
DFSDM1_FLT0_IRQHandler
|
||||
DFSDM1_FLT1_IRQHandler
|
||||
DFSDM1_FLT2_IRQHandler
|
||||
DFSDM1_FLT3_IRQHandler
|
||||
SAI3_IRQHandler
|
||||
SWPMI1_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
MDIOS_WKUP_IRQHandler
|
||||
MDIOS_IRQHandler
|
||||
JPEG_IRQHandler
|
||||
MDMA_IRQHandler
|
||||
DSI_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
HSEM1_IRQHandler
|
||||
HSEM2_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
DMAMUX2_OVR_IRQHandler
|
||||
BDMA_Channel0_IRQHandler
|
||||
BDMA_Channel1_IRQHandler
|
||||
BDMA_Channel2_IRQHandler
|
||||
BDMA_Channel3_IRQHandler
|
||||
BDMA_Channel4_IRQHandler
|
||||
BDMA_Channel5_IRQHandler
|
||||
BDMA_Channel6_IRQHandler
|
||||
BDMA_Channel7_IRQHandler
|
||||
COMP1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
WWDG_RST_IRQHandler
|
||||
CRS_IRQHandler
|
||||
ECC_IRQHandler
|
||||
SAI4_IRQHandler
|
||||
HOLD_CORE_IRQHandler
|
||||
WAKEUP_PIN_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h747xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -620,4 +619,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h750xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2018 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -610,4 +609,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h753xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -610,4 +609,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h755xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -620,4 +619,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h757xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -622,4 +621,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7a3xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -601,4 +600,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7a3xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -601,4 +600,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7b0xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -607,4 +606,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7b0xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -607,4 +606,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7b3xx.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -607,4 +606,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7b3xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||
|
|
@ -17,12 +17,11 @@
|
|||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
|
|
@ -607,4 +606,3 @@ __user_initial_stackheap
|
|||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -754,5 +753,4 @@ g_pfnVectors:
|
|||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -754,5 +753,4 @@ g_pfnVectors:
|
|||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -763,5 +762,4 @@ g_pfnVectors:
|
|||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -763,5 +762,4 @@ g_pfnVectors:
|
|||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -763,5 +762,4 @@ g_pfnVectors:
|
|||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -763,5 +762,4 @@ g_pfnVectors:
|
|||
.weak TIM24_IRQHandler
|
||||
.thumb_set TIM24_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -738,5 +737,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -747,5 +746,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,764 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h745xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H745xx Devices vector table for GCC based toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
|
||||
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word 0 /* Reserved */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word 0 /* Reserved */
|
||||
.word RNG_IRQHandler /* Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word SAI2_IRQHandler /* SAI2 */
|
||||
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN_CAL_IRQHandler
|
||||
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak CM7_SEV_IRQHandler
|
||||
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak CM4_SEV_IRQHandler
|
||||
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_Master_IRQHandler
|
||||
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMA_IRQHandler
|
||||
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMB_IRQHandler
|
||||
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMC_IRQHandler
|
||||
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMD_IRQHandler
|
||||
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIME_IRQHandler
|
||||
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_FLT_IRQHandler
|
||||
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI3_IRQHandler
|
||||
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_WKUP_IRQHandler
|
||||
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM1_IRQHandler
|
||||
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM2_IRQHandler
|
||||
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX2_OVR_IRQHandler
|
||||
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel0_IRQHandler
|
||||
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel1_IRQHandler
|
||||
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel2_IRQHandler
|
||||
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel3_IRQHandler
|
||||
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel4_IRQHandler
|
||||
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel5_IRQHandler
|
||||
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel6_IRQHandler
|
||||
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel7_IRQHandler
|
||||
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP1_IRQHandler
|
||||
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_RST_IRQHandler
|
||||
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ECC_IRQHandler
|
||||
.thumb_set ECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI4_IRQHandler
|
||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HOLD_CORE_IRQHandler
|
||||
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -762,5 +761,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,767 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h747xg.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H747xg Devices vector table for GCC based toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
|
||||
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word 0 /* Reserved */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word 0 /* Reserved */
|
||||
.word RNG_IRQHandler /* Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word SAI2_IRQHandler /* SAI2 */
|
||||
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||
.word DSI_IRQHandler /* DSI global Interrupt */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN_CAL_IRQHandler
|
||||
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak CM7_SEV_IRQHandler
|
||||
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak CM4_SEV_IRQHandler
|
||||
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_Master_IRQHandler
|
||||
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMA_IRQHandler
|
||||
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMB_IRQHandler
|
||||
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMC_IRQHandler
|
||||
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMD_IRQHandler
|
||||
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIME_IRQHandler
|
||||
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_FLT_IRQHandler
|
||||
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI3_IRQHandler
|
||||
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_WKUP_IRQHandler
|
||||
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DSI_IRQHandler
|
||||
.thumb_set DSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM1_IRQHandler
|
||||
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM2_IRQHandler
|
||||
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX2_OVR_IRQHandler
|
||||
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel0_IRQHandler
|
||||
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel1_IRQHandler
|
||||
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel2_IRQHandler
|
||||
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel3_IRQHandler
|
||||
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel4_IRQHandler
|
||||
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel5_IRQHandler
|
||||
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel6_IRQHandler
|
||||
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel7_IRQHandler
|
||||
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP1_IRQHandler
|
||||
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_RST_IRQHandler
|
||||
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ECC_IRQHandler
|
||||
.thumb_set ECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI4_IRQHandler
|
||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HOLD_CORE_IRQHandler
|
||||
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -765,5 +764,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -750,5 +749,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -750,5 +749,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -765,5 +764,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -768,5 +767,4 @@ g_pfnVectors:
|
|||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -740,5 +739,4 @@ g_pfnVectors:
|
|||
.weak BDMA1_IRQHandler
|
||||
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -740,5 +739,4 @@ g_pfnVectors:
|
|||
.weak BDMA1_IRQHandler
|
||||
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -749,5 +748,4 @@ g_pfnVectors:
|
|||
.weak BDMA1_IRQHandler
|
||||
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -749,5 +748,4 @@ g_pfnVectors:
|
|||
.weak BDMA1_IRQHandler
|
||||
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -749,5 +748,4 @@ g_pfnVectors:
|
|||
.weak BDMA1_IRQHandler
|
||||
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -749,5 +748,4 @@ g_pfnVectors:
|
|||
.weak BDMA1_IRQHandler
|
||||
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h723xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H723xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -981,4 +980,3 @@ TIM24_IRQHandler
|
|||
B TIM24_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h725xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H725xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -981,4 +980,3 @@ TIM24_IRQHandler
|
|||
B TIM24_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h730xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H730xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -996,4 +995,3 @@ TIM24_IRQHandler
|
|||
B TIM24_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h730xxq.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H730xxQ devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -996,4 +995,3 @@ TIM24_IRQHandler
|
|||
B TIM24_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h733xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H733xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -996,4 +995,3 @@ TIM24_IRQHandler
|
|||
B TIM24_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h735xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H735xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -996,4 +995,3 @@ TIM24_IRQHandler
|
|||
B TIM24_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h742xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H742xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -961,4 +960,3 @@ SAI4_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h743xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H743xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -976,4 +975,3 @@ SAI4_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h745xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H745xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -1001,4 +1000,3 @@ HOLD_CORE_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h747xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H747xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -1006,4 +1005,3 @@ HOLD_CORE_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h750xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H750xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2018 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -981,4 +980,3 @@ SAI4_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h753xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H753xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -981,4 +980,3 @@ SAI4_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h755xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H755xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -1006,4 +1005,3 @@ HOLD_CORE_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32h757xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H757xx devices vector table for EWARM toolchain.
|
||||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -1011,4 +1010,3 @@ HOLD_CORE_IRQHandler
|
|||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -953,4 +952,3 @@ GFXMMU_IRQHandler
|
|||
BDMA1_IRQHandler
|
||||
B BDMA1_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -953,4 +952,3 @@ GFXMMU_IRQHandler
|
|||
BDMA1_IRQHandler
|
||||
B BDMA1_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -968,4 +967,3 @@ GFXMMU_IRQHandler
|
|||
BDMA1_IRQHandler
|
||||
B BDMA1_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -968,4 +967,3 @@ GFXMMU_IRQHandler
|
|||
BDMA1_IRQHandler
|
||||
B BDMA1_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -968,4 +967,3 @@ GFXMMU_IRQHandler
|
|||
BDMA1_IRQHandler
|
||||
B BDMA1_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;* Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
|
|
@ -968,4 +967,3 @@ GFXMMU_IRQHandler
|
|||
BDMA1_IRQHandler
|
||||
B BDMA1_IRQHandler
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -22,13 +22,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -80,11 +79,46 @@
|
|||
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
|
||||
/* #define DATA_IN_D2_SRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate the vector table
|
||||
anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
|
||||
remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
|
|
@ -245,11 +279,9 @@ void SystemInit (void)
|
|||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#else
|
||||
|
||||
|
|
@ -260,12 +292,10 @@ void SystemInit (void)
|
|||
*/
|
||||
FMC_Bank1_R->BTCR[0] = 0x000030D2;
|
||||
|
||||
/* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
/* Configure the Vector Table location -------------------------------------*/
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#endif /*DUAL_CORE && CORE_CM4*/
|
||||
|
||||
|
|
@ -419,4 +449,3 @@ void SystemCoreClockUpdate (void)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -25,13 +25,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -85,7 +84,7 @@
|
|||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x300. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
|
|
@ -392,4 +391,3 @@ void SystemCoreClockUpdate (void)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -28,13 +28,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -88,7 +87,7 @@
|
|||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x300. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
|
|
@ -389,4 +388,3 @@ void SystemCoreClockUpdate (void)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -28,13 +28,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -88,7 +87,7 @@
|
|||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x300. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
|
|
@ -387,4 +386,3 @@ void SystemCoreClockUpdate (void)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -24,13 +24,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -87,7 +86,7 @@
|
|||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x300. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
|
|
@ -398,4 +397,3 @@ void SystemCoreClockUpdate (void)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -7,13 +7,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -38,6 +37,14 @@ extern "C" {
|
|||
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
|
||||
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
|
||||
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
|
||||
#if defined(STM32U5)
|
||||
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
|
||||
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
|
||||
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
|
||||
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
|
||||
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
|
||||
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -206,6 +213,20 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
|
||||
#if defined(STM32U5)
|
||||
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
|
||||
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
|
||||
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -235,11 +256,18 @@ extern "C" {
|
|||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
||||
#if defined(STM32G4) || defined(STM32H7)
|
||||
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
|
||||
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
|
||||
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
|
||||
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
|
||||
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
|
||||
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
|
||||
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
|
||||
|
|
@ -382,8 +410,6 @@ extern "C" {
|
|||
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -471,15 +497,24 @@ extern "C" {
|
|||
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
|
||||
#endif
|
||||
#if defined(STM32H7)
|
||||
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#endif /* STM32H7 */
|
||||
#if defined(STM32U5)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -522,6 +557,7 @@ extern "C" {
|
|||
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -596,12 +632,12 @@ extern "C" {
|
|||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
|
||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
|
||||
|
||||
#if defined(STM32L1)
|
||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||
|
|
@ -617,6 +653,20 @@ extern "C" {
|
|||
#endif /* STM32F0 || STM32F3 || STM32F1 */
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32U5)
|
||||
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -854,6 +904,20 @@ extern "C" {
|
|||
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
|
||||
|
||||
|
||||
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
|
||||
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
|
||||
#define LPTIM_CHANNEL_ALL 0x00000000U
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1192,6 +1256,10 @@ extern "C" {
|
|||
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5) || defined(STM32MP2)
|
||||
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
|
||||
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1380,6 +1448,20 @@ extern "C" {
|
|||
*/
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
|
||||
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||
|| defined(STM32H7) || defined(STM32U5)
|
||||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
|
||||
for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1398,6 +1480,29 @@ extern "C" {
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
|
||||
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
|
||||
#endif /* STM32U5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if !defined(STM32F2)
|
||||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
|
||||
/**
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F2 */
|
||||
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -3330,6 +3435,31 @@ extern "C" {
|
|||
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
|
||||
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
|
||||
#if defined(STM32U5)
|
||||
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
|
||||
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
|
||||
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
|
||||
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
|
||||
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
|
||||
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
|
||||
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
|
||||
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
|
||||
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
|
||||
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
|
||||
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
|
||||
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
|
||||
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -3347,7 +3477,7 @@ extern "C" {
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
|
@ -3404,13 +3534,22 @@ extern "C" {
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
|
||||
/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
|
||||
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
|
||||
|
||||
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
|
||||
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
|
||||
#endif
|
||||
|
||||
#if defined(STM32F4) || defined(STM32F2)
|
||||
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
|
||||
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
|
||||
|
|
@ -3753,5 +3892,4 @@ extern "C" {
|
|||
|
||||
#endif /* STM32_HAL_LEGACY */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -8,13 +8,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -54,4 +53,4 @@
|
|||
#endif /* __STM32_ASSERT_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -7,13 +7,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -1079,12 +1078,12 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG
|
|||
#if defined(SYSCFG_CCCR_NCC_MMC)
|
||||
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
|
||||
#endif /* SYSCFG_CCCR_NCC_MMC */
|
||||
void HAL_EnableDBGSleepMode(void);
|
||||
void HAL_DisableDBGSleepMode(void);
|
||||
void HAL_EnableDBGStopMode(void);
|
||||
void HAL_DisableDBGStopMode(void);
|
||||
void HAL_EnableDBGStandbyMode(void);
|
||||
void HAL_DisableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_EnableDomain2DBGSleepMode(void);
|
||||
void HAL_DisableDomain2DBGSleepMode(void);
|
||||
|
|
@ -1140,4 +1139,4 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
|
|||
|
||||
#endif /* STM32H7xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue