diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..3003f59
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,11 @@
+BasedOnStyle: Google
+IndentWidth: 4
+AlignConsecutiveMacros: AcrossEmptyLines
+AlignConsecutiveDeclarations: true
+AlignConsecutiveAssignments: AcrossEmptyLinesAndComments
+BreakBeforeBraces: Custom
+BraceWrapping:
+  AfterEnum: false
+  AfterStruct: false
+  SplitEmptyFunction: false
+ColumnLimit: 120
\ No newline at end of file
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..1e2ee89
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "Middlewares/Third_Party/lwesp"]
+	path = Middlewares/Third_Party/lwesp
+	url = https://github.com/MaJerle/lwesp.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
index fe7de82..02be299 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -16,6 +16,7 @@ set(TARGET_LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/STM32H750VBTx_RAM.ld")
 
 # Copy them from Makefile
 set(TARGET_C_SOURCES
+    "Core/Src/lwesp_ll.c"
     "Core/Src/main.c"
     "Core/Src/stm32h7xx_it.c"
     "Core/Src/stm32h7xx_hal_msp.c"
@@ -58,6 +59,26 @@ set(TARGET_C_SOURCES
     "Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c"
     "Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c"
     "Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_ap.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_buff.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_conn.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_debug.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_dns.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_evt.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_input.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_int.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_mem.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_parser.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_pbuf.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_sntp.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_sta.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_threads.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_timeout.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_unicode.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_wps.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp_utils.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/lwesp/lwesp.c"
+    "Middlewares/Third_Party/lwesp/lwesp/src/system/lwesp_sys_freertos.c"
 )
 
 # Copy them from Makefile
@@ -87,6 +108,8 @@ set(TARGET_C_INCLUDES
     "Middlewares/Third_Party/FreeRTOS/Source/include"
     "Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"
     "Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
+    "Middlewares/Third_Party/lwesp/lwesp/src/include"
+    "Middlewares/Third_Party/lwesp/lwesp/src/include/system/port/freertos"
 )
 
 # Shared libraries linked with application
diff --git a/Core/Inc/lwesp_opts.h b/Core/Inc/lwesp_opts.h
new file mode 100644
index 0000000..92e9893
--- /dev/null
+++ b/Core/Inc/lwesp_opts.h
@@ -0,0 +1,15 @@
+#ifndef LWESP_HDR_OPTS_H
+#define LWESP_HDR_OPTS_H
+
+/* Rename this file to "lwesp_opts.h" for your application */
+
+/*
+ * Open "include/lwesp/lwesp_opt.h" and
+ * copy & replace here settings you want to change values
+ */
+#define LWESP_CFG_AT_ECHO                     1
+#define LWESP_CFG_INPUT_USE_PROCESS           1
+
+#define LWESP_CFG_SNTP                        1
+
+#endif /* LWESP_HDR_OPTS_H */
diff --git a/Core/Src/lwesp_ll.c b/Core/Src/lwesp_ll.c
new file mode 100644
index 0000000..a2cd436
--- /dev/null
+++ b/Core/Src/lwesp_ll.c
@@ -0,0 +1,63 @@
+#include "system/lwesp_ll.h"
+
+#include "lwesp/lwesp.h"
+#include "lwesp/lwesp_input.h"
+#include "lwesp/lwesp_mem.h"
+#include "stm32h7xx_hal.h"
+
+#include "cmsis_os.h"
+
+#define UART_TIMEOUT 1000
+#define HEAP_SIZE    4096
+
+extern UART_HandleTypeDef huart1;
+static uint8_t            s_lwesp_heap[HEAP_SIZE];
+static uint8_t            s_initialized;
+
+static osThreadId_t usart_ll_thread_id;
+static osMessageQueueId_t usart_ll_mbox_id;
+
+static void usart_ll_thread(void *arg) {
+    for (;;) {
+    }
+}
+
+static void configure_uart(uint32_t baudrate) {
+    //
+}
+
+static size_t send_data(const void *data, size_t len) {
+    HAL_UART_Transmit(&huart1, (uint8_t *)data, len, 1000);
+
+    return len;
+}
+
+lwespr_t lwesp_ll_init(lwesp_ll_t *ll) {
+    lwesp_mem_region_t mem_regions[] = {{s_lwesp_heap, HEAP_SIZE}};
+
+    if (!s_initialized) {
+        lwesp_mem_assignmemory(mem_regions, LWESP_ARRAYSIZE(mem_regions));
+
+        ll->send_fn = send_data;
+    }
+
+    configure_uart(ll->uart.baudrate);
+
+    if(!s_initialized) {
+        const osThreadAttr_t attr = {
+            .stack_size = 1024
+        };
+
+        usart_ll_mbox_id = osMessageQueueNew(10, sizeof(void *), NULL);
+        usart_ll_thread_id = osThreadNew(usart_ll_thread, usart_ll_mbox_id, &attr);
+    }
+
+    s_initialized = 1;
+
+    return lwespOK;
+}
+
+lwespr_t lwesp_ll_deinit(lwesp_ll_t *ll) {
+    //
+    return lwespOK;
+}
\ No newline at end of file
diff --git a/Middlewares/Third_Party/lwesp b/Middlewares/Third_Party/lwesp
new file mode 160000
index 0000000..7d1dd77
--- /dev/null
+++ b/Middlewares/Third_Party/lwesp
@@ -0,0 +1 @@
+Subproject commit 7d1dd77fa844c382c8f65caf040eb7573aa5dc06
diff --git a/STM32H750VBT6_LwESP.ioc b/STM32H750VBT6_LwESP.ioc
index d8becc6..2839e3d 100644
--- a/STM32H750VBT6_LwESP.ioc
+++ b/STM32H750VBT6_LwESP.ioc
@@ -1,4 +1,23 @@
 #MicroXplorer Configuration settings - do not modify
+Bdma.LPUART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
+Bdma.LPUART1_RX.0.EventEnable=DISABLE
+Bdma.LPUART1_RX.0.Instance=BDMA_Channel0
+Bdma.LPUART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Bdma.LPUART1_RX.0.MemInc=DMA_MINC_ENABLE
+Bdma.LPUART1_RX.0.Mode=DMA_CIRCULAR
+Bdma.LPUART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Bdma.LPUART1_RX.0.PeriphInc=DMA_PINC_DISABLE
+Bdma.LPUART1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Bdma.LPUART1_RX.0.Priority=DMA_PRIORITY_LOW
+Bdma.LPUART1_RX.0.RequestNumber=1
+Bdma.LPUART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Bdma.LPUART1_RX.0.SignalID=NONE
+Bdma.LPUART1_RX.0.SyncEnable=DISABLE
+Bdma.LPUART1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Bdma.LPUART1_RX.0.SyncRequestNumber=1
+Bdma.LPUART1_RX.0.SyncSignalID=NONE
+Bdma.Request0=LPUART1_RX
+Bdma.RequestsNb=1
 FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configENABLE_FPU
 FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
 FREERTOS.configENABLE_FPU=1
@@ -9,36 +28,41 @@ KeepUserPlacement=false
 LPUART1.BaudRate=115200
 LPUART1.IPParameters=BaudRate
 Mcu.Family=STM32H7
-Mcu.IP0=CORTEX_M7
-Mcu.IP1=FREERTOS
-Mcu.IP2=LPUART1
-Mcu.IP3=NVIC
-Mcu.IP4=RCC
-Mcu.IP5=RNG
-Mcu.IP6=SYS
-Mcu.IPNb=7
+Mcu.IP0=BDMA
+Mcu.IP1=CORTEX_M7
+Mcu.IP2=FREERTOS
+Mcu.IP3=LPUART1
+Mcu.IP4=NVIC
+Mcu.IP5=RCC
+Mcu.IP6=RNG
+Mcu.IP7=SYS
+Mcu.IPNb=8
 Mcu.Name=STM32H750VBTx
 Mcu.Package=LQFP100
 Mcu.Pin0=PC14-OSC32_IN (OSC32_IN)
 Mcu.Pin1=PC15-OSC32_OUT (OSC32_OUT)
+Mcu.Pin10=VP_SYS_VS_tim7
 Mcu.Pin2=PH0-OSC_IN (PH0)
 Mcu.Pin3=PH1-OSC_OUT (PH1)
 Mcu.Pin4=PA9
 Mcu.Pin5=PA10
-Mcu.Pin6=VP_FREERTOS_VS_CMSIS_V2
-Mcu.Pin7=VP_RNG_VS_RNG
-Mcu.Pin8=VP_SYS_VS_tim7
-Mcu.PinsNb=9
+Mcu.Pin6=PA11
+Mcu.Pin7=PA12
+Mcu.Pin8=VP_FREERTOS_VS_CMSIS_V2
+Mcu.Pin9=VP_RNG_VS_RNG
+Mcu.PinsNb=11
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32H750VBTx
 MxCube.Version=6.4.0
 MxDb.Version=DB.6.0.40
+NVIC.BDMA_Channel0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.FLASH_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 NVIC.FPU_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:false
 NVIC.ForceEnableDMAVector=true
+NVIC.HASH_RNG_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 NVIC.HSEM1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.LPUART1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
@@ -59,6 +83,10 @@ NVIC.TimeBaseIP=TIM7
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 PA10.Mode=Asynchronous
 PA10.Signal=LPUART1_RX
+PA11.Mode=CTS_RTS
+PA11.Signal=LPUART1_CTS
+PA12.Mode=CTS_RTS
+PA12.Signal=LPUART1_RTS
 PA9.Mode=Asynchronous
 PA9.Signal=LPUART1_TX
 PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
@@ -97,7 +125,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=Makefile
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,4-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,4-MX_BDMA_Init-BDMA-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 RCC.ADCFreq_Value=16125000
 RCC.AHB12Freq_Value=150000000
 RCC.AHB4Freq_Value=150000000