Added clang-format, DMA2D now working.
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@ -0,0 +1,149 @@
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---
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Language: Cpp
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# BasedOnStyle: LLVM
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- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
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SpacesInParentheses: false
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- BOOST_PP_STRINGIZE
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...
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@ -55,6 +55,7 @@ set(C_SOURCES
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"Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c"
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"Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c"
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"Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c"
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"Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c"
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"Middlewares/Third_Party/FreeRTOS/Source/croutine.c"
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"Middlewares/Third_Party/FreeRTOS/Source/event_groups.c"
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"Middlewares/Third_Party/FreeRTOS/Source/list.c"
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@ -44,7 +44,7 @@
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/* #define HAL_CRYP_MODULE_ENABLED */
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/* #define HAL_DAC_MODULE_ENABLED */
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/* #define HAL_DCMI_MODULE_ENABLED */
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/* #define HAL_DMA2D_MODULE_ENABLED */
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#define HAL_DMA2D_MODULE_ENABLED
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/* #define HAL_ETH_MODULE_ENABLED */
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/* #define HAL_NAND_MODULE_ENABLED */
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/* #define HAL_NOR_MODULE_ENABLED */
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@ -177,7 +177,7 @@
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#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
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#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
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#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
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#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
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#define USE_HAL_DMA2D_REGISTER_CALLBACKS 1U /* DMA2D register callback enabled */
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#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
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#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
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#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
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@ -65,6 +65,7 @@ void TIM7_IRQHandler(void);
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void FPU_IRQHandler(void);
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void LTDC_IRQHandler(void);
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void LTDC_ER_IRQHandler(void);
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void DMA2D_IRQHandler(void);
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void HSEM1_IRQHandler(void);
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/* USER CODE BEGIN EFP */
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@ -5,8 +5,22 @@
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#include "lvgl.h"
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void user_lvgl_impl_log_cb(lv_log_level_t level, const char *file, uint32_t line, const char *fn_name, const char *dsc);
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void user_lvgl_impl_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p);
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void user_lvgl_impl_log_cb(lv_log_level_t level, const char *file,
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uint32_t line, const char *fn_name, const char *dsc);
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void user_lvgl_impl_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area,
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lv_color_t *color_p);
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void user_lvgl_impl_clean_dcache_cb(lv_disp_drv_t *disp_drv);
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void user_lvgl_impl_gpu_blend_cb(lv_disp_drv_t *disp_drv, lv_color_t *dest,
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const lv_color_t *src, uint32_t length,
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lv_opa_t opa);
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void user_lvgl_impl_gpu_fill_cb(lv_disp_drv_t *disp_drv, lv_color_t *dest_buf,
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lv_coord_t dest_width,
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const lv_area_t *fill_area, lv_color_t color);
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void user_lvgl_impl_gpu_wait_cb(lv_disp_drv_t *disp_drv);
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#endif
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@ -4,6 +4,7 @@
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#include "cmsis_os2.h"
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#define USER_LVGL_EVENT_FLAG_READY 0x00000001
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#define USER_LVGL_EVENT_DMA2D_READY 0x00000002
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void user_tasks_init(void);
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@ -44,6 +44,8 @@
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/* Private variables ---------------------------------------------------------*/
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DMA2D_HandleTypeDef hdma2d;
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LTDC_HandleTypeDef hltdc;
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RTC_HandleTypeDef hrtc;
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@ -79,6 +81,7 @@ static void MX_TIM2_Init(void);
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static void MX_FMC_Init(void);
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static void MX_USART1_UART_Init(void);
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static void MX_LTDC_Init(void);
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static void MX_DMA2D_Init(void);
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void StartDefaultTask(void *argument);
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/* USER CODE BEGIN PFP */
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@ -137,6 +140,7 @@ int main(void)
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MX_FMC_Init();
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MX_USART1_UART_Init();
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MX_LTDC_Init();
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MX_DMA2D_Init();
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/* USER CODE BEGIN 2 */
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/* USER CODE END 2 */
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@ -201,7 +205,7 @@ void SystemClock_Config(void)
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/** Macro to configure the PLL clock source
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@ -240,7 +244,7 @@ void SystemClock_Config(void)
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
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{
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Error_Handler();
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}
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@ -264,7 +268,7 @@ void PeriphCommonClock_Config(void)
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PeriphClkInitStruct.PLL3.PLL3N = 172;
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PeriphClkInitStruct.PLL3.PLL3P = 2;
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PeriphClkInitStruct.PLL3.PLL3Q = 4;
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PeriphClkInitStruct.PLL3.PLL3R = 6;
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PeriphClkInitStruct.PLL3.PLL3R = 5;
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PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0;
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PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOMEDIUM;
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PeriphClkInitStruct.PLL3.PLL3FRACN = 1762;
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@ -275,6 +279,56 @@ void PeriphCommonClock_Config(void)
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}
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}
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/**
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* @brief DMA2D Initialization Function
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* @param None
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* @retval None
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*/
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static void MX_DMA2D_Init(void)
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{
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/* USER CODE BEGIN DMA2D_Init 0 */
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/* USER CODE END DMA2D_Init 0 */
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/* USER CODE BEGIN DMA2D_Init 1 */
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/* USER CODE END DMA2D_Init 1 */
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hdma2d.Instance = DMA2D;
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hdma2d.Init.Mode = DMA2D_M2M_BLEND;
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hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
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hdma2d.Init.OutputOffset = 0;
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hdma2d.LayerCfg[1].InputOffset = 0;
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hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
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hdma2d.LayerCfg[1].AlphaMode = DMA2D_REPLACE_ALPHA;
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hdma2d.LayerCfg[1].InputAlpha = 255;
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hdma2d.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA;
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hdma2d.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR;
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hdma2d.LayerCfg[1].ChromaSubSampling = DMA2D_NO_CSS;
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hdma2d.LayerCfg[0].InputOffset = 0;
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hdma2d.LayerCfg[0].InputColorMode = DMA2D_INPUT_ARGB8888;
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hdma2d.LayerCfg[0].AlphaMode = DMA2D_REPLACE_ALPHA;
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hdma2d.LayerCfg[0].InputAlpha = 255;
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hdma2d.LayerCfg[0].AlphaInverted = DMA2D_REGULAR_ALPHA;
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hdma2d.LayerCfg[0].RedBlueSwap = DMA2D_RB_REGULAR;
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if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_DMA2D_ConfigLayer(&hdma2d, 0) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN DMA2D_Init 2 */
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/* USER CODE END DMA2D_Init 2 */
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}
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/**
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* @brief LTDC Initialization Function
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* @param None
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@ -635,15 +689,15 @@ static void MX_FMC_Init(void)
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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/* SdramTiming */
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SdramTiming.LoadToActiveDelay = 2;
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SdramTiming.ExitSelfRefreshDelay = 5;
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SdramTiming.SelfRefreshTime = 3;
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SdramTiming.RowCycleDelay = 4;
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SdramTiming.ExitSelfRefreshDelay = 9;
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SdramTiming.SelfRefreshTime = 6;
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SdramTiming.RowCycleDelay = 8;
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SdramTiming.WriteRecoveryTime = 2;
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SdramTiming.RPDelay = 2;
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SdramTiming.RCDDelay = 2;
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SdramTiming.RCDDelay = 4;
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if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
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{
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@ -676,8 +730,8 @@ static void MX_FMC_Init(void)
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cmd.ModeRegisterDefinition = 0x220; // Sequential burst length 1, CL2, single write
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HAL_SDRAM_SendCommand(&hsdram1, &cmd, 1000);
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// Refresh counter. 8192 Lines in 64ms, 7.8125us/Line, Freq = 66.5MHz
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HAL_SDRAM_ProgramRefreshRate(&hsdram1, 500);
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// Refresh counter. 8192 Lines in 64ms, 7.8125us/Line, Freq = 125MHz
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HAL_SDRAM_ProgramRefreshRate(&hsdram1, 848);
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/* USER CODE END FMC_Init 2 */
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}
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@ -857,8 +911,6 @@ void MPU_Config(void)
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MPU_InitStruct.BaseAddress = 0xD0000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_64MB;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Enables the MPU */
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@ -97,6 +97,56 @@ void HAL_MspInit(void)
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/* USER CODE END MspInit 1 */
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}
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/**
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* @brief DMA2D MSP Initialization
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* This function configures the hardware resources used in this example
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* @param hdma2d: DMA2D handle pointer
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* @retval None
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*/
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void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
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{
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if(hdma2d->Instance==DMA2D)
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{
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/* USER CODE BEGIN DMA2D_MspInit 0 */
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/* USER CODE END DMA2D_MspInit 0 */
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/* Peripheral clock enable */
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__HAL_RCC_DMA2D_CLK_ENABLE();
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/* DMA2D interrupt Init */
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HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2D_IRQn);
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/* USER CODE BEGIN DMA2D_MspInit 1 */
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/* USER CODE END DMA2D_MspInit 1 */
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}
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}
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/**
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* @brief DMA2D MSP De-Initialization
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* This function freeze the hardware resources used in this example
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* @param hdma2d: DMA2D handle pointer
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* @retval None
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*/
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void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
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{
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if(hdma2d->Instance==DMA2D)
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{
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/* USER CODE BEGIN DMA2D_MspDeInit 0 */
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/* USER CODE END DMA2D_MspDeInit 0 */
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/* Peripheral clock disable */
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__HAL_RCC_DMA2D_CLK_DISABLE();
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/* DMA2D interrupt DeInit */
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HAL_NVIC_DisableIRQ(DMA2D_IRQn);
|
||||
/* USER CODE BEGIN DMA2D_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END DMA2D_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LTDC MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
|
|
@ -515,12 +565,12 @@ static void HAL_FMC_MspInit(void){
|
|||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
|
||||
PeriphClkInitStruct.PLL2.PLL2M = 25;
|
||||
PeriphClkInitStruct.PLL2.PLL2N = 266;
|
||||
PeriphClkInitStruct.PLL2.PLL2M = 5;
|
||||
PeriphClkInitStruct.PLL2.PLL2N = 50;
|
||||
PeriphClkInitStruct.PLL2.PLL2P = 2;
|
||||
PeriphClkInitStruct.PLL2.PLL2Q = 10;
|
||||
PeriphClkInitStruct.PLL2.PLL2R = 2;
|
||||
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0;
|
||||
PeriphClkInitStruct.PLL2.PLL2R = 1;
|
||||
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;
|
||||
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
|
||||
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@
|
|||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
extern DMA_HandleTypeDef hdma_memtomem_dma1_stream0;
|
||||
extern DMA2D_HandleTypeDef hdma2d;
|
||||
extern SDRAM_HandleTypeDef hsdram1;
|
||||
extern LTDC_HandleTypeDef hltdc;
|
||||
extern TIM_HandleTypeDef htim2;
|
||||
|
|
@ -333,6 +334,20 @@ void LTDC_ER_IRQHandler(void)
|
|||
/* USER CODE END LTDC_ER_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2D global interrupt.
|
||||
*/
|
||||
void DMA2D_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2D_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2D_IRQn 0 */
|
||||
HAL_DMA2D_IRQHandler(&hdma2d);
|
||||
/* USER CODE BEGIN DMA2D_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2D_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles HSEM1 global interrupt.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "lvgl.h"
|
||||
|
||||
|
|
@ -12,14 +12,14 @@ osThreadId_t g_user_lvgl_tick_handle;
|
|||
osThreadAttr_t g_user_lvgl_tick_attributes = {
|
||||
.name = "LV_TICK",
|
||||
.stack_size = 128 * 4,
|
||||
.priority = (osPriority_t) osPriorityAboveNormal
|
||||
.priority = (osPriority_t)osPriorityAboveNormal,
|
||||
};
|
||||
|
||||
osThreadId_t g_user_lvgl_task_handle;
|
||||
osThreadAttr_t g_user_lvgl_task_attributes = {
|
||||
.name = "LV_TASK",
|
||||
.stack_size = 384 * 4,
|
||||
.priority = (osPriority_t) osPriorityBelowNormal
|
||||
.stack_size = 512 * 4,
|
||||
.priority = (osPriority_t)osPriorityBelowNormal,
|
||||
};
|
||||
|
||||
osMutexId_t g_user_lvgl_mutex_handle;
|
||||
|
|
@ -27,7 +27,7 @@ osMutexAttr_t g_user_lvgl_mutex_attributes = {
|
|||
.name = "LV_MUTX",
|
||||
.attr_bits = osMutexRecursive | osMutexPrioInherit,
|
||||
.cb_mem = NULL,
|
||||
.cb_size = 0U
|
||||
.cb_size = 0U,
|
||||
};
|
||||
|
||||
osEventFlagsId_t g_user_lvgl_event_handle;
|
||||
|
|
@ -57,25 +57,33 @@ void user_lvgl_task(void *argument) {
|
|||
lv_init();
|
||||
lv_log_register_print_cb(user_lvgl_impl_log_cb);
|
||||
|
||||
lv_disp_buf_init(&g_user_lvgl_disp_buf, (void *)0xD0100000, (void *)0xD0300000, 800 * 480);
|
||||
lv_disp_buf_init(&g_user_lvgl_disp_buf, (void *)0xD0100000,
|
||||
(void *)0xD0300000, 800 * 480);
|
||||
|
||||
lv_disp_drv_t disp_drv;
|
||||
lv_disp_drv_init(&disp_drv);
|
||||
disp_drv.buffer = &g_user_lvgl_disp_buf;
|
||||
disp_drv.flush_cb = user_lvgl_impl_flush_cb;
|
||||
disp_drv.clean_dcache_cb = user_lvgl_impl_clean_dcache_cb;
|
||||
disp_drv.gpu_blend_cb = user_lvgl_impl_gpu_blend_cb;
|
||||
disp_drv.gpu_fill_cb = user_lvgl_impl_gpu_fill_cb;
|
||||
disp_drv.gpu_wait_cb = user_lvgl_impl_gpu_wait_cb;
|
||||
|
||||
g_user_lvgl_disp = lv_disp_drv_register(&disp_drv);
|
||||
|
||||
g_user_lvgl_tick_handle = osThreadNew(user_lvgl_tick, NULL, &g_user_lvgl_tick_attributes);
|
||||
g_user_lvgl_tick_handle =
|
||||
osThreadNew(user_lvgl_tick, NULL, &g_user_lvgl_tick_attributes);
|
||||
if(g_user_lvgl_tick_handle == NULL) {
|
||||
LV_LOG_ERROR("Failed to create tick thread.");
|
||||
osThreadExit();
|
||||
}
|
||||
|
||||
LV_LOG_INFO("LVGL initialized at %ld, stack avail: %ldbytes.", osKernelGetTickCount(), osThreadGetStackSpace(g_user_lvgl_task_handle));
|
||||
LV_LOG_INFO("LVGL initialized at %ld, stack avail: %ldbytes.",
|
||||
osKernelGetTickCount(),
|
||||
osThreadGetStackSpace(g_user_lvgl_task_handle));
|
||||
|
||||
osEventFlagsSet(g_user_lvgl_event_handle, USER_LVGL_EVENT_FLAG_READY);
|
||||
osEventFlagsSet(g_user_lvgl_event_handle, USER_LVGL_EVENT_DMA2D_READY);
|
||||
|
||||
for(;;) {
|
||||
if(osMutexAcquire(g_user_lvgl_mutex_handle, 1000) == osOK) {
|
||||
|
|
|
|||
|
|
@ -2,14 +2,33 @@
|
|||
|
||||
#include "printf.h"
|
||||
|
||||
#include "main.h"
|
||||
|
||||
#include "user_lvgl_impl.h"
|
||||
#include "user_tasks.h"
|
||||
|
||||
extern LTDC_HandleTypeDef hltdc;
|
||||
extern DMA2D_HandleTypeDef hdma2d;
|
||||
|
||||
void user_lvgl_impl_log_cb(lv_log_level_t level, const char *file, uint32_t line, const char *fn_name, const char *dsc) {
|
||||
void _user_lvgl_impl_dma2d_cplt_callback(DMA2D_HandleTypeDef *hdma2d) {
|
||||
if(hdma2d->Instance == DMA2D) {
|
||||
osEventFlagsSet(g_user_lvgl_event_handle, USER_LVGL_EVENT_DMA2D_READY);
|
||||
}
|
||||
}
|
||||
|
||||
void _user_lvgl_impl_dma2d_err_callback(DMA2D_HandleTypeDef *hdma2d) {
|
||||
if(hdma2d->Instance == DMA2D) {
|
||||
osEventFlagsSet(g_user_lvgl_event_handle, USER_LVGL_EVENT_FLAG_READY);
|
||||
printf("DMA2D Error\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
void user_lvgl_impl_log_cb(lv_log_level_t level, const char *file,
|
||||
uint32_t line, const char *fn_name,
|
||||
const char *dsc) {
|
||||
if(level == LV_LOG_LEVEL_ERROR) printf("\033[31m[ERROR] ");
|
||||
if(level == LV_LOG_LEVEL_WARN) printf("\033[33m[ WARN] ");
|
||||
if(level == LV_LOG_LEVEL_INFO) printf("\033[34m[ INFO] ");
|
||||
if(level == LV_LOG_LEVEL_WARN) printf("\033[33m[ WARN] ");
|
||||
if(level == LV_LOG_LEVEL_INFO) printf("\033[34m[ INFO] ");
|
||||
if(level == LV_LOG_LEVEL_TRACE) printf("\033[36m[TRACE] ");
|
||||
|
||||
printf("%s:%d, %s(): %s", file, line, fn_name, dsc);
|
||||
|
|
@ -17,13 +36,72 @@ void user_lvgl_impl_log_cb(lv_log_level_t level, const char *file, uint32_t line
|
|||
printf("\033[m\r\n");
|
||||
}
|
||||
|
||||
void user_lvgl_impl_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) {
|
||||
void user_lvgl_impl_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area,
|
||||
lv_color_t *color_p) {
|
||||
if(HAL_LTDC_SetAddress(&hltdc, (uint32_t)color_p, LTDC_LAYER_1) != HAL_OK) {
|
||||
printf("Set LTDC address error.\r\n");
|
||||
}
|
||||
lv_disp_flush_ready(disp_drv);
|
||||
}
|
||||
|
||||
void user_lvgl_impl_gpu_blend_cb(lv_disp_drv_t *disp_drv, lv_color_t *dest,
|
||||
const lv_color_t *src, uint32_t length,
|
||||
lv_opa_t opa) {
|
||||
hdma2d.Init.Mode = DMA2D_M2M_BLEND;
|
||||
if(HAL_DMA2D_Init(&hdma2d) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
hdma2d.LayerCfg[1].InputAlpha = opa;
|
||||
HAL_DMA2D_ConfigLayer(&hdma2d, 1);
|
||||
|
||||
HAL_DMA2D_RegisterCallback(&hdma2d, HAL_DMA2D_TRANSFERCOMPLETE_CB_ID,
|
||||
_user_lvgl_impl_dma2d_cplt_callback);
|
||||
|
||||
HAL_DMA2D_RegisterCallback(&hdma2d, HAL_DMA2D_TRANSFERERROR_CB_ID,
|
||||
_user_lvgl_impl_dma2d_err_callback);
|
||||
|
||||
osEventFlagsClear(g_user_lvgl_event_handle, USER_LVGL_EVENT_DMA2D_READY);
|
||||
|
||||
HAL_DMA2D_BlendingStart_IT(&hdma2d, (uint32_t)src, (uint32_t)dest,
|
||||
(uint32_t)dest, length, 1);
|
||||
}
|
||||
|
||||
void user_lvgl_impl_gpu_fill_cb(lv_disp_drv_t *disp_drv, lv_color_t *dest_buf,
|
||||
lv_coord_t dest_width,
|
||||
const lv_area_t *fill_area, lv_color_t color) {
|
||||
hdma2d.Init.Mode = DMA2D_R2M;
|
||||
hdma2d.Init.OutputOffset = dest_width - lv_area_get_width(fill_area);
|
||||
if(HAL_DMA2D_Init(&hdma2d) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
hdma2d.LayerCfg[1].InputAlpha = 0xFF;
|
||||
HAL_DMA2D_ConfigLayer(&hdma2d, 1);
|
||||
|
||||
uint32_t dest_start =
|
||||
(uint32_t)(dest_buf + fill_area->y1 * dest_width + fill_area->x1);
|
||||
|
||||
HAL_DMA2D_RegisterCallback(&hdma2d, HAL_DMA2D_TRANSFERCOMPLETE_CB_ID,
|
||||
_user_lvgl_impl_dma2d_cplt_callback);
|
||||
|
||||
HAL_DMA2D_RegisterCallback(&hdma2d, HAL_DMA2D_TRANSFERERROR_CB_ID,
|
||||
_user_lvgl_impl_dma2d_err_callback);
|
||||
|
||||
osEventFlagsClear(g_user_lvgl_event_handle, USER_LVGL_EVENT_DMA2D_READY);
|
||||
|
||||
HAL_DMA2D_BlendingStart_IT(&hdma2d, lv_color_to32(color), dest_start,
|
||||
dest_start, lv_area_get_width(fill_area),
|
||||
lv_area_get_height(fill_area));
|
||||
}
|
||||
|
||||
void user_lvgl_impl_gpu_wait_cb(lv_disp_drv_t *disp_drv) {
|
||||
osEventFlagsWait(g_user_lvgl_event_handle, USER_LVGL_EVENT_DMA2D_READY,
|
||||
osFlagsNoClear, osWaitForever);
|
||||
HAL_DMA2D_UnRegisterCallback(&hdma2d, HAL_DMA2D_TRANSFERCOMPLETE_CB_ID);
|
||||
HAL_DMA2D_UnRegisterCallback(&hdma2d, HAL_DMA2D_TRANSFERERROR_CB_ID);
|
||||
}
|
||||
|
||||
void user_lvgl_impl_clean_dcache_cb(lv_disp_drv_t *disp_drv) {
|
||||
SCB_CleanInvalidateDCache_by_Addr((uint32_t *)0xD0100000, 0x00400000);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ void user_tasks_init(void) {
|
|||
if(g_user_lvgl_task_handle == NULL) Error_Handler();
|
||||
|
||||
// Wait here to make sure LVGL is initialized.
|
||||
osEventFlagsWait(g_user_lvgl_event_handle, USER_LVGL_EVENT_FLAG_READY, 0U, osWaitForever);
|
||||
osEventFlagsWait(g_user_lvgl_event_handle, USER_LVGL_EVENT_FLAG_READY, osFlagsNoClear, osWaitForever);
|
||||
|
||||
g_user_hello_task_handle = osThreadNew(user_hello_task, NULL, &g_user_hello_task_attributes);
|
||||
if(g_user_hello_task_handle == NULL) Error_Handler();
|
||||
|
|
|
|||
5
Makefile
5
Makefile
|
|
@ -1,5 +1,5 @@
|
|||
##########################################################################################################################
|
||||
# File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Wed Mar 03 23:47:59 CST 2021]
|
||||
# File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Thu Mar 04 22:59:26 CST 2021]
|
||||
##########################################################################################################################
|
||||
|
||||
# ------------------------------------------------
|
||||
|
|
@ -77,7 +77,8 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c \
|
|||
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \
|
||||
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \
|
||||
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c \
|
||||
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c
|
||||
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c \
|
||||
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c
|
||||
|
||||
# ASM sources
|
||||
ASM_SOURCES = \
|
||||
|
|
|
|||
25
README.md
25
README.md
|
|
@ -43,6 +43,27 @@ SDRAM clock: 66.5MHz(FMC clock divided by 2)
|
|||
Memory component: Winbond W9825G6KH-6(133MHz/CL2)
|
||||
|
||||
Memory parameters:
|
||||
* Column address = 9bits
|
||||
* Row address = 13bits
|
||||
* Common clock = 2HCLK
|
||||
* Burst read = enabled
|
||||
* Read pipe delay = 0HCLK
|
||||
* CL = 2 cycles
|
||||
* tMRD = 2 cycles
|
||||
* tXSR = 72ns (~5 cycles)
|
||||
* tMRD(Load mode rergister) = 2 cycles
|
||||
* tXSR(Exit self-refresh) = 72ns (~5 cycles)
|
||||
* tRAS(Self regresh time) = 42ns (~3 cycles)
|
||||
* tRC(Row cycle delay) = 60ns (~4 cycles)
|
||||
* tWR(Write recovery) = 2 cycles
|
||||
* tRP(Row precharge delay) = 15ns (~2 cycles)
|
||||
* tRCD(Row to column delay) = 15ns (~2 cycles, up to 3 cycles for constraints)
|
||||
|
||||
Alternative memory parameters for 250MHz FMC clock(tCK = 8ns):
|
||||
* Read pipe delay = 1HCLK
|
||||
* CL = 2 cycles
|
||||
* tMRD(Load mode rergister) = 2 cycles
|
||||
* tXSR(Exit self-refresh) = 72ns (~9 cycles)
|
||||
* tRAS(Self regresh time) = 42ns (~6 cycles)
|
||||
* tRC(Row cycle delay) = 60ns (~8 cycles)
|
||||
* tWR(Write recovery) = 2 cycles
|
||||
* tRP(Row precharge delay) = 15ns (~2 cycles)
|
||||
* tRCD(Row to column delay) = 15ns (~2 cycles, up to 4 cycles for constraints)
|
||||
|
|
@ -18,10 +18,10 @@ CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_ENABL
|
|||
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings
|
||||
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_BUFFERABLE
|
||||
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_BUFFERABLE
|
||||
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_NOT_BUFFERABLE
|
||||
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_BUFFERABLE
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_CACHEABLE
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_NOT_CACHEABLE
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_CACHEABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_SHAREABLE
|
||||
|
|
@ -33,6 +33,12 @@ CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_SIZE_64
|
|||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LEVEL1
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL1
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_TEX_LEVEL1
|
||||
DMA2D.AlphaModeBackground=DMA2D_REPLACE_ALPHA
|
||||
DMA2D.AlphaModeForeground=DMA2D_REPLACE_ALPHA
|
||||
DMA2D.IPParameters=AlphaModeForeground,InputAlphaForeground,Mode,AlphaModeBackground,InputAlphaBackground
|
||||
DMA2D.InputAlphaBackground=255
|
||||
DMA2D.InputAlphaForeground=255
|
||||
DMA2D.Mode=DMA2D_M2M_BLEND
|
||||
Dma.MEMTOMEM.0.Direction=DMA_MEMORY_TO_MEMORY
|
||||
Dma.MEMTOMEM.0.EventEnable=DISABLE
|
||||
Dma.MEMTOMEM.0.FIFOMode=DMA_FIFOMODE_ENABLE
|
||||
|
|
@ -58,20 +64,21 @@ Dma.Request0=MEMTOMEM
|
|||
Dma.RequestsNb=1
|
||||
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_2
|
||||
FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
|
||||
FMC.ExitSelfRefreshDelay1=5
|
||||
FMC.IPParameters=ColumnBitsNumber1,CASLatency1,ReadBurst1,ReadBurst2,LoadToActiveDelay1,ReadPipeDelay1,SDClockPeriod1,SDClockPeriod2,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1
|
||||
FMC.ExitSelfRefreshDelay1=9
|
||||
FMC.IPParameters=ColumnBitsNumber1,CASLatency1,ReadBurst1,ReadBurst2,LoadToActiveDelay1,ReadPipeDelay1,SDClockPeriod1,SDClockPeriod2,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1,ReadPipeDelay2
|
||||
FMC.LoadToActiveDelay1=2
|
||||
FMC.RCDDelay1=2
|
||||
FMC.RCDDelay1=4
|
||||
FMC.RPDelay1=2
|
||||
FMC.RPDelay2=2
|
||||
FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
|
||||
FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE
|
||||
FMC.ReadPipeDelay1=FMC_SDRAM_RPIPE_DELAY_0
|
||||
FMC.RowCycleDelay1=4
|
||||
FMC.RowCycleDelay2=4
|
||||
FMC.ReadPipeDelay1=FMC_SDRAM_RPIPE_DELAY_1
|
||||
FMC.ReadPipeDelay2=FMC_SDRAM_RPIPE_DELAY_1
|
||||
FMC.RowCycleDelay1=8
|
||||
FMC.RowCycleDelay2=8
|
||||
FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
|
||||
FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2
|
||||
FMC.SelfRefreshTime1=3
|
||||
FMC.SelfRefreshTime1=6
|
||||
FMC.WriteRecoveryTime1=2
|
||||
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE
|
||||
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
|
||||
|
|
@ -100,27 +107,29 @@ LTDC.WindowY1_L0=479
|
|||
Mcu.Family=STM32H7
|
||||
Mcu.IP0=CORTEX_M7
|
||||
Mcu.IP1=DEBUG
|
||||
Mcu.IP10=TIM2
|
||||
Mcu.IP11=TIM3
|
||||
Mcu.IP12=USART1
|
||||
Mcu.IP10=SYS
|
||||
Mcu.IP11=TIM2
|
||||
Mcu.IP12=TIM3
|
||||
Mcu.IP13=USART1
|
||||
Mcu.IP2=DMA
|
||||
Mcu.IP3=FMC
|
||||
Mcu.IP4=FREERTOS
|
||||
Mcu.IP5=LTDC
|
||||
Mcu.IP6=NVIC
|
||||
Mcu.IP7=RCC
|
||||
Mcu.IP8=RTC
|
||||
Mcu.IP9=SYS
|
||||
Mcu.IPNb=13
|
||||
Mcu.IP3=DMA2D
|
||||
Mcu.IP4=FMC
|
||||
Mcu.IP5=FREERTOS
|
||||
Mcu.IP6=LTDC
|
||||
Mcu.IP7=NVIC
|
||||
Mcu.IP8=RCC
|
||||
Mcu.IP9=RTC
|
||||
Mcu.IPNb=14
|
||||
Mcu.Name=STM32H750XBHx
|
||||
Mcu.Package=TFBGA240
|
||||
Mcu.Pin0=PI6
|
||||
Mcu.Pin1=PI5
|
||||
Mcu.Pin10=PA14 (JTCK/SWCLK)
|
||||
Mcu.Pin100=VP_RTC_VS_RTC_Calendar
|
||||
Mcu.Pin101=VP_SYS_VS_tim7
|
||||
Mcu.Pin102=VP_TIM2_VS_ClockSourceINT
|
||||
Mcu.Pin103=VP_TIM3_VS_ClockSourceINT
|
||||
Mcu.Pin100=VP_RTC_VS_RTC_Activate
|
||||
Mcu.Pin101=VP_RTC_VS_RTC_Calendar
|
||||
Mcu.Pin102=VP_SYS_VS_tim7
|
||||
Mcu.Pin103=VP_TIM2_VS_ClockSourceINT
|
||||
Mcu.Pin104=VP_TIM3_VS_ClockSourceINT
|
||||
Mcu.Pin11=PI2
|
||||
Mcu.Pin12=PH15
|
||||
Mcu.Pin13=PH14
|
||||
|
|
@ -216,9 +225,9 @@ Mcu.Pin94=PE7
|
|||
Mcu.Pin95=PE14
|
||||
Mcu.Pin96=PH7
|
||||
Mcu.Pin97=PD8
|
||||
Mcu.Pin98=VP_FREERTOS_VS_CMSIS_V2
|
||||
Mcu.Pin99=VP_RTC_VS_RTC_Activate
|
||||
Mcu.PinsNb=104
|
||||
Mcu.Pin98=VP_DMA2D_VS_DMA2D
|
||||
Mcu.Pin99=VP_FREERTOS_VS_CMSIS_V2
|
||||
Mcu.PinsNb=105
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32H750XBHx
|
||||
|
|
@ -226,6 +235,7 @@ MxCube.Version=6.2.0
|
|||
MxDb.Version=DB.6.0.20
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
NVIC.DMA2D_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.FLASH_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
NVIC.FMC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
|
|
@ -570,13 +580,13 @@ ProjectManager.PreviousToolchain=
|
|||
ProjectManager.ProjectBuild=false
|
||||
ProjectManager.ProjectFileName=STM32H750XB_Hello.ioc
|
||||
ProjectManager.ProjectName=STM32H750XB_Hello
|
||||
ProjectManager.RegisterCallBack=
|
||||
ProjectManager.RegisterCallBack=DMA2D
|
||||
ProjectManager.StackSize=0x400
|
||||
ProjectManager.TargetToolchain=Makefile
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_FMC_Init-FMC-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_LTDC_Init-LTDC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
RCC.ADCFreq_Value=133000000
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_FMC_Init-FMC-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_LTDC_Init-LTDC-false-HAL-true,10-MX_DMA2D_Init-DMA2D-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
RCC.ADCFreq_Value=125000000
|
||||
RCC.AHB12Freq_Value=60000000
|
||||
RCC.AHB4Freq_Value=60000000
|
||||
RCC.APB1Freq_Value=60000000
|
||||
|
|
@ -592,27 +602,28 @@ RCC.D1CPREFreq_Value=120000000
|
|||
RCC.DFSDMACLkFreq_Value=120000000
|
||||
RCC.DFSDMFreq_Value=60000000
|
||||
RCC.DIVM1=5
|
||||
RCC.DIVM2=25
|
||||
RCC.DIVM2=5
|
||||
RCC.DIVM3=25
|
||||
RCC.DIVN1=48
|
||||
RCC.DIVN2=266
|
||||
RCC.DIVN2=50
|
||||
RCC.DIVN3=172
|
||||
RCC.DIVP1Freq_Value=120000000
|
||||
RCC.DIVP2Freq_Value=133000000
|
||||
RCC.DIVP2Freq_Value=125000000
|
||||
RCC.DIVP3Freq_Value=86107543.9453125
|
||||
RCC.DIVQ1Freq_Value=120000000
|
||||
RCC.DIVQ2=10
|
||||
RCC.DIVQ2Freq_Value=26600000
|
||||
RCC.DIVQ2Freq_Value=25000000
|
||||
RCC.DIVQ3=4
|
||||
RCC.DIVQ3Freq_Value=43053771.97265625
|
||||
RCC.DIVR1Freq_Value=120000000
|
||||
RCC.DIVR2Freq_Value=133000000
|
||||
RCC.DIVR3=6
|
||||
RCC.DIVR3Freq_Value=28702514.6484375
|
||||
RCC.DIVR2=1
|
||||
RCC.DIVR2Freq_Value=250000000
|
||||
RCC.DIVR3=5
|
||||
RCC.DIVR3Freq_Value=34443017.578125
|
||||
RCC.EnbaleCSS=true
|
||||
RCC.FDCANFreq_Value=120000000
|
||||
RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_PLL2
|
||||
RCC.FMCFreq_Value=133000000
|
||||
RCC.FMCFreq_Value=250000000
|
||||
RCC.FamilyName=M
|
||||
RCC.HCLK3ClockFreq_Value=60000000
|
||||
RCC.HCLKFreq_Value=60000000
|
||||
|
|
@ -620,17 +631,17 @@ RCC.HPRE=RCC_HCLK_DIV2
|
|||
RCC.HRTIMFreq_Value=60000000
|
||||
RCC.I2C123Freq_Value=60000000
|
||||
RCC.I2C4Freq_Value=60000000
|
||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL3FRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,ProductRev,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16CLockSelection,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL3FRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,ProductRev,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16CLockSelection,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||
RCC.LPTIM1Freq_Value=60000000
|
||||
RCC.LPTIM2Freq_Value=60000000
|
||||
RCC.LPTIM345Freq_Value=60000000
|
||||
RCC.LPUART1Freq_Value=60000000
|
||||
RCC.LTDCFreq_Value=28702514.6484375
|
||||
RCC.LTDCFreq_Value=34443017.578125
|
||||
RCC.MCO1PinFreq_Value=64000000
|
||||
RCC.MCO2PinFreq_Value=120000000
|
||||
RCC.PLL3FRACN=1762
|
||||
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
||||
RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE3
|
||||
RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
|
||||
RCC.ProductRev=revV
|
||||
RCC.QSPIFreq_Value=60000000
|
||||
RCC.RNGFreq_Value=48000000
|
||||
|
|
@ -655,10 +666,10 @@ RCC.USART16Freq_Value=43053771.97265625
|
|||
RCC.USART234578Freq_Value=60000000
|
||||
RCC.USBFreq_Value=120000000
|
||||
RCC.VCO1OutputFreq_Value=240000000
|
||||
RCC.VCO2OutputFreq_Value=266000000
|
||||
RCC.VCO2OutputFreq_Value=250000000
|
||||
RCC.VCO3OutputFreq_Value=172215087.890625
|
||||
RCC.VCOInput1Freq_Value=5000000
|
||||
RCC.VCOInput2Freq_Value=1000000
|
||||
RCC.VCOInput2Freq_Value=5000000
|
||||
RCC.VCOInput3Freq_Value=1000000
|
||||
SH.FMC_A0.0=FMC_A0,13b-sda1
|
||||
SH.FMC_A0.ConfNb=1
|
||||
|
|
@ -796,6 +807,8 @@ TIM3.Pulse-PWM\ Generation4\ CH4=300 - 1
|
|||
USART1.BaudRate=921600
|
||||
USART1.IPParameters=VirtualMode-Asynchronous,BaudRate
|
||||
USART1.VirtualMode-Asynchronous=VM_ASYNC
|
||||
VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate
|
||||
VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D
|
||||
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
|
||||
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
|
||||
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
|
||||
|
|
|
|||
Loading…
Reference in New Issue