338 lines
10 KiB
C
338 lines
10 KiB
C
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/*
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* Copyright (C) 2005 by Dominic Rath
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* Dominic.Rath@gmx.de
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*
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* Copyright (C) 2006 by Magnus Lundin
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* lundin@mlu.mine.nu
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*
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* Copyright (C) 2008 by Spencer Oliver
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* spen@spen-soft.co.uk
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*
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* Copyright (C) 2009 by Øyvind Harboe
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* oyvind.harboe@zylin.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef OPENOCD_TARGET_ARM_OPCODES_H
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#define OPENOCD_TARGET_ARM_OPCODES_H
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/**
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* @file
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* Macros used to generate various ARM or Thumb opcodes.
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*/
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/* ARM mode instructions */
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/* Store multiple increment after
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* rn: base register
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* list: for each bit in list: store register
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* s: in privileged mode: store user-mode registers
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* w = 1: update the base register. w = 0: leave the base register untouched
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*/
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#define ARMV4_5_STMIA(rn, list, s, w) \
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(0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
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/* Load multiple increment after
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* rn: base register
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* list: for each bit in list: store register
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* s: in privileged mode: store user-mode registers
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* w = 1: update the base register. w = 0: leave the base register untouched
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*/
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#define ARMV4_5_LDMIA(rn, list, s, w) \
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(0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
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/* MOV r8, r8 */
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#define ARMV4_5_NOP (0xe1a08008)
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/* Move PSR to general purpose register
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* r = 1: SPSR r = 0: CPSR
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* rn: target register
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*/
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#define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
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/* Store register
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
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/* Load register
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
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/* Move general purpose register to PSR
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* r = 1: SPSR r = 0: CPSR
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* field: Field mask
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* 1: control field 2: extension field 4: status field 8: flags field
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* rm: source register
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*/
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#define ARMV4_5_MSR_GP(rm, field, r) \
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(0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
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#define ARMV4_5_MSR_IM(im, rotate, field, r) \
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(0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
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/* Load Register Word Immediate Post-Index
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
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/* Load Register Halfword Immediate Post-Index
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
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/* Load Register Byte Immediate Post-Index
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
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/* Store register Word Immediate Post-Index
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
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/* Store register Halfword Immediate Post-Index
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
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/* Store register Byte Immediate Post-Index
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
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/* Branch (and Link)
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* im: Branch target (left-shifted by 2 bits, added to PC)
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* l: 1: branch and link 0: branch only
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*/
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#define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
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/* Branch and exchange (ARM state)
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* rm: register holding branch target address
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*/
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#define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
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/* Copies two words from two ARM core registers
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* into a doubleword extension register, or
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* from a doubleword extension register to two ARM core registers.
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* See Armv7-A arch reference manual section A8.8.345
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* rt: Arm core register 1
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* rt2: Arm core register 2
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* vm: The doubleword extension register
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* m: m = UInt(m:vm);
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* op: to_arm_registers = (op == ‘1’);
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*/
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#define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
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(0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
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((rt) << 12) | ((m) << 5) | (vm))
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/* Moves the value of the FPSCR to an ARM core register
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* rt: Arm core register
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*/
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#define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
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/* Moves the value of an ARM core register to the FPSCR.
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* rt: Arm core register
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*/
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#define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
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/* Store data from coprocessor to consecutive memory
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* See Armv7-A arch doc section A8.6.187
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* p: 1=index mode (offset from rn)
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* u: 1=add, 0=subtract rn address with imm
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* d: Opcode D encoding
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* w: write back the offset start address to the rn register
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* cp: Coprocessor number (4 bits)
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* crd: Coprocessor source register (4 bits)
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* rn: Base register for memory address (4 bits)
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* imm: Immediate value (0 - 1020, must be divisible by 4)
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*/
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#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
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(0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
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((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
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/* Loads data from consecutive memory to coprocessor
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* See Armv7-A arch doc section A8.6.51
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* p: 1=index mode (offset from rn)
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* u: 1=add, 0=subtract rn address with imm
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* d: Opcode D encoding
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* w: write back the offset start address to the rn register
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* cp: Coprocessor number (4 bits)
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* crd: Coprocessor dest register (4 bits)
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* rn: Base register for memory address (4 bits)
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* imm: Immediate value (0 - 1020, must be divisible by 4)
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*/
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#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
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(0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
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((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
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/* Move to ARM register from coprocessor
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* cp: Coprocessor number
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* op1: Coprocessor opcode
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* rd: destination register
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* crn: first coprocessor operand
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* crm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
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(0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
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| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
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/* Move to coprocessor from ARM register
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* cp: Coprocessor number
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* op1: Coprocessor opcode
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* rd: destination register
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* crn: first coprocessor operand
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* crm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
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(0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
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| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
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/* Breakpoint instruction (ARMv5)
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* im: 16-bit immediate
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*/
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#define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
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/* Thumb mode instructions
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*
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* NOTE: these 16-bit opcodes fill both halves of a word with the same
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* value. The reason for this is that when we need to execute Thumb
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* opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
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* we must shift 32 bits to the bus using scan chain 1 ... if we write
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* both halves, we don't need to track which half matters. On ARMv6 and
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* ARMv7 we don't execute Thumb instructions in debug mode; the ITR
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* register does not accept Thumb (or Thumb2) opcodes.
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*/
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/* Store register (Thumb mode)
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* rd: source register
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* rn: base register
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*/
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#define ARMV4_5_T_STR(rd, rn) \
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((0x6000 | (rd) | ((rn) << 3)) | \
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((0x6000 | (rd) | ((rn) << 3)) << 16))
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/* Load register (Thumb state)
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* rd: destination register
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* rn: base register
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*/
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#define ARMV4_5_T_LDR(rd, rn) \
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((0x6800 | ((rn) << 3) | (rd)) \
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| ((0x6800 | ((rn) << 3) | (rd)) << 16))
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/* Load multiple (Thumb state)
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* rn: base register
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* list: for each bit in list: store register
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*/
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#define ARMV4_5_T_LDMIA(rn, list) \
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((0xc800 | ((rn) << 8) | (list)) \
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| ((0xc800 | ((rn) << 8) | (list)) << 16))
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/* Load register with PC relative addressing
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* rd: register to load
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*/
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#define ARMV4_5_T_LDR_PCREL(rd) \
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((0x4800 | ((rd) << 8)) \
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| ((0x4800 | ((rd) << 8)) << 16))
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/* Move hi register (Thumb mode)
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* rd: destination register
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* rm: source register
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*/
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#define ARMV4_5_T_MOV(rd, rm) \
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((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
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(((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
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| ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
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(((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
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/* No operation (Thumb mode)
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* NOTE: this is "MOV r8, r8" ... Thumb2 adds two
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* architected NOPs, 16-bit and 32-bit.
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*/
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#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
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/* Move immediate to register (Thumb state)
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* rd: destination register
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* im: 8-bit immediate value
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*/
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#define ARMV4_5_T_MOV_IM(rd, im) \
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((0x2000 | ((rd) << 8) | (im)) \
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| ((0x2000 | ((rd) << 8) | (im)) << 16))
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/* Branch and Exchange
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* rm: register containing branch target
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*/
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#define ARMV4_5_T_BX(rm) \
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((0x4700 | ((rm) << 3)) \
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| ((0x4700 | ((rm) << 3)) << 16))
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/* Branch (Thumb state)
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* imm: Branch target
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*/
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#define ARMV4_5_T_B(imm) \
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((0xe000 | (imm)) \
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| ((0xe000 | (imm)) << 16))
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/* Breakpoint instruction (ARMv5) (Thumb state)
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* Im: 8-bit immediate
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*/
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#define ARMV5_T_BKPT(im) \
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((0xbe00 | (im)) \
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| ((0xbe00 | (im)) << 16))
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/* Move to Register from Special Register
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* 32 bit Thumb2 instruction
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* rd: destination register
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* sysm: source special register
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*/
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#define ARM_T2_MRS(rd, sysm) \
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((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
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/* Move from Register from Special Register
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* 32 bit Thumb2 instruction
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* rd: source register
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* sysm: destination special register
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*/
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#define ARM_T2_MSR(sysm, rn) \
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((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
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/* Change Processor State.
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* 16 bit Thumb2 instruction
|
|||
|
|
* rd: source register
|
|||
|
|
* IF: A_FLAG and/or I_FLAG and/or F_FLAG
|
|||
|
|
*/
|
|||
|
|
#define A_FLAG 4
|
|||
|
|
#define I_FLAG 2
|
|||
|
|
#define F_FLAG 1
|
|||
|
|
#define ARM_T2_CPSID(_if) \
|
|||
|
|
((0xB660 | (1 << 8) | ((_if)&0x3)) \
|
|||
|
|
| ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
|
|||
|
|
#define ARM_T2_CPSIE(_if) \
|
|||
|
|
((0xB660 | (0 << 8) | ((_if)&0x3)) \
|
|||
|
|
| ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
|
|||
|
|
|
|||
|
|
#endif /* OPENOCD_TARGET_ARM_OPCODES_H */
|