riscv-openocd-wch/tcl/board/avnet_ultrazed-eg.cfg

17 lines
348 B
INI

#
# AVNET UltraZED EG StarterKit
# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
#
source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
# jtag transport only
transport select jtag
# reset lines are not wired
reset_config none
# slow default clock
adapter speed 1000
set CHIPNAME uscale
source [find target/xilinx_zynqmp.cfg]