u-boot-imx-next-20230404
------------------------ CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15887 - boards : DH-Electronics, Toradex, imx8mp-beacon-kit -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZCv6mg8cc2JhYmljQGRl bnguZGUACgkQ9PVl5Jpo76ZIrACfVH9xA0tG8UO87Ap+7h2J4PJU3+gAnA9QhfwC vF42NNf2OlnNEVee1jGz =vlEI -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-next-20230404' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-next-20230404 ------------------------ CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15887 - boards : DH-Electronics, Toradex, imx8mp-beacon-kit
This commit is contained in:
Tom Rini
commit
0916377b83
3
Makefile
3
Makefile
|
|
@ -1522,6 +1522,9 @@ endif
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|||
u-boot.uim: u-boot.bin FORCE
|
||||
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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||||
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||||
u-boot-nand.imx: u-boot.imx FORCE
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||||
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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||||
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||||
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
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$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
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||||
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|
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|||
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@ -995,6 +995,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mn-beacon-kit.dtb \
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||||
imx8mq-mnt-reform2.dtb \
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||||
imx8mq-phanbell.dtb \
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||||
imx8mp-beacon-kit.dtb \
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||||
imx8mp-data-modul-edm-sbc.dtb \
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imx8mp-dhcom-pdk2.dtb \
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imx8mp-dhcom-pdk3.dtb \
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||||
imx8mp-evk.dtb \
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||||
|
|
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|||
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@ -8,6 +8,12 @@
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aliases {
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||||
eeprom0 = &eeprom0;
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};
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||||
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||||
wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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};
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&fec {
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@ -25,3 +31,7 @@
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|||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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||||
};
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||||
|
||||
&wdog1 {
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bootph-pre-ram;
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||||
};
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||||
|
|
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|||
216
arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
Normal file
216
arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
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||||
/*
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* Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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bootph-pre-ram;
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||||
};
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||||
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-pre-ram;
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};
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&crypto {
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bootph-pre-ram;
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};
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|
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&eqos {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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ðphy0 {
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&flexspi {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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||||
|
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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|
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&i2c1 {
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bootph-pre-ram;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&pca6416 {
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compatible = "ti,tca6416";
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label = "exp4";
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};
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&pca6416_1 {
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compatible = "ti,tca6416";
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label = "exp4";
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};
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&pca6416_3 {
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compatible = "ti,tca6416";
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label = "exp2";
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};
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&pinctrl_i2c1 {
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bootph-pre-ram;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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||||
};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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u-boot,off-on-delay-us = <20000>;
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};
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&sec_jr0 {
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bootph-pre-ram;
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};
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&sec_jr1 {
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bootph-pre-ram;
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};
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&sec_jr2 {
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bootph-pre-ram;
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};
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&tpm {
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compatible = "tcg,tpm_tis-spi";
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};
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&uart2 {
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bootph-pre-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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||||
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||||
&usb3_0 {
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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/delete-property/ power-domains;
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};
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||||
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||||
&usb3_1 {
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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/delete-property/ power-domains;
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};
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&usb_dwc3_0 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usb_dwc3_1 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usdhc1 {
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status = "disabled";
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};
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&wdog1 {
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bootph-pre-ram;
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};
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550
arch/arm/dts/imx8mp-beacon-kit.dts
Normal file
550
arch/arm/dts/imx8mp-beacon-kit.dts
Normal file
|
|
@ -0,0 +1,550 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
*/
|
||||
|
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/dts-v1/;
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||||
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||||
#include <dt-bindings/usb/pd.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mp.dtsi"
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#include "imx8mp-beacon-som.dtsi"
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/ {
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model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";
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compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
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aliases {
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ethernet0 = &eqos;
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ethernet1 = &fec;
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};
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chosen {
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stdout-path = &uart2;
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};
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hs_ep: endpoint {
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remote-endpoint = <&usb3_hs_ep>;
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};
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};
|
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port@1 {
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reg = <1>;
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||||
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ss_ep: endpoint {
|
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remote-endpoint = <&hd3ss3220_in_ep>;
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};
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||||
};
|
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};
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};
|
||||
|
||||
gpio-keys {
|
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compatible = "gpio-keys";
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autorepeat;
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|
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button-0 {
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label = "btn0";
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linux,code = <BTN_0>;
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gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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wakeup-source;
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};
|
||||
|
||||
button-1 {
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label = "btn1";
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||||
linux,code = <BTN_1>;
|
||||
gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
button-2 {
|
||||
label = "btn2";
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||||
linux,code = <BTN_2>;
|
||||
gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
button-3 {
|
||||
label = "btn3";
|
||||
linux,code = <BTN_3>;
|
||||
gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_led3>;
|
||||
|
||||
led-0 {
|
||||
label = "gen_led0";
|
||||
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
label = "gen_led1";
|
||||
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
label = "gen_led2";
|
||||
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: clock-pcie {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <100>;
|
||||
off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
reg_usb1_host_vbus: regulator-usb1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1_host_vbus";
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
tpm: tpm@0 {
|
||||
compatible = "infineon,slb9670";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tpm>;
|
||||
reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
|
||||
spi-max-frequency = <18500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <150000>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
usb-mux-hog {
|
||||
gpio-hog;
|
||||
gpios = <20 0>;
|
||||
output-low;
|
||||
line-name = "USB-C Mux En";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <384000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
pca6416_3: gpio@20 {
|
||||
compatible = "nxp,pcal6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
/* Connected to USB Hub */
|
||||
usb-typec@52 {
|
||||
compatible = "nxp,ptn5110";
|
||||
reg = <0x52>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_typec>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
power-role = "source";
|
||||
data-role = "host";
|
||||
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clock-frequency = <384000>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "nxp,pcal6416";
|
||||
reg = <0x20>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcal6414>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pca6416_1: gpio@21 {
|
||||
compatible = "nxp,pcal6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
usb-hub-hog {
|
||||
gpio-hog;
|
||||
gpios = <7 0>;
|
||||
output-low;
|
||||
line-name = "USB Hub Enable";
|
||||
};
|
||||
};
|
||||
|
||||
usb-typec@47 {
|
||||
compatible = "ti,hd3ss3220";
|
||||
reg = <0x47>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hd3ss3220>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hd3ss3220_in_ep: endpoint {
|
||||
remote-endpoint = <&ss_ep>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hd3ss3220_out_ep: endpoint {
|
||||
remote-endpoint = <&usb3_role_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
clocks = <&pcie0_refclk>;
|
||||
clock-names = "ref";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_0 {
|
||||
dr_mode = "otg";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb3_hs_ep: endpoint {
|
||||
remote-endpoint = <&hs_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
usb3_role_switch: endpoint {
|
||||
remote-endpoint = <&hd3ss3220_out_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
vbus-supply = <®_usb1_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
|
||||
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
|
||||
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
|
||||
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
|
||||
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140
|
||||
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
||||
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hd3ss3220: hd3ss3220grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led3: led3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcal6414: pcal6414-gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */
|
||||
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tpm: tpmgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
|
||||
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_typec: typec1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
|
||||
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
|
||||
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
|
||||
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
|
||||
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
};
|
||||
416
arch/arm/dts/imx8mp-beacon-som.dtsi
Normal file
416
arch/arm/dts/imx8mp-beacon-som.dtsi
Normal file
|
|
@ -0,0 +1,416 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
rtc0 = &rtc;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0xc0000000>,
|
||||
<0x1 0x00000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
reg_wl_bt: regulator-wifi-bt {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_wl_bt>;
|
||||
regulator-name = "wl-bt-pow-dwn";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
startup-delay-us = <70000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&eqos {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eqos>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
snps,force_thresh_dma_mode;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <80000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clock-frequency = <384000>;
|
||||
status = "okay";
|
||||
|
||||
pmic@25 {
|
||||
compatible = "nxp,pca9450c";
|
||||
reg = <0x25>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
buck1: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
|
||||
buck4: BUCK4 {
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5: BUCK5 {
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clock-frequency = <384000>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
read-only; /* Manufacturing EEPROM programmed at factory */
|
||||
};
|
||||
|
||||
rtc: rtc@51 {
|
||||
compatible = "nxp,pcf85263";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_wl_bt>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
mwifiex: wifi@1 {
|
||||
compatible = "marvell,sd8997";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wlan>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
|
||||
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
|
||||
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
|
||||
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
|
||||
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
|
||||
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
|
||||
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
|
||||
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
|
||||
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
|
||||
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
|
||||
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
||||
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
||||
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
||||
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
||||
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
|
||||
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
|
||||
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_wl_bt: reg-wl-btgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
||||
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
||||
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
|
||||
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan: wlangrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
130
arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
Normal file
130
arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include "imx8mp-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
eeprom0 = &eeprom;
|
||||
mmc0 = &usdhc3; /* eMMC */
|
||||
mmc1 = &usdhc2; /* MicroSD */
|
||||
spi0 = &ecspi1;
|
||||
};
|
||||
|
||||
config {
|
||||
dmo,ram-coding-gpios = <&gpio3 20 0>, <&gpio4 3 0>, <&gpio4 1 0>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdog1>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&buck4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&buck5 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
bootph-pre-ram;
|
||||
flash@0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&eqos {
|
||||
/delete-property/ assigned-clocks;
|
||||
/delete-property/ assigned-clock-parents;
|
||||
/delete-property/ assigned-clock-rates;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_ecspi1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_hog_sbc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_i2c3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_i2c3_gpio {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_pmic {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_uart3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pmic {
|
||||
bootph-pre-ram;
|
||||
|
||||
regulators {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
bootph-pre-ram;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
bootph-pre-ram;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
973
arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
Normal file
973
arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
Normal file
|
|
@ -0,0 +1,973 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/net/qca-ar803x.h>
|
||||
#include "imx8mp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Data Modul i.MX8M Plus eDM SBC";
|
||||
compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
|
||||
|
||||
aliases {
|
||||
rtc0 = &rtc;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
/* There are 1/2/4 GiB options, adjusted by bootloader. */
|
||||
reg = <0x0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_panel_backlight>;
|
||||
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
|
||||
default-brightness-level = <7>;
|
||||
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
|
||||
pwms = <&pwm1 0 5000000 0>;
|
||||
/* Disabled by default, unless display board plugged in. */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_xtal25: clk-xtal25 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
backlight = <&backlight>;
|
||||
power-supply = <®_panel_vcc>;
|
||||
/* Disabled by default, unless display board plugged in. */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reg_panel_vcc: regulator-panel-vcc {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_panel_vcc_reg>;
|
||||
regulator-name = "PANEL_VCC";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 6 0>;
|
||||
enable-active-high;
|
||||
/* Disabled by default, unless display board plugged in. */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 19 0>; /* SD2_RESET */
|
||||
off-on-delay-us = <12000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-name = "VDD_3V3_SD";
|
||||
startup-delay-us = <100>;
|
||||
vin-supply = <&buck4>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
/* TPS3813 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_watchdog_gpio>;
|
||||
compatible = "linux,wdt-gpio";
|
||||
always-running;
|
||||
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
|
||||
hw_algo = "level";
|
||||
/* Reset triggers in 2..3 seconds */
|
||||
hw_margin_ms = <1500>;
|
||||
/* Disabled by default */
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 { /* W25Q128JVEI */
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000000>; /* Up to 133 MHz */
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi2 { /* Feature connector SPI */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
|
||||
/* Disabled by default, unless feature board plugged in. */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecspi3 { /* Display connector SPI */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi3>;
|
||||
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
|
||||
/* Disabled by default, unless display board plugged in. */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&eqos { /* First ethernet */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eqos>;
|
||||
phy-handle = <&phy_eqos>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Atheros AR8031 PHY */
|
||||
phy_eqos: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
/*
|
||||
* Dedicated ENET_WOL# signal is unused, the PHY
|
||||
* can wake the SoC up via INT signal as well.
|
||||
*/
|
||||
interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <10000>;
|
||||
qca,keep-pll-enabled;
|
||||
vddio-supply = <&vddio_eqos>;
|
||||
|
||||
vddio_eqos: vddio-regulator {
|
||||
regulator-name = "VDDIO_EQOS";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vddh_eqos: vddh-regulator {
|
||||
regulator-name = "VDDH_EQOS";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec { /* Second ethernet */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-handle = <&phy_fec>;
|
||||
phy-mode = "rgmii-id";
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Atheros AR8031 PHY */
|
||||
phy_fec: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
/*
|
||||
* Dedicated ENET_WOL# signal is unused, the PHY
|
||||
* can wake the SoC up via INT signal as well.
|
||||
*/
|
||||
interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <10000>;
|
||||
qca,keep-pll-enabled;
|
||||
vddio-supply = <&vddio_fec>;
|
||||
|
||||
vddio_fec: vddio-regulator {
|
||||
regulator-name = "VDDIO_FEC";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vddh_fec: vddh-regulator {
|
||||
regulator-name = "VDDH_FEC";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
"", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
|
||||
"", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
|
||||
"GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
|
||||
"", "", "", "ENET_RST#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names =
|
||||
"", "", "ENET2_INT#", "", "", "", "", "",
|
||||
"WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
|
||||
"", "", "", "",
|
||||
"", "", "", "SD2_RESET#", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names =
|
||||
"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
|
||||
"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
|
||||
"CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
|
||||
"", "", "EEPROM_WP_1V8#", "", "", "", "", "",
|
||||
"MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
|
||||
"", "M2_W_DISABLE1_1V8#",
|
||||
"M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
|
||||
"", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names =
|
||||
"DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
|
||||
"", "DIS_USB_DN1", "DIS_USB_DN2", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "WDOG_EN", "", "",
|
||||
"", "SPI1_CS#", "", "",
|
||||
"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
|
||||
"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
|
||||
"", "", "", "",
|
||||
"", "SPI3_CS#", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
usb-hub@2c {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_hub>;
|
||||
compatible = "microchip,usb2514bi";
|
||||
reg = <0x2c>;
|
||||
individual-port-switching;
|
||||
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
self-powered;
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc>;
|
||||
compatible = "st,m41t62";
|
||||
reg = <0x68>;
|
||||
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
pcieclk: clk@6a {
|
||||
compatible = "renesas,9fgv0241";
|
||||
reg = <0x6a>;
|
||||
clocks = <&clk_xtal25>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
||||
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
||||
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@25 {
|
||||
compatible = "nxp,pca9450c";
|
||||
reg = <0x25>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/*
|
||||
* i.MX 8M Plus Data Sheet for Consumer Products
|
||||
* 3.1.4 Operating ranges
|
||||
* MIMX8ML8CVNKZAB
|
||||
*/
|
||||
regulators {
|
||||
buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-ramp-delay = <3125>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2: BUCK2 { /* VDD_ARM */
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-ramp-delay = <3125>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck4: BUCK4 { /* VDD_3V3 */
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck5: BUCK5 { /* VDD_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck6: BUCK6 { /* NVCC_DRAM_1V1 */
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo1: LDO1 { /* NVCC_SNVS_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo3: LDO3 { /* VDDA_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo4: LDO4 { /* PMIC_LDO4 */
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo5: LDO5 { /* NVCC_SD2 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 { /* HDMI EDID bus */
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c5>;
|
||||
pinctrl-1 = <&pinctrl_i2c5_gpio>;
|
||||
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
|
||||
<&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
|
||||
<&pinctrl_panel_expansion>;
|
||||
|
||||
pinctrl_ecspi1: ecspi1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
|
||||
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
|
||||
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
|
||||
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
|
||||
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
|
||||
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
|
||||
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44
|
||||
MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44
|
||||
MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44
|
||||
MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_eqos: eqos-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
|
||||
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
|
||||
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
|
||||
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
|
||||
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
|
||||
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
|
||||
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
|
||||
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
|
||||
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
|
||||
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
|
||||
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
|
||||
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
|
||||
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
|
||||
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
|
||||
/* ENET_RST# */
|
||||
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6
|
||||
/* ENET_INT# */
|
||||
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fec-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
||||
/* ENET2_RST# */
|
||||
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6
|
||||
/* ENET2_INT# */
|
||||
MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
||||
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog_feature: hog-feature-grp {
|
||||
fsl,pins = <
|
||||
/* GPIO5_IO03 */
|
||||
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006
|
||||
/* GPIO5_IO04 */
|
||||
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006
|
||||
|
||||
/* CAN_INT# */
|
||||
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog_panel: hog-panel-grp {
|
||||
fsl,pins = <
|
||||
/* GRAPHICS_GPIO0_1V8 */
|
||||
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog_misc: hog-misc-grp {
|
||||
fsl,pins = <
|
||||
/* ENET_WOL# -- shared by both PHYs */
|
||||
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090
|
||||
|
||||
/* PG_V_IN_VAR# */
|
||||
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
|
||||
/* CSI2_PD_1V8 */
|
||||
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
|
||||
/* CSI2_RESET_1V8# */
|
||||
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
|
||||
|
||||
/* DIS_USB_DN1 */
|
||||
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
|
||||
/* DIS_USB_DN2 */
|
||||
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
|
||||
|
||||
/* EEPROM_WP_1V8# */
|
||||
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100
|
||||
/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
|
||||
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0
|
||||
/* GRAPHICS_PRSNT_1V8# */
|
||||
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
|
||||
|
||||
/* CLK_CCM_CLKO1_3V3 */
|
||||
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog_sbc: hog-sbc-grp {
|
||||
fsl,pins = <
|
||||
/* MEMCFG[0..2] straps */
|
||||
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140
|
||||
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140
|
||||
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084
|
||||
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84
|
||||
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084
|
||||
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84
|
||||
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
|
||||
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_gpio: i2c3-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
|
||||
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c5: i2c5-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
|
||||
MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c5_gpio: i2c5-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
|
||||
MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_panel_backlight: panel-backlight-grp {
|
||||
fsl,pins = <
|
||||
/* BL_ENABLE_1V8 */
|
||||
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_panel_expansion: panel-expansion-grp {
|
||||
fsl,pins = <
|
||||
/* DSI_RESET_1V8# */
|
||||
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2
|
||||
/* DSI_IRQ_1V8# */
|
||||
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_panel_pwm: panel-pwm-grp {
|
||||
fsl,pins = <
|
||||
/* BL_PWM_3V3 */
|
||||
MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_panel_vcc_reg: panel-vcc-grp {
|
||||
fsl,pins = <
|
||||
/* TFT_ENABLE_1V8 */
|
||||
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie-grp {
|
||||
fsl,pins = <
|
||||
/* M2_PCIE_RST# */
|
||||
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
|
||||
/* M2_W_DISABLE1_1V8# */
|
||||
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
|
||||
/* M2_W_DISABLE2_1V8# */
|
||||
MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
|
||||
/* CLK_M2_32K768 */
|
||||
MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
|
||||
/* M2_PCIE_WAKE# */
|
||||
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
|
||||
/* M2_PCIE_CLKREQ# */
|
||||
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pdm: pdm-grp {
|
||||
fsl,pins = <
|
||||
/* PDM_SEL */
|
||||
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0
|
||||
MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0
|
||||
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmic-grp {
|
||||
fsl,pins = <
|
||||
/* PMIC_nINT */
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rtc: rtc-grp {
|
||||
fsl,pins = <
|
||||
/* RTC_IRQ# */
|
||||
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai1: sai1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6
|
||||
MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6
|
||||
MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6
|
||||
MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6
|
||||
MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
|
||||
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
|
||||
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
|
||||
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai3: sai3-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
|
||||
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
|
||||
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
|
||||
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
|
||||
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49
|
||||
MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
|
||||
MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49
|
||||
MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49
|
||||
MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49
|
||||
MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
|
||||
MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
|
||||
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
|
||||
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_hub: usb-hub-grp {
|
||||
fsl,pins = <
|
||||
/* USBHUB_RESET# */
|
||||
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb1: usb1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6
|
||||
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_watchdog_gpio: watchdog-gpio-grp {
|
||||
fsl,pins = <
|
||||
/* WDOG_B# */
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26
|
||||
/* WDOG_EN -- ungate WDT RESET# signal propagation */
|
||||
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6
|
||||
/* WDOG_KICK# / WDI */
|
||||
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_panel_pwm>;
|
||||
/* Disabled by default, unless display board plugged in. */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SD slot */
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
vmmc-supply = <&buck4>;
|
||||
vqmmc-supply = <&buck5>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 { /* RS485 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
uart-has-rtscts;
|
||||
status = "disabled"; /* Optional */
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 { /* A53 Debug */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
fsl,over-current-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_0 { /* Lower plug direct */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 { /* Upper plug via HUB */
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -136,6 +136,12 @@ u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
|
|||
u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
|
||||
quiet_cmd_u-boot-nand_imx = GEN $@
|
||||
cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
|
||||
|
||||
u-boot-nand.imx: u-boot.imx FORCE
|
||||
$(call if_changed,u-boot-nand_imx)
|
||||
|
||||
ifeq ($(CONFIG_MULTI_DTB_FIT),y)
|
||||
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
|
||||
-T $(IMAGE_TYPE) -e $(CONFIG_TEXT_BASE)
|
||||
|
|
|
|||
|
|
@ -170,6 +170,23 @@ config TARGET_IMX8MN_VENICE
|
|||
select GATEWORKS_SC
|
||||
select MISC
|
||||
|
||||
config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
|
||||
bool "Data Modul eDM SBC i.MX8M Plus"
|
||||
select BINMAN
|
||||
select IMX8MP
|
||||
select IMX8M_LPDDR4
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_IMX8MP_BEACON
|
||||
bool "imx8mm Beacon Embedded devkit"
|
||||
select BINMAN
|
||||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
select FSL_CAAM
|
||||
select ARCH_MISC_INIT
|
||||
select SPL_CRYPTO if SPL
|
||||
|
||||
config TARGET_IMX8MP_DH_DHCOM_PDK2
|
||||
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
|
||||
select BINMAN
|
||||
|
|
@ -326,10 +343,12 @@ endchoice
|
|||
source "board/advantech/imx8mp_rsb3720a1/Kconfig"
|
||||
source "board/beacon/imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mn/Kconfig"
|
||||
source "board/beacon/imx8mp/Kconfig"
|
||||
source "board/bsh/imx8mn_smm_s2/Kconfig"
|
||||
source "board/cloos/imx8mm_phg/Kconfig"
|
||||
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
|
||||
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
|
||||
source "board/data_modul/imx8mp_edm_sbc/Kconfig"
|
||||
source "board/dhelectronics/dh_imx8mp/Kconfig"
|
||||
source "board/engicam/imx8mm/Kconfig"
|
||||
source "board/engicam/imx8mp/Kconfig"
|
||||
|
|
|
|||
16
board/beacon/imx8mp/Kconfig
Normal file
16
board/beacon/imx8mp/Kconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
if TARGET_IMX8MP_BEACON
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8mp"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "beacon"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8mp_beacon"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
|
||||
|
||||
|
||||
endif
|
||||
6
board/beacon/imx8mp/MAINTAINERS
Normal file
6
board/beacon/imx8mp/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
i.MX8MP Beacon EmbeddedWorks Devkit
|
||||
M: Adam Ford <aford173@gmail.com>
|
||||
S: Maintained
|
||||
F: board/beacon/imx8mp/
|
||||
F: include/configs/imx8mp_beacon.h
|
||||
F: configs/imx8mp_beacon_defconfig
|
||||
13
board/beacon/imx8mp/Makefile
Normal file
13
board/beacon/imx8mp/Makefile
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
#
|
||||
|
||||
obj-y += imx8mp_beacon.o
|
||||
obj-y += ../../freescale/common/
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
35
board/beacon/imx8mp/imx8mp_beacon.c
Normal file
35
board/beacon/imx8mp/imx8mp_beacon.c
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks */
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
static void setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Enable RGMII TX clk output */
|
||||
setbits_le32(&gpr->gpr[1], BIT(22));
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_NET)
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (CONFIG_IS_ENABLED(FEC_MXC))
|
||||
setup_fec();
|
||||
|
||||
return ret;
|
||||
}
|
||||
19
board/beacon/imx8mp/imx8mp_beacon.env
Normal file
19
board/beacon/imx8mp/imx8mp_beacon.env
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
boot_fdt=try
|
||||
boot_fit=no
|
||||
console=ttymxc1,115200
|
||||
fdt_addr=0x43000000
|
||||
fdt_addr_r=0x43000000
|
||||
fdt_file=imx8mp-beacon-kit.dtb
|
||||
finduuid=part uuid mmc ${mmcdev}:2 uuid
|
||||
image=Image
|
||||
kernel_addr_r=0x40480000
|
||||
loadfdt=echo ${fdt_file}; fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}
|
||||
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
mmcargs=setenv bootargs console=${console} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
|
||||
mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if run loadfdt; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi;
|
||||
mmcdev=1
|
||||
mmcpart=1
|
||||
netargs=setenv bootargs ${jh_clk} console=${console} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
|
||||
netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi;
|
||||
optargs=audit=0 video=LVDS-1:d video=LVDS-2:d
|
||||
scriptaddr=0x40480000
|
||||
9
board/beacon/imx8mp/imximage-8mp-lpddr4.cfg
Normal file
9
board/beacon/imx8mp/imximage-8mp-lpddr4.cfg
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
|
||||
ROM_VERSION v2
|
||||
BOOT_FROM sd
|
||||
LOADER u-boot-spl-ddr.bin 0x920000
|
||||
1881
board/beacon/imx8mp/lpddr4_timing.c
Normal file
1881
board/beacon/imx8mp/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load Diff
132
board/beacon/imx8mp/spl.c
Normal file
132
board/beacon/imx8mp/spl.c
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hang.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <spl.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
return BOOT_DEVICE_BOOTROM;
|
||||
}
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
|
||||
if (ret)
|
||||
printf("Failed to initialize caam_jr: %d\n", ret);
|
||||
}
|
||||
/*
|
||||
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
|
||||
* not allow to change it. Should set the clock after PMIC
|
||||
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
|
||||
* set by ROM for ND VDD_SOC
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
|
||||
clock_enable(CCGR_GIC, 0);
|
||||
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
|
||||
clock_enable(CCGR_GIC, 1);
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = pmic_get("pmic@25", &dev);
|
||||
if (ret == -ENODEV) {
|
||||
puts("No pmic@25\n");
|
||||
return 0;
|
||||
}
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
||||
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/*
|
||||
* increase VDD_SOC to typical value 0.95V before first
|
||||
* DRAM access, set DVS1 to 0.85v for suspend.
|
||||
* Enable DVS control through PMIC_STBY_REQ and
|
||||
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
|
||||
*/
|
||||
if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
|
||||
else
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
|
||||
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
|
||||
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
|
||||
|
||||
/* Kernel uses OD/OD freq for SOC */
|
||||
/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
|
||||
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(1);
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
15
board/data_modul/imx8mp_edm_sbc/Kconfig
Normal file
15
board/data_modul/imx8mp_edm_sbc/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_IMX8MP_DATA_MODUL_EDM_SBC
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8mp_edm_sbc"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "data_modul"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8mp_data_modul_edm_sbc"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/data_modul/imx8mp_edm_sbc/imximage.cfg"
|
||||
|
||||
endif
|
||||
8
board/data_modul/imx8mp_edm_sbc/MAINTAINERS
Normal file
8
board/data_modul/imx8mp_edm_sbc/MAINTAINERS
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
Data Modul eDM SBC i.MX8M Plus
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
|
||||
F: arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
|
||||
F: board/data_modul/imx8mp_data_modul_edm_sbc/
|
||||
F: configs/imx8mp_data_modul_edm_sbc_defconfig
|
||||
F: include/configs/imx8mp_data_modul_edm_sbc.h
|
||||
13
board/data_modul/imx8mp_edm_sbc/Makefile
Normal file
13
board/data_modul/imx8mp_edm_sbc/Makefile
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# Copyright (C) 2022 Marek Vasut <marex@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o lpddr4_timing_4G_32.o
|
||||
else
|
||||
obj-y += imx8mp_data_modul_edm_sbc.o
|
||||
endif
|
||||
|
||||
obj-y += ../common/common.o
|
||||
67
board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c
Normal file
67
board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <env.h>
|
||||
#include <env_internal.h>
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <spl.h>
|
||||
|
||||
#include "../common/common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void dmo_setup_second_mac_address(void)
|
||||
{
|
||||
u8 enetaddr[6];
|
||||
int ret;
|
||||
|
||||
/* In case 'eth1addr' is already set in environment, do nothing. */
|
||||
ret = eth_env_get_enetaddr_by_index("eth", 1, enetaddr);
|
||||
if (ret) /* valid 'eth1addr' is already set */
|
||||
return;
|
||||
|
||||
/* Read 'ethaddr' from environment and validate. */
|
||||
ret = eth_env_get_enetaddr_by_index("eth", 0, enetaddr);
|
||||
if (!ret) /* 'ethaddr' in environment is not valid, stop */
|
||||
return;
|
||||
|
||||
/* Set 'eth1addr' as 'ethaddr' + 1 */
|
||||
enetaddr[5]++;
|
||||
|
||||
eth_env_set_enetaddr_by_index("eth", 1, enetaddr);
|
||||
}
|
||||
|
||||
enum env_location env_get_location(enum env_operation op, int prio)
|
||||
{
|
||||
/* Environment is always in eMMC boot partitions */
|
||||
return prio ? ENVL_UNKNOWN : ENVL_MMC;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
dmo_setup_boot_device();
|
||||
dmo_setup_mac_address();
|
||||
dmo_setup_second_mac_address();
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev);
|
||||
if (ret)
|
||||
printf("Error bringing up USB hub (%d)\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
8
board/data_modul/imx8mp_edm_sbc/imximage.cfg
Normal file
8
board/data_modul/imx8mp_edm_sbc/imximage.cfg
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
ROM_VERSION v2
|
||||
BOOT_FROM sd
|
||||
LOADER u-boot-spl-ddr.bin 0x920000
|
||||
11
board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h
Normal file
11
board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#ifndef __LPDDR4_TIMING_H__
|
||||
#define __LPDDR4_TIMING_H__
|
||||
|
||||
extern struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32;
|
||||
|
||||
#endif /* __LPDDR4_TIMING_H__ */
|
||||
1849
board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
Normal file
1849
board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
Normal file
File diff suppressed because it is too large
Load Diff
124
board/data_modul/imx8mp_edm_sbc/spl.c
Normal file
124
board/data_modul/imx8mp_edm_sbc/spl.c
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hang.h>
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
#include <spl.h>
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/device-internal.h>
|
||||
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
|
||||
#include "lpddr4_timing.h"
|
||||
|
||||
#include "../common/common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int data_modul_imx_edm_sbc_board_power_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = pmic_get("pmic@25", &dev);
|
||||
if (ret == -ENODEV) {
|
||||
puts("Failed to get PMIC\n");
|
||||
return 0;
|
||||
}
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output. */
|
||||
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
|
||||
if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
|
||||
/* Set DVS0 to 0.85V for special case. */
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
|
||||
else
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
|
||||
|
||||
/* Set DVS1 to 0.85v for suspend. */
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
|
||||
|
||||
/*
|
||||
* Enable DVS control through PMIC_STBY_REQ and
|
||||
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
|
||||
*/
|
||||
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
|
||||
|
||||
/* Kernel uses OD/OD frequency for SoC. */
|
||||
|
||||
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
|
||||
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
|
||||
|
||||
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
|
||||
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
|
||||
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
if (boot_dev_spl == SPI_NOR_BOOT) /* SPI NOR */
|
||||
return BOOT_DEVICE_SPI;
|
||||
|
||||
if (boot_dev_spl == MMC3_BOOT) /* eMMC */
|
||||
return BOOT_DEVICE_MMC2;
|
||||
|
||||
return BOOT_DEVICE_MMC1; /* SD */
|
||||
}
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
int boot_device = spl_boot_device();
|
||||
|
||||
spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC 8:SPI NOR */
|
||||
|
||||
if (boot_device == BOOT_DEVICE_SPI) { /* SPI, eMMC, SD */
|
||||
spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
|
||||
spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */
|
||||
} else if (boot_device == BOOT_DEVICE_MMC1) { /* SD, eMMC, SPI */
|
||||
spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
|
||||
spl_boot_list[2] = BOOT_DEVICE_SPI; /* SPI */
|
||||
} else { /* eMMC, SPI, SD */
|
||||
spl_boot_list[1] = BOOT_DEVICE_SPI; /* SPI */
|
||||
spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */
|
||||
}
|
||||
|
||||
spl_boot_list[3] = BOOT_DEVICE_UART; /* YModem */
|
||||
spl_boot_list[4] = BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
static struct dram_timing_info *dram_timing_info[8] = {
|
||||
&dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */
|
||||
NULL, /* 32 Gbit x16 */
|
||||
NULL, /* 16 Gbit x32 */
|
||||
NULL, /* 16 Gbit x16 */
|
||||
NULL, /* 8 Gbit x32 */
|
||||
NULL, /* 8 Gbit x16 */
|
||||
NULL, /* INVALID */
|
||||
NULL, /* INVALID */
|
||||
};
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info);
|
||||
}
|
||||
|
|
@ -13,6 +13,33 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include "lpddr4_timing.h"
|
||||
|
||||
struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = {
|
||||
{ 0x3d400000, 0xa1080020},
|
||||
{ 0x3d400200, 0x1f},
|
||||
{ 0x3d40021c, 0xf07}
|
||||
};
|
||||
|
||||
struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = {
|
||||
{ 0x54012, 0x110},
|
||||
{ 0x5402c, 0x1}
|
||||
};
|
||||
|
||||
struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = {
|
||||
{ 0x54012, 0x110},
|
||||
{ 0x5402c, 0x1}
|
||||
};
|
||||
|
||||
struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = {
|
||||
{ 0x54012, 0x110},
|
||||
{ 0x5402c, 0x1}
|
||||
};
|
||||
|
||||
struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = {
|
||||
{ 0x54012, 0x110},
|
||||
{ 0x5402c, 0x1}
|
||||
};
|
||||
|
||||
struct dram_cfg_param ddr_ddrc_cfg[] = {
|
||||
/** Initialize DDRC registers **/
|
||||
|
|
@ -21,9 +48,9 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d400000, 0xa3080020 },
|
||||
{ 0x3d400020, 0x1303 },
|
||||
{ 0x3d400024, 0x1e84800 },
|
||||
{ 0x3d400064, 0x7a0118 },
|
||||
{ 0x3d400070, 0x61027f10 },
|
||||
{ 0x3d400074, 0x7b0 },
|
||||
{ 0x3d400064, 0x7a017c },
|
||||
{ 0x3d400070, 0x7027f90 },
|
||||
{ 0x3d400074, 0x790 },
|
||||
{ 0x3d4000d0, 0xc00307a3 },
|
||||
{ 0x3d4000d4, 0xc50000 },
|
||||
{ 0x3d4000dc, 0xf4003f },
|
||||
|
|
@ -31,15 +58,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d4000e8, 0x660048 },
|
||||
{ 0x3d4000ec, 0x160048 },
|
||||
{ 0x3d400100, 0x2028222a },
|
||||
{ 0x3d400104, 0x807bf },
|
||||
{ 0x3d400104, 0x8083f },
|
||||
{ 0x3d40010c, 0xe0e000 },
|
||||
{ 0x3d400110, 0x12040a12 },
|
||||
{ 0x3d400114, 0x2050f0f },
|
||||
{ 0x3d400118, 0x1010009 },
|
||||
{ 0x3d40011c, 0x501 },
|
||||
{ 0x3d40011c, 0x502 },
|
||||
{ 0x3d400130, 0x20800 },
|
||||
{ 0x3d400134, 0xe100002 },
|
||||
{ 0x3d400138, 0x120 },
|
||||
{ 0x3d400138, 0x184 },
|
||||
{ 0x3d400144, 0xc80064 },
|
||||
{ 0x3d400180, 0x3e8001e },
|
||||
{ 0x3d400184, 0x3207a12 },
|
||||
|
|
@ -53,15 +80,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d4001b0, 0x11 },
|
||||
{ 0x3d4001c0, 0x1 },
|
||||
{ 0x3d4001c4, 0x1 },
|
||||
{ 0x3d4000f4, 0xc99 },
|
||||
{ 0x3d400108, 0x9121c1c },
|
||||
{ 0x3d400200, 0x18 },
|
||||
{ 0x3d4000f4, 0x799 },
|
||||
{ 0x3d400108, 0x9121b1c },
|
||||
{ 0x3d400200, 0x17 },
|
||||
{ 0x3d400208, 0x0 },
|
||||
{ 0x3d40020c, 0x0 },
|
||||
{ 0x3d400210, 0x1f1f },
|
||||
{ 0x3d400204, 0x80808 },
|
||||
{ 0x3d400214, 0x7070707 },
|
||||
{ 0x3d400218, 0x7070707 },
|
||||
{ 0x3d40021c, 0xf07 },
|
||||
{ 0x3d40021c, 0xf08 },
|
||||
{ 0x3d400250, 0x1705 },
|
||||
{ 0x3d400254, 0x2c },
|
||||
{ 0x3d40025c, 0x4000030 },
|
||||
|
|
@ -77,7 +105,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d402020, 0x1001 },
|
||||
{ 0x3d402024, 0x30d400 },
|
||||
{ 0x3d402050, 0x20d000 },
|
||||
{ 0x3d402064, 0xc001c },
|
||||
{ 0x3d402064, 0xc0026 },
|
||||
{ 0x3d4020dc, 0x840000 },
|
||||
{ 0x3d4020e0, 0x330000 },
|
||||
{ 0x3d4020e8, 0x660048 },
|
||||
|
|
@ -89,20 +117,20 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d402110, 0x2040202 },
|
||||
{ 0x3d402114, 0x2030202 },
|
||||
{ 0x3d402118, 0x1010004 },
|
||||
{ 0x3d40211c, 0x301 },
|
||||
{ 0x3d40211c, 0x302 },
|
||||
{ 0x3d402130, 0x20300 },
|
||||
{ 0x3d402134, 0xa100002 },
|
||||
{ 0x3d402138, 0x1d },
|
||||
{ 0x3d402138, 0x27 },
|
||||
{ 0x3d402144, 0x14000a },
|
||||
{ 0x3d402180, 0x640004 },
|
||||
{ 0x3d402190, 0x3818200 },
|
||||
{ 0x3d402194, 0x80303 },
|
||||
{ 0x3d4021b4, 0x100 },
|
||||
{ 0x3d4020f4, 0xc99 },
|
||||
{ 0x3d4020f4, 0x599 },
|
||||
{ 0x3d403020, 0x1001 },
|
||||
{ 0x3d403024, 0xc3500 },
|
||||
{ 0x3d403050, 0x20d000 },
|
||||
{ 0x3d403064, 0x30007 },
|
||||
{ 0x3d403064, 0x3000a },
|
||||
{ 0x3d4030dc, 0x840000 },
|
||||
{ 0x3d4030e0, 0x330000 },
|
||||
{ 0x3d4030e8, 0x660048 },
|
||||
|
|
@ -114,16 +142,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|||
{ 0x3d403110, 0x2040202 },
|
||||
{ 0x3d403114, 0x2030202 },
|
||||
{ 0x3d403118, 0x1010004 },
|
||||
{ 0x3d40311c, 0x301 },
|
||||
{ 0x3d40311c, 0x302 },
|
||||
{ 0x3d403130, 0x20300 },
|
||||
{ 0x3d403134, 0xa100002 },
|
||||
{ 0x3d403138, 0x8 },
|
||||
{ 0x3d403138, 0xa },
|
||||
{ 0x3d403144, 0x50003 },
|
||||
{ 0x3d403180, 0x190004 },
|
||||
{ 0x3d403190, 0x3818200 },
|
||||
{ 0x3d403194, 0x80303 },
|
||||
{ 0x3d4031b4, 0x100 },
|
||||
{ 0x3d4030f4, 0xc99 },
|
||||
{ 0x3d4030f4, 0x599 },
|
||||
{ 0x3d400028, 0x0 },
|
||||
};
|
||||
|
||||
|
|
@ -1700,15 +1728,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
|
|||
{ 0x400d7, 0x20b },
|
||||
{ 0x2003a, 0x2 },
|
||||
{ 0x200be, 0x3 },
|
||||
{ 0x2000b, 0x7d },
|
||||
{ 0x2000b, 0x465 },
|
||||
{ 0x2000c, 0xfa },
|
||||
{ 0x2000d, 0x9c4 },
|
||||
{ 0x2000e, 0x2c },
|
||||
{ 0x12000b, 0xc },
|
||||
{ 0x12000b, 0x70 },
|
||||
{ 0x12000c, 0x19 },
|
||||
{ 0x12000d, 0xfa },
|
||||
{ 0x12000e, 0x10 },
|
||||
{ 0x22000b, 0x3 },
|
||||
{ 0x22000b, 0x1c },
|
||||
{ 0x22000c, 0x6 },
|
||||
{ 0x22000d, 0x3e },
|
||||
{ 0x22000e, 0x10 },
|
||||
|
|
@ -1834,311 +1862,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct dram_cfg_param ddr_ddrc_cfg2[] = {
|
||||
/** Initialize DDRC registers **/
|
||||
{ 0x3d400304, 0x1 },
|
||||
{ 0x3d400030, 0x1 },
|
||||
{ 0x3d400000, 0xa1080020 },
|
||||
{ 0x3d400020, 0x1303 },
|
||||
{ 0x3d400024, 0x1e84800 },
|
||||
{ 0x3d400064, 0x7a0118 },
|
||||
{ 0x3d400070, 0x61027f10 },
|
||||
{ 0x3d400074, 0x7b0 },
|
||||
{ 0x3d4000d0, 0xc00307a3 },
|
||||
{ 0x3d4000d4, 0xc50000 },
|
||||
{ 0x3d4000dc, 0xf4003f },
|
||||
{ 0x3d4000e0, 0x330000 },
|
||||
{ 0x3d4000e8, 0x660048 },
|
||||
{ 0x3d4000ec, 0x160048 },
|
||||
{ 0x3d400100, 0x2028222a },
|
||||
{ 0x3d400104, 0x807bf },
|
||||
{ 0x3d40010c, 0xe0e000 },
|
||||
{ 0x3d400110, 0x12040a12 },
|
||||
{ 0x3d400114, 0x2050f0f },
|
||||
{ 0x3d400118, 0x1010009 },
|
||||
{ 0x3d40011c, 0x501 },
|
||||
{ 0x3d400130, 0x20800 },
|
||||
{ 0x3d400134, 0xe100002 },
|
||||
{ 0x3d400138, 0x120 },
|
||||
{ 0x3d400144, 0xc80064 },
|
||||
{ 0x3d400180, 0x3e8001e },
|
||||
{ 0x3d400184, 0x3207a12 },
|
||||
{ 0x3d400188, 0x0 },
|
||||
{ 0x3d400190, 0x49f820e },
|
||||
{ 0x3d400194, 0x80303 },
|
||||
{ 0x3d4001b4, 0x1f0e },
|
||||
{ 0x3d4001a0, 0xe0400018 },
|
||||
{ 0x3d4001a4, 0xdf00e4 },
|
||||
{ 0x3d4001a8, 0x80000000 },
|
||||
{ 0x3d4001b0, 0x11 },
|
||||
{ 0x3d4001c0, 0x1 },
|
||||
{ 0x3d4001c4, 0x1 },
|
||||
{ 0x3d4000f4, 0xc99 },
|
||||
{ 0x3d400108, 0x9121c1c },
|
||||
{ 0x3d400200, 0x1f },
|
||||
{ 0x3d40020c, 0x0 },
|
||||
{ 0x3d400210, 0x1f1f },
|
||||
{ 0x3d400204, 0x80808 },
|
||||
{ 0x3d400214, 0x7070707 },
|
||||
{ 0x3d400218, 0x7070707 },
|
||||
{ 0x3d40021c, 0xf07 },
|
||||
{ 0x3d400250, 0x1705 },
|
||||
{ 0x3d400254, 0x2c },
|
||||
{ 0x3d40025c, 0x4000030 },
|
||||
{ 0x3d400264, 0x900093e7 },
|
||||
{ 0x3d40026c, 0x2005574 },
|
||||
{ 0x3d400400, 0x111 },
|
||||
{ 0x3d400404, 0x72ff },
|
||||
{ 0x3d400408, 0x72ff },
|
||||
{ 0x3d400494, 0x2100e07 },
|
||||
{ 0x3d400498, 0x620096 },
|
||||
{ 0x3d40049c, 0x1100e07 },
|
||||
{ 0x3d4004a0, 0xc8012c },
|
||||
{ 0x3d402020, 0x1001 },
|
||||
{ 0x3d402024, 0x30d400 },
|
||||
{ 0x3d402050, 0x20d000 },
|
||||
{ 0x3d402064, 0xc001c },
|
||||
{ 0x3d4020dc, 0x840000 },
|
||||
{ 0x3d4020e0, 0x330000 },
|
||||
{ 0x3d4020e8, 0x660048 },
|
||||
{ 0x3d4020ec, 0x160048 },
|
||||
{ 0x3d402100, 0xa040305 },
|
||||
{ 0x3d402104, 0x30407 },
|
||||
{ 0x3d402108, 0x203060b },
|
||||
{ 0x3d40210c, 0x505000 },
|
||||
{ 0x3d402110, 0x2040202 },
|
||||
{ 0x3d402114, 0x2030202 },
|
||||
{ 0x3d402118, 0x1010004 },
|
||||
{ 0x3d40211c, 0x301 },
|
||||
{ 0x3d402130, 0x20300 },
|
||||
{ 0x3d402134, 0xa100002 },
|
||||
{ 0x3d402138, 0x1d },
|
||||
{ 0x3d402144, 0x14000a },
|
||||
{ 0x3d402180, 0x640004 },
|
||||
{ 0x3d402190, 0x3818200 },
|
||||
{ 0x3d402194, 0x80303 },
|
||||
{ 0x3d4021b4, 0x100 },
|
||||
{ 0x3d4020f4, 0xc99 },
|
||||
{ 0x3d403020, 0x1001 },
|
||||
{ 0x3d403024, 0xc3500 },
|
||||
{ 0x3d403050, 0x20d000 },
|
||||
{ 0x3d403064, 0x30007 },
|
||||
{ 0x3d4030dc, 0x840000 },
|
||||
{ 0x3d4030e0, 0x330000 },
|
||||
{ 0x3d4030e8, 0x660048 },
|
||||
{ 0x3d4030ec, 0x160048 },
|
||||
{ 0x3d403100, 0xa010102 },
|
||||
{ 0x3d403104, 0x30404 },
|
||||
{ 0x3d403108, 0x203060b },
|
||||
{ 0x3d40310c, 0x505000 },
|
||||
{ 0x3d403110, 0x2040202 },
|
||||
{ 0x3d403114, 0x2030202 },
|
||||
{ 0x3d403118, 0x1010004 },
|
||||
{ 0x3d40311c, 0x301 },
|
||||
{ 0x3d403130, 0x20300 },
|
||||
{ 0x3d403134, 0xa100002 },
|
||||
{ 0x3d403138, 0x8 },
|
||||
{ 0x3d403144, 0x50003 },
|
||||
{ 0x3d403180, 0x190004 },
|
||||
{ 0x3d403190, 0x3818200 },
|
||||
{ 0x3d403194, 0x80303 },
|
||||
{ 0x3d4031b4, 0x100 },
|
||||
{ 0x3d4030f4, 0xc99 },
|
||||
{ 0x3d400028, 0x0 },
|
||||
};
|
||||
|
||||
/* P0 message block parameter for training firmware */
|
||||
struct dram_cfg_param ddr_fsp0_cfg2[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54003, 0xfa0 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
{ 0x54008, 0x131f },
|
||||
{ 0x54009, 0xc8 },
|
||||
{ 0x5400b, 0x2 },
|
||||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x3ff4 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x3ff4 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0xf400 },
|
||||
{ 0x54033, 0x333f },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0xf400 },
|
||||
{ 0x54039, 0x333f },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
{ 0x5403d, 0x1600 },
|
||||
{ 0xd0000, 0x1 },
|
||||
};
|
||||
|
||||
/* P1 message block parameter for training firmware */
|
||||
struct dram_cfg_param ddr_fsp1_cfg2[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54002, 0x101 },
|
||||
{ 0x54003, 0x190 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
{ 0x54008, 0x121f },
|
||||
{ 0x54009, 0xc8 },
|
||||
{ 0x5400b, 0x2 },
|
||||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x84 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x84 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0x8400 },
|
||||
{ 0x54033, 0x3300 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0x8400 },
|
||||
{ 0x54039, 0x3300 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
{ 0x5403d, 0x1600 },
|
||||
{ 0xd0000, 0x1 },
|
||||
};
|
||||
|
||||
/* P2 message block parameter for training firmware */
|
||||
struct dram_cfg_param ddr_fsp2_cfg2[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54002, 0x102 },
|
||||
{ 0x54003, 0x64 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
{ 0x54008, 0x121f },
|
||||
{ 0x54009, 0xc8 },
|
||||
{ 0x5400b, 0x2 },
|
||||
{ 0x5400f, 0x100 },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x84 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x84 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0x8400 },
|
||||
{ 0x54033, 0x3300 },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0x8400 },
|
||||
{ 0x54039, 0x3300 },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
{ 0x5403d, 0x1600 },
|
||||
{ 0xd0000, 0x1 },
|
||||
};
|
||||
|
||||
/* P0 2D message block parameter for training firmware */
|
||||
struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
|
||||
{ 0xd0000, 0x0 },
|
||||
{ 0x54003, 0xfa0 },
|
||||
{ 0x54004, 0x2 },
|
||||
{ 0x54005, 0x2228 },
|
||||
{ 0x54006, 0x14 },
|
||||
{ 0x54008, 0x61 },
|
||||
{ 0x54009, 0xc8 },
|
||||
{ 0x5400b, 0x2 },
|
||||
{ 0x5400d, 0x100 },
|
||||
{ 0x5400f, 0x100 },
|
||||
{ 0x54010, 0x1f7f },
|
||||
{ 0x54012, 0x110 },
|
||||
{ 0x54019, 0x3ff4 },
|
||||
{ 0x5401a, 0x33 },
|
||||
{ 0x5401b, 0x4866 },
|
||||
{ 0x5401c, 0x4800 },
|
||||
{ 0x5401e, 0x16 },
|
||||
{ 0x5401f, 0x3ff4 },
|
||||
{ 0x54020, 0x33 },
|
||||
{ 0x54021, 0x4866 },
|
||||
{ 0x54022, 0x4800 },
|
||||
{ 0x54024, 0x16 },
|
||||
{ 0x5402b, 0x1000 },
|
||||
{ 0x5402c, 0x1 },
|
||||
{ 0x54032, 0xf400 },
|
||||
{ 0x54033, 0x333f },
|
||||
{ 0x54034, 0x6600 },
|
||||
{ 0x54035, 0x48 },
|
||||
{ 0x54036, 0x48 },
|
||||
{ 0x54037, 0x1600 },
|
||||
{ 0x54038, 0xf400 },
|
||||
{ 0x54039, 0x333f },
|
||||
{ 0x5403a, 0x6600 },
|
||||
{ 0x5403b, 0x48 },
|
||||
{ 0x5403c, 0x48 },
|
||||
{ 0x5403d, 0x1600 },
|
||||
{ 0xd0000, 0x1 },
|
||||
};
|
||||
|
||||
struct dram_fsp_msg ddr_dram_fsp_msg2[] = {
|
||||
{
|
||||
/* P0 4000mts 1D */
|
||||
.drate = 4000,
|
||||
.fw_type = FW_1D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp0_cfg2,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2),
|
||||
},
|
||||
{
|
||||
/* P1 400mts 1D */
|
||||
.drate = 400,
|
||||
.fw_type = FW_1D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp1_cfg2,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2),
|
||||
},
|
||||
{
|
||||
/* P2 100mts 1D */
|
||||
.drate = 100,
|
||||
.fw_type = FW_1D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp2_cfg2,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2),
|
||||
},
|
||||
{
|
||||
/* P0 4000mts 2D */
|
||||
.drate = 4000,
|
||||
.fw_type = FW_2D_IMAGE,
|
||||
.fsp_cfg = ddr_fsp0_2d_cfg2,
|
||||
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2),
|
||||
},
|
||||
};
|
||||
|
||||
/* quad die, dual rank aka 8 GB DDR timing config params */
|
||||
/* ddr timing config params */
|
||||
struct dram_timing_info dram_timing = {
|
||||
.ddrc_cfg = ddr_ddrc_cfg,
|
||||
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
|
||||
|
|
@ -2153,17 +1877,36 @@ struct dram_timing_info dram_timing = {
|
|||
.fsp_table = { 4000, 400, 100, },
|
||||
};
|
||||
|
||||
/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */
|
||||
struct dram_timing_info dram_timing2 = {
|
||||
.ddrc_cfg = ddr_ddrc_cfg2,
|
||||
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2),
|
||||
.ddrphy_cfg = ddr_ddrphy_cfg,
|
||||
.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
|
||||
.fsp_msg = ddr_dram_fsp_msg2,
|
||||
.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2),
|
||||
.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
|
||||
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
||||
.ddrphy_pie = ddr_phy_pie,
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 4000, 400, 100, },
|
||||
};
|
||||
static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz,
|
||||
struct dram_cfg_param *patch, int patch_sz)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < cfg_sz; i++)
|
||||
for (j = 0; j < patch_sz; j++)
|
||||
if (cfg[i].reg == patch[j].reg)
|
||||
cfg[i].val = patch[j].val;
|
||||
}
|
||||
|
||||
void lpddr4_single_rank_training_patch(void)
|
||||
{
|
||||
apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg),
|
||||
ddr_ddrc_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch));
|
||||
|
||||
apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg),
|
||||
ddr_fsp0_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch));
|
||||
|
||||
apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg),
|
||||
ddr_fsp1_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch));
|
||||
|
||||
apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg),
|
||||
ddr_fsp2_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch));
|
||||
|
||||
apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
||||
ddr_fsp0_2d_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch));
|
||||
}
|
||||
|
|
|
|||
11
board/toradex/verdin-imx8mp/lpddr4_timing.h
Normal file
11
board/toradex/verdin-imx8mp/lpddr4_timing.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
#ifndef __LPDDR4_TIMING_H__
|
||||
#define __LPDDR4_TIMING_H__
|
||||
|
||||
void lpddr4_single_rank_training_patch(void);
|
||||
|
||||
#endif /* __LPDDR4_TIMING_H__ */
|
||||
|
|
@ -21,8 +21,7 @@
|
|||
#include <dm/uclass.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
|
||||
extern struct dram_timing_info dram_timing2;
|
||||
#include "lpddr4_timing.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -34,13 +33,19 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
|
|||
void spl_dram_init(void)
|
||||
{
|
||||
/*
|
||||
* try configuring for quad die, dual rank aka 8 GB falling back to
|
||||
* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails
|
||||
* Try configuring for dual rank memory falling back to single rank
|
||||
*/
|
||||
if (ddr_init(&dram_timing)) {
|
||||
printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n");
|
||||
ddr_init(&dram_timing2);
|
||||
if (!ddr_init(&dram_timing)) {
|
||||
puts("DDR configured as dual rank\n");
|
||||
return;
|
||||
}
|
||||
|
||||
lpddr4_single_rank_training_patch();
|
||||
if (!ddr_init(&dram_timing)) {
|
||||
puts("DDR configured as single rank\n");
|
||||
return;
|
||||
}
|
||||
puts("DDR configuration failed\n");
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ CONFIG_SPL_SPI=y
|
|||
CONFIG_AHCI=y
|
||||
CONFIG_SYS_MEMTEST_START=0x10000000
|
||||
CONFIG_SYS_MEMTEST_END=0x20000000
|
||||
CONFIG_LTO=y
|
||||
CONFIG_SYS_MONITOR_LEN=409600
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -39,6 +40,10 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
|
|||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
CONFIG_SYS_PBSIZE=532
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
|
|
@ -113,6 +118,7 @@ CONFIG_USB_GADGET_MANUFACTURER="dh"
|
|||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_SDP_LOADADDR=0x17ffffc0
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
|
|
|||
182
configs/imx8mp_beacon_defconfig
Normal file
182
configs/imx8mp_beacon_defconfig
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARM_SMCCC=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xFFFFDE00
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit"
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y
|
||||
CONFIG_TARGET_IMX8MP_BEACON=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK=0x960000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
|
||||
CONFIG_ARMV8_MULTIENTRY=y
|
||||
CONFIG_ARMV8_SET_SMPEN=y
|
||||
# CONFIG_PSCI_RESET is not set
|
||||
CONFIG_ARMV8_PSCI=y
|
||||
CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
|
||||
CONFIG_ARMV8_PSCI_RELOCATE=y
|
||||
CONFIG_ARMV8_SECURE_BASE=0x970000
|
||||
CONFIG_ARMV8_EA_EL3_FIRST=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb"
|
||||
# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x98fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_TPM=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_SOURCE_FILE="imx8mp_beacon"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="eth1"
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_UUU_SUPPORT=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
|
||||
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PHY_IMX8MQ_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_PCA9450=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_DM_RNG is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_NXP_FSPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_TMU=y
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_MX7 is not set
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
|
||||
CONFIG_SDP_LOADADDR=0x0
|
||||
CONFIG_USB_FUNCTION_ACM=y
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
# CONFIG_WATCHDOG_AUTOSTART is not set
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_TPM=y
|
||||
# CONFIG_SPL_SHA512 is not set
|
||||
# CONFIG_SPL_SHA384 is not set
|
||||
267
configs/imx8mp_data_modul_edm_sbc_defconfig
Normal file
267
configs/imx8mp_data_modul_edm_sbc_defconfig
Normal file
|
|
@ -0,0 +1,267 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x1000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x18000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_OFFSET=0xFFFC0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
|
||||
CONFIG_DEBUG_UART_BASE=0x30880000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x50000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_LTO=y
|
||||
CONFIG_ENV_VARS_UBOOT_CONFIG=y
|
||||
CONFIG_SYS_MONITOR_LEN=1048576
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_MAX_SIZE=0x25000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x96fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0x96fc00
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2081
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_SYS_BOOTM_LEN=0x8000000
|
||||
CONFIG_CMD_ASKENV=y
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
CONFIG_CMD_ERASEENV=y
|
||||
CONFIG_CRC32_VERIFY=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
|
||||
CONFIG_SYS_EEPROM_SIZE=16384
|
||||
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
|
||||
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
|
||||
CONFIG_CMD_MD5SUM=y
|
||||
CONFIG_MD5SUM_VERIFY=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_SHA1SUM=y
|
||||
CONFIG_SHA1SUM_VERIFY=y
|
||||
CONFIG_CMD_BIND=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_GPT_RENAME=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_LSBLK=y
|
||||
CONFIG_CMD_MBR=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_BKOPS_ENABLE=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_PXE=y
|
||||
CONFIG_CMD_BOOTCOUNT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_CMD_SYSBOOT=y
|
||||
CONFIG_CMD_UUID=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_HASH_VERIFY=y
|
||||
CONFIG_CMD_BTRFS=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_CMD_FS_UUID=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
|
||||
CONFIG_MMC_SPEED_MODE_SET=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_PART=1
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_IP_DEFRAG=y
|
||||
CONFIG_TFTP_TSIZE=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
|
||||
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_SPL_CLK_IMX8MP=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_TIMEOUT=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_MTD=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_SPL_GPIO_HOG=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_USB_HUB_USB251XB=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_SPL_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=50000000
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PHY_IMX8MQ_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_PCA9450=y
|
||||
CONFIG_SPL_DM_REGULATOR_PCA9450=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_M41T62=y
|
||||
CONFIG_CONS_INDEX=3
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_TMU=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_SDP_LOADADDR=0x0
|
||||
CONFIG_USB_FUNCTION_ACM=y
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
|
|
@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
|
|
@ -61,4 +64,6 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
|
|
|
|||
|
|
@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
|
|
@ -65,4 +68,6 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
|
|
|
|||
|
|
@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
|
|
@ -61,4 +64,6 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
|
|
|
|||
|
|
@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
|
|
@ -65,4 +68,6 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
|
|
|
|||
|
|
@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
|
|
@ -61,4 +64,6 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
|
|
|
|||
|
|
@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
|
|
@ -65,4 +68,6 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
|
|
|
|||
52
doc/board/beacon/beacon-imx8mp.rst
Normal file
52
doc/board/beacon/beacon-imx8mp.rst
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
U-Boot for the Beacon EmbeddedWorks i.MX8M Plus Devkit
|
||||
======================================================
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Build the ARM Trusted firmware binary
|
||||
- Get DDR firmware
|
||||
- Build U-Boot
|
||||
- Burn U-Noot to microSD Card
|
||||
- Boot
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
--------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6
|
||||
$ make PLAT=imx8mp bl31 CROSS_COMPILE=aarch64-linux-gnu-
|
||||
$ cp build/imx8mn/release/bl31.bin ../
|
||||
|
||||
Get the DDR firmware
|
||||
--------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin
|
||||
$ chmod +x firmware-imx-8.15.bin
|
||||
$ ./firmware-imx-8.15
|
||||
$ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin .
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ make imx8mp_beacon_defconfig
|
||||
$ make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
Burn U-Boot to microSD Card
|
||||
---------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
|
||||
|
||||
Boot
|
||||
----
|
||||
Set baseboard DIP switch:
|
||||
S17: 1100XXXX
|
||||
9
doc/board/beacon/index.rst
Normal file
9
doc/board/beacon/index.rst
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Beacon
|
||||
======
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
beacon-imx8mp
|
||||
|
|
@ -14,6 +14,7 @@ Board-specific doc
|
|||
apple/index
|
||||
armltd/index
|
||||
atmel/index
|
||||
beacon/index
|
||||
broadcom/index
|
||||
bsh/index
|
||||
cloos/index
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@
|
|||
#define CFG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* USB Configs */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CFG_MXC_USB_FLAGS 0
|
||||
|
||||
|
|
@ -39,7 +38,6 @@
|
|||
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
|
||||
#define DFU_DEFAULT_POLL_TIMEOUT 300
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"console=ttymxc0,115200\0" \
|
||||
|
|
|
|||
29
include/configs/imx8mp_beacon.h
Normal file
29
include/configs/imx8mp_beacon.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MP_BEACON_H
|
||||
#define __IMX8MP_BEACON_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
#endif
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
/* Totally 6GB DDR */
|
||||
#define CFG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
|
||||
#define PHYS_SDRAM_2 0x100000000
|
||||
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
|
||||
|
||||
#endif
|
||||
45
include/configs/imx8mp_data_modul_edm_sbc.h
Normal file
45
include/configs/imx8mp_data_modul_edm_sbc.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MP_DATA_MODUL_EDM_SBC_H
|
||||
#define __IMX8MP_DATA_MODUL_EDM_SBC_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* Link Definitions */
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x200000
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
|
||||
|
||||
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
|
||||
|
||||
/* PHY needs a longer autonegotiation timeout after reset */
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
|
||||
"bootlimit=3\0" \
|
||||
"devtype=mmc\0" \
|
||||
"devpart=1\0" \
|
||||
/* Give slow devices beyond USB HUB chance to come up. */ \
|
||||
"usb_pgood_delay=2000\0" \
|
||||
"dmo_update_env=" \
|
||||
"setenv dmo_update_env true ; saveenv ; saveenv\0" \
|
||||
"dmo_update_sf_write_data=" \
|
||||
"sf probe && sf update ${loadaddr} 0 ${filesize}\0" \
|
||||
"dmo_update_emmc_to_sf=" \
|
||||
"load mmc 0:1 ${loadaddr} boot/flash.bin && " \
|
||||
"run dmo_update_sf_write_data\0" \
|
||||
"dmo_update_sd_to_sf=" \
|
||||
"load mmc 1:1 ${loadaddr} boot/flash.bin && " \
|
||||
"run dmo_update_sf_write_data\0"
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user