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arm: dts: msm: add GENI SE QUP device tree node

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On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.

The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
This commit is contained in:
Vladimir Zapolskiy 2023-04-21 20:50:41 +03:00 committed by Tom Rini
parent 10ea2a7a93
commit 0e889a7c1b
3 changed files with 17 additions and 12 deletions
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2
arch/arm/dts/dragonboard845c.dts
View File

@ -21,7 +21,7 @@
};
aliases {
serial0 = &debug_uart;
serial0 = &uart9;
};
memory {

25
arch/arm/dts/sdm845.dtsi
View File

@ -51,16 +51,21 @@
};
};
debug_uart: serial@a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9>;
qcom,wrapper-core = <0x8a>;
status = "disabled";
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x00ac0000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
uart9: serial@a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0xa84000 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9>;
};
};
spmi@c440000 {

2
arch/arm/dts/starqltechn.dts
View File

@ -21,7 +21,7 @@
};
aliases {
serial0 = &debug_uart;
serial0 = &uart9;
};
memory {