clk: exynos: Add CMU_CORE and CMU_HSI for Exynos850
CMU_CORE generates clocks needed for eMMC enablement, and CMU_HSI provides clocks for SD card and USB. Most of the code is copied from the Linux kernel counterpart driver. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Sam Protsenko
Minkyu Kang
parent
f77780b0ee
commit
1751ba9a3b
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@ -13,6 +13,8 @@
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enum exynos850_cmu_id {
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CMU_TOP,
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CMU_PERI,
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CMU_CORE,
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CMU_HSI,
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};
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/* ---- CMU_TOP ------------------------------------------------------------- */
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@ -24,9 +26,23 @@ enum exynos850_cmu_id {
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#define PLL_CON3_PLL_SHARED0 0x014c
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#define PLL_CON0_PLL_SHARED1 0x0180
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#define PLL_CON3_PLL_SHARED1 0x018c
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
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#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
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#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
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#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
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#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
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#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
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#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
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#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
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#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
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#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
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#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
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#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
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#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
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#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
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#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
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#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
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#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
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@ -36,6 +52,13 @@ enum exynos850_cmu_id {
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#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
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#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
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#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
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#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
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#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
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#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
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#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
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#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
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#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
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@ -44,6 +67,25 @@ enum exynos850_cmu_id {
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PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
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PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
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PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
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/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
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PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
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"dout_shared1_div3", "dout_shared0_div4" };
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PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
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"dout_shared0_div3", "dout_shared1_div3" };
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PNAME(mout_core_mmc_embd_p) = { "clock-oscclk", "dout_shared0_div2",
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"dout_shared1_div2", "dout_shared0_div3",
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"dout_shared1_div3", "mout_mmc_pll",
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"clock-oscclk", "clock-oscclk" };
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PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
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"dout_shared0_div4", "dout_shared1_div4" };
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/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
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PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
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PNAME(mout_hsi_mmc_card_p) = { "clock-oscclk", "dout_shared0_div2",
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"dout_shared1_div2", "dout_shared0_div3",
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"dout_shared1_div3", "mout_mmc_pll",
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"clock-oscclk", "clock-oscclk" };
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PNAME(mout_hsi_usb20drd_p) = { "clock-oscclk", "dout_shared0_div4",
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"dout_shared1_div4", "clock-oscclk" };
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/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
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PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
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PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4",
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@ -86,6 +128,70 @@ static const struct samsung_div_clock top_pure_div_clks[] = {
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CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
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};
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/* CORE */
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static const struct samsung_mux_clock top_core_mux_clks[] = {
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MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
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CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
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MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
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CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
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MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
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CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
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MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
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CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
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};
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static const struct samsung_gate_clock top_core_gate_clks[] = {
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GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
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CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
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GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
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CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
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GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
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CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
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GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
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CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
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};
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static const struct samsung_div_clock top_core_div_clks[] = {
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DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
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CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
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DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
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CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
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DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
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CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
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DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
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CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
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};
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/* HSI */
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static const struct samsung_mux_clock top_hsi_mux_clks[] = {
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MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
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CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
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MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
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CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
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MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
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CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
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};
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static const struct samsung_gate_clock top_hsi_gate_clks[] = {
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GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
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CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
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GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
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CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
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GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
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CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
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};
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static const struct samsung_div_clock top_hsi_div_clks[] = {
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DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
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CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
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DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
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CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
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DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
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CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
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};
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/* PERI */
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static const struct samsung_mux_clock top_peri_mux_clks[] = {
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@ -121,6 +227,16 @@ static const struct samsung_clk_group top_cmu_clks[] = {
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{ S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) },
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{ S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) },
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/* CMU_TOP clocks for CMU_CORE */
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{ S_CLK_MUX, top_core_mux_clks, ARRAY_SIZE(top_core_mux_clks) },
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{ S_CLK_GATE, top_core_gate_clks, ARRAY_SIZE(top_core_gate_clks) },
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{ S_CLK_DIV, top_core_div_clks, ARRAY_SIZE(top_core_div_clks) },
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/* CMU_TOP clocks for CMU_HSI */
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{ S_CLK_MUX, top_hsi_mux_clks, ARRAY_SIZE(top_hsi_mux_clks) },
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{ S_CLK_GATE, top_hsi_gate_clks, ARRAY_SIZE(top_hsi_gate_clks) },
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{ S_CLK_DIV, top_hsi_div_clks, ARRAY_SIZE(top_hsi_div_clks) },
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/* CMU_TOP clocks for CMU_PERI */
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{ S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) },
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{ S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) },
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@ -201,3 +317,139 @@ U_BOOT_DRIVER(exynos850_cmu_peri) = {
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.probe = exynos850_cmu_peri_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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/* ---- CMU_CORE ------------------------------------------------------------ */
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/* Register Offset definitions for CMU_CORE (0x12000000) */
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#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
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#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
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#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
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#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
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/* List of parent clocks for Muxes in CMU_CORE */
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PNAME(mout_core_bus_user_p) = { "clock-oscclk", "dout_core_bus" };
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PNAME(mout_core_mmc_embd_user_p) = { "clock-oscclk",
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"dout_core_mmc_embd" };
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static const struct samsung_mux_clock core_mux_clks[] = {
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MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
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PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
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MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
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mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
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4, 1, CLK_SET_RATE_PARENT, 0),
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};
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static const struct samsung_div_clock core_div_clks[] = {
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DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
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CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
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};
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static const struct samsung_gate_clock core_gate_clks[] = {
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GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
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CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
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GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
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"mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
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21, CLK_SET_RATE_PARENT, 0),
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};
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static const struct samsung_clk_group core_cmu_clks[] = {
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{ S_CLK_MUX, core_mux_clks, ARRAY_SIZE(core_mux_clks) },
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{ S_CLK_DIV, core_div_clks, ARRAY_SIZE(core_div_clks) },
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{ S_CLK_GATE, core_gate_clks, ARRAY_SIZE(core_gate_clks) },
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};
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static int exynos850_cmu_core_probe(struct udevice *dev)
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{
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return samsung_register_cmu(dev, CMU_CORE, core_cmu_clks,
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exynos850_cmu_top);
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}
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static const struct udevice_id exynos850_cmu_core_ids[] = {
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{ .compatible = "samsung,exynos850-cmu-core" },
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{ }
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};
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SAMSUNG_CLK_OPS(exynos850_cmu_core, CMU_CORE);
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U_BOOT_DRIVER(exynos850_cmu_core) = {
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.name = "exynos850-cmu-core",
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.id = UCLASS_CLK,
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.of_match = exynos850_cmu_core_ids,
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.ops = &exynos850_cmu_core_clk_ops,
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.probe = exynos850_cmu_core_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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/* ---- CMU_HSI ------------------------------------------------------------- */
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/* Register Offset definitions for CMU_HSI (0x13400000) */
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#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
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#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
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#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
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#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
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#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
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#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
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#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
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#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
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/* List of parent clocks for Muxes in CMU_HSI */
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PNAME(mout_hsi_bus_user_p) = { "clock-oscclk", "dout_hsi_bus" };
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PNAME(mout_hsi_mmc_card_user_p) = { "clock-oscclk", "dout_hsi_mmc_card" };
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PNAME(mout_hsi_usb20drd_user_p) = { "clock-oscclk", "dout_hsi_usb20drd" };
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static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
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MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
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PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
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MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
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mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
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4, 1, CLK_SET_RATE_PARENT, 0),
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MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
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mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
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4, 1),
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};
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static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
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GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
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CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
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GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "clock-oscclk",
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CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
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GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
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CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
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GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
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"mout_hsi_mmc_card_user",
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CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
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CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
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GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
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"mout_hsi_bus_user",
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CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
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};
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static const struct samsung_clk_group hsi_cmu_clks[] = {
|
||||
{ S_CLK_MUX, hsi_mux_clks, ARRAY_SIZE(hsi_mux_clks) },
|
||||
{ S_CLK_GATE, hsi_gate_clks, ARRAY_SIZE(hsi_gate_clks) },
|
||||
};
|
||||
|
||||
static int exynos850_cmu_hsi_probe(struct udevice *dev)
|
||||
{
|
||||
return samsung_register_cmu(dev, CMU_HSI, hsi_cmu_clks,
|
||||
exynos850_cmu_hsi);
|
||||
}
|
||||
|
||||
static const struct udevice_id exynos850_cmu_hsi_ids[] = {
|
||||
{ .compatible = "samsung,exynos850-cmu-hsi" },
|
||||
{ }
|
||||
};
|
||||
|
||||
SAMSUNG_CLK_OPS(exynos850_cmu_hsi, CMU_HSI);
|
||||
|
||||
U_BOOT_DRIVER(exynos850_cmu_hsi) = {
|
||||
.name = "exynos850-cmu-hsi",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = exynos850_cmu_hsi_ids,
|
||||
.ops = &exynos850_cmu_hsi_clk_ops,
|
||||
.probe = exynos850_cmu_hsi_probe,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user