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arm64: zynqmp: Fix Siva's email address format

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Some patches didn't have his full name and also there was one more ">" at
the end of email address. That's why correct both of these issues.

Fixes: 174d728471 ("arm64: zynqmp: Switch to amd.com emails")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e970cc0dfabe293c2baf6b231d34f3af0386f1eb.1695378830.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-09-22 12:35:35 +02:00
parent 1b273a960a
commit 2036621a61
16 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/versal-mini-emmc0.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/versal-mini-emmc1.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/versal-mini-ospi.dtsi
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/versal-mini-qspi.dtsi
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/versal-mini.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2019, Xilinx, Inc.
*
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-mini-emmc0.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-mini-emmc1.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-mini-nand.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/zynqmp-mini-qspi.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/zynqmp-zc1254-revA.dts
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@ -5,7 +5,7 @@
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
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@ -4,7 +4,7 @@
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/

2
arch/arm/dts/zynqmp-zcu1275-revA.dts
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@ -5,7 +5,7 @@
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-zcu1275-revB.dts
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@ -5,7 +5,7 @@
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/dts/zynqmp-zcu1285-revA.dts
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@ -5,7 +5,7 @@
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;

2
arch/arm/mach-versal/mp.c
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@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2019 Xilinx, Inc.
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
#include <common.h>

2
drivers/fpga/zynqmppl.c
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@ -2,7 +2,7 @@
/*
* (C) Copyright 2015 - 2016, Xilinx, Inc,
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
#include <console.h>