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pci: Drop pci_init_board()

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With the conversion to driver model, this is not needed now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2021-08-01 18:54:39 -06:00 committed by Tom Rini
parent e15ba68029
commit 23cd8a63a0
6 changed files with 0 additions and 243 deletions
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7
board/cavium/thunderx/thunderx.c
View File

@ -123,10 +123,3 @@ int board_eth_init(struct bd_info *bis)
return rc;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
printf("DEBUG: PCI Init TODO *****\n");
}
#endif

73
board/freescale/mpc8349emds/pci.c
View File

@ -115,77 +115,4 @@ void pib_init(void)
i2c_set_bus_num(orig_i2c_bus);
}
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
#ifndef CONFIG_MPC83XX_PCI2
struct pci_region *reg[] = { pci1_regions };
#else
struct pci_region *reg[] = { pci1_regions, pci2_regions };
#endif
/* initialize the PCA9555PW IO expander on the PIB board */
pib_init();
/* Enable all 8 PCI_CLK_OUTPUTS */
clk->occr = 0xff000000;
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg);
#endif
}
#else
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
struct pci_region *reg[] = { pci1_regions };
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
mpc83xx_pci_init(1, reg);
/* Configure PCI Inbound Translation Windows (3 1MB windows) */
pci_ctrl->pitar0 = 0x0;
pci_ctrl->pibar0 = 0x0;
pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
pci_ctrl->pitar1 = 0x0;
pci_ctrl->pibar1 = 0x0;
pci_ctrl->piebar1 = 0x0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
pci_ctrl->pitar2 = 0x0;
pci_ctrl->pibar2 = 0x0;
pci_ctrl->piebar2 = 0x0;
pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
/* Unlock the configuration bit */
mpc83xx_pcislave_unlock(0);
printf("PCI: Agent mode enabled\n");
}
#endif /* CONFIG_PCISLAVE */

1
board/freescale/mpc837xerdb/Makefile
View File

@ -4,4 +4,3 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += mpc837xerdb.o
obj-$(CONFIG_PCI) += pci.o

109
board/freescale/mpc837xerdb/pci.c
View File

@ -1,109 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <mpc83xx.h>
#include <pci.h>
#include <asm/io.h>
#include <linux/delay.h>
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI_MEM_BASE,
phys_start: CONFIG_SYS_PCI_MEM_PHYS,
size: CONFIG_SYS_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI_MMIO_BASE,
phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
size: CONFIG_SYS_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CONFIG_SYS_PCI_IO_BASE,
phys_start: CONFIG_SYS_PCI_IO_PHYS,
size: CONFIG_SYS_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
u32 spridr = in_be32(&immr->sysconf.spridr);
/* Enable all 5 PCI_CLK_OUTPUTS */
clk->occr |= 0xf8000000;
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg);
/* There is no PEX in MPC8379 parts. */
if (PARTID_NO_E(spridr) == SPR_8379)
return;
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg);
}

50
board/xes/common/fsl_8xxx_pci.c
View File

@ -14,56 +14,6 @@
#include <linux/libfdt.h>
#include <fdt_support.h>
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif
void pci_init_board(void)
{
int first_free_busno = 0;
#ifdef CONFIG_PCI1
int pcie_ep;
struct fsl_pci_info pci_info;
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info, 1);
set_next_law(pci_info.mem_phys,
law_size_bits(pci_info.mem_size), pci_info.law);
set_next_law(pci_info.io_phys,
law_size_bits(pci_info.io_size), pci_info.law);
pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
pci_32 ? 32 : 64,
pcix ? "PCIX" : "PCI",
pci_spd_norm ? ">=" : "<=",
pcix ? freq * 2 : freq,
pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
} else {
printf("PCI1: disabled\n");
}
#elif defined CONFIG_ARCH_MPC8548
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* PCI1 not present on MPC8572 */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
#endif
fsl_pcie_init_board(first_free_busno);
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_pci_setup(void *blob, struct bd_info *bd)
{

3
include/init.h
View File

@ -297,9 +297,6 @@ int board_late_init(void);
int board_postclk_init(void); /* after clocks/timebase, before env/serial */
int board_early_init_r(void);
/* TODO(sjg@chromium.org): Drop this when DM_PCI migration is completed */
void pci_init_board(void);
/**
* arch_initr_trap() - Init traps
*