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arm64: dts: imx8mp: Add DT overlay describing i.MX8MP DHCOM SoM rev.100

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The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM,
add DT overlay which reinstates rev.100 SoM description to permit
prototype rev.100 SoMs to be used until they get phased out.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2023-09-21 20:44:20 +02:00 committed by Stefano Babic
parent 68e0d92d33
commit 24985686fe
5 changed files with 152 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/Makefile
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@ -1064,11 +1064,13 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-phanbell.dtb \
imx8mp-beacon-kit.dtb \
imx8mp-data-modul-edm-sbc.dtb \
imx8mp-dhcom-som-overlay-rev100.dtbo \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \

10
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts Normal file
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@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
/plugin/;
&ethphy0g {
reg = <7>;
};

120
arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts Normal file
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@ -0,0 +1,120 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mp-pinfunc.h"
&brcmf {
reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
&eeprom0 { /* EEPROM with EQoS MAC address */
compatible = "atmel,24c02";
pagesize = <16>;
};
&eeprom1 { /* EEPROM with FEC MAC address */
compatible = "atmel,24c02";
pagesize = <16>;
};
&ethphy0f { /* SMSC LAN8740Ai */
pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
&ethphy0g { /* Micrel KSZ9131RNXI */
pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
&i2c3 {
adc@48 {
compatible = "ti,tla2024";
interrupts-extended;
};
};
&ioexp {
status = "disabled";
};
&reg_eth_vio {
gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_enet_vio>;
pinctrl-names = "default";
};
&rv3032 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
};
&uart2 {
bluetooth {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
};
&usb_dwc3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_vbus>;
};
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>;
};
&iomuxc {
pinctrl-0 = <&pinctrl_hog_base
&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
/* GPIO_M is connected to CLKOUT2 */
&pinctrl_dhcom_int>;
pinctrl_enet_vio: dhcom-enet-vio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
>;
};
pinctrl_rtc: dhcom-rtc-grp {
fsl,pins = <
/* RTC_#INT Interrupt */
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
>;
};
pinctrl_uart2_bt: dhcom-uart2-bt-grp {
fsl,pins = <
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
>;
};
pinctrl_usb0_vbus: dhcom-usb0-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
>;
};
pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp {
fsl,pins = <
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
};
};

8
arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
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@ -178,13 +178,13 @@
};
};
fdt-dto-imx8mp-dhcom-pdk-overlay-rev100 {
description = "imx8mp-dhcom-pdk-overlay-rev100";
fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
description = "imx8mp-dhcom-pdk3-overlay-rev100";
type = "flat_dt";
compression = "none";
blob-ext {
filename = "imx8mp-dhcom-pdk-overlay-rev100.dtbo";
filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
};
};
};
@ -198,7 +198,7 @@
"fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
"fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
"fdt-dto-imx8mp-dhcom-som-overlay-rev100",
"fdt-dto-imx8mp-dhcom-pdk-overlay-rev100";
"fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
};
};
};

16
board/dhelectronics/dh_imx8mp/spl.c
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@ -44,6 +44,7 @@ static const iomux_v3_cfg_t wdog_pads[] = {
};
static bool dh_gigabit_eqos, dh_gigabit_fec;
static u8 dh_som_rev;
static void dh_imx8mp_early_init_f(void)
{
@ -166,6 +167,15 @@ int board_spl_fit_append_fdt_skip(const char *name)
}
}
if (dh_som_rev == 0x0) { /* Prototype SoM rev.100 */
if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-rev100"))
return 0;
if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100") &&
of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
return 0;
}
return 1; /* Skip this DTO */
}
@ -175,6 +185,9 @@ static void dh_imx8mp_board_cache_config(void)
const u32 mux_sion[] = {
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24),
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10),
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_NAND_DQS__GPIO3_IO14),
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXD7__GPIO4_IO19),
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI5_MCLK__GPIO3_IO25),
};
int i;
@ -183,6 +196,9 @@ static void dh_imx8mp_board_cache_config(void)
dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24));
dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10));
dh_som_rev = !!(readl(GPIO3_BASE_ADDR) & BIT(14));
dh_som_rev |= !!(readl(GPIO4_BASE_ADDR) & BIT(19)) << 1;
dh_som_rev |= !!(readl(GPIO3_BASE_ADDR) & BIT(25)) << 2;
for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);