Initial pinctrl macro support and additional UARTs.
Signed-off-by: Yilin Sun <imi415@imi.moe>
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@ -11,6 +11,7 @@
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compatible = "milk-v,duo", "cvitek,cv1800b";
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aliases {
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i2c0 = &i2c0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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@ -28,3 +29,7 @@
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&uart0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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@ -74,6 +74,11 @@
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
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};
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pinctrl: pinctrl@03000000 {
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compatible = "cvitek,cv1800b-pinctrl";
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reg = <0x0 0x03000000 0x0 0x00001000>;
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};
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uart0: serial@04140000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04140000 0x0 0x1000>;
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@ -93,5 +98,43 @@
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@04160000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04160000 0x0 0x1000>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@04170000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04170000 0x0 0x1000>;
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interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart4: serial@041C0000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x041C0000 0x0 0x1000>;
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interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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i2c0: i2c@04000000 {
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compatible = "cvitek,cv1800b-i2c", "snps,designware-i2c";
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reg = <0x0 0x04000000 0x0 0x1000>;
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interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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status = "disabled";
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};
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};
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};
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@ -195,6 +195,12 @@ config PINCTRL_AT91
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can also control the multi-driver capability, pull-up and pull-down
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feature on each I/O pin.
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config PINCTRL_CV1800B
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bool "CVITEK CV1800B pinctrl driver"
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depends_on DM
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help
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This option is to enable the CV1800B pinctrl driver.
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config PINCTRL_AT91PIO4
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bool "AT91 PIO4 pinctrl driver"
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depends on DM
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@ -10,6 +10,7 @@ obj-y += nxp/
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obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_ATH79) += ath79/
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obj-$(CONFIG_PINCTRL_CV1800B) += pinctrl-cv1800b.o
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obj-$(CONFIG_PINCTRL_INTEL) += intel/
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obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
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obj-$(CONFIG_ARCH_NPCM) += nuvoton/
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46
drivers/pinctrl/pinctrl-cv1800b.c
Normal file
46
drivers/pinctrl/pinctrl-cv1800b.c
Normal file
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@ -0,0 +1,46 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2023 Yilin Sun <imi415@imi.moe>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/pinctrl/cv1800b-pinctrl.h>
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#include <mapmem.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <linux/err.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#define CV1800B_PC_FUNC GENMASK(3, 0)
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struct cv1800b_pinmux{
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u32 ctrl[75];
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};
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struct cv1800b_pc_priv {
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struct cv1800b_pinmux __iomem *pinmux;
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};
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static int cv1800b_pc_probe(struct udevice *dev)
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{
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return 0;
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}
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static const struct device_id cv1800b_pc_ids[] = {
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{ .compatible = "cvitek,cv1800b-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_cv1800b) = {
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.name = "pinctrl_cv1800b",
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.id = UCLASS_PINCTRL,
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.of_match = cv1800b_pc_ids,
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.probe = cv1800b_pc_probe,
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.priv_auto = sizeof(struct cv1800b_pc_priv),
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.ops = &cv1800b_pc_ops,
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}
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86
include/dt-bindings/pinctrl/cv1800b-pinctrl.h
Normal file
86
include/dt-bindings/pinctrl/cv1800b-pinctrl.h
Normal file
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@ -0,0 +1,86 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2023 Yilin Sun <imi415@imi.moe>
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*/
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#ifndef DT_CV1800B_PINCTRL_H
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#define DT_CV1800B_PINCTRL_H
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#define CVI_CTRL_SD0_CLK (0x000U)
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#define CVI_CTRL_SD0_CMD (0x004U)
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#define CVI_CTRL_SD0_D0 (0x008U)
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#define CVI_CTRL_SD0_D1 (0x00CU)
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#define CVI_CTRL_SD0_D2 (0x010U)
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#define CVI_CTRL_SD0_D3 (0x014U)
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#define CVI_CTRL_SD0_CD (0x018U)
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#define CVI_CTRL_SD0_PWR_EN (0x01CU)
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#define CVI_CTRL_SPK_EN (0x020U)
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#define CVI_CTRL_UART0_TX (0x024U)
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#define CVI_CTRL_UART0_RX (0x028U)
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#define CVI_CTRL_SPINOR_HOLD_X (0x02CU)
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#define CVI_CTRL_SPINOR_SCK (0x030U)
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#define CVI_CTRL_SPINOR_MOSI (0x034U)
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#define CVI_CTRL_SPINOR_WP_X (0x038U)
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#define CVI_CTRL_SPINOR_MISO (0x03CU)
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#define CVI_CTRL_SPINOR_CS_X (0x040U)
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#define CVI_CTRL_JTAG_CPU_TMS (0x044U)
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#define CVI_CTRL_JTAG_CPU_TCK (0x048U)
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#define CVI_CTRL_IIC0_SCL (0x04CU)
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#define CVI_CTRL_IIC0_SDA (0x050U)
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#define CVI_CTRL_AUX0 (0x054U)
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#define CVI_CTRL_GPIO_ZQ (0x058U)
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#define CVI_CTRL_PWR_VBAT_DET (0x05CU)
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#define CVI_CTRL_PWR_RSTN (0x060U)
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#define CVI_CTRL_PWR_SEQ1 (0x064U)
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#define CVI_CTRL_PWR_SEQ2 (0x068U)
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#define CVI_CTRL_PWR_WAKEUP0 (0x06CU)
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#define CVI_CTRL_PWR_BUTTON1 (0x070U)
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#define CVI_CTRL_XTAL_XIN (0x074U)
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#define CVI_CTRL_PWR_GPIO0 (0x078U)
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#define CVI_CTRL_PWR_GPIO1 (0x07CU)
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#define CVI_CTRL_PWR_GPIO2 (0x080U)
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#define CVI_CTRL_SD1_GPIO1 (0x084U)
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#define CVI_CTRL_SD1_GPIO0 (0x088U)
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#define CVI_CTRL_SD1_D3 (0x08CU)
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#define CVI_CTRL_SD1_D2 (0x090U)
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#define CVI_CTRL_SD1_D1 (0x094U)
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#define CVI_CTRL_SD1_D0 (0x098U)
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#define CVI_CTRL_SD1_CMD (0x09CU)
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#define CVI_CTRL_SD1_CLK (0x0A0U)
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#define CVI_CTRL_PWM0_BUCK (0x0A4U)
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#define CVI_CTRL_ADC1 (0x0A8U)
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#define CVI_CTRL_USB_VBUS_DET (0x0ACU)
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#define CVI_CTRL_MUX_SPI1_MISO (0x0B0U)
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#define CVI_CTRL_MUX_SPI1_MOSI (0x0B4U)
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#define CVI_CTRL_MUX_SPI1_CS (0x0B8U)
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#define CVI_CTRL_MUX_SPI1_SCK (0x0BCU)
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#define CVI_CTRL_PAD_ETH_TXP (0x0C0U)
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#define CVI_CTRL_PAD_ETH_TXM (0x0C4U)
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#define CVI_CTRL_PAD_ETH_RXP (0x0C8U)
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#define CVI_CTRL_PAD_ETH_RXM (0x0CCU)
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#define CVI_CTRL_GPIO_RTX (0x0D0U)
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#define CVI_CTRL_PAD_MIPIRX4N (0x0D4U)
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#define CVI_CTRL_PAD_MIPIRX4P (0x0D8U)
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#define CVI_CTRL_PAD_MIPIRX3N (0x0DCU)
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#define CVI_CTRL_PAD_MIPIRX3P (0x0E0U)
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#define CVI_CTRL_PAD_MIPIRX2N (0x0E4U)
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#define CVI_CTRL_PAD_MIPIRX2P (0x0E8U)
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#define CVI_CTRL_PAD_MIPIRX1N (0x0ECU)
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#define CVI_CTRL_PAD_MIPIRX1P (0x0F0U)
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#define CVI_CTRL_PAD_MIPIRX0N (0x0F4U)
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#define CVI_CTRL_PAD_MIPIRX0P (0x0F8U)
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#define CVI_CTRL_PAD_MIPI_TXM2 (0x0FCU)
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#define CVI_CTRL_PAD_MIPI_TXP2 (0x100U)
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#define CVI_CTRL_PAD_MIPI_TXM1 (0x104U)
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#define CVI_CTRL_PAD_MIPI_TXP1 (0x108U)
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#define CVI_CTRL_PAD_MIPI_TXM0 (0x10CU)
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#define CVI_CTRL_PAD_MIPI_TXP0 (0x110U)
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#define CVI_CTRL_PKG_TYPE0 (0x114U)
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#define CVI_CTRL_PKG_TYPE1 (0x118U)
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#define CVI_CTRL_PKG_TYPE2 (0x11CU)
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#define CVI_CTRL_PAD_AUD_AINL_MIC (0x120U)
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#define CVI_CTRL_PAD_AUD_AINR_MIC (0x124U)
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#define CVI_CTRL_PAD_AUD_AOUTL (0x128U)
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#define CVI_CTRL_PAD_AUD_AOUTR (0x12CU)
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#endif /* DT_CV1800B_PINCTRL_H */
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