arm: Remove unused ep93xx code
There are no platforms for this architecture anymore, remove unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
9035caf080
commit
2fc0995cc0
|
|
@ -7,7 +7,6 @@ extra-y = start.o
|
|||
|
||||
obj-y += cpu.o
|
||||
|
||||
obj-$(CONFIG_EP93XX) += ep93xx/
|
||||
obj-$(CONFIG_IMX) += imx/
|
||||
|
||||
# some files can only build in ARM mode
|
||||
|
|
|
|||
|
|
@ -1,19 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Cirrus Logic EP93xx CPU-specific Makefile
|
||||
#
|
||||
# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
#
|
||||
# Copyright (C) 2004, 2005
|
||||
# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
#
|
||||
# Copyright (C) 2006
|
||||
# Dominic Rath <Dominic.Rath@gmx.de>
|
||||
#
|
||||
# Based on an original Makefile, which is
|
||||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
obj-y = cpu.o led.o speed.o timer.o
|
||||
obj-y += lowlevel_init.o
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Cirrus Logic EP93xx CPU-specific support.
|
||||
*
|
||||
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <asm/arch/ep93xx.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
|
||||
extern void reset_cpu(void)
|
||||
{
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
uint32_t value;
|
||||
|
||||
/* Unlock DeviceCfg and set SWRST */
|
||||
writel(0xAA, &syscon->sysswlock);
|
||||
value = readl(&syscon->devicecfg);
|
||||
value |= SYSCON_DEVICECFG_SWRST;
|
||||
writel(value, &syscon->devicecfg);
|
||||
|
||||
/* Unlock DeviceCfg and clear SWRST */
|
||||
writel(0xAA, &syscon->sysswlock);
|
||||
value = readl(&syscon->devicecfg);
|
||||
value &= ~SYSCON_DEVICECFG_SWRST;
|
||||
writel(value, &syscon->devicecfg);
|
||||
|
||||
/* Dying... */
|
||||
while (1)
|
||||
; /* noop */
|
||||
}
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/ep93xx.h>
|
||||
#include <config.h>
|
||||
#include <status_led.h>
|
||||
|
||||
static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
|
||||
static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
|
||||
1 << CONFIG_LED_STATUS_RED};
|
||||
|
||||
static inline void switch_LED_on(uint8_t led)
|
||||
{
|
||||
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
|
||||
|
||||
writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
|
||||
saved_state[led] = CONFIG_LED_STATUS_ON;
|
||||
}
|
||||
|
||||
static inline void switch_LED_off(uint8_t led)
|
||||
{
|
||||
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
|
||||
|
||||
writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
|
||||
saved_state[led] = CONFIG_LED_STATUS_OFF;
|
||||
}
|
||||
|
||||
void red_led_on(void)
|
||||
{
|
||||
switch_LED_on(CONFIG_LED_STATUS_RED);
|
||||
}
|
||||
|
||||
void red_led_off(void)
|
||||
{
|
||||
switch_LED_off(CONFIG_LED_STATUS_RED);
|
||||
}
|
||||
|
||||
void green_led_on(void)
|
||||
{
|
||||
switch_LED_on(CONFIG_LED_STATUS_GREEN);
|
||||
}
|
||||
|
||||
void green_led_off(void)
|
||||
{
|
||||
switch_LED_off(CONFIG_LED_STATUS_GREEN);
|
||||
}
|
||||
|
||||
void __led_init(led_id_t mask, int state)
|
||||
{
|
||||
__led_set(mask, state);
|
||||
}
|
||||
|
||||
void __led_toggle(led_id_t mask)
|
||||
{
|
||||
if (CONFIG_LED_STATUS_RED == mask) {
|
||||
if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
|
||||
red_led_off();
|
||||
else
|
||||
red_led_on();
|
||||
} else if (CONFIG_LED_STATUS_GREEN == mask) {
|
||||
if (CONFIG_LED_STATUS_ON ==
|
||||
saved_state[CONFIG_LED_STATUS_GREEN])
|
||||
green_led_off();
|
||||
else
|
||||
green_led_on();
|
||||
}
|
||||
}
|
||||
|
||||
void __led_set(led_id_t mask, int state)
|
||||
{
|
||||
if (CONFIG_LED_STATUS_RED == mask) {
|
||||
if (CONFIG_LED_STATUS_ON == state)
|
||||
red_led_on();
|
||||
else
|
||||
red_led_off();
|
||||
} else if (CONFIG_LED_STATUS_GREEN == mask) {
|
||||
if (CONFIG_LED_STATUS_ON == state)
|
||||
green_led_on();
|
||||
else
|
||||
green_led_off();
|
||||
}
|
||||
}
|
||||
|
|
@ -1,457 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Low-level initialization for EP93xx
|
||||
*
|
||||
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
* Copyright (C) 2013
|
||||
* Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
|
||||
*
|
||||
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
|
||||
* Copyright (C) 2006 Cirrus Logic Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch-ep93xx/ep93xx.h>
|
||||
|
||||
/*
|
||||
/* Configure the SDRAM based on the supplied settings.
|
||||
*
|
||||
* Input: r0 - SDRAM DEVCFG register
|
||||
* r2 - configuration for SDRAM chips
|
||||
* Output: none
|
||||
* Modifies: r3, r4
|
||||
*/
|
||||
ep93xx_sdram_config:
|
||||
/* Program the SDRAM device configuration register. */
|
||||
ldr r3, =SDRAM_BASE
|
||||
#ifdef CONFIG_EDB93XX_SDCS0
|
||||
str r0, [r3, #SDRAM_OFF_DEVCFG0]
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS1
|
||||
str r0, [r3, #SDRAM_OFF_DEVCFG1]
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS2
|
||||
str r0, [r3, #SDRAM_OFF_DEVCFG2]
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS3
|
||||
str r0, [r3, #SDRAM_OFF_DEVCFG3]
|
||||
#endif
|
||||
|
||||
/* Set the Initialize and MRS bits (issue continuous NOP commands
|
||||
* (INIT & MRS set))
|
||||
*/
|
||||
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
|
||||
EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
|
||||
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
|
||||
str r4, [r3, #SDRAM_OFF_GLCONFIG]
|
||||
|
||||
/* Delay for 200us. */
|
||||
mov r4, #0x3000
|
||||
delay1:
|
||||
subs r4, r4, #1
|
||||
bne delay1
|
||||
|
||||
/* Clear the MRS bit to issue a precharge all. */
|
||||
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
|
||||
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
|
||||
str r4, [r3, #SDRAM_OFF_GLCONFIG]
|
||||
|
||||
/* Temporarily set the refresh timer to 0x10. Make it really low so
|
||||
* that refresh cycles are generated.
|
||||
*/
|
||||
ldr r4, =0x10
|
||||
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
|
||||
|
||||
/* Delay for at least 80 SDRAM clock cycles. */
|
||||
mov r4, #80
|
||||
delay2:
|
||||
subs r4, r4, #1
|
||||
bne delay2
|
||||
|
||||
/* Set the refresh timer to the fastest required for any device
|
||||
* that might be used. Set 9.6 ms refresh time.
|
||||
*/
|
||||
ldr r4, =0x01e0
|
||||
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
|
||||
|
||||
/* Select mode register update mode. */
|
||||
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
|
||||
EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
|
||||
str r4, [r3, #SDRAM_OFF_GLCONFIG]
|
||||
|
||||
/* Program the mode register on the SDRAM by performing fake read */
|
||||
ldr r4, [r2]
|
||||
|
||||
/* Select normal operating mode. */
|
||||
ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
|
||||
str r4, [r3, #SDRAM_OFF_GLCONFIG]
|
||||
|
||||
/* Return to the caller. */
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* Test to see if the SDRAM has been configured in a usable mode.
|
||||
*
|
||||
* Input: r0 - Test address of SDRAM
|
||||
* Output: r0 - 0 -- Test OK, -1 -- Failed
|
||||
* Modifies: r0-r5
|
||||
*/
|
||||
ep93xx_sdram_test:
|
||||
/* Load the test patterns to be written to SDRAM. */
|
||||
ldr r1, =0xf00dface
|
||||
ldr r2, =0xdeadbeef
|
||||
ldr r3, =0x08675309
|
||||
ldr r4, =0xdeafc0ed
|
||||
|
||||
/* Store the test patterns to SDRAM. */
|
||||
stmia r0, {r1-r4}
|
||||
|
||||
/* Load the test patterns from SDRAM one at a time and compare them
|
||||
* to the actual pattern.
|
||||
*/
|
||||
ldr r5, [r0]
|
||||
cmp r5, r1
|
||||
ldreq r5, [r0, #0x0004]
|
||||
cmpeq r5, r2
|
||||
ldreq r5, [r0, #0x0008]
|
||||
cmpeq r5, r3
|
||||
ldreq r5, [r0, #0x000c]
|
||||
cmpeq r5, r4
|
||||
|
||||
/* Return -1 if a mismatch was encountered, 0 otherwise. */
|
||||
mvnne r0, #0xffffffff
|
||||
moveq r0, #0x00000000
|
||||
|
||||
/* Return to the caller. */
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* Determine the size of the SDRAM. Use data=address for the scan.
|
||||
*
|
||||
* Input: r0 - Start SDRAM address
|
||||
* Return: r0 - Single block size
|
||||
* r1 - Valid block mask
|
||||
* r2 - Total block count
|
||||
* Modifies: r0-r5
|
||||
*/
|
||||
ep93xx_sdram_size:
|
||||
/* Store zero at offset zero. */
|
||||
str r0, [r0]
|
||||
|
||||
/* Start checking for an alias at 1MB into SDRAM. */
|
||||
ldr r1, =0x00100000
|
||||
|
||||
/* Store the offset at the current offset. */
|
||||
check_block_size:
|
||||
str r1, [r0, r1]
|
||||
|
||||
/* Read back from zero. */
|
||||
ldr r2, [r0]
|
||||
|
||||
/* Stop searching of an alias was found. */
|
||||
cmp r1, r2
|
||||
beq found_block_size
|
||||
|
||||
/* Advance to the next power of two boundary. */
|
||||
mov r1, r1, lsl #1
|
||||
|
||||
/* Loop back if the size has not reached 256MB. */
|
||||
cmp r1, #0x10000000
|
||||
bne check_block_size
|
||||
|
||||
/* A full 256MB of memory was found, so return it now. */
|
||||
ldr r0, =0x10000000
|
||||
ldr r1, =0x00000000
|
||||
ldr r2, =0x00000001
|
||||
mov pc, lr
|
||||
|
||||
/* An alias was found. See if the first block is 128MB in size. */
|
||||
found_block_size:
|
||||
cmp r1, #0x08000000
|
||||
|
||||
/* The first block is 128MB, so there is no further memory. Return it
|
||||
* now.
|
||||
*/
|
||||
ldreq r0, =0x08000000
|
||||
ldreq r1, =0x00000000
|
||||
ldreq r2, =0x00000001
|
||||
moveq pc, lr
|
||||
|
||||
/* Save the block size, set the block address bits to zero, and
|
||||
* initialize the block count to one.
|
||||
*/
|
||||
mov r3, r1
|
||||
ldr r4, =0x00000000
|
||||
ldr r5, =0x00000001
|
||||
|
||||
/* Look for additional blocks of memory by searching for non-aliases. */
|
||||
find_blocks:
|
||||
/* Store zero back to address zero. It may be overwritten. */
|
||||
str r0, [r0]
|
||||
|
||||
/* Advance to the next power of two boundary. */
|
||||
mov r1, r1, lsl #1
|
||||
|
||||
/* Store the offset at the current offset. */
|
||||
str r1, [r0, r1]
|
||||
|
||||
/* Read back from zero. */
|
||||
ldr r2, [r0]
|
||||
|
||||
/* See if a non-alias was found. */
|
||||
cmp r1, r2
|
||||
|
||||
/* If a non-alias was found, then or in the block address bit and
|
||||
* multiply the block count by two (since there are two unique
|
||||
* blocks, one with this bit zero and one with it one).
|
||||
*/
|
||||
orrne r4, r4, r1
|
||||
movne r5, r5, lsl #1
|
||||
|
||||
/* Continue searching if there are more address bits to check. */
|
||||
cmp r1, #0x08000000
|
||||
bne find_blocks
|
||||
|
||||
/* Return the block size, address mask, and count. */
|
||||
mov r0, r3
|
||||
mov r1, r4
|
||||
mov r2, r5
|
||||
|
||||
/* Return to the caller. */
|
||||
mov pc, lr
|
||||
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
mov r6, lr
|
||||
|
||||
/* Make sure caches are off and invalidated. */
|
||||
ldr r0, =0x00000000
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
/* Turn off the green LED and turn on the red LED. If the red LED
|
||||
* is left on for too long, the external reset circuit described
|
||||
* by application note AN258 will cause the system to reset.
|
||||
*/
|
||||
ldr r1, =EP93XX_LED_DATA
|
||||
ldr r0, [r1]
|
||||
bic r0, r0, #EP93XX_LED_GREEN_ON
|
||||
orr r0, r0, #EP93XX_LED_RED_ON
|
||||
str r0, [r1]
|
||||
|
||||
/* Undo the silly static memory controller programming performed
|
||||
* by the boot rom.
|
||||
*/
|
||||
ldr r0, =SMC_BASE
|
||||
|
||||
/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
|
||||
ldr r1, =0x0000fbe0
|
||||
|
||||
/* Reset EP93XX_OFF_SMCBCR0 */
|
||||
ldr r2, [r0]
|
||||
orr r2, r2, r1
|
||||
str r2, [r0]
|
||||
|
||||
ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
|
||||
orr r2, r2, r1
|
||||
str r2, [r0, #EP93XX_OFF_SMCBCR1]
|
||||
|
||||
ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
|
||||
orr r2, r2, r1
|
||||
str r2, [r0, #EP93XX_OFF_SMCBCR2]
|
||||
|
||||
ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
|
||||
orr r2, r2, r1
|
||||
str r2, [r0, #EP93XX_OFF_SMCBCR3]
|
||||
|
||||
ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
|
||||
orr r2, r2, r1
|
||||
str r2, [r0, #EP93XX_OFF_SMCBCR6]
|
||||
|
||||
ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
|
||||
orr r2, r2, r1
|
||||
str r2, [r0, #EP93XX_OFF_SMCBCR7]
|
||||
|
||||
/* Set the PLL1 and processor clock. */
|
||||
ldr r0, =SYSCON_BASE
|
||||
#ifdef CONFIG_EDB9301
|
||||
/* 332MHz, giving a 166MHz processor clock. */
|
||||
ldr r1, = 0x02b49907
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_EDB93XX_INDUSTRIAL
|
||||
/* 384MHz, giving a 196MHz processor clock. */
|
||||
ldr r1, =0x02a4bb38
|
||||
#else
|
||||
/* 400MHz, giving a 200MHz processor clock. */
|
||||
ldr r1, =0x02a4e39e
|
||||
#endif
|
||||
#endif
|
||||
str r1, [r0, #SYSCON_OFF_CLKSET1]
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
/* Need to make sure that SDRAM is configured correctly before
|
||||
* coping the code into it.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_EDB93XX_SDCS0
|
||||
mov r11, #SDRAM_DEVCFG0_BASE
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS1
|
||||
mov r11, #SDRAM_DEVCFG1_BASE
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS2
|
||||
mov r11, #SDRAM_DEVCFG2_BASE
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS3
|
||||
ldr r0, =SYSCON_BASE
|
||||
ldr r0, [r0, #SYSCON_OFF_SYSCFG]
|
||||
ands r0, r0, #SYSCON_SYSCFG_LASDO
|
||||
moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
|
||||
movne r11, #SDRAM_DEVCFG3_ASD1_BASE
|
||||
#endif
|
||||
/* See Table 13-5 in EP93xx datasheet for more info about DRAM
|
||||
* register mapping */
|
||||
|
||||
/* Try a 32-bit wide configuration of SDRAM. */
|
||||
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
|
||||
|
||||
/* Set burst count: 4 and CAS: 2
|
||||
* Burst mode [A11:A10]; CAS [A16:A14]
|
||||
*/
|
||||
orr r2, r11, #0x00008800
|
||||
bl ep93xx_sdram_config
|
||||
|
||||
/* Test the SDRAM. */
|
||||
mov r0, r11
|
||||
bl ep93xx_sdram_test
|
||||
cmp r0, #0x00000000
|
||||
beq ep93xx_sdram_done
|
||||
|
||||
/* Try a 16-bit wide configuration of SDRAM. */
|
||||
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
|
||||
EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
|
||||
|
||||
/* Set burst count: 8, CAS: 2, sequential burst
|
||||
* Accoring to Table 13-3 for 16bit operations mapping must be shifted.
|
||||
* Burst mode [A10:A9]; CAS [A15:A13]
|
||||
*/
|
||||
orr r2, r11, #0x00004600
|
||||
bl ep93xx_sdram_config
|
||||
|
||||
/* Test the SDRAM. */
|
||||
mov r0, r11
|
||||
bl ep93xx_sdram_test
|
||||
cmp r0, #0x00000000
|
||||
beq ep93xx_sdram_done
|
||||
|
||||
/* Turn off the red LED. */
|
||||
ldr r0, =EP93XX_LED_DATA
|
||||
ldr r1, [r0]
|
||||
bic r1, r1, #EP93XX_LED_RED_ON
|
||||
str r1, [r0]
|
||||
|
||||
/* There is no SDRAM so flash the green LED. */
|
||||
flash_green:
|
||||
orr r1, r1, #EP93XX_LED_GREEN_ON
|
||||
str r1, [r0]
|
||||
ldr r2, =0x00010000
|
||||
flash_green_delay_1:
|
||||
subs r2, r2, #1
|
||||
bne flash_green_delay_1
|
||||
bic r1, r1, #EP93XX_LED_GREEN_ON
|
||||
str r1, [r0]
|
||||
ldr r2, =0x00010000
|
||||
flash_green_delay_2:
|
||||
subs r2, r2, #1
|
||||
bne flash_green_delay_2
|
||||
orr r1, r1, #EP93XX_LED_GREEN_ON
|
||||
str r1, [r0]
|
||||
ldr r2, =0x00010000
|
||||
flash_green_delay_3:
|
||||
subs r2, r2, #1
|
||||
bne flash_green_delay_3
|
||||
bic r1, r1, #EP93XX_LED_GREEN_ON
|
||||
str r1, [r0]
|
||||
ldr r2, =0x00050000
|
||||
flash_green_delay_4:
|
||||
subs r2, r2, #1
|
||||
bne flash_green_delay_4
|
||||
b flash_green
|
||||
|
||||
|
||||
ep93xx_sdram_done:
|
||||
ldr r1, =EP93XX_LED_DATA
|
||||
ldr r0, [r1]
|
||||
bic r0, r0, #EP93XX_LED_RED_ON
|
||||
str r0, [r1]
|
||||
|
||||
/* Determine the size of the SDRAM. */
|
||||
mov r0, r11
|
||||
bl ep93xx_sdram_size
|
||||
|
||||
/* Save the SDRAM characteristics. */
|
||||
mov r8, r0
|
||||
mov r9, r1
|
||||
mov r10, r2
|
||||
|
||||
/* Compute total memory size into r1 */
|
||||
mul r1, r8, r10
|
||||
#ifdef CONFIG_EDB93XX_SDCS0
|
||||
ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS1
|
||||
ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS2
|
||||
ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
|
||||
#endif
|
||||
#ifdef CONFIG_EDB93XX_SDCS3
|
||||
ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
|
||||
#endif
|
||||
|
||||
/* Consider small DRAM size as:
|
||||
* < 32Mb for 32bit bus
|
||||
* < 64Mb for 16bit bus
|
||||
*/
|
||||
tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
|
||||
moveq r1, r1, lsr #1
|
||||
cmp r1, #0x02000000
|
||||
|
||||
#if defined(CONFIG_EDB9301)
|
||||
/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
|
||||
movlt r1, #0x03f0
|
||||
movge r1, #0x01e0
|
||||
#else
|
||||
/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
|
||||
movlt r1, #0x0600
|
||||
movge r1, #0x2f0
|
||||
#endif
|
||||
str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
|
||||
|
||||
/* Save the memory configuration information. */
|
||||
orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
|
||||
stmia r0, {r8-r11}
|
||||
|
||||
mov lr, r6
|
||||
mov pc, lr
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Cirrus Logic EP93xx PLL support.
|
||||
*
|
||||
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clock_legacy.h>
|
||||
#include <asm/arch/ep93xx.h>
|
||||
#include <asm/io.h>
|
||||
#include <div64.h>
|
||||
|
||||
/*
|
||||
* get_board_sys_clk() should be defined as the input frequency of the PLL.
|
||||
*
|
||||
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
|
||||
* the specified bus in HZ.
|
||||
*/
|
||||
|
||||
/*
|
||||
* return the PLL output frequency
|
||||
*
|
||||
* PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
|
||||
* / (X2IPD + 1) / 2^PS
|
||||
*/
|
||||
static ulong get_PLLCLK(uint32_t *pllreg)
|
||||
{
|
||||
uint8_t i;
|
||||
const uint32_t clkset = readl(pllreg);
|
||||
uint64_t rate = get_board_sys_clk();
|
||||
rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
|
||||
rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
|
||||
do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
|
||||
for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
|
||||
rate >>= 1;
|
||||
|
||||
return (ulong)rate;
|
||||
}
|
||||
|
||||
/* return FCLK frequency */
|
||||
ulong get_FCLK(void)
|
||||
{
|
||||
const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
|
||||
const uint32_t clkset1 = readl(&syscon->clkset1);
|
||||
const uint8_t fclk_div =
|
||||
fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
|
||||
const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
|
||||
|
||||
return fclk_rate;
|
||||
}
|
||||
|
||||
/* return HCLK frequency */
|
||||
ulong get_HCLK(void)
|
||||
{
|
||||
const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
|
||||
const uint32_t clkset1 = readl(&syscon->clkset1);
|
||||
const uint8_t hclk_div =
|
||||
hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
|
||||
const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
|
||||
|
||||
return hclk_rate;
|
||||
}
|
||||
|
||||
/* return PCLK frequency */
|
||||
ulong get_PCLK(void)
|
||||
{
|
||||
const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
|
||||
const uint32_t clkset1 = readl(&syscon->clkset1);
|
||||
const uint8_t pclk_div =
|
||||
pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
|
||||
const ulong pclk_rate = get_HCLK() / pclk_div;
|
||||
|
||||
return pclk_rate;
|
||||
}
|
||||
|
||||
/* return UCLK frequency */
|
||||
ulong get_UCLK(void)
|
||||
{
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
ulong uclk_rate;
|
||||
|
||||
const uint32_t value = readl(&syscon->pwrcnt);
|
||||
if (value & SYSCON_PWRCNT_UART_BAUD)
|
||||
uclk_rate = get_board_sys_clk();
|
||||
else
|
||||
uclk_rate = get_board_sys_clk() / 2;
|
||||
|
||||
return uclk_rate;
|
||||
}
|
||||
|
|
@ -1,117 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Cirrus Logic EP93xx timer support.
|
||||
*
|
||||
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*
|
||||
* Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
|
||||
* author unknown.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <time.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/arch/ep93xx.h>
|
||||
#include <asm/io.h>
|
||||
#include <div64.h>
|
||||
|
||||
#define TIMER_CLKSEL (1 << 3)
|
||||
#define TIMER_ENABLE (1 << 7)
|
||||
|
||||
#define TIMER_FREQ 508469 /* ticks / second */
|
||||
#define TIMER_MAX_VAL 0xFFFFFFFF
|
||||
|
||||
static struct ep93xx_timer
|
||||
{
|
||||
unsigned long long ticks;
|
||||
unsigned long last_read;
|
||||
} timer;
|
||||
|
||||
static inline unsigned long long usecs_to_ticks(unsigned long usecs)
|
||||
{
|
||||
unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
|
||||
do_div(ticks, 1000 * 1000);
|
||||
|
||||
return ticks;
|
||||
}
|
||||
|
||||
static inline void read_timer(void)
|
||||
{
|
||||
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
|
||||
const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
|
||||
|
||||
if (now >= timer.last_read)
|
||||
timer.ticks += now - timer.last_read;
|
||||
else
|
||||
/* an overflow occurred */
|
||||
timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
|
||||
|
||||
timer.last_read = now;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the number of ticks (in CONFIG_SYS_HZ resolution)
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
unsigned long long sys_ticks;
|
||||
|
||||
read_timer();
|
||||
|
||||
sys_ticks = timer.ticks * CONFIG_SYS_HZ;
|
||||
do_div(sys_ticks, TIMER_FREQ);
|
||||
|
||||
return sys_ticks;
|
||||
}
|
||||
|
||||
unsigned long get_timer(unsigned long base)
|
||||
{
|
||||
return get_ticks() - base;
|
||||
}
|
||||
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long target;
|
||||
|
||||
read_timer();
|
||||
|
||||
target = timer.ticks + usecs_to_ticks(usec);
|
||||
|
||||
while (timer.ticks < target)
|
||||
read_timer();
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
|
||||
|
||||
/* use timer 3 with 508KHz and free running, not enabled now */
|
||||
writel(TIMER_CLKSEL, &timer_regs->timer3.control);
|
||||
|
||||
/* set initial timer value */
|
||||
writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
|
||||
|
||||
/* Enable the timer */
|
||||
writel(TIMER_ENABLE | TIMER_CLKSEL,
|
||||
&timer_regs->timer3.control);
|
||||
|
||||
/* Reset the timer */
|
||||
read_timer();
|
||||
timer.ticks = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
unsigned long get_tbclk(void)
|
||||
{
|
||||
return CONFIG_SYS_HZ;
|
||||
}
|
||||
|
|
@ -1,666 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Cirrus Logic EP93xx register definitions.
|
||||
*
|
||||
* Copyright (C) 2013
|
||||
* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
|
||||
*
|
||||
* Copyright (C) 2009
|
||||
* Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2006
|
||||
* Dominic Rath <Dominic.Rath@gmx.de>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*
|
||||
* Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
|
||||
*
|
||||
* Copyright (C) 2004 Ray Lehtiniemi
|
||||
* Copyright (C) 2003 Cirrus Logic, Inc
|
||||
* Copyright (C) 1999 ARM Limited.
|
||||
*/
|
||||
|
||||
#define EP93XX_AHB_BASE 0x80000000
|
||||
#define EP93XX_APB_BASE 0x80800000
|
||||
|
||||
/*
|
||||
* 0x80000000 - 0x8000FFFF: DMA
|
||||
*/
|
||||
#define DMA_OFFSET 0x000000
|
||||
#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct dma_channel {
|
||||
uint32_t control;
|
||||
uint32_t interrupt;
|
||||
uint32_t ppalloc;
|
||||
uint32_t status;
|
||||
uint32_t reserved0;
|
||||
uint32_t remain;
|
||||
uint32_t reserved1[2];
|
||||
uint32_t maxcnt0;
|
||||
uint32_t base0;
|
||||
uint32_t current0;
|
||||
uint32_t reserved2;
|
||||
uint32_t maxcnt1;
|
||||
uint32_t base1;
|
||||
uint32_t current1;
|
||||
uint32_t reserved3;
|
||||
};
|
||||
|
||||
struct dma_regs {
|
||||
struct dma_channel m2p_channel_0;
|
||||
struct dma_channel m2p_channel_1;
|
||||
struct dma_channel m2p_channel_2;
|
||||
struct dma_channel m2p_channel_3;
|
||||
struct dma_channel m2m_channel_0;
|
||||
struct dma_channel m2m_channel_1;
|
||||
struct dma_channel reserved0[2];
|
||||
struct dma_channel m2p_channel_5;
|
||||
struct dma_channel m2p_channel_4;
|
||||
struct dma_channel m2p_channel_7;
|
||||
struct dma_channel m2p_channel_6;
|
||||
struct dma_channel m2p_channel_9;
|
||||
struct dma_channel m2p_channel_8;
|
||||
uint32_t channel_arbitration;
|
||||
uint32_t reserved[15];
|
||||
uint32_t global_interrupt;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80010000 - 0x8001FFFF: Ethernet MAC
|
||||
*/
|
||||
#define MAC_OFFSET 0x010000
|
||||
#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mac_queue {
|
||||
uint32_t badd;
|
||||
union { /* deal with half-word aligned registers */
|
||||
uint32_t blen;
|
||||
union {
|
||||
uint16_t filler;
|
||||
uint16_t curlen;
|
||||
};
|
||||
};
|
||||
uint32_t curadd;
|
||||
};
|
||||
|
||||
struct mac_regs {
|
||||
uint32_t rxctl;
|
||||
uint32_t txctl;
|
||||
uint32_t testctl;
|
||||
uint32_t reserved0;
|
||||
uint32_t miicmd;
|
||||
uint32_t miidata;
|
||||
uint32_t miists;
|
||||
uint32_t reserved1;
|
||||
uint32_t selfctl;
|
||||
uint32_t inten;
|
||||
uint32_t intstsp;
|
||||
uint32_t intstsc;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t diagad;
|
||||
uint32_t diagdata;
|
||||
uint32_t gt;
|
||||
uint32_t fct;
|
||||
uint32_t fcf;
|
||||
uint32_t afp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t indad;
|
||||
uint32_t indad_upper;
|
||||
};
|
||||
uint32_t hashtbl;
|
||||
};
|
||||
uint32_t reserved3[2];
|
||||
uint32_t giintsts;
|
||||
uint32_t giintmsk;
|
||||
uint32_t giintrosts;
|
||||
uint32_t giintfrc;
|
||||
uint32_t txcollcnt;
|
||||
uint32_t rxmissnct;
|
||||
uint32_t rxruntcnt;
|
||||
uint32_t reserved4;
|
||||
uint32_t bmctl;
|
||||
uint32_t bmsts;
|
||||
uint32_t rxbca;
|
||||
uint32_t reserved5;
|
||||
struct mac_queue rxdq;
|
||||
uint32_t rxdqenq;
|
||||
struct mac_queue rxstsq;
|
||||
uint32_t rxstsqenq;
|
||||
struct mac_queue txdq;
|
||||
uint32_t txdqenq;
|
||||
struct mac_queue txstsq;
|
||||
uint32_t reserved6;
|
||||
uint32_t rxbufthrshld;
|
||||
uint32_t txbufthrshld;
|
||||
uint32_t rxststhrshld;
|
||||
uint32_t txststhrshld;
|
||||
uint32_t rxdthrshld;
|
||||
uint32_t txdthrshld;
|
||||
uint32_t maxfrmlen;
|
||||
uint32_t maxhdrlen;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define SELFCTL_RWP (1 << 7)
|
||||
#define SELFCTL_GPO0 (1 << 5)
|
||||
#define SELFCTL_PUWE (1 << 4)
|
||||
#define SELFCTL_PDWE (1 << 3)
|
||||
#define SELFCTL_MIIL (1 << 2)
|
||||
#define SELFCTL_RESET (1 << 0)
|
||||
|
||||
#define INTSTS_RWI (1 << 30)
|
||||
#define INTSTS_RXMI (1 << 29)
|
||||
#define INTSTS_RXBI (1 << 28)
|
||||
#define INTSTS_RXSQI (1 << 27)
|
||||
#define INTSTS_TXLEI (1 << 26)
|
||||
#define INTSTS_ECIE (1 << 25)
|
||||
#define INTSTS_TXUHI (1 << 24)
|
||||
#define INTSTS_MOI (1 << 18)
|
||||
#define INTSTS_TXCOI (1 << 17)
|
||||
#define INTSTS_RXROI (1 << 16)
|
||||
#define INTSTS_MIII (1 << 12)
|
||||
#define INTSTS_PHYI (1 << 11)
|
||||
#define INTSTS_TI (1 << 10)
|
||||
#define INTSTS_AHBE (1 << 8)
|
||||
#define INTSTS_OTHER (1 << 4)
|
||||
#define INTSTS_TXSQ (1 << 3)
|
||||
#define INTSTS_RXSQ (1 << 2)
|
||||
|
||||
#define BMCTL_MT (1 << 13)
|
||||
#define BMCTL_TT (1 << 12)
|
||||
#define BMCTL_UNH (1 << 11)
|
||||
#define BMCTL_TXCHR (1 << 10)
|
||||
#define BMCTL_TXDIS (1 << 9)
|
||||
#define BMCTL_TXEN (1 << 8)
|
||||
#define BMCTL_EH2 (1 << 6)
|
||||
#define BMCTL_EH1 (1 << 5)
|
||||
#define BMCTL_EEOB (1 << 4)
|
||||
#define BMCTL_RXCHR (1 << 2)
|
||||
#define BMCTL_RXDIS (1 << 1)
|
||||
#define BMCTL_RXEN (1 << 0)
|
||||
|
||||
#define BMSTS_TXACT (1 << 7)
|
||||
#define BMSTS_TP (1 << 4)
|
||||
#define BMSTS_RXACT (1 << 3)
|
||||
#define BMSTS_QID_MASK 0x07
|
||||
#define BMSTS_QID_RXDATA 0x00
|
||||
#define BMSTS_QID_TXDATA 0x01
|
||||
#define BMSTS_QID_RXSTS 0x02
|
||||
#define BMSTS_QID_TXSTS 0x03
|
||||
#define BMSTS_QID_RXDESC 0x04
|
||||
#define BMSTS_QID_TXDESC 0x05
|
||||
|
||||
#define AFP_MASK 0x07
|
||||
#define AFP_IAPRIMARY 0x00
|
||||
#define AFP_IASECONDARY1 0x01
|
||||
#define AFP_IASECONDARY2 0x02
|
||||
#define AFP_IASECONDARY3 0x03
|
||||
#define AFP_TX 0x06
|
||||
#define AFP_HASH 0x07
|
||||
|
||||
#define RXCTL_PAUSEA (1 << 20)
|
||||
#define RXCTL_RXFCE1 (1 << 19)
|
||||
#define RXCTL_RXFCE0 (1 << 18)
|
||||
#define RXCTL_BCRC (1 << 17)
|
||||
#define RXCTL_SRXON (1 << 16)
|
||||
#define RXCTL_RCRCA (1 << 13)
|
||||
#define RXCTL_RA (1 << 12)
|
||||
#define RXCTL_PA (1 << 11)
|
||||
#define RXCTL_BA (1 << 10)
|
||||
#define RXCTL_MA (1 << 9)
|
||||
#define RXCTL_IAHA (1 << 8)
|
||||
#define RXCTL_IA3 (1 << 3)
|
||||
#define RXCTL_IA2 (1 << 2)
|
||||
#define RXCTL_IA1 (1 << 1)
|
||||
#define RXCTL_IA0 (1 << 0)
|
||||
|
||||
#define TXCTL_DEFDIS (1 << 7)
|
||||
#define TXCTL_MBE (1 << 6)
|
||||
#define TXCTL_ICRC (1 << 5)
|
||||
#define TXCTL_TPD (1 << 4)
|
||||
#define TXCTL_OCOLL (1 << 3)
|
||||
#define TXCTL_SP (1 << 2)
|
||||
#define TXCTL_PB (1 << 1)
|
||||
#define TXCTL_STXON (1 << 0)
|
||||
|
||||
#define MIICMD_REGAD_MASK (0x001F)
|
||||
#define MIICMD_PHYAD_MASK (0x03E0)
|
||||
#define MIICMD_OPCODE_MASK (0xC000)
|
||||
#define MIICMD_PHYAD_8950 (0x0000)
|
||||
#define MIICMD_OPCODE_READ (0x8000)
|
||||
#define MIICMD_OPCODE_WRITE (0x4000)
|
||||
|
||||
#define MIISTS_BUSY (1 << 0)
|
||||
|
||||
/*
|
||||
* 0x80020000 - 0x8002FFFF: USB OHCI
|
||||
*/
|
||||
#define USB_OFFSET 0x020000
|
||||
#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80030000 - 0x8003FFFF: Raster engine
|
||||
*/
|
||||
#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
|
||||
#define RASTER_OFFSET 0x030000
|
||||
#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80040000 - 0x8004FFFF: Graphics accelerator
|
||||
*/
|
||||
#if defined(CONFIG_EP9315)
|
||||
#define GFX_OFFSET 0x040000
|
||||
#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80050000 - 0x8005FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80060000 - 0x8006FFFF: SDRAM controller
|
||||
*/
|
||||
#define SDRAM_OFFSET 0x060000
|
||||
#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sdram_regs {
|
||||
uint32_t reserved;
|
||||
uint32_t glconfig;
|
||||
uint32_t refrshtimr;
|
||||
uint32_t bootsts;
|
||||
uint32_t devcfg0;
|
||||
uint32_t devcfg1;
|
||||
uint32_t devcfg2;
|
||||
uint32_t devcfg3;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
|
||||
#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
|
||||
#define SDRAM_DEVCFG_SROMLL (1 << 5)
|
||||
#define SDRAM_DEVCFG_CASLAT_2 0x00010000
|
||||
#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
|
||||
|
||||
#define SDRAM_OFF_GLCONFIG 0x0004
|
||||
#define SDRAM_OFF_REFRSHTIMR 0x0008
|
||||
|
||||
#define SDRAM_OFF_DEVCFG0 0x0010
|
||||
#define SDRAM_OFF_DEVCFG1 0x0014
|
||||
#define SDRAM_OFF_DEVCFG2 0x0018
|
||||
#define SDRAM_OFF_DEVCFG3 0x001C
|
||||
|
||||
#define SDRAM_DEVCFG0_BASE 0xC0000000
|
||||
#define SDRAM_DEVCFG1_BASE 0xD0000000
|
||||
#define SDRAM_DEVCFG2_BASE 0xE0000000
|
||||
#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
|
||||
#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
|
||||
|
||||
#define GLCONFIG_INIT (1 << 0)
|
||||
#define GLCONFIG_MRS (1 << 1)
|
||||
#define GLCONFIG_SMEMBUSY (1 << 5)
|
||||
#define GLCONFIG_LCR (1 << 6)
|
||||
#define GLCONFIG_REARBEN (1 << 7)
|
||||
#define GLCONFIG_CLKSHUTDOWN (1 << 30)
|
||||
#define GLCONFIG_CKE (1 << 31)
|
||||
|
||||
#define EP93XX_SDRAMCTRL 0x80060000
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
|
||||
|
||||
#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
|
||||
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
|
||||
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
|
||||
|
||||
/*
|
||||
* 0x80070000 - 0x8007FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
|
||||
*/
|
||||
#define SMC_OFFSET 0x080000
|
||||
#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct smc_regs {
|
||||
uint32_t bcr0;
|
||||
uint32_t bcr1;
|
||||
uint32_t bcr2;
|
||||
uint32_t bcr3;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t bcr6;
|
||||
uint32_t bcr7;
|
||||
#if defined(CONFIG_EP9315)
|
||||
uint32_t pcattribute;
|
||||
uint32_t pccommon;
|
||||
uint32_t pcio;
|
||||
uint32_t reserved1[5];
|
||||
uint32_t pcmciactrl;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#define EP93XX_OFF_SMCBCR0 0x00
|
||||
#define EP93XX_OFF_SMCBCR1 0x04
|
||||
#define EP93XX_OFF_SMCBCR2 0x08
|
||||
#define EP93XX_OFF_SMCBCR3 0x0C
|
||||
#define EP93XX_OFF_SMCBCR6 0x18
|
||||
#define EP93XX_OFF_SMCBCR7 0x1C
|
||||
|
||||
#define SMC_BCR_IDCY_SHIFT 0
|
||||
#define SMC_BCR_WST1_SHIFT 5
|
||||
#define SMC_BCR_BLE (1 << 10)
|
||||
#define SMC_BCR_WST2_SHIFT 11
|
||||
#define SMC_BCR_MW_SHIFT 28
|
||||
|
||||
/*
|
||||
* 0x80090000 - 0x8009FFFF: Boot ROM
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800A0000 - 0x800AFFFF: IDE interface
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800B0000 - 0x800BFFFF: VIC1
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800C0000 - 0x800CFFFF: VIC2
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800D0000 - 0x800FFFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80800000 - 0x8080FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80810000 - 0x8081FFFF: Timers
|
||||
*/
|
||||
#define TIMER_OFFSET 0x010000
|
||||
#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct timer {
|
||||
uint32_t load;
|
||||
uint32_t value;
|
||||
uint32_t control;
|
||||
uint32_t clear;
|
||||
};
|
||||
|
||||
struct timer4 {
|
||||
uint32_t value_low;
|
||||
uint32_t value_high;
|
||||
};
|
||||
|
||||
struct timer_regs {
|
||||
struct timer timer1;
|
||||
uint32_t reserved0[4];
|
||||
struct timer timer2;
|
||||
uint32_t reserved1[12];
|
||||
struct timer4 timer4;
|
||||
uint32_t reserved2[6];
|
||||
struct timer timer3;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80820000 - 0x8082FFFF: I2S
|
||||
*/
|
||||
#define I2S_OFFSET 0x020000
|
||||
#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80830000 - 0x8083FFFF: Security
|
||||
*/
|
||||
#define SECURITY_OFFSET 0x030000
|
||||
#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
|
||||
|
||||
#define EXTENSIONID (SECURITY_BASE + 0x2714)
|
||||
|
||||
/*
|
||||
* 0x80840000 - 0x8084FFFF: GPIO
|
||||
*/
|
||||
#define GPIO_OFFSET 0x040000
|
||||
#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpio_int {
|
||||
uint32_t inttype1;
|
||||
uint32_t inttype2;
|
||||
uint32_t eoi;
|
||||
uint32_t inten;
|
||||
uint32_t intsts;
|
||||
uint32_t rawintsts;
|
||||
uint32_t db;
|
||||
};
|
||||
|
||||
struct gpio_regs {
|
||||
uint32_t padr;
|
||||
uint32_t pbdr;
|
||||
uint32_t pcdr;
|
||||
uint32_t pddr;
|
||||
uint32_t paddr;
|
||||
uint32_t pbddr;
|
||||
uint32_t pcddr;
|
||||
uint32_t pdddr;
|
||||
uint32_t pedr;
|
||||
uint32_t peddr;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t pfdr;
|
||||
uint32_t pfddr;
|
||||
uint32_t pgdr;
|
||||
uint32_t pgddr;
|
||||
uint32_t phdr;
|
||||
uint32_t phddr;
|
||||
uint32_t reserved1;
|
||||
uint32_t finttype1;
|
||||
uint32_t finttype2;
|
||||
uint32_t reserved2;
|
||||
struct gpio_int pfint;
|
||||
uint32_t reserved3[10];
|
||||
struct gpio_int paint;
|
||||
struct gpio_int pbint;
|
||||
uint32_t eedrive;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define EP93XX_LED_DATA 0x80840020
|
||||
#define EP93XX_LED_GREEN_ON 0x0001
|
||||
#define EP93XX_LED_RED_ON 0x0002
|
||||
|
||||
#define EP93XX_LED_DDR 0x80840024
|
||||
#define EP93XX_LED_GREEN_ENABLE 0x0001
|
||||
#define EP93XX_LED_RED_ENABLE 0x00020000
|
||||
|
||||
/*
|
||||
* 0x80850000 - 0x8087FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80880000 - 0x8088FFFF: AAC
|
||||
*/
|
||||
#define AAC_OFFSET 0x080000
|
||||
#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80890000 - 0x8089FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x808A0000 - 0x808AFFFF: SPI
|
||||
*/
|
||||
#define SPI_OFFSET 0x0A0000
|
||||
#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808B0000 - 0x808BFFFF: IrDA
|
||||
*/
|
||||
#define IRDA_OFFSET 0x0B0000
|
||||
#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808C0000 - 0x808CFFFF: UART1
|
||||
*/
|
||||
#define UART1_OFFSET 0x0C0000
|
||||
#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808D0000 - 0x808DFFFF: UART2
|
||||
*/
|
||||
#define UART2_OFFSET 0x0D0000
|
||||
#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808E0000 - 0x808EFFFF: UART3
|
||||
*/
|
||||
#define UART3_OFFSET 0x0E0000
|
||||
#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808F0000 - 0x808FFFFF: Key Matrix
|
||||
*/
|
||||
#define KEY_OFFSET 0x0F0000
|
||||
#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80900000 - 0x8090FFFF: Touchscreen
|
||||
*/
|
||||
#define TOUCH_OFFSET 0x900000
|
||||
#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80910000 - 0x8091FFFF: Pulse Width Modulation
|
||||
*/
|
||||
#define PWM_OFFSET 0x910000
|
||||
#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80920000 - 0x8092FFFF: Real time clock
|
||||
*/
|
||||
#define RTC_OFFSET 0x920000
|
||||
#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80930000 - 0x8093FFFF: Syscon
|
||||
*/
|
||||
#define SYSCON_OFFSET 0x930000
|
||||
#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
|
||||
|
||||
/* Security */
|
||||
#define SECURITY_EXTENSIONID 0x80832714
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct syscon_regs {
|
||||
uint32_t pwrsts;
|
||||
uint32_t pwrcnt;
|
||||
uint32_t halt;
|
||||
uint32_t stby;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t teoi;
|
||||
uint32_t stfclr;
|
||||
uint32_t clkset1;
|
||||
uint32_t clkset2;
|
||||
uint32_t reserved1[6];
|
||||
uint32_t scratch0;
|
||||
uint32_t scratch1;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t apbwait;
|
||||
uint32_t bustmstrarb;
|
||||
uint32_t bootmodeclr;
|
||||
uint32_t reserved3[9];
|
||||
uint32_t devicecfg;
|
||||
uint32_t vidclkdiv;
|
||||
uint32_t mirclkdiv;
|
||||
uint32_t i2sclkdiv;
|
||||
uint32_t keytchclkdiv;
|
||||
uint32_t chipid;
|
||||
uint32_t reserved4;
|
||||
uint32_t syscfg;
|
||||
uint32_t reserved5[8];
|
||||
uint32_t sysswlock;
|
||||
};
|
||||
#else
|
||||
#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
|
||||
#endif
|
||||
|
||||
#define SYSCON_OFF_CLKSET1 0x0020
|
||||
#define SYSCON_OFF_SYSCFG 0x009c
|
||||
|
||||
#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
|
||||
#define SYSCON_PWRCNT_USH_EN (1 << 28)
|
||||
|
||||
#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
|
||||
#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
|
||||
#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
|
||||
#define SYSCON_CLKSET_PLL_PS_SHIFT 16
|
||||
#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
|
||||
#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
|
||||
#define SYSCON_CLKSET1_NBYP1 (1 << 23)
|
||||
#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
|
||||
|
||||
#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
|
||||
#define SYSCON_CLKSET2_NBYP2 (1 << 19)
|
||||
#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
|
||||
|
||||
#define SYSCON_CHIPID_REV_MASK 0xF0000000
|
||||
#define SYSCON_DEVICECFG_SWRST (1 << 31)
|
||||
|
||||
#define SYSCON_SYSCFG_LASDO 0x00000020
|
||||
|
||||
/*
|
||||
* 0x80930000 - 0x8093FFFF: Watchdog Timer
|
||||
*/
|
||||
#define WATCHDOG_OFFSET 0x940000
|
||||
#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80950000 - 0x9000FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* During low_level init we store memory layout in memory at specific location
|
||||
*/
|
||||
#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
|
||||
#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
|
||||
#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
|
||||
|
|
@ -22,7 +22,6 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
|
|||
obj-$(CONFIG_E1000) += e1000.o
|
||||
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
|
||||
obj-$(CONFIG_EEPRO100) += eepro100.o
|
||||
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
|
||||
obj-$(CONFIG_ETHOC) += ethoc.o
|
||||
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
|
||||
obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
|
||||
|
|
|
|||
|
|
@ -1,654 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Cirrus Logic EP93xx ethernet MAC / MII driver.
|
||||
*
|
||||
* Copyright (C) 2010, 2009
|
||||
* Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*
|
||||
* Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
|
||||
* which is
|
||||
*
|
||||
* (C) Copyright 2002 2003
|
||||
* Adam Bezanson, Network Audio Technologies, Inc.
|
||||
* <bezanson@netaudiotech.com>
|
||||
*/
|
||||
|
||||
#include <command.h>
|
||||
#include <common.h>
|
||||
#include <log.h>
|
||||
#include <net.h>
|
||||
#include <asm/arch/ep93xx.h>
|
||||
#include <asm/io.h>
|
||||
#include <malloc.h>
|
||||
#include <miiphy.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/types.h>
|
||||
#include "ep93xx_eth.h"
|
||||
|
||||
#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
|
||||
#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
|
||||
|
||||
/* ep93xx_miiphy ops forward declarations */
|
||||
static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
|
||||
int reg);
|
||||
static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
|
||||
int reg, u16 value);
|
||||
|
||||
#if defined(EP93XX_MAC_DEBUG)
|
||||
/**
|
||||
* Dump ep93xx_mac values to the terminal.
|
||||
*/
|
||||
static void dump_dev(struct eth_device *dev)
|
||||
{
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int i;
|
||||
|
||||
printf("\ndump_dev()\n");
|
||||
printf(" rx_dq.base %p\n", priv->rx_dq.base);
|
||||
printf(" rx_dq.current %p\n", priv->rx_dq.current);
|
||||
printf(" rx_dq.end %p\n", priv->rx_dq.end);
|
||||
printf(" rx_sq.base %p\n", priv->rx_sq.base);
|
||||
printf(" rx_sq.current %p\n", priv->rx_sq.current);
|
||||
printf(" rx_sq.end %p\n", priv->rx_sq.end);
|
||||
|
||||
for (i = 0; i < NUMRXDESC; i++)
|
||||
printf(" rx_buffer[%2.d] %p\n", i, net_rx_packets[i]);
|
||||
|
||||
printf(" tx_dq.base %p\n", priv->tx_dq.base);
|
||||
printf(" tx_dq.current %p\n", priv->tx_dq.current);
|
||||
printf(" tx_dq.end %p\n", priv->tx_dq.end);
|
||||
printf(" tx_sq.base %p\n", priv->tx_sq.base);
|
||||
printf(" tx_sq.current %p\n", priv->tx_sq.current);
|
||||
printf(" tx_sq.end %p\n", priv->tx_sq.end);
|
||||
}
|
||||
|
||||
/**
|
||||
* Dump all RX status queue entries to the terminal.
|
||||
*/
|
||||
static void dump_rx_status_queue(struct eth_device *dev)
|
||||
{
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int i;
|
||||
|
||||
printf("\ndump_rx_status_queue()\n");
|
||||
printf(" descriptor address word1 word2\n");
|
||||
for (i = 0; i < NUMRXDESC; i++) {
|
||||
printf(" [ %p ] %08X %08X\n",
|
||||
priv->rx_sq.base + i,
|
||||
(priv->rx_sq.base + i)->word1,
|
||||
(priv->rx_sq.base + i)->word2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Dump all RX descriptor queue entries to the terminal.
|
||||
*/
|
||||
static void dump_rx_descriptor_queue(struct eth_device *dev)
|
||||
{
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int i;
|
||||
|
||||
printf("\ndump_rx_descriptor_queue()\n");
|
||||
printf(" descriptor address word1 word2\n");
|
||||
for (i = 0; i < NUMRXDESC; i++) {
|
||||
printf(" [ %p ] %08X %08X\n",
|
||||
priv->rx_dq.base + i,
|
||||
(priv->rx_dq.base + i)->word1,
|
||||
(priv->rx_dq.base + i)->word2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Dump all TX descriptor queue entries to the terminal.
|
||||
*/
|
||||
static void dump_tx_descriptor_queue(struct eth_device *dev)
|
||||
{
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int i;
|
||||
|
||||
printf("\ndump_tx_descriptor_queue()\n");
|
||||
printf(" descriptor address word1 word2\n");
|
||||
for (i = 0; i < NUMTXDESC; i++) {
|
||||
printf(" [ %p ] %08X %08X\n",
|
||||
priv->tx_dq.base + i,
|
||||
(priv->tx_dq.base + i)->word1,
|
||||
(priv->tx_dq.base + i)->word2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Dump all TX status queue entries to the terminal.
|
||||
*/
|
||||
static void dump_tx_status_queue(struct eth_device *dev)
|
||||
{
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int i;
|
||||
|
||||
printf("\ndump_tx_status_queue()\n");
|
||||
printf(" descriptor address word1\n");
|
||||
for (i = 0; i < NUMTXDESC; i++) {
|
||||
printf(" [ %p ] %08X\n",
|
||||
priv->rx_sq.base + i,
|
||||
(priv->rx_sq.base + i)->word1);
|
||||
}
|
||||
}
|
||||
#else
|
||||
#define dump_dev(x)
|
||||
#define dump_rx_descriptor_queue(x)
|
||||
#define dump_rx_status_queue(x)
|
||||
#define dump_tx_descriptor_queue(x)
|
||||
#define dump_tx_status_queue(x)
|
||||
#endif /* defined(EP93XX_MAC_DEBUG) */
|
||||
|
||||
/**
|
||||
* Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
|
||||
* it's cleared.
|
||||
*/
|
||||
static void ep93xx_mac_reset(struct eth_device *dev)
|
||||
{
|
||||
struct mac_regs *mac = GET_REGS(dev);
|
||||
uint32_t value;
|
||||
|
||||
debug("+ep93xx_mac_reset");
|
||||
|
||||
value = readl(&mac->selfctl);
|
||||
value |= SELFCTL_RESET;
|
||||
writel(value, &mac->selfctl);
|
||||
|
||||
while (readl(&mac->selfctl) & SELFCTL_RESET)
|
||||
; /* noop */
|
||||
|
||||
debug("-ep93xx_mac_reset");
|
||||
}
|
||||
|
||||
/* Eth device open */
|
||||
static int ep93xx_eth_open(struct eth_device *dev, struct bd_info *bd)
|
||||
{
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
struct mac_regs *mac = GET_REGS(dev);
|
||||
uchar *mac_addr = dev->enetaddr;
|
||||
int i;
|
||||
|
||||
debug("+ep93xx_eth_open");
|
||||
|
||||
/* Reset the MAC */
|
||||
ep93xx_mac_reset(dev);
|
||||
|
||||
/* Reset the descriptor queues' current and end address values */
|
||||
priv->tx_dq.current = priv->tx_dq.base;
|
||||
priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
|
||||
|
||||
priv->tx_sq.current = priv->tx_sq.base;
|
||||
priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
|
||||
|
||||
priv->rx_dq.current = priv->rx_dq.base;
|
||||
priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
|
||||
|
||||
priv->rx_sq.current = priv->rx_sq.base;
|
||||
priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
|
||||
|
||||
/*
|
||||
* Set the transmit descriptor and status queues' base address,
|
||||
* current address, and length registers. Set the maximum frame
|
||||
* length and threshold. Enable the transmit descriptor processor.
|
||||
*/
|
||||
writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
|
||||
writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
|
||||
writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
|
||||
|
||||
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
|
||||
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
|
||||
writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
|
||||
|
||||
writel(0x00040000, &mac->txdthrshld);
|
||||
writel(0x00040000, &mac->txststhrshld);
|
||||
|
||||
writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
|
||||
writel(BMCTL_TXEN, &mac->bmctl);
|
||||
|
||||
/*
|
||||
* Set the receive descriptor and status queues' base address,
|
||||
* current address, and length registers. Enable the receive
|
||||
* descriptor processor.
|
||||
*/
|
||||
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
|
||||
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
|
||||
writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
|
||||
|
||||
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
|
||||
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
|
||||
writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
|
||||
|
||||
writel(0x00040000, &mac->rxdthrshld);
|
||||
|
||||
writel(BMCTL_RXEN, &mac->bmctl);
|
||||
|
||||
writel(0x00040000, &mac->rxststhrshld);
|
||||
|
||||
/* Wait until the receive descriptor processor is active */
|
||||
while (!(readl(&mac->bmsts) & BMSTS_RXACT))
|
||||
; /* noop */
|
||||
|
||||
/*
|
||||
* Initialize the RX descriptor queue. Clear the TX descriptor queue.
|
||||
* Clear the RX and TX status queues. Enqueue the RX descriptor and
|
||||
* status entries to the MAC.
|
||||
*/
|
||||
for (i = 0; i < NUMRXDESC; i++) {
|
||||
/* set buffer address */
|
||||
(priv->rx_dq.base + i)->word1 = (uint32_t)net_rx_packets[i];
|
||||
|
||||
/* set buffer length, clear buffer index and NSOF */
|
||||
(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
|
||||
}
|
||||
|
||||
memset(priv->tx_dq.base, 0,
|
||||
(sizeof(struct tx_descriptor) * NUMTXDESC));
|
||||
memset(priv->rx_sq.base, 0,
|
||||
(sizeof(struct rx_status) * NUMRXDESC));
|
||||
memset(priv->tx_sq.base, 0,
|
||||
(sizeof(struct tx_status) * NUMTXDESC));
|
||||
|
||||
writel(NUMRXDESC, &mac->rxdqenq);
|
||||
writel(NUMRXDESC, &mac->rxstsqenq);
|
||||
|
||||
/* Set the primary MAC address */
|
||||
writel(AFP_IAPRIMARY, &mac->afp);
|
||||
writel(mac_addr[0] | (mac_addr[1] << 8) |
|
||||
(mac_addr[2] << 16) | (mac_addr[3] << 24),
|
||||
&mac->indad);
|
||||
writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
|
||||
|
||||
/* Turn on RX and TX */
|
||||
writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
|
||||
RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
|
||||
writel(TXCTL_STXON, &mac->txctl);
|
||||
|
||||
/* Dump data structures if we're debugging */
|
||||
dump_dev(dev);
|
||||
dump_rx_descriptor_queue(dev);
|
||||
dump_rx_status_queue(dev);
|
||||
dump_tx_descriptor_queue(dev);
|
||||
dump_tx_status_queue(dev);
|
||||
|
||||
debug("-ep93xx_eth_open");
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
|
||||
* registers.
|
||||
*/
|
||||
static void ep93xx_eth_close(struct eth_device *dev)
|
||||
{
|
||||
struct mac_regs *mac = GET_REGS(dev);
|
||||
|
||||
debug("+ep93xx_eth_close");
|
||||
|
||||
writel(0x00000000, &mac->rxctl);
|
||||
writel(0x00000000, &mac->txctl);
|
||||
|
||||
debug("-ep93xx_eth_close");
|
||||
}
|
||||
|
||||
/**
|
||||
* Copy a frame of data from the MAC into the protocol layer for further
|
||||
* processing.
|
||||
*/
|
||||
static int ep93xx_eth_rcv_packet(struct eth_device *dev)
|
||||
{
|
||||
struct mac_regs *mac = GET_REGS(dev);
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int len = -1;
|
||||
|
||||
debug("+ep93xx_eth_rcv_packet");
|
||||
|
||||
if (RX_STATUS_RFP(priv->rx_sq.current)) {
|
||||
if (RX_STATUS_RWE(priv->rx_sq.current)) {
|
||||
/*
|
||||
* We have a good frame. Extract the frame's length
|
||||
* from the current rx_status_queue entry, and copy
|
||||
* the frame's data into net_rx_packets[] of the
|
||||
* protocol stack. We track the total number of
|
||||
* bytes in the frame (nbytes_frame) which will be
|
||||
* used when we pass the data off to the protocol
|
||||
* layer via net_process_received_packet().
|
||||
*/
|
||||
len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
|
||||
|
||||
net_process_received_packet(
|
||||
(uchar *)priv->rx_dq.current->word1, len);
|
||||
|
||||
debug("reporting %d bytes...\n", len);
|
||||
} else {
|
||||
/* Do we have an erroneous packet? */
|
||||
pr_err("packet rx error, status %08X %08X",
|
||||
priv->rx_sq.current->word1,
|
||||
priv->rx_sq.current->word2);
|
||||
dump_rx_descriptor_queue(dev);
|
||||
dump_rx_status_queue(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear the associated status queue entry, and
|
||||
* increment our current pointers to the next RX
|
||||
* descriptor and status queue entries (making sure
|
||||
* we wrap properly).
|
||||
*/
|
||||
memset((void *)priv->rx_sq.current, 0,
|
||||
sizeof(struct rx_status));
|
||||
|
||||
priv->rx_sq.current++;
|
||||
if (priv->rx_sq.current >= priv->rx_sq.end)
|
||||
priv->rx_sq.current = priv->rx_sq.base;
|
||||
|
||||
priv->rx_dq.current++;
|
||||
if (priv->rx_dq.current >= priv->rx_dq.end)
|
||||
priv->rx_dq.current = priv->rx_dq.base;
|
||||
|
||||
/*
|
||||
* Finally, return the RX descriptor and status entries
|
||||
* back to the MAC engine, and loop again, checking for
|
||||
* more descriptors to process.
|
||||
*/
|
||||
writel(1, &mac->rxdqenq);
|
||||
writel(1, &mac->rxstsqenq);
|
||||
} else {
|
||||
len = 0;
|
||||
}
|
||||
|
||||
debug("-ep93xx_eth_rcv_packet %d", len);
|
||||
return len;
|
||||
}
|
||||
|
||||
/**
|
||||
* Send a block of data via ethernet.
|
||||
*/
|
||||
static int ep93xx_eth_send_packet(struct eth_device *dev,
|
||||
void * const packet, int const length)
|
||||
{
|
||||
struct mac_regs *mac = GET_REGS(dev);
|
||||
struct ep93xx_priv *priv = GET_PRIV(dev);
|
||||
int ret = -1;
|
||||
|
||||
debug("+ep93xx_eth_send_packet");
|
||||
|
||||
/* Parameter check */
|
||||
BUG_ON(packet == NULL);
|
||||
|
||||
/*
|
||||
* Initialize the TX descriptor queue with the new packet's info.
|
||||
* Clear the associated status queue entry. Enqueue the packet
|
||||
* to the MAC for transmission.
|
||||
*/
|
||||
|
||||
/* set buffer address */
|
||||
priv->tx_dq.current->word1 = (uint32_t)packet;
|
||||
|
||||
/* set buffer length and EOF bit */
|
||||
priv->tx_dq.current->word2 = length | TX_DESC_EOF;
|
||||
|
||||
/* clear tx status */
|
||||
priv->tx_sq.current->word1 = 0;
|
||||
|
||||
/* enqueue the TX descriptor */
|
||||
writel(1, &mac->txdqenq);
|
||||
|
||||
/* wait for the frame to become processed */
|
||||
while (!TX_STATUS_TXFP(priv->tx_sq.current))
|
||||
; /* noop */
|
||||
|
||||
if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
|
||||
pr_err("packet tx error, status %08X",
|
||||
priv->tx_sq.current->word1);
|
||||
dump_tx_descriptor_queue(dev);
|
||||
dump_tx_status_queue(dev);
|
||||
|
||||
/* TODO: Add better error handling? */
|
||||
goto eth_send_out;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
/* Fall through */
|
||||
|
||||
eth_send_out:
|
||||
debug("-ep93xx_eth_send_packet %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MII)
|
||||
int ep93xx_miiphy_initialize(struct bd_info * const bd)
|
||||
{
|
||||
int retval;
|
||||
struct mii_dev *mdiodev = mdio_alloc();
|
||||
if (!mdiodev)
|
||||
return -ENOMEM;
|
||||
strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
|
||||
mdiodev->read = ep93xx_miiphy_read;
|
||||
mdiodev->write = ep93xx_miiphy_write;
|
||||
|
||||
retval = mdio_register(mdiodev);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
|
||||
* allocated, if necessary, for the TX and RX descriptor and status queues,
|
||||
* as well as for received packets. The EP93XX MAC hardware is initialized.
|
||||
* Transmit and receive operations are enabled.
|
||||
*/
|
||||
int ep93xx_eth_initialize(u8 dev_num, int base_addr)
|
||||
{
|
||||
int ret = -1;
|
||||
struct eth_device *dev;
|
||||
struct ep93xx_priv *priv;
|
||||
|
||||
debug("+ep93xx_eth_initialize");
|
||||
|
||||
priv = malloc(sizeof(*priv));
|
||||
if (!priv) {
|
||||
pr_err("malloc() failed");
|
||||
goto eth_init_failed_0;
|
||||
}
|
||||
memset(priv, 0, sizeof(*priv));
|
||||
|
||||
priv->regs = (struct mac_regs *)base_addr;
|
||||
|
||||
priv->tx_dq.base = calloc(NUMTXDESC,
|
||||
sizeof(struct tx_descriptor));
|
||||
if (priv->tx_dq.base == NULL) {
|
||||
pr_err("calloc() failed");
|
||||
goto eth_init_failed_1;
|
||||
}
|
||||
|
||||
priv->tx_sq.base = calloc(NUMTXDESC,
|
||||
sizeof(struct tx_status));
|
||||
if (priv->tx_sq.base == NULL) {
|
||||
pr_err("calloc() failed");
|
||||
goto eth_init_failed_2;
|
||||
}
|
||||
|
||||
priv->rx_dq.base = calloc(NUMRXDESC,
|
||||
sizeof(struct rx_descriptor));
|
||||
if (priv->rx_dq.base == NULL) {
|
||||
pr_err("calloc() failed");
|
||||
goto eth_init_failed_3;
|
||||
}
|
||||
|
||||
priv->rx_sq.base = calloc(NUMRXDESC,
|
||||
sizeof(struct rx_status));
|
||||
if (priv->rx_sq.base == NULL) {
|
||||
pr_err("calloc() failed");
|
||||
goto eth_init_failed_4;
|
||||
}
|
||||
|
||||
dev = malloc(sizeof *dev);
|
||||
if (dev == NULL) {
|
||||
pr_err("malloc() failed");
|
||||
goto eth_init_failed_5;
|
||||
}
|
||||
memset(dev, 0, sizeof *dev);
|
||||
|
||||
dev->iobase = base_addr;
|
||||
dev->priv = priv;
|
||||
dev->init = ep93xx_eth_open;
|
||||
dev->halt = ep93xx_eth_close;
|
||||
dev->send = ep93xx_eth_send_packet;
|
||||
dev->recv = ep93xx_eth_rcv_packet;
|
||||
|
||||
sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
/* Done! */
|
||||
ret = 1;
|
||||
goto eth_init_done;
|
||||
|
||||
eth_init_failed_5:
|
||||
free(priv->rx_sq.base);
|
||||
/* Fall through */
|
||||
|
||||
eth_init_failed_4:
|
||||
free(priv->rx_dq.base);
|
||||
/* Fall through */
|
||||
|
||||
eth_init_failed_3:
|
||||
free(priv->tx_sq.base);
|
||||
/* Fall through */
|
||||
|
||||
eth_init_failed_2:
|
||||
free(priv->tx_dq.base);
|
||||
/* Fall through */
|
||||
|
||||
eth_init_failed_1:
|
||||
free(priv);
|
||||
/* Fall through */
|
||||
|
||||
eth_init_failed_0:
|
||||
/* Fall through */
|
||||
|
||||
eth_init_done:
|
||||
debug("-ep93xx_eth_initialize %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MII)
|
||||
|
||||
/**
|
||||
* Maximum MII address we support
|
||||
*/
|
||||
#define MII_ADDRESS_MAX 31
|
||||
|
||||
/**
|
||||
* Maximum MII register address we support
|
||||
*/
|
||||
#define MII_REGISTER_MAX 31
|
||||
|
||||
/**
|
||||
* Read a 16-bit value from an MII register.
|
||||
*/
|
||||
static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
|
||||
int reg)
|
||||
{
|
||||
unsigned short value = 0;
|
||||
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
|
||||
int ret = -1;
|
||||
uint32_t self_ctl;
|
||||
|
||||
debug("+ep93xx_miiphy_read");
|
||||
|
||||
/* Parameter checks */
|
||||
BUG_ON(bus->name == NULL);
|
||||
BUG_ON(addr > MII_ADDRESS_MAX);
|
||||
BUG_ON(reg > MII_REGISTER_MAX);
|
||||
|
||||
/*
|
||||
* Save the current SelfCTL register value. Set MAC to suppress
|
||||
* preamble bits. Wait for any previous MII command to complete
|
||||
* before issuing the new command.
|
||||
*/
|
||||
self_ctl = readl(&mac->selfctl);
|
||||
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
|
||||
writel(self_ctl & ~(1 << 8), &mac->selfctl);
|
||||
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
|
||||
|
||||
while (readl(&mac->miists) & MIISTS_BUSY)
|
||||
; /* noop */
|
||||
|
||||
/*
|
||||
* Issue the MII 'read' command. Wait for the command to complete.
|
||||
* Read the MII data value.
|
||||
*/
|
||||
writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
|
||||
&mac->miicmd);
|
||||
while (readl(&mac->miists) & MIISTS_BUSY)
|
||||
; /* noop */
|
||||
|
||||
value = (unsigned short)readl(&mac->miidata);
|
||||
|
||||
/* Restore the saved SelfCTL value and return. */
|
||||
writel(self_ctl, &mac->selfctl);
|
||||
|
||||
ret = 0;
|
||||
/* Fall through */
|
||||
|
||||
debug("-ep93xx_miiphy_read");
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a 16-bit value to an MII register.
|
||||
*/
|
||||
static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad,
|
||||
int reg, u16 value)
|
||||
{
|
||||
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
|
||||
int ret = -1;
|
||||
uint32_t self_ctl;
|
||||
|
||||
debug("+ep93xx_miiphy_write");
|
||||
|
||||
/* Parameter checks */
|
||||
BUG_ON(bus->name == NULL);
|
||||
BUG_ON(addr > MII_ADDRESS_MAX);
|
||||
BUG_ON(reg > MII_REGISTER_MAX);
|
||||
|
||||
/*
|
||||
* Save the current SelfCTL register value. Set MAC to suppress
|
||||
* preamble bits. Wait for any previous MII command to complete
|
||||
* before issuing the new command.
|
||||
*/
|
||||
self_ctl = readl(&mac->selfctl);
|
||||
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
|
||||
writel(self_ctl & ~(1 << 8), &mac->selfctl);
|
||||
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
|
||||
|
||||
while (readl(&mac->miists) & MIISTS_BUSY)
|
||||
; /* noop */
|
||||
|
||||
/* Issue the MII 'write' command. Wait for the command to complete. */
|
||||
writel((uint32_t)value, &mac->miidata);
|
||||
writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
|
||||
&mac->miicmd);
|
||||
while (readl(&mac->miists) & MIISTS_BUSY)
|
||||
; /* noop */
|
||||
|
||||
/* Restore the saved SelfCTL value and return. */
|
||||
writel(self_ctl, &mac->selfctl);
|
||||
|
||||
ret = 0;
|
||||
/* Fall through */
|
||||
|
||||
debug("-ep93xx_miiphy_write");
|
||||
return ret;
|
||||
}
|
||||
#endif /* defined(CONFIG_MII) */
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*/
|
||||
|
||||
#ifndef _EP93XX_ETH_H
|
||||
#define _EP93XX_ETH_H
|
||||
|
||||
#include <net.h>
|
||||
|
||||
/**
|
||||
* #define this to dump device status and queue info during initialization and
|
||||
* following errors.
|
||||
*/
|
||||
#undef EP93XX_MAC_DEBUG
|
||||
|
||||
/**
|
||||
* Number of descriptor and status entries in our RX queues.
|
||||
* It must be power of 2 !
|
||||
*/
|
||||
#define NUMRXDESC PKTBUFSRX
|
||||
|
||||
/**
|
||||
* Number of descriptor and status entries in our TX queues.
|
||||
*/
|
||||
#define NUMTXDESC 1
|
||||
|
||||
/**
|
||||
* 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
|
||||
*/
|
||||
#define TXSTARTMAX 944
|
||||
|
||||
/**
|
||||
* Receive descriptor queue entry
|
||||
*/
|
||||
struct rx_descriptor {
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
};
|
||||
|
||||
/**
|
||||
* Receive status queue entry
|
||||
*/
|
||||
struct rx_status {
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
};
|
||||
|
||||
#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
|
||||
#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
|
||||
#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
|
||||
|
||||
/**
|
||||
* Transmit descriptor queue entry
|
||||
*/
|
||||
struct tx_descriptor {
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
};
|
||||
|
||||
#define TX_DESC_EOF (1 << 31)
|
||||
|
||||
/**
|
||||
* Transmit status queue entry
|
||||
*/
|
||||
struct tx_status {
|
||||
uint32_t word1;
|
||||
};
|
||||
|
||||
#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
|
||||
#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
|
||||
|
||||
/**
|
||||
* Transmit descriptor queue
|
||||
*/
|
||||
struct tx_descriptor_queue {
|
||||
struct tx_descriptor *base;
|
||||
struct tx_descriptor *current;
|
||||
struct tx_descriptor *end;
|
||||
};
|
||||
|
||||
/**
|
||||
* Transmit status queue
|
||||
*/
|
||||
struct tx_status_queue {
|
||||
struct tx_status *base;
|
||||
volatile struct tx_status *current;
|
||||
struct tx_status *end;
|
||||
};
|
||||
|
||||
/**
|
||||
* Receive descriptor queue
|
||||
*/
|
||||
struct rx_descriptor_queue {
|
||||
struct rx_descriptor *base;
|
||||
struct rx_descriptor *current;
|
||||
struct rx_descriptor *end;
|
||||
};
|
||||
|
||||
/**
|
||||
* Receive status queue
|
||||
*/
|
||||
struct rx_status_queue {
|
||||
struct rx_status *base;
|
||||
volatile struct rx_status *current;
|
||||
struct rx_status *end;
|
||||
};
|
||||
|
||||
/**
|
||||
* EP93xx MAC private data structure
|
||||
*/
|
||||
struct ep93xx_priv {
|
||||
struct rx_descriptor_queue rx_dq;
|
||||
struct rx_status_queue rx_sq;
|
||||
void *rx_buffer[NUMRXDESC];
|
||||
|
||||
struct tx_descriptor_queue tx_dq;
|
||||
struct tx_status_queue tx_sq;
|
||||
|
||||
struct mac_regs *regs;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -14,7 +14,6 @@ obj-$(CONFIG_USB_ATMEL) += ohci-at91.o
|
|||
obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
|
||||
obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
|
||||
obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
|
||||
obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
|
||||
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
|
||||
obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o
|
||||
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
|
||||
|
|
|
|||
|
|
@ -1,37 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013
|
||||
* Sergey Kostanbaev < sergey.kostanbaev <at> fairwaves.ru >
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/ep93xx.h>
|
||||
|
||||
int usb_cpu_init(void)
|
||||
{
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
unsigned long pwr = readl(&syscon->pwrcnt);
|
||||
writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_cpu_stop(void)
|
||||
{
|
||||
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
|
||||
unsigned long pwr = readl(&syscon->pwrcnt);
|
||||
writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_cpu_init_fail(void)
|
||||
{
|
||||
return usb_cpu_stop();
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
|
||||
Loading…
Reference in New Issue
Block a user