liteeth: LiteX Ethernet device
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
Joel Stanley
Tom Rini
parent
597e7b784d
commit
3167b4d722
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@ -438,6 +438,11 @@ config KSZ9477
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This driver implements a DSA switch driver for the KSZ9477 family
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of GbE switches using the I2C interface.
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config LITEETH
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bool "LiteX LiteEth Ethernet MAC"
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help
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Driver for the LiteEth Ethernet MAC from LiteX.
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config MVGBE
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bool "Marvell Orion5x/Kirkwood network interface support"
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depends on ARCH_KIRKWOOD || ARCH_ORION5X
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@ -47,6 +47,7 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
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obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
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obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
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obj-$(CONFIG_KSZ9477) += ksz9477.o
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obj-$(CONFIG_LITEETH) += liteeth.o
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obj-$(CONFIG_MACB) += macb.o
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obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
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obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
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214
drivers/net/liteeth.c
Normal file
214
drivers/net/liteeth.c
Normal file
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@ -0,0 +1,214 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* LiteX Liteeth Ethernet
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*
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* Copyright 2021 Joel Stanley <joel@jms.id.au>, IBM Corp.
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*/
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#include <linux/litex.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <net.h>
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#define LITEETH_WRITER_SLOT 0x00
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#define LITEETH_WRITER_LENGTH 0x04
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#define LITEETH_WRITER_ERRORS 0x08
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#define LITEETH_WRITER_EV_STATUS 0x0C
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#define LITEETH_WRITER_EV_PENDING 0x10
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#define LITEETH_WRITER_EV_ENABLE 0x14
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#define LITEETH_READER_START 0x18
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#define LITEETH_READER_READY 0x1C
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#define LITEETH_READER_LEVEL 0x20
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#define LITEETH_READER_SLOT 0x24
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#define LITEETH_READER_LENGTH 0x28
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#define LITEETH_READER_EV_STATUS 0x2C
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#define LITEETH_READER_EV_PENDING 0x30
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#define LITEETH_READER_EV_ENABLE 0x34
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#define LITEETH_PREAMBLE_CRC 0x38
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#define LITEETH_PREAMBLE_ERRORS 0x3C
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#define LITEETH_CRC_ERRORS 0x40
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struct liteeth {
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struct udevice *dev;
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void __iomem *base;
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u32 slot_size;
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/* Tx */
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u32 tx_slot;
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u32 num_tx_slots;
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void __iomem *tx_base;
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/* Rx */
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u32 rx_slot;
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u32 num_rx_slots;
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void __iomem *rx_base;
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};
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static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct liteeth *priv = dev_get_priv(dev);
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u8 rx_slot;
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int len;
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if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {
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debug("liteeth: No packet ready\n");
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return -EAGAIN;
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}
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rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);
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len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
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debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len);
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*packetp = priv->rx_base + rx_slot * priv->slot_size;
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return len;
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}
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static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct liteeth *priv = dev_get_priv(dev);
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litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
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return 0;
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}
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static int liteeth_start(struct udevice *dev)
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{
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struct liteeth *priv = dev_get_priv(dev);
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/* Clear pending events */
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litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
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litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1);
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/* Enable events */
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litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1);
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litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1);
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return 0;
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}
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static void liteeth_stop(struct udevice *dev)
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{
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struct liteeth *priv = dev_get_priv(dev);
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litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);
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litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);
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}
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static int liteeth_send(struct udevice *dev, void *packet, int len)
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{
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struct liteeth *priv = dev_get_priv(dev);
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void __iomem *txbuffer;
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if (!litex_read8(priv->base + LITEETH_READER_READY)) {
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printf("liteeth: reader not ready\n");
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return -EAGAIN;
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}
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/* Reject oversize packets */
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if (unlikely(len > priv->slot_size))
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return -EMSGSIZE;
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txbuffer = priv->tx_base + priv->tx_slot * priv->slot_size;
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memcpy_toio(txbuffer, packet, len);
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litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot);
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litex_write16(priv->base + LITEETH_READER_LENGTH, len);
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litex_write8(priv->base + LITEETH_READER_START, 1);
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priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
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return 0;
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}
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static void liteeth_setup_slots(struct liteeth *priv)
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{
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int err;
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err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,rx-slots", &priv->num_rx_slots);
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if (err) {
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dev_dbg(priv->dev, "unable to get litex,rx-slots, using 2\n");
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priv->num_rx_slots = 2;
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}
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err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,tx-slots", &priv->num_tx_slots);
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if (err) {
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dev_dbg(priv->dev, "unable to get litex,tx-slots, using 2\n");
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priv->num_tx_slots = 2;
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}
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err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,slot-size", &priv->slot_size);
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if (err) {
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dev_dbg(priv->dev, "unable to get litex,slot-size, using 0x800\n");
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priv->slot_size = 0x800;
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}
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}
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static int liteeth_remove(struct udevice *dev)
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{
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liteeth_stop(dev);
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return 0;
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}
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static const struct eth_ops liteeth_ops = {
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.start = liteeth_start,
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.stop = liteeth_stop,
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.send = liteeth_send,
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.recv = liteeth_recv,
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.free_pkt = liteeth_free_pkt,
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};
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static int liteeth_of_to_plat(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct liteeth *priv = dev_get_priv(dev);
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void __iomem *buf_base;
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pdata->iobase = dev_read_addr(dev);
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priv->dev = dev;
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priv->base = dev_remap_addr_name(dev, "mac");
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if (!priv->base) {
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dev_err(dev, "failed to map registers\n");
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return -EINVAL;
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}
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buf_base = dev_remap_addr_name(dev, "buffer");
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if (!buf_base) {
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dev_err(dev, "failed to map buffer\n");
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return -EINVAL;
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}
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liteeth_setup_slots(priv);
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/* Rx slots */
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priv->rx_base = buf_base;
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priv->rx_slot = 0;
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/* Tx slots come after Rx slots */
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priv->tx_base = buf_base + priv->num_rx_slots * priv->slot_size;
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priv->tx_slot = 0;
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return 0;
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}
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static const struct udevice_id liteeth_ids[] = {
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{ .compatible = "litex,liteeth" },
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{}
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};
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U_BOOT_DRIVER(liteeth) = {
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.name = "liteeth",
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.id = UCLASS_ETH,
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.of_match = liteeth_ids,
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.of_to_plat = liteeth_of_to_plat,
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.plat_auto = sizeof(struct eth_pdata),
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.remove = liteeth_remove,
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.ops = &liteeth_ops,
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.priv_auto = sizeof(struct liteeth),
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};
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84
include/linux/litex.h
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84
include/linux/litex.h
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@ -0,0 +1,84 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common LiteX header providing
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* helper functions for accessing CSRs.
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*
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* Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
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*/
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#ifndef _LINUX_LITEX_H
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#define _LINUX_LITEX_H
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#include <linux/io.h>
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#include <asm/byteorder.h>
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static inline void _write_litex_subregister(u32 val, void __iomem *addr)
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{
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writel((u32 __force)cpu_to_le32(val), addr);
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}
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static inline u32 _read_litex_subregister(void __iomem *addr)
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{
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return le32_to_cpu((__le32 __force)readl(addr));
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}
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/*
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* LiteX SoC Generator, depending on the configuration, can split a single
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* logical CSR (Control&Status Register) into a series of consecutive physical
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* registers.
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*
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* For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
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* 32-bit wide logical CSR will be laid out as four 32-bit physical
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* subregisters, each one containing one byte of meaningful data.
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*
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* For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
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* means that only larger-than-32-bit CSRs will be split across multiple
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* subregisters (e.g., a 64-bit CSR will be spread across two consecutive
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* 32-bit subregisters).
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*
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* For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
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*/
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static inline void litex_write8(void __iomem *reg, u8 val)
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{
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_write_litex_subregister(val, reg);
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}
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static inline void litex_write16(void __iomem *reg, u16 val)
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{
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_write_litex_subregister(val, reg);
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}
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static inline void litex_write32(void __iomem *reg, u32 val)
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{
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_write_litex_subregister(val, reg);
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}
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static inline void litex_write64(void __iomem *reg, u64 val)
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{
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_write_litex_subregister(val >> 32, reg);
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_write_litex_subregister(val, reg + 4);
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}
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static inline u8 litex_read8(void __iomem *reg)
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{
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return _read_litex_subregister(reg);
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}
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static inline u16 litex_read16(void __iomem *reg)
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{
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return _read_litex_subregister(reg);
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}
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static inline u32 litex_read32(void __iomem *reg)
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{
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return _read_litex_subregister(reg);
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}
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static inline u64 litex_read64(void __iomem *reg)
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{
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return ((u64)_read_litex_subregister(reg) << 32) |
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_read_litex_subregister(reg + 4);
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}
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#endif /* _LINUX_LITEX_H */
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