arm: mvebu: Add Allied Telesis x240 board
The x240 and SE240 are a series of L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
Stefan Roese
parent
e6719fab6c
commit
4c97c4b590
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@ -305,7 +305,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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cn9132-db-B.dtb \
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cn9130-crb-A.dtb \
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cn9130-crb-B.dtb \
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ac5-98dx35xx-rd.dtb
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ac5-98dx35xx-rd.dtb \
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ac5-98dx35xx-atl-x240.dtb
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endif
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dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
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212
arch/arm/dts/ac5-98dx35xx-atl-x240.dts
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212
arch/arm/dts/ac5-98dx35xx-atl-x240.dts
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@ -0,0 +1,212 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "ac5-98dx35xx.dtsi"
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/ {
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model = "Allied Telesis x240";
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compatible = "alliedtelesis,x240", "marvell,ac5x", "marvell,ac5";
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aliases {
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serial0 = &uart0;
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spiflash0 = &spiflash0;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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spi0 = &spi0;
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i2c0 = &i2c0;
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usb0 = &usb0;
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pinctrl0 = &pinctrl0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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boot-board {
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compatible = "atl,boot-board";
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present-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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override-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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fault {
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label = "fault:red";
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gpios = <&system_gpio 11 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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};
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};
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&nand {
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@user {
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reg = <0x00000000 0x10000000>;
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label = "user";
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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mux@71 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9546";
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* MPP36 */
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status = "okay";
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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rtc@68 {
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compatible = "adi,max31331";
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reg = <0x68>;
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};
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system_gpio: gpio@27 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells= <2>;
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reg = <0x27>;
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interrupt-parent = <&gpio0>;
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interrupts = <25 IRQ_TYPE_LEVEL_LOW>; /* MPP25 */
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};
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};
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};
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};
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&spi0 {
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status = "okay";
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spiflash0: flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&gpio0 {
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phy-reset {
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gpio-hog;
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gpios = <19 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "phy-reset";
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};
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usb-en {
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gpio-hog;
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gpios = <28 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-en";
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};
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led-oe-n {
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gpio-hog;
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gpios = <23 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "led-oe-n";
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};
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};
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&gpio1 {
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nand-protect {
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gpio-hog;
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gpios = <8 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "nand-protect";
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};
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};
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&pinctrl0 {
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/*
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* MPP Bus: MPP#
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* NF_IO [0-7]
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* NF_Wen [8]
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* NF_ALE [9]
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* NF_CLE [10]
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* NF_Cen [11]
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* QSPI_SCK/SPI0_SCK [12]
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* QSPI_CSn/SPI0_CSn [13]
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* QSPI_DIO[0]/SPI0_MOSI [14]
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* QSPI_DIO[1]/SPI0_MISO [15]
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* NF_Ren [16]
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* NF_RBn [17]
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* WD_INTn [18]
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* B_B_OVRIDE_N [19]
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* GREEN_SW_N [20]
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* PHY_INT_N[0] [21]
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* SPI_WPn [22]
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* LED_OE_N [23]
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* USB_PWR_FLT_N [24]
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* SFP_INT_N [25]
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* I2C0_SCL [26]
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* I2C0_SDA [27]
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* USB_EN [28]
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* MONITOR_INT_N [29]
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* XM1_MDC [30]
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* XM1_MDIO [31]
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* UA0_RXD [32]
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* UA0_TXD [33]
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* PHY_RST0n [34]
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* TPM_INT_N [35]
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* I2CMUX_RESET_N [36]
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* SPI_SRAM_SEL_N [37]
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* B_B_PRESENT [38]
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* SPI_FLASH_SEL_N [39]
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* NF_WP_N [40]
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* POE_INT_N [41]
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* PoE_RST_N [42]
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* LED0_CLK [43]
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* LED0_STB [44]
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* LED0_DATA [45]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 1 1 1 1 0xff 0xff 0 0
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0 0 0 0 0 0 1 1 0 0
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1 1 1 1 0 0 0 0 0 0
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0 0 0 1 1 1 >;
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nand_pins: nand-pins {
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marvell,pins = <0 1 2 3 4 5 6 7 8 9 10 11 16 17>;
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marvell,function = <2>;
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};
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};
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@ -202,6 +202,10 @@ config TARGET_X530
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bool "Support Allied Telesis x530"
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select 88F6820
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config TARGET_X240
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bool "Support Allied Telesis x240"
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select ALLEYCAT_5
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config TARGET_DB_XC3_24G4XG
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bool "Support DB-XC3-24G4XG"
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select 98DX3336
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@ -274,6 +278,7 @@ config SYS_BOARD
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default "theadorable" if TARGET_THEADORABLE
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default "a38x" if TARGET_CONTROLCENTERDC
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default "x530" if TARGET_X530
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default "x240" if TARGET_X240
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default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
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default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
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default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
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@ -297,6 +302,7 @@ config SYS_CONFIG_NAME
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default "turris_mox" if TARGET_TURRIS_MOX
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default "controlcenterdc" if TARGET_CONTROLCENTERDC
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default "x530" if TARGET_X530
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default "x240" if TARGET_X240
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default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
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default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
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default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
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@ -320,6 +326,7 @@ config SYS_VENDOR
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default "CZ.NIC" if TARGET_TURRIS_MOX
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default "gdsys" if TARGET_CONTROLCENTERDC
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default "alliedtelesis" if TARGET_X530
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default "alliedtelesis" if TARGET_X240
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default "mikrotik" if TARGET_CRS3XX_98DX3236
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default "Marvell" if TARGET_MVEBU_ALLEYCAT5
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7
board/alliedtelesis/x240/MAINTAINERS
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7
board/alliedtelesis/x240/MAINTAINERS
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@ -0,0 +1,7 @@
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X240 BOARD
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: board/alliedtelesis/x240/
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F: arch/arm/dts/ac5-98dx35xx-rd.dts
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F: include/configs/x240.h
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F: configs/x240_defconfig
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6
board/alliedtelesis/x240/Makefile
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6
board/alliedtelesis/x240/Makefile
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2022 Allied Telesis
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#
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obj-y += x240.o
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13
board/alliedtelesis/x240/x240.c
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13
board/alliedtelesis/x240/x240.c
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@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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86
configs/x240_defconfig
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86
configs/x240_defconfig
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@ -0,0 +1,86 @@
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CONFIG_ARM=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_TEXT_BASE=0x200000000
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CONFIG_SYS_MALLOC_LEN=0x900000
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
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CONFIG_TARGET_X240=y
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CONFIG_ENV_SIZE=0x10000
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CONFIG_ENV_OFFSET=0x00f80000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="ac5-98dx35xx-atl-x240"
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CONFIG_SYS_LOAD_ADDR=0x220000000
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_UBI=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_CLK=y
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CONFIG_CLK_MVEBU=y
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CONFIG_GPIO_HOG=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_MVTWSI=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MISC=y
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# CONFIG_MMC is not set
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_PXA3XX=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SPI_FLASH_SFDP_SUPPORT=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_PHY=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_ARMADA_8K=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_MAX313XX=y
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CONFIG_DM_SCSI=y
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CONFIG_SYS_NS16550=y
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CONFIG_MVEBU_A3700_SPI=y
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CONFIG_DM_THERMAL=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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# CONFIG_FAT_WRITE is not set
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37
include/configs/x240.h
Normal file
37
include/configs/x240.h
Normal file
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@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 Allied Telesis
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*/
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#ifndef __X240_H_
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#define __X240_H_
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#include <asm/arch/soc.h>
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/* additions for new ARM relocation support */
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#define CFG_SYS_SDRAM_BASE 0x200000000
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#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
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115200, 230400, 460800, 921600 }
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/* Default Env vars */
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#define CFG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"kernel_addr_r=0x202000000\0" \
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"fdt_addr_r=0x201000000\0" \
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"ramdisk_addr_r=0x206000000\0" \
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"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CFG_SYS_TCLK 325000000
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#endif /* __X240_H_ */
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