board: gateworks: venice: add imx8mm-gw7905-0x support
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard. The GW700x SOM contains the following: - i.MX8M Mini SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - RGMII PHY - PMIC - SOM connector providing: - FEC GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 2.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
parent
8aa5e6973c
commit
52346fcb90
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@ -1046,6 +1046,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-venice-gw7902.dtb \
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imx8mm-venice-gw7903.dtb \
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imx8mm-venice-gw7904.dtb \
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imx8mm-venice-gw7905-0x.dtb \
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imx8mm-verdin-wifi-dev.dtb \
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phycore-imx8mm.dtb \
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imx8mn-bsh-smm-s2.dtb \
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58
arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi
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58
arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 Gateworks Corporation
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*/
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#include "imx8mm-venice-gw700x-u-boot.dtsi"
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&gpio1 {
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app_gpioa {
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gpio-hog;
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input;
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gpios = <13 GPIO_ACTIVE_HIGH>;
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line-name = "gpioa";
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};
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app_gpiob {
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gpio-hog;
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input;
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gpios = <14 GPIO_ACTIVE_HIGH>;
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line-name = "gpiob";
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};
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};
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&gpio4 {
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pci_usb_sel {
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gpio-hog;
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output-low;
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gpios = <3 GPIO_ACTIVE_HIGH>;
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line-name = "pci_usb_sel";
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};
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pci_wdis {
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gpio-hog;
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output-high;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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line-name = "pci_wdis#";
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};
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};
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&gpio5 {
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app_gpioc {
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gpio-hog;
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input;
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gpios = <4 GPIO_ACTIVE_HIGH>;
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line-name = "gpioc";
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};
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app_gpiod {
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gpio-hog;
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input;
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gpios = <5 GPIO_ACTIVE_HIGH>;
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line-name = "gpiod";
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};
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};
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/* Disable SOM interfaces not used on baseboard */
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&fec1 {
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status = "disabled";
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};
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28
arch/arm/dts/imx8mm-venice-gw7905-0x.dts
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arch/arm/dts/imx8mm-venice-gw7905-0x.dts
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Gateworks Corporation
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*/
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/dts-v1/;
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#include "imx8mm.dtsi"
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#include "imx8mm-venice-gw700x.dtsi"
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#include "imx8mm-venice-gw7905.dtsi"
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/ {
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model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit";
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compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm";
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chosen {
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stdout-path = &uart2;
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};
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};
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/* Disable SOM interfaces not used on baseboard */
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&fec1 {
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status = "disabled";
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};
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&usdhc1 {
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status = "disabled";
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};
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303
arch/arm/dts/imx8mm-venice-gw7905.dtsi
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arch/arm/dts/imx8mm-venice-gw7905.dtsi
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@ -0,0 +1,303 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Gateworks Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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/ {
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led-controller {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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pps {
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compatible = "pps-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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reg_usb2_vbus: regulator-usb2-vbus {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb2_en>;
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compatible = "regulator-fixed";
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regulator-name = "usb2_vbus";
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gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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compatible = "regulator-fixed";
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regulator-name = "SD2_3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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/* off-board header */
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&gpio1 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "gpioa", "gpiob", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio4 {
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gpio-line-names =
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"", "", "", "pci_usb_sel",
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"", "", "", "pci_wdis#",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio5 {
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gpio-line-names =
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"", "", "", "",
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"gpioc", "gpiod", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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eeprom@52 {
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compatible = "atmel,24c32";
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reg = <0x52>;
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pagesize = <32>;
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};
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};
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/* off-board header */
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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fsl,clkreq-unsupported;
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clocks = <&pcie0_refclk>;
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clock-names = "ref";
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status = "okay";
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* GPS */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* USB1 - Type C front panel SINK port J14 */
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&usbotg1 {
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dr_mode = "peripheral";
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status = "okay";
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};
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/* USB2 4-port USB3.0 HUB:
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* P1 - USBC connector (host only)
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* P2 - USB2 test connector
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* P3 - miniPCIe full card
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* P4 - miniPCIe half card
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*/
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&usbotg2 {
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dr_mode = "host";
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vbus-supply = <®_usb2_vbus>;
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status = "okay";
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};
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/* microSD */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */
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MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */
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MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */
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MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */
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MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */
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MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
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>;
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};
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pinctrl_gpio_leds: gpioledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */
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MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
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MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
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MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
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>;
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};
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pinctrl_pcie0: pciegrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106
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>;
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};
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pinctrl_pps: ppsgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106
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>;
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};
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pinctrl_reg_usb2_en: regusb2grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
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>;
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};
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pinctrl_spi2: spi2grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
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MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
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MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
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MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
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>;
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};
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};
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@ -75,7 +75,7 @@ CONFIG_CMD_EXT4_WRITE=y
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# CONFIG_SPL_EFI_PARTITION is not set
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904"
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CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904 imx8mm-venice-gw7905-0x"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_SYS_MMC_ENV_DEV=2
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