Squashed 'dts/upstream/' content from commit aaba2d45dc2a

git-subtree-dir: dts/upstream
git-subtree-split: aaba2d45dc2a1b3bbb710f2a3808ee1c9f340abe
This commit is contained in:
Tom Rini 2024-02-29 12:33:36 -05:00
commit 53633a893a
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.*
!.gitignore
*.dtb

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# SPDX-License-Identifier: GPL-2.0-only
*.example.dts
/processed-schema*.yaml
/processed-schema*.json
#
# We don't want to ignore the following even if they are dot-files
#
!.yamllint

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extends: relaxed
rules:
quoted-strings:
required: only-when-needed
extra-allowed:
- '[$^,[]'
- '^/$'
line-length:
# 80 chars should be enough, but don't fail if a line is longer
max: 110
allow-non-breakable-words: true
level: warning
braces:
min-spaces-inside: 0
max-spaces-inside: 1
min-spaces-inside-empty: 0
max-spaces-inside-empty: 0
brackets:
min-spaces-inside: 0
max-spaces-inside: 1
min-spaces-inside-empty: 0
max-spaces-inside-empty: 0
colons: {max-spaces-before: 0, max-spaces-after: 1}
commas: {min-spaces-after: 1, max-spaces-after: 1}
comments:
require-starting-space: true
min-spaces-from-content: 1
comments-indentation: disable
document-start:
present: true
empty-lines:
max: 3
max-end: 1
empty-values:
forbid-in-block-mappings: true
forbid-in-flow-mappings: true
hyphens:
max-spaces-after: 1
indentation:
spaces: 2
indent-sequences: true
check-multi-line-strings: false
trailing-spaces: false

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.. SPDX-License-Identifier: GPL-2.0
===================
Devicetree (DT) ABI
===================
I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit
summary document:
"That still leaves the question of, what does a stable binding look
like? Certainly a stable binding means that a newer kernel will not
break on an older device tree, but that doesn't mean the binding is
frozen for all time. Grant said there are ways to change bindings that
don't result in breakage. For instance, if a new property is added,
then default to the previous behaviour if it is missing. If a binding
truly needs an incompatible change, then change the compatible string
at the same time. The driver can bind against both the old and the
new. These guidelines aren't new, but they desperately need to be
documented."
II. General binding rules
1) Maintainers, don't let perfect be the enemy of good. Don't hold up a
binding because it isn't perfect.
2) Use specific compatible strings so that if we need to add a feature (DMA)
in the future, we can create a new compatible string. See I.
3) Bindings can be augmented, but the driver shouldn't break when given
the old binding. ie. add additional properties, but don't change the
meaning of an existing property. For drivers, default to the original
behaviour when a newly added property is missing.
4) Don't submit bindings for staging or unstable. That will be decided by
the devicetree maintainers *after* discussion on the mailinglist.
III. Notes
1) This document is intended as a general familiarization with the process as
decided at the 2013 Kernel Summit. When in doubt, the current word of the
devicetree maintainers overrules this document. In that situation, a patch
updating this document would be appreciated.

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# SPDX-License-Identifier: GPL-2.0
DT_DOC_CHECKER ?= dt-doc-validate
DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
DT_SCHEMA_LINT = $(shell which yamllint || \
echo "warning: python package 'yamllint' not installed, skipping" >&2)
DT_SCHEMA_MIN_VERSION = 2023.9
PHONY += check_dtschema_version
check_dtschema_version:
@which $(DT_DOC_CHECKER) >/dev/null || \
{ echo "Error: '$(DT_DOC_CHECKER)' not found!" >&2; \
echo "Ensure dtschema python package is installed and in your PATH." >&2; \
echo "Current PATH is:" >&2; \
echo "$$PATH" >&2; false; }
@{ echo $(DT_SCHEMA_MIN_VERSION); \
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
quiet_cmd_extract_ex = DTEX $@
cmd_extract_ex = $(DT_EXTRACT_EX) $< > $@
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
$(call if_changed,extract_ex)
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' \)
find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
xargs -n200 -P$$(nproc) \
$(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = ($(find_cmd) | \
xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)) || true
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(find_all_cmd) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f
define rule_chkdt
$(if $(DT_SCHEMA_LINT),$(call cmd,yamllint),)
$(call cmd,chk_bindings)
$(call cmd,mk_schema)
endef
DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
-Wno-graph_child_address \
-Wno-interrupt_provider \
-Wno-unique_unit_address \
-Wunique_unit_address_if_enabled
# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=
$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)
always-y += processed-schema.json
always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dts, $(CHK_DT_DOCS))
always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, $(CHK_DT_DOCS))
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
# build artifacts here before they are processed by scripts/Makefile.clean
clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
-name '*.example.dtb' \) -delete 2>/dev/null)
dt_compatible_check: $(obj)/processed-schema.json
$(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) | xargs dt-check-compatible -v -s $<

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* ARC HS Performance Counters
The ARC HS can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
are 100+ hardware conditions dynamically mapped to up to 32 counters.
It also supports overflow interrupts.
Required properties:
- compatible : should contain
"snps,archs-pct"
Example:
pmu {
compatible = "snps,archs-pct";
};

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Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
---------------------------------------------------------------------------
SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
Required root node properties:
- compatible = "snps,axs101", "snps,arc-sdp";

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Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
---------------------------------------------------------------------------
SDP Main Board with an AXC003 FPGA Card which can contain various flavours of
HS38x cores.
Required root node properties:
- compatible = "snps,axs103", "snps,arc-sdp";

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EZchip NPS Network Processor Platforms Device Tree Bindings
---------------------------------------------------------------------------
Appliance main board with NPS400 ASIC.
Required root node properties:
- compatible = "ezchip,arc-nps";

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Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
---------------------------------------------------------------------------
ARC HSDK Board with quad-core ARC HS38x4 in silicon.
Required root node properties:
- compatible = "snps,hsdk";

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* ARC Performance Counters
The ARC700 can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
are 100+ hardware conditions dynamically mapped to up to 32 counters
Note that:
* The ARC 700 PCT does not support interrupts; although HW events may be
counted, the HW events themselves cannot serve as a trigger for a sample.
Required properties:
- compatible : should contain
"snps,arc700-pct"
Example:
pmu {
compatible = "snps,arc700-pct";
};

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# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/actions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi platforms
maintainers:
- Andreas Färber <afaerber@suse.de>
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
# The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
- items:
- enum:
- allo,sparky # Allo.com Sparky
- cubietech,cubieboard6 # Cubietech CubieBoard6
- roseapplepi,roseapplepi # RoseapplePi.org RoseapplePi
- const: actions,s500
- items:
- enum:
- caninos,labrador-base-m # Labrador Base Board M v1
- const: caninos,labrador-v2 # Labrador Core v2
- const: actions,s500
- items:
- enum:
- lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B
- const: lemaker,guitar
- const: actions,s500
# The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC.
- items:
- enum:
- caninos,labrador-base-m2 # Labrador Base Board M v2
- const: caninos,labrador-v3 # Labrador Core v3
- const: actions,s700
- items:
- enum:
- cubietech,cubieboard7 # Cubietech CubieBoard7
- const: actions,s700
# The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
- items:
- enum:
- ucrobotics,bubblegum-96 # uCRobotics Bubblegum-96
- const: actions,s900
additionalProperties: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/airoha.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Airoha SoC based Platforms
maintainers:
- Felix Fietkau <nbd@nbd.name>
- John Crispin <john@phrozen.org>
description:
Boards with an Airoha SoC shall have the following properties.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- airoha,en7523-evb
- const: airoha,en7523
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/altera.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera's SoCFPGA platform
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Arria 5 boards
items:
- enum:
- altr,socfpga-arria5-socdk
- const: altr,socfpga-arria5
- const: altr,socfpga
- description: Arria 10 boards
items:
- enum:
- altr,socfpga-arria10-socdk
- const: altr,socfpga-arria10
- const: altr,socfpga
- description: Mercury+ AA1 boards
items:
- enum:
- enclustra,mercury-pe1
- google,chameleon-v3
- const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
- description: Cyclone 5 boards
items:
- enum:
- altr,socfpga-cyclone5-socdk
- denx,mcvevk
- ebv,socrates
- macnica,sodia
- novtech,chameleon96
- samtec,vining
- terasic,de0-atlas
- terasic,socfpga-cyclone5-sockit
- const: altr,socfpga-cyclone5
- const: altr,socfpga
- description: Stratix 10 boards
items:
- enum:
- altr,socfpga-stratix10-socdk
- altr,socfpga-stratix10-swvp
- const: altr,socfpga-stratix10
- description: SoCFPGA VT
items:
- const: altr,socfpga-vt
- const: altr,socfpga
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera SOCFPGA Clock Manager
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description: test
properties:
compatible:
items:
- const: altr,clk-mgr
reg:
maxItems: 1
required:
- compatible
additionalProperties: false
examples:
- |
clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
};
...

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Altera SOCFPGA SDRAM Controller
Required properties:
- compatible : Should contain "altr,sdr-ctl" and "syscon".
syscon is required by the Altera SOCFPGA SDRAM EDAC.
- reg : Should contain 1 register range (address and length)
Example:
sdr: sdr@ffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
};

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Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
The EDAC accesses a range of registers in the SDRAM controller.
Required properties:
- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
- altr,sdr-syscon : phandle of the sdr module
- interrupts : Should contain the SDRAM ECC IRQ in the
appropriate format for the IRQ controller.
Example:
sdramedac {
compatible = "altr,sdram-edac";
altr,sdr-syscon = <&sdr>;
interrupts = <0 39 4>;
};

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Altera SOCFPGA System Manager
Required properties:
- compatible : "altr,sys-mgr"
- reg : Should contain 1 register ranges(address and length)
- cpu1-start-addr : CPU1 start address in hex.
Example:
sysmgr@ffd08000 {
compatible = "altr,sys-mgr";
reg = <0xffd08000 0x1000>;
cpu1-start-addr = <0xffd080c4>;
};
ARM64 - Stratix10
Required properties:
- compatible : "altr,sys-mgr-s10"
- reg : Should contain 1 register range(address and length)
for system manager register.
Example:
sysmgr@ffd12000 {
compatible = "altr,sys-mgr-s10";
reg = <0xffd12000 0x228>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amazon,al.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amazon's Annapurna Labs Alpine Platform
maintainers:
- Hanna Hawa <hhhawa@amazon.com>
- Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com>
- Ronen Krupnik <ronenk@amazon.com>
properties:
compatible:
oneOf:
- description: Boards with Alpine V1 SoC
items:
- const: al,alpine
- description: Boards with Alpine V2 SoC
items:
- enum:
- al,alpine-v2-evp
- const: al,alpine-v2
- description: Boards with Alpine V3 SoC
items:
- enum:
- amazon,al-alpine-v3-evp
- const: amazon,al-alpine-v3
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amd,pensando.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMD Pensando SoC Platforms
maintainers:
- Brad Larson <blarson@amd.com>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Boards with Pensando Elba SoC
items:
- enum:
- amd,pensando-elba-ortano
- const: amd,pensando-elba
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amlogic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic SoC based Platforms
maintainers:
- Kevin Hilman <khilman@baylibre.com>
description: |+
Work in progress statement:
Device tree files and bindings applying to Amlogic SoCs and boards are
considered "unstable". Any Amlogic device tree binding may change at
any time. Be sure to use a device tree binary and a kernel image
generated from the same source tree.
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
stable binding/ABI.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Boards with the Amlogic Meson6 SoC
items:
- enum:
- geniatech,atv1200
- const: amlogic,meson6
- description: Boards with the Amlogic Meson8 SoC
items:
- enum:
- minix,neo-x8
- const: amlogic,meson8
- description: Boards with the Amlogic Meson8m2 SoC
items:
- enum:
- tronsmart,mxiii-plus
- const: amlogic,meson8m2
- description: Boards with the Amlogic Meson8b SoC
items:
- enum:
- endless,ec100
- hardkernel,odroid-c1
- tronfy,mxq
- const: amlogic,meson8b
- description: Boards with the Amlogic Meson GXBaby SoC
items:
- enum:
- amlogic,p200
- amlogic,p201
- friendlyarm,nanopi-k2
- hardkernel,odroid-c2
- nexbox,a95x
- videostrong,kii-pro
- wetek,hub
- wetek,play2
- const: amlogic,meson-gxbb
- description: Tronsmart Vega S95 devices
items:
- enum:
- tronsmart,vega-s95-pro
- tronsmart,vega-s95-meta
- tronsmart,vega-s95-telos
- const: tronsmart,vega-s95
- const: amlogic,meson-gxbb
- description: Boards with the Amlogic Meson GXL S805X SoC
items:
- enum:
- amlogic,p241
- libretech,aml-s805x-ac
- const: amlogic,s805x
- const: amlogic,meson-gxl
- description: Boards with the Amlogic Meson GXL S905W SoC
items:
- enum:
- amlogic,p281
- oranth,tx3-mini
- jethome,jethub-j80
- const: amlogic,s905w
- const: amlogic,meson-gxl
- description: Boards with the Amlogic Meson GXL S905X SoC
items:
- enum:
- amlogic,p212
- hwacom,amazetv
- khadas,vim
- libretech,aml-s905x-cc
- libretech,aml-s905x-cc-v2
- nexbox,a95x
- const: amlogic,s905x
- const: amlogic,meson-gxl
- description: Boards with the Amlogic Meson GXL S905D SoC
items:
- enum:
- amlogic,p230
- amlogic,p231
- libretech,aml-s905d-pc
- osmc,vero4k-plus
- phicomm,n1
- smartlabs,sml5442tw
- videostrong,gxl-kii-pro
- const: amlogic,s905d
- const: amlogic,meson-gxl
- description: Boards with the Amlogic Meson GXM S912 SoC
items:
- enum:
- amlogic,q200
- amlogic,q201
- azw,gt1-ultimate
- khadas,vim2
- kingnovel,r-box-pro
- libretech,aml-s912-pc
- minix,neo-u9h
- nexbox,a1
- tronsmart,vega-s96
- videostrong,gxm-kiii-pro
- wetek,core2
- const: amlogic,s912
- const: amlogic,meson-gxm
- description: Boards with the Amlogic Meson AXG A113D SoC
items:
- enum:
- amlogic,s400
- jethome,jethub-j100
- jethome,jethub-j110
- const: amlogic,a113d
- const: amlogic,meson-axg
- description: Boards with the Amlogic Meson G12A S905D2/X2/Y2 SoC
items:
- enum:
- amediatech,x96-max
- amlogic,u200
- radxa,zero
- seirobotics,sei510
- const: amlogic,g12a
- description: Boards with the Amlogic Meson G12B A311D SoC
items:
- enum:
- bananapi,bpi-m2s
- khadas,vim3
- libretech,aml-a311d-cc
- radxa,zero2
- const: amlogic,a311d
- const: amlogic,g12b
- description: Boards using the BPI-CM4 module with Amlogic Meson G12B A311D SoC
items:
- enum:
- bananapi,bpi-cm4io
- const: bananapi,bpi-cm4
- const: amlogic,a311d
- const: amlogic,g12b
- description: Boards with the Amlogic Meson G12B S922X SoC
items:
- enum:
- azw,gsking-x
- azw,gtking
- azw,gtking-pro
- bananapi,bpi-m2s
- hardkernel,odroid-go-ultra
- hardkernel,odroid-n2
- hardkernel,odroid-n2l
- hardkernel,odroid-n2-plus
- khadas,vim3
- ugoos,am6
- const: amlogic,s922x
- const: amlogic,g12b
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
- amediatech,x96-air
- amediatech,x96-air-gbit
- bananapi,bpi-m2-pro
- bananapi,bpi-m5
- cyx,a95xf3-air
- cyx,a95xf3-air-gbit
- hardkernel,odroid-c4
- hardkernel,odroid-hc4
- haochuangyi,h96-max
- khadas,vim3l
- libretech,aml-s905d3-cc
- seirobotics,sei610
- const: amlogic,sm1
- description: Boards with the Amlogic Meson A1 A113L SoC
items:
- enum:
- amlogic,ad401
- amlogic,ad402
- const: amlogic,a1
- description: Boards with the Amlogic C3 C302X/C308L SoC
items:
- enum:
- amlogic,aw409
- amlogic,aw419
- const: amlogic,c3
- description: Boards with the Amlogic Meson S4 S805X2 SoC
items:
- enum:
- amlogic,aq222
- const: amlogic,s4
- description: Boards with the Amlogic T7 A311D2 SoC
items:
- enum:
- amlogic,an400
- khadas,vim4
- const: amlogic,a311d2
- const: amlogic,t7
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson Firmware registers Interface
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The Meson SoCs have a register bank with status and data shared with the
secure firmware.
# We need a select here so we don't match all nodes with 'syscon'
select:
properties:
compatible:
contains:
const: amlogic,meson-gx-ao-secure
required:
- compatible
properties:
compatible:
items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
reg:
maxItems: 1
amlogic,has-chip-id:
description: |
A firmware register encodes the SoC type, package and revision
information on the Meson GX SoCs. If present, the interface gives
the current SoC version.
type: boolean
required:
- compatible
- reg
additionalProperties: false
examples:
- |
ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x140 0x140>;
amlogic,has-chip-id;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
description: |
The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which
contains registers for various IP blocks such as pin-controller bits for
the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits.
The registers can be accessed directly when not running in "secure mode".
When "secure mode" is enabled then these registers have to be accessed
through secure monitor calls.
properties:
compatible:
items:
- enum:
- amlogic,meson8-secbus2
- amlogic,meson8b-secbus2
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
secbus2: system-controller@4000 {
compatible = "amlogic,meson8-secbus2", "syscon";
reg = <0x4000 0x2000>;
};

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Amlogic Meson8 and Meson8b "analog top" registers:
--------------------------------------------------
The analog top registers contain information about the so-called
"metal revision" (which encodes the "minor version") of the SoC.
Required properties:
- reg: the register range of the analog top registers
- compatible: depending on the SoC this should be one of:
- "amlogic,meson8-analog-top"
- "amlogic,meson8b-analog-top"
along with "syscon"
Example:
analog_top: analog-top@81a8 {
compatible = "amlogic,meson8-analog-top", "syscon";
reg = <0x81a8 0x14>;
};

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Amlogic Meson6/Meson8/Meson8b assist registers:
-----------------------------------------------
The assist registers contain basic information about the SoC,
for example the encoded SoC part number.
Required properties:
- reg: the register range of the assist registers
- compatible: should be "amlogic,meson-mx-assist" along with "syscon"
Example:
assist: assist@7c00 {
compatible = "amlogic,meson-mx-assist", "syscon";
reg = <0x7c00 0x200>;
};

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Amlogic Meson6/Meson8/Meson8b bootrom:
--------------------------------------
The bootrom register area can be used to access SoC specific
information, such as the "misc version".
Required properties:
- reg: the register range of the bootrom registers
- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon"
Example:
bootrom: bootrom@d9040000 {
compatible = "amlogic,meson-mx-bootrom", "syscon";
reg = <0xd9040000 0x10000>;
};

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Amlogic Meson8 and Meson8b power-management-unit:
-------------------------------------------------
The pmu is used to turn off and on different power domains of the SoCs
This includes the power to the CPU cores.
Required node properties:
- compatible value : depending on the SoC this should be one of:
"amlogic,meson8-pmu"
"amlogic,meson8b-pmu"
- reg : physical base address and the size of the registers window
Example:
pmu@c81000e4 {
compatible = "amlogic,meson8b-pmu", "syscon";
reg = <0xc81000e0 0x18>;
};

17
Bindings/arm/apm/scu.txt Normal file
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APM X-GENE SoC series SCU Registers
This system clock unit contain various register that control block resets,
clock enable/disables, clock divisors and other deepsleep registers.
Properties:
- compatible : should contain two values. First value must be:
- "apm,xgene-scu"
second value must be always "syscon".
- reg : offset and length of the register set.
Example :
scu: system-clk-controller@17000000 {
compatible = "apm,xgene-scu","syscon";
reg = <0x0 0x17000000 0x0 0x400>;
};

114
Bindings/arm/apple.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple ARM Machine
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
This currently includes devices based on the "M1" SoC:
- Mac mini (M1, 2020)
- MacBook Pro (13-inch, M1, 2020)
- MacBook Air (M1, 2020)
- iMac (24-inch, M1, 2021)
Devices based on the "M2" SoC:
- MacBook Air (M2, 2022)
- MacBook Pro (13-inch, M2, 2022)
- Mac mini (M2, 2023)
And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:
- MacBook Pro (14-inch, M1 Pro, 2021)
- MacBook Pro (14-inch, M1 Max, 2021)
- MacBook Pro (16-inch, M1 Pro, 2021)
- MacBook Pro (16-inch, M1 Max, 2021)
- Mac Studio (M1 Max, 2022)
- Mac Studio (M1 Ultra, 2022)
The compatible property should follow this format:
compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform";
<targettype> represents the board/device and comes from the `target-type`
property of the root node of the Apple Device Tree, lowercased. It can be
queried on macOS using the following command:
$ ioreg -d2 -l | grep target-type
<socid> is the lowercased SoC ID. Apple uses at least *five* different
names for their SoCs:
- Marketing name ("M1")
- Internal name ("H13G")
- Codename ("Tonga")
- SoC ID ("T8103")
- Package/IC part number ("APL1102")
Devicetrees should use the lowercased SoC ID, to avoid confusion if
multiple SoCs share the same marketing name. This can be obtained from
the `compatible` property of the arm-io node of the Apple Device Tree,
which can be queried as follows on macOS:
$ ioreg -n arm-io | grep compatible
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Apple M1 SoC based platforms
items:
- enum:
- apple,j274 # Mac mini (M1, 2020)
- apple,j293 # MacBook Pro (13-inch, M1, 2020)
- apple,j313 # MacBook Air (M1, 2020)
- apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021)
- apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
- const: apple,t8103
- const: apple,arm-platform
- description: Apple M2 SoC based platforms
items:
- enum:
- apple,j413 # MacBook Air (M2, 2022)
- apple,j473 # Mac mini (M2, 2023)
- apple,j493 # MacBook Pro (13-inch, M2, 2022)
- const: apple,t8112
- const: apple,arm-platform
- description: Apple M1 Pro SoC based platforms
items:
- enum:
- apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021)
- apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
- const: apple,t6000
- const: apple,arm-platform
- description: Apple M1 Max SoC based platforms
items:
- enum:
- apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
- apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
- apple,j375c # Mac Studio (M1 Max, 2022)
- const: apple,t6001
- const: apple,arm-platform
- description: Apple M1 Ultra SoC based platforms
items:
- enum:
- apple,j375d # Mac Studio (M1 Ultra, 2022)
- const: apple,t6002
- const: apple,arm-platform
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SoC Power Manager (PMGR)
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
Apple SoCs include PMGR blocks responsible for power management,
which can control various clocks, resets, power states, and
performance features. This node represents the PMGR as a syscon,
with sub-nodes representing individual features.
properties:
$nodename:
pattern: "^power-management@[0-9a-f]+$"
compatible:
items:
- enum:
- apple,t8103-pmgr
- apple,t8112-pmgr
- apple,t6000-pmgr
- const: apple,pmgr
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
patternProperties:
"power-controller@[0-9a-f]+$":
description:
The individual power management domains within this controller
type: object
$ref: /schemas/power/apple,pmgr-pwrstate.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
power-management@23b700000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3b700000 0x0 0x14000>;
ps_sio: power-controller@1c0 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x1c0 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "sio";
apple,always-on;
};
ps_uart_p: power-controller@220 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x220 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "uart_p";
power-domains = <&ps_sio>;
};
ps_uart0: power-controller@270 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x270 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "uart0";
power-domains = <&ps_uart_p>;
};
};
power-management@23d280000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3d280000 0x0 0xc000>;
ps_aop_filter: power-controller@4000 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4000 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_filter";
};
ps_aop_base: power-controller@4010 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4010 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_base";
power-domains = <&ps_aop_filter>;
};
ps_aop_shim: power-controller@4038 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4038 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_shim";
power-domains = <&ps_aop_base>;
};
ps_aop_uart0: power-controller@4048 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4048 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_uart0";
power-domains = <&ps_aop_shim>;
};
};
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM CCI Cache Coherent Interconnect
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: >
ARM multi-cluster systems maintain intra-cluster coherency through a cache
coherent interconnect (CCI) that is capable of monitoring bus transactions
and manage coherency, TLB invalidations and memory barriers.
It allows snooping and distributed virtual memory message broadcast across
clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
interface.
properties:
$nodename:
pattern: "^cci(@[0-9a-f]+)?$"
compatible:
enum:
- arm,cci-400
- arm,cci-500
- arm,cci-550
reg:
maxItems: 1
description: >
Specifies base physical address of CCI control registers common to all
interfaces.
"#address-cells": true
"#size-cells": true
ranges: true
patternProperties:
"^slave-if@[0-9a-f]+$":
type: object
properties:
compatible:
const: arm,cci-400-ctrl-if
interface-type:
enum:
- ace
- ace-lite
reg:
maxItems: 1
required:
- compatible
- interface-type
- reg
additionalProperties: false
"^pmu@[0-9a-f]+$":
type: object
properties:
compatible:
oneOf:
- const: arm,cci-400-pmu,r0
- const: arm,cci-400-pmu,r1
- const: arm,cci-400-pmu
deprecated: true
description: >
Permitted only where OS has secure access to CCI registers
- const: arm,cci-500-pmu,r0
- const: arm,cci-550-pmu,r0
interrupts:
minItems: 1
maxItems: 8
description: >
List of counter overflow interrupts, one per counter. The interrupts
must be specified starting with the cycle counter overflow interrupt,
followed by counter0 overflow interrupt, counter1 overflow
interrupt,... ,counterN overflow interrupt.
The CCI PMU has an interrupt signal for each counter. The number of
interrupts must be equal to the number of counters.
reg:
maxItems: 1
required:
- compatible
- interrupts
- reg
additionalProperties: false
required:
- "#address-cells"
- "#size-cells"
- compatible
- ranges
- reg
additionalProperties: false
examples:
- |
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
model = "V2P-CA15_CA7";
arm,hbi = <0x249>;
interrupt-parent = <&gic>;
gic: interrupt-controller {
interrupt-controller;
#interrupt-cells = <3>;
};
/*
* This CCI node corresponds to a CCI component whose control
* registers sits at address 0x000000002c090000.
*
* CCI slave interface @0x000000002c091000 is connected to dma
* controller dma0.
*
* CCI slave interface @0x000000002c094000 is connected to CPUs
* {CPU0, CPU1};
*
* CCI slave interface @0x000000002c095000 is connected to CPUs
* {CPU2, CPU3};
*/
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x1>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x100>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x101>;
};
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu";
reg = <0x9000 0x5000>;
interrupts = <0 101 4>,
<0 102 4>,
<0 103 4>,
<0 104 4>,
<0 105 4>;
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Address Translation Unit (CATU)
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Address Translation Unit (CATU) translates addresses between an
AXI master and system memory. The CATU is normally used along with the TMC to
implement scattering of virtual trace buffers in physical memory. The CATU
translates contiguous Virtual Addresses (VAs) from an AXI master into
non-contiguous Physical Addresses (PAs) that are intended for system memory.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-catu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-catu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
interrupts:
maxItems: 1
description: Address translation error interrupt
power-domains:
maxItems: 1
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI Slave connected to another Coresight component
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
catu@207e0000 {
compatible = "arm,coresight-catu", "arm,primecell";
reg = <0x207e0000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
in-ports {
port {
catu_in_port: endpoint {
remote-endpoint = <&etr_out_port>;
};
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight CPU Debug Component
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight CPU debug component are compliant with the ARMv8 architecture
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
external debug module is mainly used for two modes: self-hosted debug and
external debug, and it can be accessed from mmio region from Coresight and
eventually the debug module connects with CPU for debugging. And the debug
module provides sample-based profiling extension, which can be used to sample
CPU program counter, secure state and exception level, etc; usually every CPU
has one dedicated debug module to be connected.
select:
properties:
compatible:
contains:
const: arm,coresight-cpu-debug
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-cpu-debug
- const: arm,primecell
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
cpu:
description:
A phandle to the cpu this debug component is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
power-domains:
maxItems: 1
description:
A phandle to the debug power domain if the debug logic has its own
dedicated power domain. CPU idle states may also need to be separately
constrained to keep CPU cores powered.
required:
- compatible
- reg
- clocks
- clock-names
- cpu
unevaluatedProperties: false
examples:
- |
debug@f6590000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0xf6590000 0x1000>;
clocks = <&sys_ctrl 1>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Cross Trigger Interface (CTI) device.
description: |
The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
to one or more CoreSight components and/or a CPU, with CTIs interconnected in
a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
The ECT components are not part of the trace generation data path and are thus
not part of the CoreSight graph.
The CTI component properties define the connections between the individual
CTI and the components it is directly connected to, consisting of input and
output hardware trigger signals. CTIs can have a maximum number of input and
output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
number is defined at design time, the maximum of each defined in the DEVID
register.
CTIs are interconnected in a star topology via the CTM, using a number of
programmable channels, usually 4, but again implementation defined and
described in the DEVID register. The star topology is not required to be
described in the bindings as the actual connections are software
programmable.
In general the connections between CTI and components via the trigger signals
are implementation defined, except when the CTI is connected to an ARM v8
architecture core and optional ETM.
In this case the ARM v8 architecture defines the required signal connections
between CTI and the CPU core and ETM if present. In the case of a v8
architecturally connected CTI an additional compatible string is used to
indicate this feature (arm,coresight-cti-v8-arch).
When CTI trigger connection information is unavailable then a minimal driver
binding can be declared with no explicit trigger signals. This will result
the driver detecting the maximum available triggers and channels from the
DEVID register and make them all available for use as a single default
connection. Any user / client application will require additional information
on the connections between the CTI and other components for correct operation.
This information might be found by enabling the Integration Test registers in
the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
configuration). These registers may be used to explore the trigger connections
between CTI and other CoreSight components.
Certain triggers between CoreSight devices and the CTI have specific types
and usages. These can be defined along with the signal indexes with the
constants defined in <dt-bindings/arm/coresight-cti-dt.h>
For example a CTI connected to a core will usually have a DBGREQ signal. This
is defined in the binding as type PE_EDBGREQ. These types will appear in an
optional array alongside the signal indexes. Omitting types will default all
signals to GEN_IO.
Note that some hardware trigger signals can be connected to non-CoreSight
components (e.g. UART etc) depending on hardware implementation.
maintainers:
- Mike Leach <mike.leach@linaro.org>
allOf:
- $ref: /schemas/arm/primecell.yaml#
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
enum:
- arm,coresight-cti
required:
- compatible
properties:
$nodename:
pattern: "^cti(@[0-9a-f]+)$"
compatible:
oneOf:
- items:
- const: arm,coresight-cti
- const: arm,primecell
- items:
- const: arm,coresight-cti-v8-arch
- const: arm,coresight-cti
- const: arm,primecell
reg:
maxItems: 1
cpu:
description:
Handle to cpu this CTI is associated with.
power-domains:
maxItems: 1
arm,cti-ctm-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the CTM this CTI is connected to, in large systems with multiple
separate CTI/CTM nets. Typically multi-socket systems where the CTM is
propagated between sockets.
arm,cs-dev-assoc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
defines a phandle reference to an associated CoreSight trace device.
When the associated trace device is enabled, then the respective CTI
will be enabled. Use in CTI base node when compatible string
arm,coresight-cti-v8-arch used. If the associated device has not been
registered then the node name will be stored as the connection name for
later resolution. If the associated device is not a CoreSight device or
not registered then the node name will remain the connection name and
automatic enabling will not occur.
# size cells and address cells required if trig-conns node present.
"#size-cells":
const: 0
"#address-cells":
const: 1
patternProperties:
'^trig-conns@([0-9]+)$':
type: object
additionalProperties: false
description:
A trigger connections child node which describes the trigger signals
between this CTI and another hardware device. This device may be a CPU,
CoreSight device, any other hardware device or simple external IO lines.
The connection may have both input and output triggers, or only one or the
other.
properties:
reg:
maxItems: 1
cpu:
description:
Handle to cpu this trigger connection is associated with.
arm,cs-dev-assoc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
defines a phandle reference to an associated CoreSight trace device.
When the associated trace device is enabled, then the respective CTI
will be enabled. If the associated device has not been registered
then the node name will be stored as the connection name for later
resolution. If the associated device is not a CoreSight device or
not registered then the node name will remain the connection name
and automatic enabling will not occur.
arm,trig-in-sigs:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger in signal numbers in use by a trig-conns node.
arm,trig-in-types:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of constants representing the types for the CTI trigger in
signals. Types in this array match to the corresponding signal in the
arm,trig-in-sigs array. If the -types array is smaller, or omitted
completely, then the types will default to GEN_IO.
arm,trig-out-sigs:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger out signal numbers in use by a trig-conns node.
arm,trig-out-types:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of constants representing the types for the CTI trigger out
signals. Types in this array match to the corresponding signal
in the arm,trig-out-sigs array. If the "-types" array is smaller,
or omitted completely, then the types will default to GEN_IO.
arm,trig-filters:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger out signals that will be blocked from becoming
active, unless filtering is disabled on the driver.
arm,trig-conn-name:
$ref: /schemas/types.yaml#/definitions/string
description:
Defines a connection name that will be displayed, if the cpu or
arm,cs-dev-assoc properties are not being used in this connection.
Principle use for CTI that are connected to non-CoreSight devices, or
external IO.
anyOf:
- required:
- arm,trig-in-sigs
- required:
- arm,trig-out-sigs
oneOf:
- required:
- arm,trig-conn-name
- required:
- cpu
- required:
- arm,cs-dev-assoc
required:
- reg
required:
- compatible
- reg
- clocks
- clock-names
if:
properties:
compatible:
contains:
const: arm,coresight-cti-v8-arch
then:
required:
- cpu
unevaluatedProperties: false
examples:
# minimum CTI definition. DEVID register used to set number of triggers.
- |
cti@20020000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x20020000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
};
# v8 architecturally defined CTI - CPU + ETM connections generated by the
# driver according to the v8 architecture specification.
- |
cti@859000 {
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
"arm,primecell";
reg = <0x859000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
arm,cs-dev-assoc = <&etm1>;
};
# Implementation defined CTI - CPU + ETM connections explicitly defined..
# Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
# #size-cells and #address-cells are required if trig-conns@ nodes present.
- |
#include <dt-bindings/arm/coresight-cti-dt.h>
cti@858000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x858000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
arm,cti-ctm-id = <1>;
#address-cells = <1>;
#size-cells = <0>;
trig-conns@0 {
reg = <0>;
arm,trig-in-sigs = <4 5 6 7>;
arm,trig-in-types = <ETM_EXTOUT
ETM_EXTOUT
ETM_EXTOUT
ETM_EXTOUT>;
arm,trig-out-sigs = <4 5 6 7>;
arm,trig-out-types = <ETM_EXTIN
ETM_EXTIN
ETM_EXTIN
ETM_EXTIN>;
arm,cs-dev-assoc = <&etm0>;
};
trig-conns@1 {
reg = <1>;
cpu = <&CPU0>;
arm,trig-in-sigs = <0 1>;
arm,trig-in-types = <PE_DBGTRIGGER
PE_PMUIRQ>;
arm,trig-out-sigs = <0 1 2 >;
arm,trig-out-types = <PE_EDBGREQ
PE_DBGRESTART
PE_CTIIRQ>;
arm,trig-filters = <0>;
};
};
# Implementation defined CTI - non CoreSight component connections.
- |
cti@20110000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x20110000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
trig-conns@0 {
reg = <0>;
arm,trig-in-sigs = <0>;
arm,trig-in-types = <GEN_INTREQ>;
arm,trig-out-sigs = <0>;
arm,trig-out-types = <GEN_HALTREQ>;
arm,trig-conn-name = "sys_profiler";
};
trig-conns@1 {
reg = <1>;
arm,trig-out-sigs = <2 3>;
arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-conn-name = "watchdog";
};
trig-conns@2 {
reg = <2>;
arm,trig-in-sigs = <1 6>;
arm,trig-in-types = <GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-conn-name = "g_counter";
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Dummy sink component
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight dummy sink component is for the specific coresight sink devices
kernel don't have permission to access or configure, e.g., CoreSight EUD on
Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based
debug and trace capabilities. For this device, a dummy driver is needed to
register it as Coresight sink device in kernel side, so that path can be
created in the driver. Then the trace flow would be transferred to EUD via
coresight link of AP processor. It provides Coresight API for operations on
dummy source devices, such as enabling and disabling them. It also provides
the Coresight dummy source paths for debugging.
The primary use case of the coresight dummy sink is to build path in kernel
side for dummy sink component.
maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@arm.com>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:
compatible:
enum:
- arm,coresight-dummy-sink
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Input connection from the Coresight Trace bus to
dummy sink, such as Embedded USB debugger(EUD).
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
additionalProperties: false
examples:
# Minimum dummy sink definition. Dummy sink connect to coresight replicator.
- |
sink {
compatible = "arm,coresight-dummy-sink";
in-ports {
port {
eud_in_replicator_swao: endpoint {
remote-endpoint = <&replicator_swao_out_eud>;
};
};
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Dummy source component
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight dummy source component is for the specific coresight source
devices kernel don't have permission to access or configure. For some SOCs,
there would be Coresight source trace components on sub-processor which
are conneted to AP processor via debug bus. For these devices, a dummy driver
is needed to register them as Coresight source devices, so that paths can be
created in the driver. It provides Coresight API for operations on dummy
source devices, such as enabling and disabling them. It also provides the
Coresight dummy source paths for debugging.
The primary use case of the coresight dummy source is to build path in kernel
side for dummy source component.
maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@arm.com>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:
compatible:
enum:
- arm,coresight-dummy-source
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Output connection from the source to Coresight
Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- out-ports
additionalProperties: false
examples:
# Minimum dummy source definition. Dummy source connect to coresight funnel.
- |
source {
compatible = "arm,coresight-dummy-source";
out-ports {
port {
dummy_riscv_out_funnel_swao: endpoint {
remote-endpoint = <&funnel_swao_in_dummy_riscv>;
};
};
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Programmable Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight funnel merges 2-8 trace sources into a single trace
stream with programmable enable and priority of input ports.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-funnel
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-funnel
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
power-domains:
maxItems: 1
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-7])?$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
funnel@20040000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x20040000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Programmable Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-replicator
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-replicator
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
power-domains:
maxItems: 1
qcom,replicator-loses-context:
type: boolean
description:
Indicates that the replicator will lose register context when AMBA clock
is removed which is observed in some replicator designs.
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[01])?$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
replicator@20120000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x20120000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&csys2_funnel_out_port>;
};
};
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace Buffer
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is
used as a circular buffer.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-etb10
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-etb10
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
power-domains:
maxItems: 1
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etb@20010000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x20010000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Embedded Trace Macrocell (ETM) is a real-time trace module providing
instruction and data tracing of a processor.
select:
properties:
compatible:
contains:
enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- arm,coresight-etm4x-sysreg
required:
- compatible
allOf:
- if:
not:
properties:
compatible:
contains:
const: arm,coresight-etm4x-sysreg
then:
$ref: /schemas/arm/primecell.yaml#
required:
- reg
properties:
compatible:
oneOf:
- description:
Embedded Trace Macrocell with memory mapped access.
items:
- enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- const: arm,primecell
- description:
Embedded Trace Macrocell (version 4.x), with system register access only
const: arm,coresight-etm4x-sysreg
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
power-domains:
maxItems: 1
arm,coresight-loses-context-with-cpu:
type: boolean
description:
Indicates that the hardware will lose register context on CPU power down
(e.g. CPUIdle). An example of where this may be needed are systems which
contain a coresight component and CPU in the same power domain. When the
CPU powers down the coresight component also powers down and loses its
context.
arm,cp14:
type: boolean
description:
Must be present if the system accesses ETM/PTM management registers via
co-processor 14.
qcom,skip-power-up:
type: boolean
description:
Indicates that an implementation can skip powering up the trace unit.
TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
since ETMs are in the same power domain as their CPU cores. This property
is required to identify such systems with hardware errata where the CPU
watchdog counter is stopped when TRCPDCR.PU is set.
cpu:
description:
phandle to the cpu this ETM is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection from the ETM to CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- clocks
- clock-names
- cpu
- out-ports
unevaluatedProperties: false
examples:
- |
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201c000 0x1000>;
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
ptm@2201d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201d000 0x1000>;
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight static funnel merges 2-8 trace sources into a single trace
stream.
properties:
compatible:
const: arm,coresight-static-funnel
power-domains:
maxItems: 1
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[0-7]$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
funnel {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
out-ports {
port {
combo_funnel_out: endpoint {
remote-endpoint = <&top_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
combo_funnel_in0: endpoint {
remote-endpoint = <&cluster0_etf_out>;
};
};
port@1 {
reg = <1>;
combo_funnel_in1: endpoint {
remote-endpoint = <&cluster1_etf_out>;
};
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
properties:
compatible:
const: arm,coresight-static-replicator
power-domains:
maxItems: 1
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[01]$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
replicator {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight System Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The STM is a trace source that is integrated into a CoreSight system, designed
primarily for high-bandwidth trace of instrumentation embedded into software.
This instrumentation is made up of memory-mapped writes to the STM Advanced
eXtensible Interface (AXI) slave, which carry information about the behavior
of the software.
select:
properties:
compatible:
contains:
const: arm,coresight-stm
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-stm
- const: arm,primecell
reg:
maxItems: 2
reg-names:
items:
- const: stm-base
- const: stm-stimulus-base
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
power-domains:
maxItems: 1
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- out-ports
unevaluatedProperties: false
examples:
- |
stm@20100000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x20100000 0x1000>,
<0x28000000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port2>;
};
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Memory Controller
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tmc
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tmc
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
iommus:
maxItems: 1
power-domains:
maxItems: 1
arm,buffer-size:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
description:
Size of contiguous buffer space for TMC ETR (embedded trace router). The
buffer size can be configured dynamically via buffer_size property in
sysfs instead.
arm,scatter-gather:
type: boolean
description:
Indicates that the TMC-ETR can safely use the SG mode on this system.
arm,max-burst-size:
description:
The maximum burst size initiated by TMC on the AXI master interface. The
burst size can be in the range [0..15], the setting supports one data
transfer per burst up to a maximum of 16 data transfers per burst.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI or ATB Master output connection. Used for ETR
and ETF configurations.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x20070000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator2_out_port0>;
};
};
};
out-ports {
port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Port Interface Unit
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Trace Port Interface Unit captures trace data from the trace bus
and outputs it to an external trace port.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tpiu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tpiu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
power-domains:
maxItems: 1
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
tpiu@e3c05000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xe3c05000 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&funnel4_out_port0>;
};
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Corstone1000
maintainers:
- Vishnu Banavath <vishnu.banavath@arm.com>
- Rui Miguel Silva <rui.silva@linaro.org>
description: |+
ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
provides a flexible compute architecture that combines CortexA and CortexM
processors.
Support for CortexA32, CortexA35 and CortexA53 processors. Two expansion
systems for M-Class (or other) processors for adding sensors, connectivity,
video, audio and machine learning at the edge System and security IPs to build
a secure SoC for a range of rich IoT applications, for example gateways, smart
cameras and embedded systems.
Integrated Secure Enclave providing hardware Root of Trust and supporting
seamless integration of the optional CryptoCell™-312 cryptographic
accelerator.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
implementation of the Corstone1000 in the MPS3 prototyping board. See
ARM document DAI0550.
items:
- const: arm,corstone1000-mps3
- description: Corstone1000 FVP is the Fixed Virtual Platform
implementation of this system. See ARM ecosystems FVP's.
items:
- const: arm,corstone1000-fvp
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Embedded Trace Extensions
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Mathieu Poirier <mathieu.poirier@linaro.org>
description: |
Arm Embedded Trace Extension(ETE) is a per CPU trace component that
allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
architecture and has extended support for future architecture changes.
The trace generated by the ETE could be stored via legacy CoreSight
components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
legacy CoreSight components, a node must be listed per instance, along
with any optional connection graph as per the coresight bindings.
properties:
$nodename:
pattern: "^ete([0-9a-f]+)$"
compatible:
items:
- const: arm,embedded-trace-extension
cpu:
description: |
Handle to the cpu this ETE is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
power-domains:
maxItems: 1
out-ports:
description: |
Output connections from the ETE to legacy CoreSight trace bus.
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Output connection from the ETE to legacy CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- cpu
additionalProperties: false
examples:
# An ETE node without legacy CoreSight connections
- |
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu_0>;
};
# An ETE node with legacy CoreSight connections
- |
ete1 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu_1>;
out-ports { /* legacy coresight connection */
port {
ete1_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,integrator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Integrator Boards
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |+
These were the first ARM platforms officially supported by ARM Ltd.
They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
so the system is modular and can host a variety of CPU tiles called
"core tiles" and referred to in the device tree as "core modules".
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: ARM Integrator Application Platform, this board has a PCI
host and several PCI slots, as well as a number of slots for logical
expansion modules, it is referred to as an "ASIC Development
Motherboard" and is extended with custom FPGA and is intended for
rapid prototyping. See ARM DUI 0098B. This board can physically come
pre-packaged in a PC Tower form factor called Integrator/PP1 or a
special metal fixture called Integrator/PP2, see ARM DUI 0169A.
items:
- const: arm,integrator-ap
- description: ARM Integrator Compact Platform (HBI-0086), this board has
a compact form factor and mainly consists of the bare minimum
peripherals to make use of the core module. See ARM DUI 0159B.
items:
- const: arm,integrator-cp
- description: ARM Integrator Standard Development Board (SDB) Platform,
this board is a PCI-based board conforming to the Microsoft SDB
(HARP) specification. See ARM DUI 0099A.
items:
- const: arm,integrator-sp
required:
- compatible
- core-module@10000000
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,realview.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM RealView Boards
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |+
The ARM RealView series of reference designs were built to explore the ARM
11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
the earlier CPUs such as TrustZone and multicore (MPCore).
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: ARM RealView Emulation Baseboard (HBI-0140) was created
as a generic platform to test different FPGA designs, and has
pluggable CPU modules, see ARM DUI 0303E.
items:
- const: arm,realview-eb
- description: ARM RealView Platform Baseboard for ARM1176JZF-S
(HBI-0147) was created as a development board to test ARM TrustZone,
CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
items:
- const: arm,realview-pb1176
- description: ARM RealView Platform Baseboard for ARM 11 MPCore
(HBI-0159, HBI-0175 and HBI-0176) was created to showcase
multiprocessing with ARM11 using MPCore using symmetric
multiprocessing (SMP). See ARM DUI 0351E.
items:
- const: arm,realview-pb11mp
- description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
HBI-0176 and HBI-0175) was the first reference platform for the
Cortex CPU family, including a Cortex-A8 test chip.
items:
- const: arm,realview-pba8
- description: ARM RealView Platform Baseboard Explore for Cortex-A9
(HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
CPU.
items:
- const: arm,realview-pbx
soc:
description: All RealView boards must provide a soc node in the root of the
device tree, representing the System-on-Chip since these test chips are
rather complex.
type: object
properties:
compatible:
oneOf:
- items:
- const: arm,realview-eb-soc
- const: simple-bus
- items:
- const: arm,realview-pb1176-soc
- const: simple-bus
- items:
- const: arm,realview-pb11mp-soc
- const: simple-bus
- items:
- const: arm,realview-pba8-soc
- const: simple-bus
- items:
- const: arm,realview-pbx-soc
- const: simple-bus
patternProperties:
"^.*syscon@[0-9a-f]+$":
type: object
description: All RealView boards must provide a syscon system controller
node inside the soc node.
required:
- compatible
required:
- compatible
- soc
additionalProperties: true
...

46
Bindings/arm/arm,scu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Snoop Control Unit (SCU)
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
with a Snoop Control Unit. The register range is usually 256 (0x100)
bytes.
References:
- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
Revision r2p0
- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
Revision r0p1
- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
Manial Revision r2p0
properties:
compatible:
enum:
- arm,cortex-a9-scu
- arm,cortex-a5-scu
- arm,arm11mp-scu
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
scu@a0410000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Trace Buffer Extensions
maintainers:
- Anshuman Khandual <anshuman.khandual@arm.com>
description: |
Arm Trace Buffer Extension (TRBE) is a per CPU component
for storing trace generated on the CPU to memory. It is
accessed via CPU system registers. The software can verify
if it is permitted to use the component by checking the
TRBIDR register.
properties:
$nodename:
const: trbe
compatible:
items:
- const: arm,trace-buffer-extension
interrupts:
description: |
Exactly 1 PPI must be listed. For heterogeneous systems where
TRBE is only supported on a subset of the CPUs, please consult
the arm,gic-v3 binding for details on describing a PPI partition.
maxItems: 1
required:
- compatible
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,versatile-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Versatile system registers
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
This is a system control registers block, providing multiple low level
platform functions like board detection and identification, software
interrupt generation, MMC and NOR Flash control, etc.
properties:
compatible:
items:
- const: arm,versatile-sysreg
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
panel:
type: object
required:
- compatible
- reg
additionalProperties: false
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,versatile.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Boards
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |+
The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
with various pluggable interface boards, in essence the Versatile PB version
is a superset of the Versatile AB version.
The root node in the Versatile platforms must contain a core module child
node. They are always at physical address 0x10000000 in all the Versatile
variants.
When fitted with the IB2 Interface Board, the Versatile AB will present an
optional system controller node which controls the extra peripherals on the
interface board.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: The ARM Versatile Application Baseboard (HBI-0118) is an
evaluation board specifically for the ARM926EJ-S. It can be connected
to an IB1 interface board for a touchscreen-type use case or an IB2
for a candybar phone-type use case. See ARM DUI 0225D.
items:
- const: arm,versatile-ab
- description: The ARM Versatile Platform Baseboard (HBI-0117) is an
extension of the Versatile Application Baseboard that includes a
PCI host controller. Like the sibling board, it is done specifically
for ARM926EJ-S. See ARM DUI 0224B.
items:
- const: arm,versatile-pb
required:
- compatible
- core-module@10000000
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express and Juno Boards
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Linus Walleij <linus.walleij@linaro.org>
description: |+
ARM's Versatile Express platform were built as reference designs for exploring
multicore Cortex-A class systems. The Versatile Express family contains both
32 bit (Aarch32) and 64 bit (Aarch64) systems.
The board consist of a motherboard and one or more daughterboards (tiles). The
motherboard provides a set of peripherals. Processor and RAM "live" on the
tiles.
The motherboard and each core tile should be described by a separate Device
Tree source file, with the tile's description including the motherboard file
using an include directive. As the motherboard can be initialized in one of
two different configurations ("memory maps"), care must be taken to include
the correct one.
When a new generation of boards were introduced under the name "Juno", these
shared to many common characteristics with the Versatile Express that the
"arm,vexpress" compatible was retained in the root node, and these are
included in this binding schema as well.
The root node indicates the CPU SoC on the core tile, and this
is a daughterboard to the main motherboard. The name used in the compatible
string shall match the name given in the core tile's technical reference
manual, followed by "arm,vexpress" as an additional compatible value. If
further subvariants are released of the core tile, even more fine-granular
compatible strings with up to three compatible strings are used.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
in MPCore configuration in a test chip on the core tile. See ARM
DUI 0448I. This was the first Versatile Express platform.
items:
- const: arm,vexpress,v2p-ca9
- const: arm,vexpress
- description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
in a test chip on the core tile. It is intended to evaluate NEON, FPU
and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
items:
- const: arm,vexpress,v2p-ca5s
- const: arm,vexpress
- description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
cores in a MPCore configuration in a test chip on the core tile. See
ARM DUI 0604F.
items:
- const: arm,vexpress,v2p-ca15
- const: arm,vexpress
- description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
A15 CPU cores in a test chip on the core tile. This is the first test
chip called "TC1".
items:
- const: arm,vexpress,v2p-ca15,tc1
- const: arm,vexpress,v2p-ca15
- const: arm,vexpress
- description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
in a test chip on the core tile. See ARM DDI 0503I.
items:
- const: arm,vexpress,v2p-ca15_a7
- const: arm,vexpress
- description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
cores in a test chip on the core tile. See ARM DDI 0498D.
items:
- const: arm,vexpress,v2f-1xv7,ca53x2
- const: arm,vexpress,v2f-1xv7
- const: arm,vexpress
- description: Arm Versatile Express Juno "r0" (the first Juno board,
V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
cores in a big.LITTLE configuration. It also features the MALI T624
GPU. See ARM document 100113_0000_07_en.
items:
- const: arm,juno
- const: arm,vexpress
- description: Arm Versatile Express Juno r1 Development Platform
(V2M-Juno r1) was introduced mainly aimed at development of PCIe
based systems. Juno r1 also has support for AXI masters placed on
the TLX connectors to join the coherency domain. Otherwise it is the
same configuration as Juno r0. See ARM document 100122_0100_06_en.
items:
- const: arm,juno-r1
- const: arm,juno
- const: arm,vexpress
- description: Arm Versatile Express Juno r2 Development Platform
(V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
ARM document 100114_0200_04_en.
items:
- const: arm,juno-r2
- const: arm,juno
- const: arm,vexpress
- description: Arm AEMv8a Versatile Express Real-Time System Model
(VE RTSM) is a programmers view of the Versatile Express with Arm
v8A hardware. See ARM DUI 0575D.
items:
- const: arm,rtsm_ve,aemv8a
- const: arm,vexpress
- description: Arm FVP (Fixed Virtual Platform) base model revision C
See ARM Document 100964_1190_00_en.
items:
- const: arm,fvp-base-revc
- const: arm,vexpress
- description: Arm Foundation model for Aarch64
items:
- const: arm,foundation-aarch64
- const: arm,vexpress
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
in the stack be be described this attribute.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
arm,vexpress,dcc:
description: When describing tiles consisting of more than one DCC, its
number can be specified with this attribute.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
patternProperties:
"^bus@[0-9a-f]+$":
description: Static Memory Bus (SMB) node, if this exists it describes
the connection between the motherboard and any tiles. Sometimes the
compatible is placed directly under this node, sometimes it is placed
in a subnode named "motherboard-bus". Sometimes the compatible includes
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
"simple-bus". If the compatible is placed in the "motherboard-bus" node,
it is stricter and always has two compatibles.
type: object
$ref: /schemas/simple-bus.yaml
unevaluatedProperties: false
properties:
compatible:
oneOf:
- items:
- enum:
- arm,vexpress,v2m-p1
- arm,vexpress,v2p-p1
- const: simple-bus
- const: simple-bus
patternProperties:
'^motherboard-bus@':
type: object
description: The motherboard description provides a single "motherboard"
node using 2 address cells corresponding to the Static Memory Bus
used between the motherboard and the tile. The first cell defines the
Chip Select (CS) line number, the second cell address offset within
the CS. All interrupt lines between the motherboard and the tile
are active high and are described using single cell.
properties:
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges: true
compatible:
items:
- enum:
- arm,vexpress,v2m-p1
- arm,vexpress,v2p-p1
- const: simple-bus
arm,v2m-memory-map:
description: This describes the memory map type.
$ref: /schemas/types.yaml#/definitions/string
enum:
- rs1
- rs2
arm,hbi:
$ref: /schemas/types.yaml#/definitions/uint32
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
arm,vexpress,site:
description: As Versatile Express can be configured in number of physically
different setups, the device tree should describe platform topology.
For this reason the root node and main motherboard node must define this
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
required:
- compatible
additionalProperties:
type: object
required:
- compatible
allOf:
- if:
properties:
compatible:
contains:
enum:
- arm,vexpress,v2p-ca9
- arm,vexpress,v2p-ca5s
- arm,vexpress,v2p-ca15
- arm,vexpress,v2p-ca15_a7
- arm,vexpress,v2f-1xv7,ca53x2
then:
required:
- arm,hbi
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2021 Joel Stanley, IBM Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED Secure Boot Controller
maintainers:
- Joel Stanley <joel@jms.id.au>
- Andrew Jeffery <andrew@aj.id.au>
description: |
The ASPEED SoCs have a register bank for interacting with the secure boot
controller.
properties:
compatible:
items:
- const: aspeed,ast2600-sbc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sbc: secure-boot-controller@1e6f2000 {
compatible = "aspeed,ast2600-sbc";
reg = <0x1e6f2000 0x1000>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed SoC based boards
maintainers:
- Joel Stanley <joel@jms.id.au>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: AST2400 based boards
items:
- enum:
- delta,ahe50dc-bmc
- facebook,galaxy100-bmc
- facebook,wedge100-bmc
- facebook,wedge40-bmc
- microsoft,olympus-bmc
- quanta,q71l-bmc
- tyan,palmetto-bmc
- yadro,vesnin-bmc
- const: aspeed,ast2400
- description: AST2500 based boards
items:
- enum:
- amd,daytonax-bmc
- amd,ethanolx-bmc
- ampere,mtjade-bmc
- aspeed,ast2500-evb
- asrock,e3c246d4i-bmc
- asrock,romed8hm3-bmc
- bytedance,g220a-bmc
- facebook,cmm-bmc
- facebook,minipack-bmc
- facebook,tiogapass-bmc
- facebook,yamp-bmc
- facebook,yosemitev2-bmc
- facebook,wedge400-bmc
- hxt,stardragon4800-rep2-bmc
- ibm,mihawk-bmc
- ibm,mowgli-bmc
- ibm,romulus-bmc
- ibm,swift-bmc
- ibm,witherspoon-bmc
- ingrasys,zaius-bmc
- inspur,fp5280g2-bmc
- inspur,nf5280m6-bmc
- inspur,on5263m5-bmc
- intel,s2600wf-bmc
- inventec,lanyang-bmc
- lenovo,hr630-bmc
- lenovo,hr855xg2-bmc
- portwell,neptune-bmc
- qcom,centriq2400-rep-bmc
- supermicro,x11spi-bmc
- tyan,s7106-bmc
- tyan,s8036-bmc
- yadro,nicole-bmc
- yadro,vegman-n110-bmc
- yadro,vegman-rx20-bmc
- yadro,vegman-sx20-bmc
- const: aspeed,ast2500
- description: AST2600 based boards
items:
- enum:
- ampere,mtmitchell-bmc
- aspeed,ast2600-evb
- aspeed,ast2600-evb-a1
- facebook,bletchley-bmc
- facebook,cloudripper-bmc
- facebook,elbert-bmc
- facebook,fuji-bmc
- facebook,greatlakes-bmc
- facebook,minerva-cmc
- facebook,yosemite4-bmc
- ibm,everest-bmc
- ibm,rainier-bmc
- ibm,tacoma-bmc
- inventec,starscream-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
- qcom,dc-scm-v1-bmc
- quanta,s6q-bmc
- ufispace,ncplite-bmc
- const: aspeed,ast2600
additionalProperties: true

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/atmel-at91.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel AT91.
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Claudiu Beznea <claudiu.beznea@microchip.com>
- Nicolas Ferre <nicolas.ferre@microchip.com>
description: |
Boards with a SoC of the Atmel AT91 or SMART family shall have the following
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- const: atmel,at91rm9200
- items:
- enum:
- olimex,sam9-l9260
- enum:
- atmel,at91sam9260
- atmel,at91sam9261
- atmel,at91sam9263
- atmel,at91sam9g20
- atmel,at91sam9g45
- atmel,at91sam9n12
- atmel,at91sam9rl
- atmel,at91sam9xe
- atmel,at91sam9x60
- const: atmel,at91sam9
- items:
- enum:
- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
- overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board
- overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN
- overkiz,smartkiz # Overkiz SmartKiz Board
- gardena,smart-gateway-at91sam # GARDENA smart Gateway (Article No. 19000)
- const: atmel,at91sam9g25
- const: atmel,at91sam9x5
- const: atmel,at91sam9
- items:
- enum:
- atmel,at91sam9g15
- atmel,at91sam9g25
- atmel,at91sam9g35
- atmel,at91sam9x25
- atmel,at91sam9x35
- const: atmel,at91sam9x5
- const: atmel,at91sam9
- description: Overkiz kizbox3 board
items:
- const: overkiz,kizbox3-hs
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D27 WLSOM1
items:
- const: microchip,sama5d27-wlsom1
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D27 WLSOM1 Evaluation Kit
items:
- const: microchip,sama5d27-wlsom1-ek
- const: microchip,sama5d27-wlsom1
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D29 Curiosity
items:
- const: microchip,sama5d29-curiosity
- const: atmel,sama5d29
- const: atmel,sama5d2
- const: atmel,sama5
- items:
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D2 Industrial Connectivity Platform
items:
- const: microchip,sama5d2-icp
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAM9X60 Evaluation Boards
items:
- enum:
- microchip,sam9x60ek
- microchip,sam9x60-curiosity
- const: microchip,sam9x60
- const: atmel,at91sam9
- description: Nattis v2 board with Natte v2 power board
items:
- const: axentia,nattis-2
- const: axentia,natte-2
- const: axentia,linea
- const: atmel,sama5d31
- const: atmel,sama5d3
- const: atmel,sama5
- description: TSE-850 v3 board
items:
- const: axentia,tse850v3
- const: axentia,linea
- const: atmel,sama5d31
- const: atmel,sama5d3
- const: atmel,sama5
- items:
- const: axentia,linea
- const: atmel,sama5d31
- const: atmel,sama5d3
- const: atmel,sama5
- description: Overkiz kizbox2 board with two heads
items:
- const: overkiz,kizbox2-2
- const: atmel,sama5d31
- const: atmel,sama5d3
- const: atmel,sama5
- description: Microchip SAMA5D3 Ethernet Development System Board
items:
- const: microchip,sama5d3-eds
- const: atmel,sama5d36
- const: atmel,sama5d3
- const: atmel,sama5
- description: CalAmp LMU5000 board
items:
- const: calamp,lmu5000
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- description: Exegin Q5xR5 board
items:
- const: exegin,q5xr5
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- items:
- enum:
- atmel,sama5d31
- atmel,sama5d33
- atmel,sama5d34
- atmel,sama5d35
- atmel,sama5d36
- const: atmel,sama5d3
- const: atmel,sama5
- items:
- enum:
- atmel,sama5d41
- atmel,sama5d42
- atmel,sama5d43
- atmel,sama5d44
- const: atmel,sama5d4
- const: atmel,sama5
- items:
- const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
- const: microchip,sama7g5
- const: microchip,sama7
- description: Microchip LAN9662 Evaluation Boards.
items:
- enum:
- microchip,lan9662-pcb8291
- microchip,lan9662-pcb8309
- const: microchip,lan9662
- const: microchip,lan966
- description: Microchip LAN9668 PCB8290 Evaluation Board.
items:
- const: microchip,lan9668-pcb8290
- const: microchip,lan9668
- const: microchip,lan966
- description: Kontron KSwitch D10 MMT series
items:
- enum:
- kontron,kswitch-d10-mmt-8g
- kontron,kswitch-d10-mmt-6g-2gs
- const: kontron,s1921
- const: microchip,lan9668
- const: microchip,lan966
- items:
- enum:
- atmel,sams70j19
- atmel,sams70j20
- atmel,sams70j21
- atmel,sams70n19
- atmel,sams70n20
- atmel,sams70n21
- atmel,sams70q19
- atmel,sams70q20
- atmel,sams70q21
- const: atmel,sams70
- const: atmel,samv7
- items:
- enum:
- atmel,samv70j19
- atmel,samv70j20
- atmel,samv70n19
- atmel,samv70n20
- atmel,samv70q19
- atmel,samv70q20
- const: atmel,samv70
- const: atmel,samv7
- items:
- enum:
- atmel,samv71j19
- atmel,samv71j20
- atmel,samv71j21
- atmel,samv71n19
- atmel,samv71n20
- atmel,samv71n21
- atmel,samv71q19
- atmel,samv71q20
- atmel,samv71q21
- const: atmel,samv71
- const: atmel,samv7
additionalProperties: true
...

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Atmel system registers
Chipid required properties:
- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
- reg : Should contain registers location and length
PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the PIT which is the IRQ line
shared across all System Controller members.
PIT64B Timer required properties:
- compatible: Should be "microchip,sam9x60-pit64b"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for PIT64B timer
- clocks: Should contain the available clock sources for PIT64B timer.
System Timer (ST) required properties:
- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line
shared across all System Controller members.
- clocks: phandle to input clock.
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
"microchip,sam9x60-ddramc",
"microchip,sama7g5-uddrc"
- reg: Should contain registers location and length
Examples:
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
};
RAMC PHY Controller required properties:
- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
- reg: Should contain registers location and length
Example:
ddr3phy: ddr3phy@e3804000 {
compatible = "microchip,sama7g5-ddr3phy", "syscon";
reg = <0xe3804000 0x1000>;
};
Special Function Registers (SFR)
Special Function Registers (SFR) manage specific aspects of the integrated
memory, bridge implementations, processor and other functionality not controlled
elsewhere.
required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
"atmel,<chip>-sfrbu", "syscon"
<chip> can be "sama5d3", "sama5d4" or "sama5d2".
It also can be "microchip,sam9x60-sfr", "syscon".
- reg: Should contain registers location and length
sfr@f0038000 {
compatible = "atmel,sama5d3-sfr", "syscon";
reg = <0xf0038000 0x60>;
};
Security Module (SECUMOD)
The Security Module macrocell provides all necessary secure functions to avoid
voltage, temperature, frequency and mechanical attacks on the chip. It also
embeds secure memories that can be scrambled.
The Security Module also offers the PIOBU pins which can be used as GPIO pins.
Note that they maintain their voltage during Backup/Self-refresh.
required properties:
- compatible: Should be "atmel,<chip>-secumod", "syscon".
<chip> can be "sama5d2".
- reg: Should contain registers location and length
- gpio-controller: Marks the port as GPIO controller.
- #gpio-cells: There are 2. The pin number is the
first, the second represents additional
parameters such as GPIO_ACTIVE_HIGH/LOW.
secumod@fc040000 {
compatible = "atmel,sama5d2-secumod", "syscon";
reg = <0xfc040000 0x100>;
gpio-controller;
#gpio-cells = <2>;
};

29
Bindings/arm/axis.txt Normal file
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Axis Communications AB
ARTPEC series SoC Device Tree Bindings
ARTPEC-6 ARM SoC
================
Required root node properties:
- compatible = "axis,artpec6";
ARTPEC-6 System Controller
--------------------------
The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
and resets.
Required properties:
- compatible: "axis,artpec6-syscon", "syscon"
- reg: Address and length of the register bank.
Example:
syscon {
compatible = "axis,artpec6-syscon", "syscon";
reg = <0xf8000000 0x48>;
};
ARTPEC-6 Development board:
---------------------------
Required root node properties:
- compatible = "axis,artpec6-dev-board", "axis,artpec6";

23
Bindings/arm/axxia.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/axxia.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axxia AXM55xx
maintainers:
- Anders Berg <anders.berg@lsi.com>
properties:
$nodename:
const: "/"
compatible:
description: LSI AXM5516 Validation board (Amarillo)
items:
- const: lsi,axm5516-amarillo
- const: lsi,axm5516
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM2711/BCM2835 Platforms
maintainers:
- Eric Anholt <eric@anholt.net>
- Stefan Wahren <wahrenst@gmx.net>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM2711 based Boards
items:
- enum:
- raspberrypi,400
- raspberrypi,4-compute-module
- raspberrypi,4-model-b
- const: brcm,bcm2711
- description: BCM2835 based Boards
items:
- enum:
- raspberrypi,model-a
- raspberrypi,model-a-plus
- raspberrypi,model-b
- raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5)
- raspberrypi,model-b-rev2
- raspberrypi,model-b-plus
- raspberrypi,compute-module
- raspberrypi,model-zero
- raspberrypi,model-zero-w
- const: brcm,bcm2835
- description: BCM2836 based Boards
items:
- enum:
- raspberrypi,2-model-b
- const: brcm,bcm2836
- description: BCM2837 based Boards
items:
- enum:
- raspberrypi,3-model-a-plus
- raspberrypi,3-model-b
- raspberrypi,3-model-b-plus
- raspberrypi,3-compute-module
- raspberrypi,3-compute-module-lite
- raspberrypi,model-zero-2-w
- const: brcm,bcm2837
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM11351
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm28155-ap
- const: brcm,bcm11351
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM21664
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm21664-garnet
- const: brcm,bcm21664
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM23550
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm23550-sparrow
- const: brcm,bcm23550
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4708
description:
Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
on the iProc architecture (Northstar).
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
- Hauke Mehrtens <hauke@hauke-m.de>
- Rafal Milecki <zajec5@gmail.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM4708 based boards
items:
- enum:
- asus,rt-ac56u
- asus,rt-ac68u
- buffalo,wzr-1166dhp
- buffalo,wzr-1166dhp2
- buffalo,wzr-1750dhp
- linksys,ea6300-v1
- linksys,ea6500-v2
- luxul,xap-1510-v1
- luxul,xwc-1000
- netgear,r6250-v1
- netgear,r6300-v2
- smartrg,sr400ac
- brcm,bcm94708
- const: brcm,bcm4708
- description: BCM47081 based boards
items:
- enum:
- asus,rt-n18u
- buffalo,wzr-600dhp2
- buffalo,wzr-900dhp
- luxul,xap-1410-v1
- luxul,xwr-1200-v1
- tplink,archer-c5-v2
- const: brcm,bcm47081
- const: brcm,bcm4708
- description: BCM4709 based boards
items:
- enum:
- asus,rt-ac87u
- buffalo,wxr-1900dhp
- linksys,ea9200
- netgear,r7000
- netgear,r8000
- tplink,archer-c9-v1
- brcm,bcm94709
- const: brcm,bcm4709
- const: brcm,bcm4708
- description: BCM47094 based boards
items:
- enum:
- asus,rt-ac3100
- asus,rt-ac88u
- dlink,dir-885l
- dlink,dir-890l
- linksys,panamera
- luxul,abr-4500-v1
- luxul,xap-1610-v1
- luxul,xbr-4500-v1
- luxul,xwc-2000-v1
- luxul,xwr-3100-v1
- luxul,xwr-3150-v1
- netgear,r8500
- phicomm,k3
- const: brcm,bcm47094
- const: brcm,bcm4708
- description: BCM53012 based boards
items:
- enum:
- brcm,bcm953012er
- brcm,bcm953012hr
- brcm,bcm953012k
- const: brcm,bcm53012
- const: brcm,bcm4708
- description: BCM53015 based boards
items:
- enum:
- meraki,mr26
- const: brcm,bcm53015
- const: brcm,bcm4708
- description: BCM53016 based boards
items:
- enum:
- dlink,dwl-8610ap
- meraki,mr32
- const: brcm,bcm53016
- const: brcm,bcm4708
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm53573.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53573 SoCs family
description:
Broadcom BCM53573 / BCM47189 Wi-Fi SoCs derived from Northstar.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM53573 based boards
items:
- enum:
- tenda,ac6-v1
- tenda,w15e-v1
- const: brcm,bcm53573
- description: BCM47189 based boards
items:
- enum:
- brcm,bcm947189acdbmr
- luxul,xap-810-v1
- luxul,xap-1440-v1
- tenda,ac9
- const: brcm,bcm47189
- const: brcm,bcm53573
additionalProperties: true
...

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Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
-----------------------------------------------------------
Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
following properties:
Required root node property:
compatible: should be "brcm,bcm63138"
An optional Boot lookup table Device Tree node is required for secondary CPU
initialization as well as a 'resets' phandle to the correct PMB controller as
defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
'enable-method' property.
Required properties for the Boot lookup table node:
- compatible: should be "brcm,bcm63138-bootlut"
- reg: register base address and length for the Boot Lookup table
Optional properties for the primary CPU node:
- enable-method: should be "brcm,bcm63138"
Optional properties for the secondary CPU node:
- enable-method: should be "brcm,bcm63138"
- resets: phandle to the relevant PMB controller, one integer indicating the internal
bus number, and a second integer indicating the address of the CPU in the PMB
internal bus number.
Example:
cpus {
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
...
enable-method = "brcm,bcm63138";
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
...
enable-method = "brcm,bcm63138";
resets = <&pmb0 4 1>;
};
};
bootlut: bootlut@8000 {
compatible = "brcm,bcm63138-bootlut";
reg = <0x8000 0x50>;
};
=======
reboot
------
Two nodes are required for software reboot: a timer node and a syscon-reboot node.
Timer node:
- compatible: Must be "brcm,bcm6328-timer", "syscon"
- reg: Register base address and length
Syscon reboot node:
See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
detailed list of properties, the two values defined below are specific to the
BCM6328-style timer:
- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register
from the beginning of the TIMER block
- mask: Should be 1 for the SoftRst bit.
Example:
timer: timer@80 {
compatible = "brcm,bcm6328-timer", "syscon";
reg = <0x80 0x3c>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&timer>;
offset = <0x34>;
mask = <0x1>;
};

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Broadband SoC
description:
Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
chips that can be used as home gateway, router and WLAN AP for residential,
enterprise and carrier applications.
maintainers:
- William Zhang <william.zhang@broadcom.com>
- Anand Gore <anand.gore@broadcom.com>
- Kursad Oney <kursad.oney@broadcom.com>
- Rafał Miłecki <rafal@milecki.pl>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM47622 based boards
items:
- enum:
- brcm,bcm947622
- const: brcm,bcm47622
- const: brcm,bcmbca
- description: BCM4906 based boards
items:
- enum:
- netgear,r8000p
- tplink,archer-c2300-v1
- const: brcm,bcm4906
- const: brcm,bcm4908
- const: brcm,bcmbca
- description: BCM4908 based boards
items:
- enum:
- asus,gt-ac5300
- brcm,bcm94908
- netgear,raxe500
- const: brcm,bcm4908
- const: brcm,bcmbca
- description: BCM49408 based boards
items:
- const: brcm,bcm49408
- const: brcm,bcm4908
- const: brcm,bcmbca
- description: BCM4912 based boards
items:
- enum:
- asus,gt-ax6000
- brcm,bcm94912
- const: brcm,bcm4912
- const: brcm,bcmbca
- description: BCM63138 based boards
items:
- enum:
- brcm,bcm963138
- brcm,BCM963138DVT
- const: brcm,bcm63138
- const: brcm,bcmbca
- description: BCM63146 based boards
items:
- enum:
- brcm,bcm963146
- const: brcm,bcm63146
- const: brcm,bcmbca
- description: BCM63148 based boards
items:
- enum:
- brcm,bcm963148
- const: brcm,bcm63148
- const: brcm,bcmbca
- description: BCM63158 based boards
items:
- enum:
- brcm,bcm963158
- const: brcm,bcm63158
- const: brcm,bcmbca
- description: BCM63178 based boards
items:
- enum:
- brcm,bcm963178
- const: brcm,bcm63178
- const: brcm,bcmbca
- description: BCM6756 based boards
items:
- enum:
- brcm,bcm96756
- const: brcm,bcm6756
- const: brcm,bcmbca
- description: BCM6813 based boards
items:
- enum:
- brcm,bcm96813
- const: brcm,bcm6813
- const: brcm,bcmbca
- description: BCM6846 based boards
items:
- enum:
- brcm,bcm96846
- const: brcm,bcm6846
- const: brcm,bcmbca
- description: BCM6855 based boards
items:
- enum:
- brcm,bcm96855
- const: brcm,bcm6855
- const: brcm,bcmbca
- description: BCM6856 based boards
items:
- enum:
- brcm,bcm96856
- const: brcm,bcm6856
- const: brcm,bcmbca
- description: BCM6858 based boards
items:
- enum:
- brcm,bcm96858
- const: brcm,bcm6858
- const: brcm,bcmbca
- description: BCM6878 based boards
items:
- enum:
- brcm,bcm96878
- const: brcm,bcm6878
- const: brcm,bcmbca
additionalProperties: true
...

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ARM Broadcom STB platforms Device Tree Bindings
-----------------------------------------------
Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
SoC shall have the following DT organization:
Required root node properties:
- compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
example:
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Broadcom STB (bcm7445)";
compatible = "brcm,bcm7445", "brcm,brcmstb";
Further, syscon nodes that map platform-specific registers used for general
system control is required:
- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
- compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
"brcm,brcmstb-cpu-biu-ctrl",
"syscon"
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
cpu-biu-ctrl node
-------------------
SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
complex to the different Memory Controller Ports (MCP), one per memory
controller (MEMC). This BIU block offers a feature called Write Pairing which
consists in collapsing two adjacent cache lines into a single (bursted) write
transaction towards the memory controller (MEMC) to maximize write bandwidth.
Required properties:
- compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
Optional properties:
- brcm,write-pairing:
Boolean property, which when present indicates that the chip
supports write-pairing.
example:
rdb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0x00 0xf0000000 0x1000000>;
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
};
hif_cpubiuctrl: syscon@3e2400 {
compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
reg = <0x3e2400 0x5b4>;
brcm,write-pairing;
};
hif_continuation: syscon@452000 {
compatible = "brcm,bcm7445-hif-continuation", "syscon";
reg = <0x452000 0x100>;
};
};
Nodes that allow for support of SMP initialization and reboot are required:
smpboot
-------
Required properties:
- compatible
The string "brcm,brcmstb-smpboot".
- syscon-cpu
A phandle / integer array property which lets the BSP know the location
of certain CPU power-on registers.
The layout of the property is as follows:
o a phandle to the "hif_cpubiuctrl" syscon node
o offset to the base CPU power zone register
o offset to the base CPU reset register
- syscon-cont
A phandle pointing to the syscon node which describes the CPU boot
continuation registers.
o a phandle to the "hif_continuation" syscon node
example:
smpboot {
compatible = "brcm,brcmstb-smpboot";
syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
syscon-cont = <&hif_continuation>;
};
reboot
-------
Required properties
- compatible
The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
chips with the old SUN_TOP_CTRL interface.
- syscon
A phandle / integer array that points to the syscon node which describes
the general system reset registers.
o a phandle to "sun_top_ctrl"
o offset to the "reset source enable" register
o offset to the "software master reset" register
example:
reboot {
compatible = "brcm,brcmstb-reboot";
syscon = <&sun_top_ctrl 0x304 0x308>;
};
Power management
----------------
For power management (particularly, S2/S3/S5 system suspend), the following SoC
components are needed:
= Always-On control block (AON CTRL)
This hardware provides control registers for the "always-on" (even in low-power
modes) hardware, such as the Power Management State Machine (PMSM).
Required properties:
- compatible : should contain "brcm,brcmstb-aon-ctrl"
- reg : the register start and length for the AON CTRL block
Example:
aon-ctrl@410000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x410000 0x400>;
};
= Memory controllers
A Broadcom STB SoC typically has a number of independent memory controllers,
each of which may have several associated hardware blocks, which are versioned
independently (control registers, DDR PHYs, etc.). One might consider
describing these controllers as a parent "memory controllers" block, which
contains N sub-nodes (one for each controller in the system), each of which is
associated with a number of hardware register resources (e.g., its PHY). See
the example device tree snippet below.
== MEMC (MEMory Controller)
Represents a single memory controller instance.
Required properties:
- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
Should contain subnodes for any of the following relevant hardware resources:
== DDR PHY control
Control registers for this memory controller's DDR PHY.
Required properties:
- compatible : should contain one of these
"brcm,brcmstb-ddr-phy-v71.1"
"brcm,brcmstb-ddr-phy-v72.0"
"brcm,brcmstb-ddr-phy-v225.1"
"brcm,brcmstb-ddr-phy-v240.1"
"brcm,brcmstb-ddr-phy-v240.2"
- reg : the DDR PHY register range
== DDR SHIMPHY
Control registers for this memory controller's DDR SHIMPHY.
Required properties:
- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
- reg : the DDR SHIMPHY register range
== MEMC DDR control
Sequencer DRAM parameters and control registers. Used for Self-Refresh
Power-Down (SRPD), among other things.
See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
full list of supported compatible strings and properties.
Example:
memory_controllers {
ranges;
compatible = "simple-bus";
memc@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges;
ddr-phy@f1106000 {
compatible = "brcm,brcmstb-ddr-phy-v240.1";
reg = <0xf1106000 0x21c>;
};
shimphy@f1108000 {
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
reg = <0xf1108000 0xe4>;
};
memc-ddr@f1102000 {
reg = <0xf1102000 0x800>;
compatible = "brcm,brcmstb-memc-ddr";
};
};
memc@1 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges;
ddr-phy@f1186000 {
compatible = "brcm,brcmstb-ddr-phy-v240.1";
reg = <0xf1186000 0x21c>;
};
shimphy@f1188000 {
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
reg = <0xf1188000 0xe4>;
};
memc-ddr@f1182000 {
reg = <0xf1182000 0x800>;
compatible = "brcm,brcmstb-memc-ddr";
};
};
memc@2 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges;
ddr-phy@f1206000 {
compatible = "brcm,brcmstb-ddr-phy-v240.1";
reg = <0xf1206000 0x21c>;
};
shimphy@f1208000 {
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
reg = <0xf1208000 0xe4>;
};
memc-ddr@f1202000 {
reg = <0xf1202000 0x800>;
compatible = "brcm,brcmstb-memc-ddr";
};
};
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Cygnus
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm11300
- brcm,bcm11320
- brcm,bcm11350
- brcm,bcm11360
- brcm,bcm58300
- brcm,bcm58302
- brcm,bcm58303
- brcm,bcm58305
- const: brcm,cygnus
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Hurricane 2
description:
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
flash and a PCIe attached integrated switching engine.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- ubnt,unifi-switch8
- const: brcm,bcm53342
- const: brcm,hr2
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom North Star 2 (NS2)
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,ns2-svk
- brcm,ns2-xmc
- const: brcm,ns2
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar Plus
description:
Broadcom Northstar Plus family of SoCs are used for switching control
and management applications as well as residential router/gateway
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
SATA and several other IO controllers.
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM58522 based boards
items:
- enum:
- brcm,bcm958522er
- const: brcm,bcm58522
- const: brcm,nsp
- description: BCM58525 based boards
items:
- enum:
- brcm,bcm958525er
- brcm,bcm958525xmc
- const: brcm,bcm58525
- const: brcm,nsp
- description: BCM58535 based boards
items:
- const: brcm,bcm58535
- const: brcm,nsp
- description: BCM58622 based boards
items:
- enum:
- brcm,bcm958622hr
- const: brcm,bcm58622
- const: brcm,nsp
- description: BCM58623 based boards
items:
- enum:
- brcm,bcm958623hr
- const: brcm,bcm58623
- const: brcm,nsp
- description: BCM58625 based boards
items:
- enum:
- brcm,bcm958625hr
- brcm,bcm958625k
- meraki,mx64
- meraki,mx64-a0
- meraki,mx64w
- meraki,mx64w-a0
- meraki,mx65
- meraki,mx65w
- const: brcm,bcm58625
- const: brcm,nsp
- description: BCM88312 based boards
items:
- enum:
- brcm,bcm988312hr
- const: brcm,bcm88312
- const: brcm,nsp
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Stingray
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm958742k
- brcm,bcm958742t
- brcm,bcm958802a802x
- const: brcm,stingray
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Vulcan
maintainers:
- Robert Richter <rrichter@marvell.com>
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,vulcan-eval
- cavium,thunderx2-cn9900
- const: brcm,vulcan-soc
additionalProperties: true
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Raspberry Pi VideoCore firmware driver
maintainers:
- Eric Anholt <eric@anholt.net>
- Stefan Wahren <wahrenst@gmx.net>
select:
properties:
compatible:
contains:
const: raspberrypi,bcm2835-firmware
required:
- compatible
properties:
compatible:
items:
- const: raspberrypi,bcm2835-firmware
- const: simple-mfd
mboxes:
maxItems: 1
clocks:
type: object
additionalProperties: false
properties:
compatible:
const: raspberrypi,firmware-clocks
"#clock-cells":
const: 1
description: >
The argument is the ID of the clocks contained by the
firmware messages.
required:
- compatible
- "#clock-cells"
reset:
type: object
additionalProperties: false
properties:
compatible:
const: raspberrypi,firmware-reset
"#reset-cells":
const: 1
description: >
The argument is the ID of the firmware reset line to affect.
required:
- compatible
- "#reset-cells"
pwm:
type: object
additionalProperties: false
properties:
compatible:
const: raspberrypi,firmware-poe-pwm
"#pwm-cells":
# See pwm.yaml in this directory for a description of the cells format.
const: 2
required:
- compatible
- "#pwm-cells"
required:
- compatible
- mboxes
additionalProperties: false
examples:
- |
firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
mboxes = <&mailbox>;
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
reset: reset {
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
pwm: pwm {
compatible = "raspberrypi,firmware-poe-pwm";
#pwm-cells = <2>;
};
};
...

23
Bindings/arm/bitmain.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bitmain.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bitmain platform
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
$nodename:
const: "/"
compatible:
items:
- enum:
- bitmain,sophon-edge
- const: bitmain,bm1880
additionalProperties: true
...

24
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda Platforms
maintainers:
- Rob Herring <robh@kernel.org>
description: |+
Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
or Cortex-A15 based ECX-2000 SOCs
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- calxeda,highbank
- calxeda,ecx-2000
additionalProperties: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda Highbank system registers
description: |
The Calxeda Highbank system has a block of MMIO registers controlling
several generic system aspects. Those can be used to control some power
management, they also contain some gate and PLL clocks.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: calxeda,hb-sregs
reg:
maxItems: 1
clocks:
type: object
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sregs@fff3c000 {
compatible = "calxeda,hb-sregs";
reg = <0xfff3c000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333000>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda Highbank L2 cache ECC
description: |
Binding for the Calxeda Highbank L2 cache controller ECC device.
This does not cover the actual L2 cache controller control registers,
but just the error reporting functionality.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: "calxeda,hb-sregs-l2-ecc"
reg:
maxItems: 1
interrupts:
items:
- description: single bit error interrupt
- description: double bit error interrupt
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
interrupts = <0 71 4>, <0 72 4>;
};

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Cavium Thunder platform device tree bindings
--------------------------------------------
Boards with Cavium's Thunder SoC shall have following properties.
Root Node
---------
Required root node properties:
- compatible = "cavium,thunder-88xx";

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Cavium ThunderX2 CN99XX platform tree bindings
----------------------------------------------
Boards with Cavium ThunderX2 CN99XX SoC shall have the root property:
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
These SoC uses the "cavium,thunder2" core which will be compatible
with "brcm,vulcan".

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CCI Interconnect Bus Masters
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: |
Masters in the device tree connected to a CCI port (inclusive of CPUs
and their cpu nodes).
select: true
properties:
cci-control-port:
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: true
examples:
- |
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
cci-control-port = <&cci_control1>;
reg = <0>;
};
};
...

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========================================================
Secondary CPU enable-method "al,alpine-smp" binding
========================================================
This document describes the "al,alpine-smp" method for
enabling secondary CPUs. To apply to all CPUs, a single
"al,alpine-smp" enable method should be defined in the
"cpus" node.
Enable method name: "al,alpine-smp"
Compatible machines: "al,alpine"
Compatible CPUs: "arm,cortex-a15"
Related properties: (none)
Note:
This enable method requires valid nodes compatible with
"al,alpine-cpu-resume" and "al,alpine-nb-service".
* Alpine CPU resume registers
The CPU resume register are used to define required resume address after
reset.
Properties:
- compatible : Should contain "al,alpine-cpu-resume".
- reg : Offset and length of the register set for the device
* Alpine System-Fabric Service Registers
The System-Fabric Service Registers allow various operation on CPU and
system fabric, like powering CPUs off.
Properties:
- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
- reg : Offset and length of the register set for the device
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "al,alpine-smp";
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <1>;
};
cpu@2 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <2>;
};
cpu@3 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <3>;
};
};
cpu_resume {
compatible = "al,alpine-cpu-resume";
reg = <0xfbff5ed0 0x30>;
};
nb_service {
compatible = "al,alpine-sysfabric-service", "syscon";
reg = <0xfb070000 0x10000>;
};

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========================================================
Secondary CPU enable-method "marvell,berlin-smp" binding
========================================================
This document describes the "marvell,berlin-smp" method for enabling secondary
CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
be defined in the "cpus" node.
Enable method name: "marvell,berlin-smp"
Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
Related properties: (none)
Note:
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
"marvell,berlin-cpu-ctrl"[1].
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,berlin-smp";
cpu@0 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
cpu@1 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
};
};
--
[1] arm/marvell,berlin.txt

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=========================================================
Secondary CPU enable-method "nuvoton,npcm750-smp" binding
=========================================================
To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
defined in the "cpus" node.
Enable method name: "nuvoton,npcm750-smp"
Compatible machines: "nuvoton,npcm750"
Compatible CPUs: "arm,cortex-a9"
Related properties: (none)
Note:
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
"nuvoton,npcm750-gcr".
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "nuvoton,npcm750-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};

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Bindings/arm/cpus.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM CPUs
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: |+
The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.
Bindings for CPU nodes follow the Devicetree Specification, available from:
https://www.devicetree.org/specifications/
with updates for 32-bit and 64-bit ARM systems provided in this document.
================================
Convention used in this document
================================
This document follows the conventions described in the Devicetree
Specification, with the addition:
- square brackets define bitfields, eg reg[7:0] value of the bitfield in
the reg property contained in bits 7 down to 0
=====================================
cpus and cpu node bindings definition
=====================================
The ARM architecture, in accordance with the Devicetree Specification,
requires the cpus and cpu nodes to be present and contain the properties
described below.
properties:
reg:
maxItems: 1
description: |
Usage and definition depend on ARM architecture version and
configuration:
On uniprocessor ARM architectures previous to v7
this property is required and must be set to 0.
On ARM 11 MPcore based systems this property is
required and matches the CPUID[11:0] register bits.
Bits [11:0] in the reg cell must be set to
bits [11:0] in CPU ID register.
All other bits in the reg cell must be set to 0.
On 32-bit ARM v7 or later systems this property is
required and matches the CPU MPIDR[23:0] register
bits.
Bits [23:0] in the reg cell must be set to
bits [23:0] in MPIDR.
All other bits in the reg cell must be set to 0.
On ARM v8 64-bit systems this property is required
and matches the MPIDR_EL1 register affinity bits.
* If cpus node's #address-cells property is set to 2
The first reg cell bits [7:0] must be set to
bits [39:32] of MPIDR_EL1.
The second reg cell bits [23:0] must be set to
bits [23:0] of MPIDR_EL1.
* If cpus node's #address-cells property is set to 1
The reg cell bits [23:0] must be set to bits [23:0]
of MPIDR_EL1.
All other bits in the reg cells must be set to 0.
compatible:
enum:
- apple,avalanche
- apple,blizzard
- apple,icestorm
- apple,firestorm
- arm,arm710t
- arm,arm720t
- arm,arm740t
- arm,arm7ej-s
- arm,arm7tdmi
- arm,arm7tdmi-s
- arm,arm9es
- arm,arm9ej-s
- arm,arm920t
- arm,arm922t
- arm,arm925
- arm,arm926e-s
- arm,arm926ej-s
- arm,arm940t
- arm,arm946e-s
- arm,arm966e-s
- arm,arm968e-s
- arm,arm9tdmi
- arm,arm1020e
- arm,arm1020t
- arm,arm1022e
- arm,arm1026ej-s
- arm,arm1136j-s
- arm,arm1136jf-s
- arm,arm1156t2-s
- arm,arm1156t2f-s
- arm,arm1176jzf
- arm,arm1176jz-s
- arm,arm1176jzf-s
- arm,arm11mpcore
- arm,armv8 # Only for s/w models
- arm,cortex-a5
- arm,cortex-a7
- arm,cortex-a8
- arm,cortex-a9
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
- arm,cortex-a32
- arm,cortex-a34
- arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
- arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
- arm,cortex-a78c
- arm,cortex-a510
- arm,cortex-a520
- arm,cortex-a710
- arm,cortex-a715
- arm,cortex-a720
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
- arm,cortex-m3
- arm,cortex-m4
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-r52
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,cortex-x4
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
- arm,neoverse-v1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
- cavium,thunder
- cavium,thunder2
- faraday,fa526
- intel,sa110
- intel,sa1100
- marvell,feroceon
- marvell,mohawk
- marvell,pj4a
- marvell,pj4b
- marvell,sheeva-v5
- marvell,sheeva-v7
- nvidia,tegra132-denver
- nvidia,tegra186-denver
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
- qcom,kryo240
- qcom,kryo250
- qcom,kryo260
- qcom,kryo280
- qcom,kryo360
- qcom,kryo385
- qcom,kryo465
- qcom,kryo468
- qcom,kryo485
- qcom,kryo560
- qcom,kryo570
- qcom,kryo660
- qcom,kryo685
- qcom,kryo780
- qcom,scorpion
enable-method:
$ref: /schemas/types.yaml#/definitions/string
oneOf:
# On ARM v8 64-bit this property is required
- enum:
- psci
- spin-table
# On ARM 32-bit systems this property is optional
- enum:
- actions,s500-smp
- allwinner,sun6i-a31
- allwinner,sun8i-a23
- allwinner,sun9i-a80-smp
- allwinner,sun8i-a83t-smp
- amlogic,meson8-smp
- amlogic,meson8b-smp
- arm,realview-smp
- aspeed,ast2600-smp
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm2836-smp
- brcm,bcm63138
- brcm,bcm-nsp-smp
- brcm,brahma-b15
- marvell,armada-375-smp
- marvell,armada-380-smp
- marvell,armada-390-smp
- marvell,armada-xp-smp
- marvell,98dx3236-smp
- marvell,mmp3-smp
- mediatek,mt6589-smp
- mediatek,mt81xx-tz-smp
- qcom,gcc-msm8660
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
- qcom,msm8226-smp
- qcom,msm8909-smp
# Only valid on ARM 32-bit, see above for ARM v8 64-bit
- qcom,msm8916-smp
- renesas,apmu
- renesas,r9a06g032-smp
- rockchip,rk3036-smp
- rockchip,rk3066-smp
- socionext,milbeaut-m10v-smp
- ste,dbx500-smp
- ti,am3352
- ti,am4372
cpu-release-addr:
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- $ref: /schemas/types.yaml#/definitions/uint64
description:
The DT specification defines this as 64-bit always, but some 32-bit Arm
systems have used a 32-bit value which must be supported.
Required for systems that have an "enable-method"
property value of "spin-table".
cpu-idle-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
List of phandles to idle state nodes supported
by this cpu (see ./idle-states.yaml).
capacity-dmips-mhz:
description:
u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
cci-control-port: true
dynamic-power-coefficient:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the CPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
performance-domains:
maxItems: 1
description:
List of phandles and performance domain specifiers, as defined by
bindings of the performance domain provider. See also
dvfs/performance-domain.yaml.
power-domains:
description:
List of phandles and PM domain specifiers, as defined by bindings of the
PM domain provider (see also ../power_domain.txt).
power-domain-names:
description:
A list of power domain name strings sorted in the same order as the
power-domains property.
For PSCI based platforms, the name corresponding to the index of the PSCI
PM domain provider, must be "psci". For SCMI based platforms, the name
corresponding to the index of an SCMI performance domain provider, must be
"perf".
qcom,saw:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the SAW* node associated with this CPU.
Required for systems that have an "enable-method" property
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
* arm/msm/qcom,saw2.txt
qcom,acc:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the ACC* node associated with this CPU.
Required for systems that have an "enable-method" property
value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
"qcom,msm8916-smp".
* arm/msm/qcom,kpss-acc.txt
rockchip,pmu:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the syscon node controlling the cpu core power domains.
Optional for systems that have an "enable-method"
property value of "rockchip,rk3066-smp"
While optional, it is the preferred way to get access to
the cpu-core power-domains.
secondary-boot-reg:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Required for systems that have an "enable-method" property value of
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
This includes the following SoCs: |
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register used to request the ROM holding pen
code release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
if:
# If the enable-method property contains one of those values
properties:
enable-method:
contains:
enum:
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm-nsp-smp
# and if enable-method is present
required:
- enable-method
then:
required:
- secondary-boot-reg
required:
- device_type
- reg
- compatible
dependencies:
rockchip,pmu: [enable-method]
additionalProperties: true
examples:
- |
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
};
};
- |
// Example 2 (Cortex-A8 uniprocessor 32-bit system):
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
};
};
- |
// Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
reg = <0x0>;
};
};
- |
// Example 4 (ARM Cortex-A57 64-bit system):
cpus {
#size-cells = <0>;
#address-cells = <2>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@10000 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@10001 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@10100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@10101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100000000 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100000001 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100000100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100000101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100010000 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100010001 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100010100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
cpu@100010101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/digicolor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Conexant Digicolor Platforms
maintainers:
- Baruch Siach <baruch@tkos.co.il>
properties:
$nodename:
const: "/"
compatible:
const: cnxt,cx92755
additionalProperties: true
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OP-TEE
maintainers:
- Jens Wiklander <jens.wiklander@linaro.org>
description: |
OP-TEE is a piece of software using hardware features to provide a Trusted
Execution Environment. The security can be provided with ARM TrustZone, but
also by virtualization or a separate chip.
We're using "linaro" as the first part of the compatible property for
the reference implementation maintained by Linaro.
properties:
$nodename:
const: optee
compatible:
const: linaro,optee-tz
interrupts:
maxItems: 1
description: |
This interrupt which is used to signal an event by the secure world
software is expected to be either a per-cpu interrupt or an
edge-triggered peripheral interrupt.
method:
enum: [smc, hvc]
description: |
The method of calling the OP-TEE Trusted OS depending on smc or hvc
instruction usage.
SMC #0, register assignments
or
HVC #0, register assignments
register assignments are specified in drivers/tee/optee/optee_smc.h
required:
- compatible
- method
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
};
};
- |
firmware {
optee {
compatible = "linaro,optee-tz";
method = "hvc";
};
};

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* Software Delegated Exception Interface (SDEI)
Firmware implementing the SDEI functions described in ARM document number
ARM DEN 0054A ("Software Delegated Exception Interface") can be used by
Linux to receive notification of events such as those generated by
firmware-first error handling, or from an IRQ that has been promoted to
a firmware-assisted NMI.
The interface provides a number of API functions for registering callbacks
and enabling/disabling events. Functions are invoked by trapping to the
privilege level of the SDEI firmware (specified as part of the binding
below) and passing arguments in a manner specified by the "SMC Calling
Convention (ARM DEN 0028B):
r0 => 32-bit Function ID / return value
{r1 - r3} => Parameters
Note that the immediate field of the trapping instruction must be set
to #0.
The SDEI_EVENT_REGISTER function registers a callback in the kernel
text to handle the specified event number.
The sdei node should be a child node of '/firmware' and have required
properties:
- compatible : should contain:
* "arm,sdei-1.0" : For implementations complying to SDEI version 1.x.
- method : The method of calling the SDEI firmware. Permitted
values are:
* "smc" : SMC #0, with the register assignments specified in this
binding.
* "hvc" : HVC #0, with the register assignments specified in this
binding.
Example:
firmware {
sdei {
compatible = "arm,sdei-1.0";
method = "smc";
};
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Trusted Foundations
description: |
Boards that use the Trusted Foundations secure monitor can signal its
presence by declaring a node compatible under the /firmware/ node
maintainers:
- Stephen Warren <swarren@nvidia.com>
properties:
$nodename:
const: trusted-foundations
compatible:
const: tlm,trusted-foundations
tlm,version-major:
$ref: /schemas/types.yaml#/definitions/uint32
description: major version number of Trusted Foundations firmware
tlm,version-minor:
$ref: /schemas/types.yaml#/definitions/uint32
description: minor version number of Trusted Foundations firmware
required:
- compatible
- tlm,version-major
- tlm,version-minor
additionalProperties: false
examples:
- |
firmware {
trusted-foundations {
compatible = "tlm,trusted-foundations";
tlm,version-major = <2>;
tlm,version-minor = <8>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP Power Management Components
maintainers:
- A.s. Dong <aisheng.dong@nxp.com>
description: |
The Multi-System Mode Controller (MSMC) is responsible for sequencing
the MCU into and out of all stop and run power modes. Specifically, it
monitors events to trigger transitions between power modes while
controlling the power, clocks, and memories of the MCU to achieve the
power consumption and functionality of that mode.
The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
Standby modes for either Cortex family. Run, Wait, and Stop are the
common terms used for the primary operating modes of Kinetis
microcontrollers.
properties:
compatible:
const: fsl,imx7ulp-smc1
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
smc1@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP System Integration Module
maintainers:
- Anson Huang <anson.huang@nxp.com>
description: |
The system integration module (SIM) provides system control and chip configuration
registers. In this module, chip revision information is located in JTAG ID register,
and a set of registers have been made available in DGO domain for SW use, with the
objective to maintain its value between system resets.
properties:
compatible:
items:
- const: fsl,imx7ulp-sim
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};

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Freescale Vybrid Miscellaneous System Control - CPU Configuration
The MSCM IP contains multiple sub modules, this binding describes the first
block of registers which contains CPU configuration information.
Required properties:
- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
- reg: the register range of the MSCM CPU configuration registers
Example:
mscm_cpucfg: cpucfg@40001000 {
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
reg = <0x40001000 0x800>;
}

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Freescale Vybrid Miscellaneous System Control - Interrupt Router
The MSCM IP contains multiple sub modules, this binding describes the second
block of registers which control the interrupt router. The interrupt router
allows to configure the recipient of each peripheral interrupt. Furthermore
it controls the directed processor interrupts. The module is available in all
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
which comes with a Cortex-A5/Cortex-M4 combination).
Required properties:
- compatible: "fsl,vf610-mscm-ir"
- reg: the register range of the MSCM Interrupt Router
- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
to get the current CPU ID
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Two cells, interrupt number and cells.
The hardware interrupt number according to interrupt
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
Example:
mscm_ir: interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
}

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* Freescale Multi Master Multi Memory Interface (M4IF) module
Required properties:
- compatible : Should be "fsl,imx51-m4if"
- reg : Address and length of the register set for the device
Example:
m4if: m4if@83fd8000 {
compatible = "fsl,imx51-m4if";
reg = <0x83fd8000 0x1000>;
};

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* Freescale Tigerp platform module
Required properties:
- compatible : Should be "fsl,imx51-tigerp"
- reg : Address and length of the register set for the device
Example:
tigerp: tigerp@83fa0000 {
compatible = "fsl,imx51-tigerp";
reg = <0x83fa0000 0x28>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/gemini.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina systems Gemini platforms
description: |
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
produced by Storlink Semiconductor around 2005. The company was renamed
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
It was derived from earlier products from Storm named SL3316 (Centroid) and
SL3512 (Bulverde).
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
in turn acquired by Inphi, who seem to have discontinued this product family.
Many of the IP blocks used in the SoC comes from Faraday Technology.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Storlink Semiconductor Gemini324 EV-Board also known
as Storm Semiconductor SL93512R_BRD
items:
- const: storlink,gemini324
- const: storm,sl93512r
- const: cortina,gemini
- description: D-Link DIR-685 Xtreme N Storage Router
items:
- const: dlink,dir-685
- const: cortina,gemini
- description: D-Link DNS-313 1-Bay Network Storage Enclosure
items:
- const: dlink,dns-313
- const: cortina,gemini
- description: Edimax NS-2502
items:
- const: edimax,ns-2502
- const: cortina,gemini
- description: ITian Square One SQ201
items:
- const: itian,sq201
- const: cortina,gemini
- description: Raidsonic NAS IB-4220-B
items:
- const: raidsonic,ib-4220-b
- const: cortina,gemini
- description: SSI 1328
items:
- const: ssi,1328
- const: cortina,gemini
- description: Teltonika RUT1xx Mobile Router
items:
- const: teltonika,rut1xx
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-111
items:
- const: wiligear,wiliboard-wbd111
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-222
items:
- const: wiligear,wiliboard-wbd222
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-111 - old incorrect binding
items:
- const: wiliboard,wbd111
- const: cortina,gemini
deprecated: true
- description: Wiligear Wiliboard WBD-222 - old incorrect binding
items:
- const: wiliboard,wbd222
- const: cortina,gemini
deprecated: true
additionalProperties: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon CPU controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
The clock registers and power registers of secondary cores are defined
in CPU controller, especially in HIX5HD2 SoC.
properties:
compatible:
items:
- const: hisilicon,cpuctrl
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^clock@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
const: hisilicon,hix5hd2-clock
reg:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
cpuctrl@a22000 {
compatible = "hisilicon,cpuctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00a22000 0x2000>;
ranges = <0 0x00a22000 0x2000>;
clock: clock@0 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0 0x2000>;
#clock-cells = <1>;
};
};
...

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