dts: dragonboard820c: use correct bindings for clocks
Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be compatible with upstream. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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@ -8,6 +8,7 @@
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/dts-v1/;
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#include "skeleton64.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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/ {
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model = "Qualcomm Technologies, Inc. DB820c";
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@ -78,7 +79,7 @@
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blsp2_uart2: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x75b0000 0x1000>;
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clocks = <&gcc 4>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
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clock-names = "core";
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pinctrl-names = "uart";
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pinctrl-0 = <&blsp8_uart>;
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@ -89,7 +90,7 @@
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reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
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index = <0x0>;
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bus-width = <4>;
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clock = <&gcc 0>;
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clock = <&gcc GCC_SDCC1_APPS_CLK>;
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clock-frequency = <200000000>;
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};
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@ -13,6 +13,7 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include "clock-qcom.h"
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@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0: /* SDC1 */
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case GCC_SDCC1_APPS_CLK: /* SDC1 */
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return clk_init_sdc(priv, rate);
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break;
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case 4: /*UART2*/
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case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
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return clk_init_uart(priv);
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default:
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return 0;
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