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sunxi: remove CONFIG_MACPWR

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The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
the power for the Ethernet "MAC" (mostly PHY, really).
In the DT this is described with the phy-supply property in the MAC DT
node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
only in U-Boot proper, and use a DM driver there, we should use the DT
instead of hardcoding this.

Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
that regulator and enable it, at probe time. Then drop the current code
from board.c, which was doing that job before.
This allows us to remove the MACPWR Kconfig definition and the respective
values from the defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
This commit is contained in:
Andre Przywara 2022-06-08 14:56:56 +01:00
parent 091442993c
commit 5ad98c57b8
26 changed files with 10 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/mach-sunxi/Kconfig
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@ -695,13 +695,6 @@ config OLD_SUNXI_KERNEL_COMPAT
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
config MACPWR
string "MAC power pin"
default ""
help
Set the pin used to power the MAC. This takes a string in the format
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config MMC1_PINS_PH
bool "Pins for mmc1 are on Port H"
depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40

12
board/sunxi/board.c
View File

@ -187,7 +187,7 @@ enum env_location env_get_location(enum env_operation op, int prio)
/* add board specific code here */
int board_init(void)
{
__maybe_unused int id_pfr1, ret, macpwr_pin;
__maybe_unused int id_pfr1, ret;
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
@ -224,15 +224,6 @@ int board_init(void)
if (ret)
return ret;
/* strcmp() would look better, but doesn't get optimised away. */
if (CONFIG_MACPWR[0]) {
macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
if (macpwr_pin >= 0) {
gpio_request(macpwr_pin, "macpwr");
gpio_direction_output(macpwr_pin, 1);
}
}
#if CONFIG_IS_ENABLED(DM_I2C)
/*
* Temporary workaround for enabling I2C clocks until proper sunxi DM
@ -240,7 +231,6 @@ int board_init(void)
*/
i2c_init_board();
#endif
eth_init_board();
return 0;

1
configs/Bananapi_M2_Ultra_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_MACPWR="PA17"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH23"
CONFIG_USB2_VBUS_PIN="PH23"

1
configs/Bananapi_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y

1
configs/Bananapro_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y

1
configs/Lamobo_R1_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/Mele_A1000_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_MACPWR="PH15"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y

1
configs/Orangepi_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y

1
configs/Orangepi_mini_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"

1
configs/bananapi_m1_plus_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y

1
configs/bananapi_m2_plus_h3_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/bananapi_m2_plus_h5_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/i12-tvbox_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/jesurun_q5_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_MACPWR="PH19"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/mixtile_loftq_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MACPWR="PA21"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""

1
configs/nanopi_m1_plus_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/nanopi_neo_plus2_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/nanopi_r1s_h5_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/orangepi_pc2_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/orangepi_plus2e_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/orangepi_plus_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/orangepi_win_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_MACPWR="PD14"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPI_FLASH_WINBOND=y

1
configs/pine_h64_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MACPWR="PC16"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_SPL_SPI_SUNXI=y

1
configs/zeropi_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_MACPWR="PD6"
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y

7
drivers/net/sun8i_emac.c
View File

@ -29,6 +29,7 @@
#include <net.h>
#include <reset.h>
#include <wait_bit.h>
#include <power/regulator.h>
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
@ -170,6 +171,7 @@ struct emac_eth_dev {
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
#endif
struct udevice *phy_reg;
};
@ -720,6 +722,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
sun8i_emac_set_syscon(sun8i_pdata, priv);
if (priv->phy_reg)
regulator_set_enable(priv->phy_reg, true);
sun8i_mdio_init(dev->name, dev);
priv->bus = miiphy_get_dev_by_name(dev->name);
@ -829,6 +834,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;
device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
pdata->phy_interface = -1;
priv->phyaddr = -1;
priv->use_internal_phy = false;

4
drivers/net/sunxi_emac.c
View File

@ -598,9 +598,9 @@ static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr(dev);
phy_node = dev_get_phy_node(dev);
if (phy_node == ofnode_null()) {
if (!ofnode_valid(phy_node)) {
dev_err(dev, "failed to get PHY node\n");
return ret;
return -ENOENT;
}
/*
* The PHY regulator is in the MDIO node, not the EMAC or PHY node.