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Merge branch '2022-06-28-Kconfig-migrations' into next

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- Convert a large number of CONFIG symbols to Kconfig.  Of note is a
  large chunk of USB symbols (and dead code removal), ensuring all
  SPL/TPL/VPL symbols have an appropriate dependency, largely (but not
  entirely) removing the testing of CONFIG_SPL_BUILD in board headers,
  and allowing CONFIG_EXTRA_ENV_TEXT and CONFIG_EXTRA_ENV_SETTINGS to
  co-exist as this facilities migration of many platforms.
This commit is contained in:
Tom Rini 2022-06-29 09:54:02 -04:00
commit 5c873269fc
660 changed files with 1130 additions and 11900 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -2207,7 +2207,7 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
include/generated/env.in drivers/video/u_boot_logo.S \
include/generated/env.* drivers/video/u_boot_logo.S \
tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \

32
README
View File

@ -664,18 +664,6 @@ The following options need to be configured:
CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
- LBA48 Support
CONFIG_LBA48
Set this to enable support for disks larger than 137GB
Also look at CONFIG_SYS_64BIT_LBA.
Whithout these , LBA48 support uses 32bit variables and will 'only'
support disks up to 2.1TB.
CONFIG_SYS_64BIT_LBA:
When enabled, makes the IDE subsystem use 64bit sector addresses.
Default is 32bit.
- NETWORK Support (PCI):
CONFIG_E1000_SPI
Utility code for direct access to the SPI bus on Intel 8257x.
@ -793,9 +781,6 @@ The following options need to be configured:
Supported are USB Keyboards and USB Floppy drives
(TEAC FD-05PUB).
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
HW module registers.
@ -1365,10 +1350,6 @@ The following options need to be configured:
Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
CONFIG_FPGA_COUNT
Specify the number of FPGA devices to support.
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
@ -1892,14 +1873,6 @@ Configuration Settings:
while unprotecting/erasing/programming. Please only enable
this option if you really know what you are doing.
- CONFIG_ENV_MAX_ENTRIES
Maximum number of entries in the hash table that is used
internally to store the environment settings. The default
setting is supposed to be generous and should work in most
cases. This setting can be used to tune behaviour; see
lib/hashtable.c for details.
- CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when
@ -2179,11 +2152,6 @@ Low Level (hardware related) configuration options:
proper). Code that needs stage-specific behavior should check
this.
- CONFIG_SYS_MPC85XX_NO_RESETVEC
Only for 85xx systems. If this variable is specified, the section
.resetvec is not kept and the section .bootpg is placed in the
previous 4k of the .text section.
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
effective address. It is therefore not necessary to regard

14
arch/arm/Kconfig
View File

@ -609,6 +609,9 @@ config ARM64_SUPPORT_AARCH32
help
This ARM64 system supports AArch32 execution state.
config S5P
def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
choice
prompt "Target select"
default TARGET_HIKEY
@ -996,11 +999,6 @@ config ARCH_MX6
imply SYS_THUMB_BUILD
imply SPL_SEPARATE_BSS
if ARCH_MX6
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
config ARCH_MX5
bool "Freescale MX5"
select BOARD_EARLY_INIT_F
@ -2354,6 +2352,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"
source "board/st/stv0991/Kconfig"
@ -2368,8 +2367,3 @@ source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug"
endmenu
config SPL_LDSCRIPT
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64

3
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -701,9 +701,6 @@ config SYS_FSL_HAS_RGMII
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
config HAS_FSL_XHCI_USB
bool
help

8
arch/arm/dts/Makefile
View File

@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb
dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-universal_c210.dtb \
exynos4210-trats.dtb \
@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-spring.dtb \
exynos5250-smdk5250.dtb \

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -37,7 +37,6 @@
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)

2
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -34,7 +34,6 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
@ -96,7 +95,6 @@
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined

5
arch/arm/include/asm/spl.h
View File

@ -6,9 +6,8 @@
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
#if defined(CONFIG_ARCH_OMAP2PLUS) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3)
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) || \
defined(CONFIG_ARCH_K3) || defined(CONFIG_ARCH_OMAP2PLUS)
/* Platform-specific defines */
#include <asm/arch/spl.h>

11
arch/arm/mach-at91/Kconfig
View File

@ -327,6 +327,13 @@ config AT91_EFLASH
Enable the driver for the embedded flash used in the Atmel
AT91SAM9XE devices.
config EFLASH_PROTSECTORS
int "Number of flash sectors to protect from erasing"
depends on AT91_EFLASH
help
If non-zero, this will be the number of sectors of the flash to disallow
U-Boot to ease, starting from the beginning of flash.
config AT91_GPIO_PULLUP
bool "Keep pullups on peripheral pins"
depends on CPU_ARM926EJS
@ -370,8 +377,4 @@ source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7A
endif

4
arch/arm/mach-at91/arm926ejs/eflash.c
View File

@ -120,7 +120,7 @@ unsigned long flash_init(void)
if (i%32 == 0)
tmp = readl(&eefc->frr);
flash_info[0].protect[i] = (tmp >> (i%32)) & 1;
#if defined(CONFIG_EFLASH_PROTSECTORS)
#if CONFIG_VAL(EFLASH_PROTSECTORS)
if (i < CONFIG_EFLASH_PROTSECTORS)
flash_info[0].protect[i] = 1;
#endif
@ -158,7 +158,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot)
debug("protect sector=%ld prot=%d\n", sector, prot);
#if defined(CONFIG_EFLASH_PROTSECTORS)
#if CONFIG_VAL(EFLASH_PROTSECTORS)
if (sector < CONFIG_EFLASH_PROTSECTORS) {
if (!prot) {
printf("eflash: sector %lu cannot be unprotected\n",

3
arch/arm/mach-davinci/Kconfig
View File

@ -134,7 +134,4 @@ endif
source "board/davinci/da8xxevm/Kconfig"
source "board/lego/ev3/Kconfig"
config SPL_LDSCRIPT
default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds"
endif

42
arch/arm/mach-exynos/Kconfig
View File

@ -54,11 +54,15 @@ endchoice
if ARCH_EXYNOS4
config EXYNOS4210
bool
choice
prompt "EXYNOS4 board select"
config TARGET_SMDKV310
bool "Exynos4210 SMDKV310 board"
select EXYNOS4210
select OF_CONTROL
select SUPPORT_SPL
@ -70,6 +74,7 @@ config TARGET_S5PC210_UNIVERSAL
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
select EXYNOS4210
select SUPPORT_SPL
config TARGET_TRATS2
@ -83,6 +88,15 @@ endif
if ARCH_EXYNOS5
config EXYNOS5250
bool
config EXYNOS5420
bool
config EXYNOS5_DT
bool
config SPL_GPIO
default y
@ -97,6 +111,8 @@ choice
config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
config TARGET_ARNDALE
@ -105,36 +121,49 @@ config TARGET_ARNDALE
select ARM_ERRATA_774769
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SMDK5250
bool "SMDK5250 board"
select EXYNOS5_DT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SNOW
bool "Snow board"
select EXYNOS5_DT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SPRING
bool "Spring board"
select EXYNOS5_DT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SMDK5420
bool "SMDK5420 board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
select SUPPORT_SPL
config TARGET_PEACH_PI
bool "Peach Pi board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
select SUPPORT_SPL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
select SUPPORT_SPL
@ -189,6 +218,16 @@ endif
config SYS_SOC
default "exynos"
config EXYNOS_ACE_SHA
bool "Advanced Crypto Engine SHA support"
depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && (LIB_HW_RAND || SHA_HW_ACCEL)
default y if ARCH_EXYNOS5
config EXYNOS_TMU
bool "Exynos5 thermal management unit support"
depends on ARCH_EXYNOS5
default y
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
@ -201,7 +240,4 @@ source "board/samsung/smdk5420/Kconfig"
source "board/samsung/espresso7420/Kconfig"
source "board/samsung/axy17lte/Kconfig"
config SPL_LDSCRIPT
default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
endif

4
arch/arm/mach-exynos/Makefile
View File

@ -10,8 +10,8 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
obj-y += spl_boot.o tzpc.o
obj-y += lowlevel_init.o

2
arch/arm/mach-exynos/dmc_init_exynos4.c
View File

@ -175,7 +175,7 @@ void mem_ctrl_init(int reset)
* 0: full_sync
*/
writel(1, ASYNC_CONFIG);
#ifdef CONFIG_ORIGEN
#ifdef CONFIG_TARGET_ORIGEN
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
APB_SFR_INTERLEAVE_CONF_OFFSET);

4
arch/arm/mach-exynos/exynos4_setup.h
View File

@ -420,7 +420,7 @@ struct mem_timings {
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
#ifdef CONFIG_ORIGEN
#ifdef CONFIG_TARGET_ORIGEN
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
@ -542,7 +542,7 @@ struct mem_timings {
#define CONTROL2_VAL 0x00000000
#ifdef CONFIG_ORIGEN
#ifdef CONFIG_TARGET_ORIGEN
#define TIMINGREF_VAL 0x000000BB
#define TIMINGROW_VAL 0x4046654f
#define TIMINGDATA_VAL 0x46400506

20
arch/arm/mach-exynos/include/mach/pwm_backlight.h
View File

@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: Donghwa Lee <dh09.lee@samsung.com>
*/
#ifndef _PWM_BACKLIGHT_H_
#define _PWM_BACKLIGHT_H_
struct pwm_backlight_data {
int pwm_id;
int period;
int max_brightness;
int brightness;
};
extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
#endif /* _PWM_BACKLIGHT_H_ */

1
arch/arm/mach-exynos/include/mach/system.h
View File

@ -116,6 +116,5 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */

8
arch/arm/mach-exynos/lowlevel_init.c
View File

@ -49,6 +49,10 @@ enum {
};
#ifdef CONFIG_EXYNOS5420
/* Address for relocating helper code (Last 4 KB of IRAM) */
#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000)
/*
* Power up secondary CPUs.
*/
@ -56,7 +60,7 @@ static void secondary_cpu_start(void)
{
v7_enable_smp(EXYNOS5420_INFORM_BASE);
svc32_mode_en();
branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
branch_bx(EXYNOS_RELOCATE_CODE_BASE);
}
/*
@ -153,7 +157,7 @@ static void power_down_core(void)
static void secondary_cores_configure(void)
{
/* Clear secondary boot iRAM base */
writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C));
/* set lowpower flag and address */
writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);

2
arch/arm/mach-exynos/sec_boot.S
View File

@ -21,7 +21,7 @@ relocate_wait_code:
.ltorg
/*
* Secondary core waits here until Primary wake it up.
* Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
* Below code is copied to (CONFIG_IRAM_TOP - 0x1000)
* This is a workaround code which is supposed to act as a
* substitute/supplement to the iROM code.
*

2
arch/arm/mach-imx/imx8/Kconfig
View File

@ -57,11 +57,13 @@ config TARGET_COLIBRI_IMX8X
config TARGET_DENEB
bool "Support i.MX8QXP Capricorn Deneb board"
select BOARD_LATE_INIT
select FACTORYSET
select IMX8QXP
config TARGET_GIEDI
bool "Support i.MX8QXP Capricorn Giedi board"
select BOARD_LATE_INIT
select FACTORYSET
select IMX8QXP
config TARGET_IMX8QM_MEK

2
arch/arm/mach-kirkwood/include/mach/config.h
View File

@ -49,8 +49,6 @@
#define __io
/* Data, registers and alternate blocks are at the same offset */
/* Each 8-bit ATA register is aligned to a 4-bytes address */
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_IDE requires some #defines for ATA registers */
/* ATA registers base is at SATA controller base */
#endif /* CONFIG_IDE */

3
arch/arm/mach-omap2/Kconfig
View File

@ -190,7 +190,4 @@ source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/phytec/phycore_am335x_r2/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif

6
arch/arm/mach-omap2/am33xx/Kconfig
View File

@ -138,6 +138,7 @@ config TARGET_DRACO
select DM
select DM_GPIO
select DM_SERIAL
select FACTORYSET
imply CMD_DM
config TARGET_ETAMIN
@ -146,6 +147,7 @@ config TARGET_ETAMIN
select DM
select DM_GPIO
select DM_SERIAL
select FACTORYSET
imply CMD_DM
config TARGET_PCM051
@ -168,6 +170,7 @@ config TARGET_PXM2
select DM
select DM_GPIO
select DM_SERIAL
select FACTORYSET
imply CMD_DM
config TARGET_RASTABAN
@ -176,6 +179,7 @@ config TARGET_RASTABAN
select DM
select DM_GPIO
select DM_SERIAL
select FACTORYSET
imply CMD_DM
config TARGET_RUT
@ -184,6 +188,7 @@ config TARGET_RUT
select DM
select DM_GPIO
select DM_SERIAL
select FACTORYSET
imply CMD_DM
config TARGET_THUBAN
@ -192,6 +197,7 @@ config TARGET_THUBAN
select DM
select DM_GPIO
select DM_SERIAL
select FACTORYSET
imply CMD_DM
config TARGET_PDU001

3
arch/arm/mach-rockchip/rk3368/Kconfig
View File

@ -65,9 +65,6 @@ source "board/rockchip/sheep_rk3368/Kconfig"
source "board/geekbuying/geekbox/Kconfig"
source "board/rockchip/evb_px5/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds"
config SPL_STACK_R_ADDR
default 0x04000000

4
arch/arm/mach-sunxi/Kconfig
View File

@ -1,9 +1,5 @@
if ARCH_SUNXI
config SPL_LDSCRIPT
default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
config IDENT_STRING
default " Allwinner Technology"

4
arch/arm/mach-tegra/Kconfig
View File

@ -178,6 +178,10 @@ source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
source "arch/arm/mach-tegra/tegra186/Kconfig"
config TEGRA_GPU
bool "Enable setting up the GPU"
depends on TEGRA124 || TEGRA210
config CMD_ENTERRCM
bool "Enable 'enterrcm' command"
default y

3
arch/arm/mach-zynq/Kconfig
View File

@ -1,8 +1,5 @@
if ARCH_ZYNQ
config SPL_LDSCRIPT
default "arch/arm/mach-zynq/u-boot-spl.lds"
config SPL_FS_FAT
default y

13
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -251,19 +251,6 @@ void cpu_init_f (volatile immap_t * im)
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
/* Configure interface. */
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
/* Wait for clock to stabilize */
do {
temp = __raw_readl(&ehci->control);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
}
int cpu_init_r (void)

23
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -1185,6 +1185,29 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx
help
If this variable is specified, the section .resetvec is not kept and
the section .bootpg is placed in the previous 4k of the .text section.
config SPL_SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up, in SPL"
depends on MPC85xx && SPL
help
If this variable is specified, the section .resetvec is not kept and
the section .bootpg is placed in the previous 4k of the .text section,
of the SPL portion of the binary.
config TPL_SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up, in TPL"
depends on MPC85xx && TPL
help
If this variable is specified, the section .resetvec is not kept and
the section .bootpg is placed in the previous 4k of the .text section,
of the SPL portion of the binary.
config FSL_VIA
bool

4
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
View File

@ -15,7 +15,7 @@ SECTIONS
. = IMAGE_TEXT_BASE;
.text : {
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
KEEP(*(.bootpg))
#endif
*(.text*)
@ -66,7 +66,7 @@ SECTIONS
#endif
/* For nor and nand is needed the SPL with section .resetvec */
#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
#ifndef BOOT_PAGE_OFFSET
#define BOOT_PAGE_OFFSET 0x1000

4
arch/powerpc/cpu/mpc85xx/u-boot.lds
View File

@ -19,7 +19,7 @@ SECTIONS
/* Read-only sections, merged into text segment: */
.text :
{
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
#endif
*(.text*)
@ -74,7 +74,7 @@ SECTIONS
__init_end = .;
_end = .;
#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)

4
arch/powerpc/cpu/mpc8xxx/fdt.c
View File

@ -17,10 +17,6 @@
#include <phy.h>
#include <hwconfig.h>
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
{

24
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -31,7 +31,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@ -41,25 +40,19 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_TSECV2
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_TSECV2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
@ -68,11 +61,9 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_TSECV2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@ -84,7 +75,6 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@ -92,9 +82,6 @@
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@ -118,7 +105,6 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -132,7 +118,6 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
@ -151,7 +136,6 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
@ -163,7 +147,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
@ -172,7 +155,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
@ -204,7 +186,6 @@
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
@ -234,7 +215,6 @@
#define CONFIG_SYS_CPRI
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_CPRI_CLK 3
#define CONFIG_SYS_ULB_CLK 4
@ -255,7 +235,6 @@
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -278,7 +257,6 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
@ -309,7 +287,6 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
@ -343,7 +320,6 @@
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0

22
arch/powerpc/include/asm/immap_83xx.h
View File

@ -666,19 +666,6 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
#ifndef CONFIG_ARCH_MPC834X
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
#else
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
#endif
#else
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
#endif
#elif defined(CONFIG_ARCH_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
@ -944,15 +931,6 @@ struct ccsr_gpio {
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000
#endif
#define CONFIG_SYS_MPC83xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
#if defined(CONFIG_ARCH_MPC834X)
#define CONFIG_SYS_MPC83xx_USB2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
#endif
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000

1
arch/x86/Kconfig
View File

@ -956,6 +956,7 @@ config SPL_ACPI_GPE
config TPL_ACPI_GPE
bool "Support ACPI general-purpose events in TPL"
depends on TPL
help
Enable a driver for ACPI GPEs to allow peripherals to send interrupts
via ACPI to the OS. In U-Boot this is only used when U-Boot itself

2
arch/xtensa/dts/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb
dtb-$(CONFIG_XTENSA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb
include $(srctree)/scripts/Makefile.dts

133
board/armadeus/opos6uldev/opos6uldev.env Normal file
View File

@ -0,0 +1,133 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Armadeus Systems
*/
/* Environment is stored in the eMMC boot partition */
env_version=100
consoledev=ttymxc0
board_name=opos6ul
fdt_addr=0x88000000
fdt_high=0xffffffff
fdt_name=opos6uldev
initrd_high=0xffffffff
ip_dyn=yes
stdin=serial
stdout=serial
stderr=serial
mmcdev=0
mmcpart=2
mmcroot=/dev/mmcblk0p2 ro
mmcrootfstype=ext4 rootwait
kernelimg=opos6ul-linux.bin
splashpos=0,0
splashimage=CONFIG_SYS_LOAD_ADDR
videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0
check_env=if test -n ${flash_env_version};
then env default env_version;
else env set flash_env_version ${env_version}; env save;
fi;
if itest ${flash_env_version} != ${env_version}; then
echo "*** Warning - Environment version
change suggests: run flash_reset_env; reset";
env default flash_reset_env;
else exit; fi;
flash_reset_env=env default -f -a && saveenv &&
echo Environment variables erased!
download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl
flash_uboot_spl=
if mmc dev 0 1; then
setexpr sz ${filesize} / 0x200;
setexpr sz ${sz} + 1;
if mmc write ${loadaddr} 0x2 ${sz}; then
echo Flashing of U-boot SPL succeed;
else echo Flashing of U-boot SPL failed;
fi;
fi;
download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img
flash_uboot_img=
if mmc dev 0 1; then
setexpr sz ${filesize} / 0x200;
setexpr sz ${sz} + 1;
if mmc write ${loadaddr} 0x8a ${sz}; then
echo Flashing of U-boot image succeed;
else echo Flashing of U-boot image failed;
fi;
fi;
update_uboot=run download_uboot_spl flash_uboot_spl
download_uboot_img flash_uboot_img
download_kernel=tftpboot ${loadaddr} ${kernelimg}
flash_kernel=
if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then
echo kernel update succeed;
else echo kernel update failed;
fi;
update_kernel=run download_kernel flash_kernel
download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb
flash_dtb=
if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then
echo dtb update succeed;
else echo dtb update in failed;
fi;
update_dtb=run download_dtb flash_dtb
download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4
flash_rootfs=
if mmc dev 0 0; then
setexpr nbblocks ${filesize} / 0x200;
setexpr nbblocks ${nbblocks} + 1;
if mmc write ${loadaddr} 0x40800 ${nbblocks}; then
echo Flashing of rootfs image succeed;
else echo Flashing of rootfs image failed;
fi;
fi;
update_rootfs=run download_rootfs flash_rootfs
flash_failsafe=
if mmc dev 0 0; then
setexpr nbblocks ${filesize} / 0x200;
setexpr nbblocks ${nbblocks} + 1;
if mmc write ${loadaddr} 0x800 ${nbblocks}; then
echo Flashing of rootfs image in failsafe partition succeed;
else echo Flashing of rootfs image in failsafe partition failed;
fi;
fi;
update_failsafe=run download_rootfs flash_failsafe
download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4
flash_userdata=
if mmc dev 0 0; then
setexpr nbblocks ${filesize} / 0x200;
setexpr nbblocks ${nbblocks} + 1;
if mmc write ${loadaddr} 0 ${nbblocks}; then
echo Flashing of user_data image succeed;
else echo Flashing of user_data image failed;
fi;
fi;
update_userdata=run download_userdata flash_userdata; mmc rescan
erase_userdata=
if mmc dev 0 0; then
echo Erasing eMMC User Data partition, no way out...;
mw ${loadaddr} 0 0x200000;
mmc write ${loadaddr} 0 0x1000;
mmc write ${loadaddr} 0x800 0x1000;
mmc write ${loadaddr} 0x40800 0x1000;
mmc write ${loadaddr} 0x440800 0x1000;
fi;
mmc rescan
update_all=run update_rootfs update_uboot
initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}
addipargs=setenv bootargs ${bootargs}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off
addmmcargs=setenv bootargs ${bootargs} root=${mmcroot}
rootfstype=${mmcrootfstype}
emmcboot=run initargs; run addmmcargs;
load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} &&
load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb &&
bootz ${loadaddr} - ${fdt_addr};
emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;
addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw
nfsroot=${serverip}:${rootpath}
nfsboot=run initargs; run addnfsargs addipargs;
nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} &&
nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb &&
bootz ${loadaddr} - ${fdt_addr};

9
board/astro/mcf5373l/fpga.c
View File

@ -168,7 +168,8 @@ Altera_CYC2_Passive_Serial_fns altera_fns = {
altera_post_fn
};
Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
#define FPGA_COUNT 1
Altera_desc altera_fpga[FPGA_COUNT] = {
{Altera_CYC2,
passive_serial,
85903,
@ -182,7 +183,7 @@ int astro5373l_altera_load(void)
{
int i;
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
for (i = 0; i < FPGA_COUNT; i++) {
/*
* I did not yet manage to get relocation work properly,
* so set stuff here instead of static initialisation:
@ -372,7 +373,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_fastwr_config_fn
};
xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
xilinx_desc xilinx_fpga[FPGA_COUNT] = {
{xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
@ -388,7 +389,7 @@ int astro5373l_xilinx_load(void)
fpga_init();
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
for (i = 0; i < FPGA_COUNT; i++) {
/*
* I did not yet manage to get relocation work properly,
* so set stuff here instead of static initialisation:

4
board/freescale/common/Kconfig
View File

@ -108,3 +108,7 @@ config QIXIS_I2C_ACCESS
bool "Access to QIXIS is over i2c"
depends on FSL_QIXIS
default y
config HAS_FSL_DR_USB
def_bool y
depends on USB_EHCI_HCD && PPC

5
board/freescale/m5253demo/m5253demo.c
View File

@ -93,11 +93,6 @@ int testdram(void)
#ifdef CONFIG_IDE
#include <ata.h>
int ide_preinit(void)
{
return (0);
}
void ide_set_reset(int idereset)
{
atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;

2
board/freescale/p1_p2_rdb_pc/Kconfig
View File

@ -11,4 +11,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "p1_p2_rdb_pc"
source "board/freescale/common/Kconfig"
endif

2
board/freescale/p2041rdb/p2041rdb.c
View File

@ -229,7 +229,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
#if defined(CONFIG_HAS_FSL_DR_USB)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif

145
board/gateworks/gw_ventana/gw_ventana.env Normal file
View File

@ -0,0 +1,145 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Gateworks Corporation
*/
splashpos=m,m
splashimage=CONFIG_SYS_LOAD_ADDR
usb_pgood_delay=2000
console=ttymxc1
bootdevs=usb mmc sata flash
hwconfig=_UNKNOWN_
disk=0
part=1
fdt_high=0xffffffff
fdt_addr=0x18000000
initrd_high=0xffffffff
fixfdt=fdt addr ${fdt_addr}
bootdir=boot
loadfdt=
if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then
echo Loaded DTB from ${bootdir}/${fdt_file};
run fixfdt;
elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then
echo Loaded DTB from ${bootdir}/${fdt_file1};
run fixfdt;
elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then
echo Loaded DTB from ${bootdir}/${fdt_file2};
run fixfdt;
fi
fs=ext4
script=6x_bootscript-ventana
loadscript=
if ${fsload} ${loadaddr} ${bootdir}/${script}; then
source ${loadaddr};
fi
uimage=uImage
mmc_root=mmcblk0p1
mmc_boot=
setenv fsload "${fs}load mmc ${disk}:${part}";
mmc dev ${disk} && mmc rescan &&
setenv dtype mmc; run loadscript;
if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
setenv bootargs console=${console},${baudrate}
root=/dev/${mmc_root} rootfstype=${fs}
rootwait rw ${video} ${extra};
if run loadfdt; then
bootm ${loadaddr} - ${fdt_addr};
else
bootm;
fi;
fi
sata_boot=
setenv fsload "${fs}load sata ${disk}:${part}";
sata init &&
setenv dtype sata; run loadscript;
if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
setenv bootargs console=${console},${baudrate}
root=/dev/sda1 rootfstype=${fs}
rootwait rw ${video} ${extra};
if run loadfdt; then
bootm ${loadaddr} - ${fdt_addr};
else
bootm;
fi;
fi
usb_boot=
setenv fsload "${fs}load usb ${disk}:${part}";
usb start && usb dev ${disk} &&
setenv dtype usb; run loadscript;
if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
setenv bootargs console=${console},${baudrate}
root=/dev/sda1 rootfstype=${fs}
rootwait rw ${video} ${extra};
if run loadfdt; then
bootm ${loadaddr} - ${fdt_addr};
else
bootm;
fi;
fi
#ifdef CONFIG_SPI_FLASH
image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin
image_uboot=ventana/u-boot_spi.imx
spi_koffset=0x90000
spi_klen=0x200000
spi_updateuboot=echo Updating uboot from
${serverip}:${image_uboot}...;
tftpboot ${loadaddr} ${image_uboot} &&
sf probe && sf erase 0 80000 &&
sf write ${loadaddr} 400 ${filesize}
spi_update=echo Updating OS from ${serverip}:${image_os}
to ${spi_koffset} ...;
tftp ${loadaddr} ${image_os} &&
sf probe &&
sf update ${loadaddr} ${spi_koffset} ${filesize}
flash_boot=
if sf probe &&
sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then
setenv bootargs console=${console},${baudrate}
root=/dev/mtdblock3
rootfstype=squashfs,jffs2
${video} ${extra};
bootm;
fi
#else
image_rootfs=openwrt-imx6-ventana-rootfs.ubi
nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...;
tftp ${loadaddr} ${image_rootfs} &&
nand erase.part rootfs &&
nand write ${loadaddr} rootfs ${filesize}
flash_boot=
setenv fsload 'ubifsload';
ubi part rootfs;
if ubi check boot; then
ubifsmount ubi0:boot;
setenv root ubi0:rootfs ubi.mtd=2
rootfstype=squashfs,ubifs;
setenv bootdir;
elif ubi check rootfs; then
ubifsmount ubi0:rootfs;
setenv root ubi0:rootfs ubi.mtd=2
rootfstype=ubifs;
fi;
setenv dtype nand; run loadscript;
if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then
setenv bootargs console=${console},${baudrate}
root=${root} ${video} ${extra};
if run loadfdt; then
ubifsumount;
bootm ${loadaddr} - ${fdt_addr};
else
ubifsumount; bootm;
fi;
fi
#endif

36
board/qualcomm/dragonboard410c/dragonboard410c.env Normal file
View File

@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Does what recovery does */
#define REFLASH(file, partnum) \
part start mmc 0 partnum start && \
part size mmc 0 partnum size && \
tftp $loadaddr file && \
mmc write $loadaddr $start $size &&
reflash=
mmc dev 0 &&
usb start &&
dhcp &&
tftp $loadaddr dragonboard/rescue/gpt_both0.bin &&
mmc write $loadaddr 0 43 &&
mmc rescan &&
REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)
REFLASH(dragonboard/rescue/sbl1.mbn, 2)
REFLASH(dragonboard/rescue/rpm.mbn, 3)
REFLASH(dragonboard/rescue/tz.mbn, 4)
REFLASH(dragonboard/rescue/hyp.mbn, 5)
REFLASH(dragonboard/rescue/sec.dat, 6)
REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)
REFLASH(dragonboard/u-boot.img, 8)
usb stop &&
echo Reflash completed
loadaddr=0x81000000
initrd_high=0xffffffffffffffff
linux_image=Image
kernel_addr_r=0x81000000
fdtfile=qcom/apq8016-sbc.dtb
fdt_addr_r=0x83000000
ramdisk_addr_r=0x84000000
scriptaddr=0x90000000
pxefile_addr_r=0x90100000

4
board/samsung/arndale/arndale.c
View File

@ -112,10 +112,10 @@ int checkboard(void)
}
#endif
#ifdef CONFIG_S5P_PA_SYSRAM
#ifdef CONFIG_SMP_PEN_ADDR
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
writel(addr, CONFIG_S5P_PA_SYSRAM);
writel(addr, CONFIG_SMP_PEN_ADDR);
/* make sure this write is really executed */
__asm__ volatile ("dsb\n");

23
board/samsung/trats/trats.c
View File

@ -403,16 +403,6 @@ int exynos_early_init_f(void)
return 0;
}
void exynos_reset_lcd(void)
{
gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
}
int lcd_power(void)
{
#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
@ -460,16 +450,3 @@ int mipi_power(void)
#endif
return 0;
}
#ifdef CONFIG_LCD
void exynos_lcd_misc_init(vidinfo_t *vid)
{
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
#ifdef CONFIG_S6E8AX0
s6e8ax0_init();
env_set("lcdinfo", "lcd=s6e8ax0");
#endif
}
#endif

35
board/samsung/trats2/trats2.c
View File

@ -302,39 +302,4 @@ int mipi_power(void)
return 0;
}
void exynos_lcd_power_on(void)
{
#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
struct pmic *p = pmic_get("MAX77686_PMIC");
/* LCD_2.2V_EN: GPC0[1] */
gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en");
gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
/* LDO25 VCC_3.1V_LCD */
pmic_probe(p);
max77686_set_ldo_voltage(p, 25, 3100000);
max77686_set_ldo_mode(p, 25, OPMODE_LPM);
#endif
}
void exynos_reset_lcd(void)
{
/* reset lcd */
gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset");
gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
udelay(10);
gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
}
void exynos_lcd_misc_init(vidinfo_t *vid)
{
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
#ifdef CONFIG_S6E8AX0
s6e8ax0_init();
#endif
}
#endif /* LCD */

107
board/samsung/universal_c210/universal.c
View File

@ -267,98 +267,6 @@ static int init_pmic_lcd(void)
return 0;
}
void exynos_cfg_lcd_gpio(void)
{
unsigned int i, f3_end = 4;
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
}
for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
gpio_set_drv(i, S5P_GPIO_DRV_4X);
gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
}
/* gpio pad configuration for LCD reset. */
gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
}
int mipi_power(void)
{
return 0;
}
void exynos_reset_lcd(void)
{
gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
gpio_set_value(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(100);
}
void exynos_lcd_power_on(void)
{
struct udevice *dev;
int ret;
u8 reg;
ret = pmic_get("max8998-pmic", &dev);
if (ret) {
puts("Failed to get MAX8998!\n");
return;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
reg |= MAX8998_LDO17;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg |= MAX8998_LDO7;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return;
}
}
void exynos_cfg_ldo(void)
{
ld9040_cfg_ldo();
}
void exynos_enable_ldo(unsigned int onoff)
{
ld9040_enable_ldo(onoff);
}
int exynos_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
@ -390,18 +298,3 @@ int exynos_init(void)
return 0;
}
#ifdef CONFIG_LCD
void exynos_lcd_misc_init(vidinfo_t *vid)
{
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
/* for LD9040. */
vid->pclk_name = 1; /* MPLL */
vid->sclk_div = 1;
env_set("lcdinfo", "lcd=ld9040");
}
#endif

2
board/siemens/common/Kconfig Normal file
View File

@ -0,0 +1,2 @@
config FACTORYSET
bool

3
board/ti/am64x/Kconfig
View File

@ -54,9 +54,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "am64x_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif

3
board/ti/am65x/Kconfig
View File

@ -53,9 +53,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "am65x_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif

6
board/ti/j721e/Kconfig
View File

@ -75,9 +75,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "j721e_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif
@ -108,9 +105,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "j721e_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif

3
board/ti/j721s2/Kconfig
View File

@ -55,9 +55,6 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "j721s2_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif

2
boot/Kconfig
View File

@ -622,7 +622,7 @@ config SPL_BOOTSTAGE
config TPL_BOOTSTAGE
bool "Boot timing and reported in TPL"
depends on BOOTSTAGE
depends on BOOTSTAGE && TPL
help
Enable recording of boot time in SPL. To make this visible to U-Boot
proper, enable BOOTSTAGE_STASH as well. This will stash the timing

9
cmd/Kconfig
View File

@ -1737,6 +1737,15 @@ config NFS_TIMEOUT
"ERROR: Cannot umount" in nfs command, try longer timeout such as
10000.
config SYS_DISABLE_AUTOLOAD
bool "Disable automatically loading files over the network"
depends on CMD_BOOTP || CMD_DHCP || CMD_NFS || CMD_RARP
help
Typically, commands such as "dhcp" will attempt to automatically
load a file from the network, once the initial network configuration
is complete. Enable this option to disable this behavior and instead
require files to be loaded over the network by subsequent commands.
config CMD_MII
bool "mii"
imply CMD_MDIO

15
common/Kconfig
View File

@ -87,10 +87,12 @@ config SPL_LOGLEVEL
config TPL_LOGLEVEL
int
depends on TPL
default LOGLEVEL
config VPL_LOGLEVEL
int "loglevel for VPL"
depends on VPL
default LOGLEVEL
help
All Messages with a loglevel smaller than the console loglevel will
@ -271,15 +273,6 @@ config LOG
if LOG
config VPL_LOG
bool "Enable logging support in VPL"
depends on LOG
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or
discarded if not needed. Logging supports various categories and
levels of severity.
config LOG_MAX_LEVEL
int "Maximum log level to record"
default 6
@ -408,7 +401,7 @@ endif
config TPL_LOG
bool "Enable logging support in TPL"
depends on LOG
depends on LOG && TPL
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or
@ -451,7 +444,7 @@ endif
config VPL_LOG
bool "Enable logging support in VPL"
depends on LOG
depends on LOG && VPL
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or

13
common/Makefile
View File

@ -23,10 +23,9 @@ obj-$(CONFIG_MII) += miiphyutil.o
obj-$(CONFIG_CMD_MII) += miiphyutil.o
obj-$(CONFIG_PHYLIB) += miiphyutil.o
ifdef CONFIG_USB
obj-y += usb.o usb_hub.o
obj-$(CONFIG_USB_HOST) += usb.o usb_hub.o
obj-$(CONFIG_USB_GADGET) += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
# others
obj-$(CONFIG_CONSOLE_MUX) += iomux.o
@ -57,13 +56,9 @@ endif
obj-$(CONFIG_SPL_NET) += miiphyutil.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
ifdef CONFIG_SPL_USB_HOST
obj-y += usb.o
obj-y += usb_hub.o
obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o
obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o
else
obj-$(CONFIG_USB_MUSB_HOST) += usb.o
endif
obj-$(CONFIG_SPL_MUSB_NEW) += usb.o
endif # CONFIG_SPL_BUILD
#others

19
common/spl/Kconfig
View File

@ -221,6 +221,18 @@ config SPL_HANDOFF
config SPL_LDSCRIPT
string "Linker script for the SPL stage"
default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if ARCH_SUNXI && !MACH_SUNIV && !ARM64
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if ARCH_AT91 && CPU_ARM926EJS
default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if ARCH_AT91 && CPU_V7A
default "arch/arm/mach-omap2/u-boot-spl.lds" if ARCH_MX6 || ARCH_OMAP2PLUS || (ARCH_K3 && !ARM64)
default "arch/arm/mach-zynq/u-boot-spl.lds" if ARCH_ZYNQ
default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds" if ARCH_DAVINCI
default "arch/\$(ARCH)/cpu/u-boot-spl.lds"
help
The SPL stage will usually require a different linker-script
@ -1305,6 +1317,13 @@ config SPL_USB_STORAGE
config options. This enables loading from USB using a configured
device.
config SYS_USB_FAT_BOOT_PARTITION
int "Partition on USB to use to load U-Boot from"
depends on SPL_USB_STORAGE
default 1
help
Partition on the USB storage device to load U-Boot from
config SPL_USB_GADGET
bool "Suppport USB Gadget drivers"
help

4
common/usb.c
View File

@ -49,10 +49,6 @@ char usb_started; /* flag for the started/stopped USB status */
static struct usb_device usb_dev[USB_MAX_DEVICE];
static int dev_index;
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
/***************************************************************************
* Init USB Device
*/

1
configs/A10-OLinuXino-Lime_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/A20-OLinuXino-Lime2-eMMC_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_MVTWSI=y

1
configs/A20-OLinuXino-Lime2_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_MVTWSI=y

1
configs/A20-OLinuXino-Lime_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/A20-OLinuXino_MICRO_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/A20-Olimex-SOM-EVB_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/A20-Olimex-SOM204-EVB_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Bananapi_M2_Ultra_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Bananapi_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Bananapro_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Cubieboard2_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Cubieboard_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Cubietruck_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_MVTWSI=y

1
configs/Itead_Ibox_A20_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Lamobo_R1_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Linksprite_pcDuino3_Nano_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Linksprite_pcDuino3_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Marsboard_A10_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_AHCI=y
CONFIG_SPL_STACK=0x8000
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Mele_A1000_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Mele_M5_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Orangepi_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/Orangepi_mini_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

4
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -66,12 +68,14 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_RANGE=0xc000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

2
configs/P1010RDB-PA_36BIT_NOR_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -41,6 +42,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -62,6 +64,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -15,6 +15,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -65,6 +67,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

4
configs/P1010RDB-PA_NAND_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -65,12 +67,14 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_RANGE=0xc000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

2
configs/P1010RDB-PA_NOR_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -40,6 +41,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -61,6 +63,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -15,6 +15,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -64,6 +66,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

4
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -67,12 +69,14 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_RANGE=0x80000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

2
configs/P1010RDB-PB_36BIT_NOR_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -42,6 +43,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -63,6 +65,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -15,6 +15,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -66,6 +68,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

4
configs/P1010RDB-PB_NAND_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -66,12 +68,14 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_RANGE=0x80000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

2
configs/P1010RDB-PB_NOR_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -41,6 +42,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -62,6 +64,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

3
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -15,6 +15,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -65,6 +67,7 @@ CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666

5
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
@ -66,12 +68,14 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_RANGE=0xc000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y
@ -134,5 +138,6 @@ CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y

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