Embedded_Projects/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm64: zynqmp: Aligned QSPI configuration with latest spec

Browse Source 
Official DT binding description for dual stacked/paralllel configurations
have been merged that's why switch to it.

Link: https://lore.kernel.org/r/20220126112608.955728-3-miquel.raynal@bootlin.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2912091c231f5e945ee44601c285fe16263448da.1695378830.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-09-22 12:35:43 +02:00
parent d095631d8d
commit 5d80889783
6 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -354,11 +354,13 @@
&qspi {
status = "okay";
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */

4
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -972,11 +972,13 @@
&qspi {
status = "okay";
is-dual = <1>;
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */

4
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -979,11 +979,13 @@
&qspi {
status = "okay";
is-dual = <1>;
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */

4
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -790,11 +790,13 @@
&qspi {
status = "okay";
is-dual = <1>;
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */

4
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@ -644,11 +644,13 @@
&qspi {
status = "okay";
is-dual = <1>;
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */

4
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@ -654,11 +654,13 @@
&qspi {
status = "okay";
is-dual = <1>;
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */