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clock/qcom: qcs404: fix clk_set_rate

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We should be returning the rate that we set the clock to, drivers like
MMC rely on this. So fix it.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly 2024-02-26 17:26:10 +00:00
parent 7d96cca9e1
commit 641237bf99
No known key found for this signature in database
GPG Key ID: 7930459FB9303217
1 changed files with 13 additions and 12 deletions
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25
drivers/clk/qcom/clock-qcs404.c
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@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
switch (clk->id) {
case GCC_BLSP1_UART2_APPS_CLK:
/* UART: 115200 */
/* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO, 16);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
break;
case GCC_BLSP1_AHB_CLK:
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
break;
return 1843200;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
break;
case GCC_SDCC1_AHB_CLK:
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
break;
return rate;
case GCC_ETH_RGMII_CLK:
if (rate == 250000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
else if (rate == 5000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
CFG_CLK_SRC_GPLL1, 8);
break;
default:
return 0;
return rate;
}
/* There is a bug only seeming to affect this board where the MMC driver somehow calls
* clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
* The only clock with ID 0 is the xo_board clock which should not be associated with
* this device...
*/
log_debug("Unknown clock id %ld\n", clk->id);
return 0;
}
@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk)
clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_SDCC1_AHB_CLK:
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
break;
default:
return 0;
}