arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and features include: * Main 12V/54V power supply * 270 Gbps throughput packet processor on the main board * DDR4: * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs) * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs) * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement * 16GB eMMC (Samsung KLMAG1JETD-B041006) * 16MB SPI NOR(GD25Q127C) * 32 x 1000 Base-T interfaces * 16 x 2500 Base-T interfaces * SR1: 88E2540*4 * SR2: 88E2580*1+88E2540*2 * Six (6) x 25G Base-R SFP28 interfaces * One (1) x RJ-45 console connector, interfacing to the on board UART * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0) * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1) * One (1) x RJ-45 1G Base-T Management port, interfacing to the host port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy * One (1) x Oculink port, interfacing to the PCIe port for external CPU connection * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 solution) * POE total power budget 780W * LED interfaces per network port/POE * LED interfaces (common) showing system status * PTP TC mode Supported (Reserved M.2 connector to support BC mode) Signed-off-by: Chris Packham <judge.packham@gmail.com>
This commit is contained in:
Chris Packham
Stefan Roese
parent
7d7bb99e22
commit
6cc8b5db40
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@ -278,7 +278,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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cn9132-db-A.dtb \
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cn9132-db-B.dtb \
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cn9130-crb-A.dtb \
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cn9130-crb-B.dtb
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cn9130-crb-B.dtb \
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ac5-98dx35xx-rd.dtb
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endif
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dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
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129
arch/arm/dts/ac5-98dx35xx-rd.dts
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129
arch/arm/dts/ac5-98dx35xx-rd.dts
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@ -0,0 +1,129 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree For RD-AC5X.
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*
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* Copyright (C) 2021 Marvell
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* Copyright (C) 2022 Allied Telesis Labs
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*/
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/*
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* Device Tree file for Marvell Alleycat 5X development board
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* This board file supports the B configuration of the board
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*/
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/dts-v1/;
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#include "ac5-98dx35xx.dtsi"
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/ {
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model = "Marvell RD-AC5X Board";
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compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
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aliases {
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serial0 = &uart0;
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spiflash0 = &spiflash0;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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ethernet0 = ð0;
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ethernet1 = ð1;
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spi0 = &spi0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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usb0 = &usb0;
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usb1 = &usb1;
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pinctrl0 = &pinctrl0;
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sar-reg0 = "/config-space/sar-reg";
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};
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usb1phy: usb-phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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ð0 {
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status = "okay";
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phy-handle = <&phy0>;
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};
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/* USB0 is a host USB */
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&usb0 {
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status = "okay";
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};
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/* USB1 is a peripheral USB */
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&usb1 {
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status = "okay";
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phys = <&usb1phy>;
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phy-names = "usb-phy";
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dr_mode = "peripheral";
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};
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&spi0 {
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status = "okay";
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spiflash0: flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&pinctrl0 {
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/*
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* MPP Bus: MPP# mode#
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* eMMC [0-11] 0x1
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* SPI[0] [12-17] 0x1
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* TSEN_INT [18] 0x1
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* DEV_INIT [19] 0x1
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* SPI[1] [20-23] 0x3
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* UART[1] [24-25] 0x3
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* I2C[0] [26-27] 0x1
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* XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem
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* SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem
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* UART[0] [32-33] 0x1
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* OOB_SMI [34-35] 0x1
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* PTP_CLK0_OUT [36] 0x1
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* PTP_PULSE_OUT [37] 0x1
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* RCVR_CLK_OUT [38] 0x1
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* GPIO(in/out) [39] 0x0
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* GPIO(in/out) [40] 0x0
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* PTP_REF_CLK [41] 0x1
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* PTP_CLK0 [42] 0x1
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* LED0_CLK [43] 0x1
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* LED0_STB [44] 0x1
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* LED0_DATA [45] 0x1
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 1 1 1 1
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1 1 1 1 1 1 1 1 1 1
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3 3 3 3 3 3 1 1 1 1
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2 2 1 1 1 1 1 1 1 0
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0 1 1 1 1 1 >;
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};
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@ -98,7 +98,7 @@ config CUSTOMER_BOARD_SUPPORT
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bool
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choice
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prompt "Armada XP/375/38x/3700/7K/8K board select"
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prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
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optional
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config TARGET_CLEARFOG
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@ -150,6 +150,10 @@ config TARGET_MVEBU_ARMADA_8K
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select BOARD_LATE_INIT
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imply SCSI
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config TARGET_MVEBU_ALLEYCAT5
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bool "Support AlleyCat 5 platforms"
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select ALLEYCAT_5
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config TARGET_OCTEONTX2_CN913x
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bool "Support CN913x platforms"
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select ARMADA_8K
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@ -258,6 +262,7 @@ config SYS_BOARD
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default "x530" if TARGET_X530
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default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
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default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
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default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
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config SYS_CONFIG_NAME
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default "clearfog" if TARGET_CLEARFOG
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@ -278,6 +283,7 @@ config SYS_CONFIG_NAME
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default "x530" if TARGET_X530
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default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
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default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
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default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
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config SYS_VENDOR
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default "Marvell" if TARGET_DB_MV784MP_GP
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@ -297,6 +303,7 @@ config SYS_VENDOR
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default "gdsys" if TARGET_CONTROLCENTERDC
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default "alliedtelesis" if TARGET_X530
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default "mikrotik" if TARGET_CRS3XX_98DX3236
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default "Marvell" if TARGET_MVEBU_ALLEYCAT5
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config SYS_SOC
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default "mvebu"
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6
board/Marvell/mvebu_alleycat-5/MAINTAINERS
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6
board/Marvell/mvebu_alleycat-5/MAINTAINERS
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@ -0,0 +1,6 @@
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RD-AC5X BOARD
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: board/Marvell/mvebu_alleycat-5/
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F: include/configs/mvebu_alleycat-5.h
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F: configs/mvebu_ac5_rd_defconfig
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3
board/Marvell/mvebu_alleycat-5/Makefile
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3
board/Marvell/mvebu_alleycat-5/Makefile
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := board.o
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13
board/Marvell/mvebu_alleycat-5/board.c
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13
board/Marvell/mvebu_alleycat-5/board.c
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@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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81
configs/mvebu_ac5_rd_defconfig
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81
configs/mvebu_ac5_rd_defconfig
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@ -0,0 +1,81 @@
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CONFIG_ARM=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_TEXT_BASE=0x200000000
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CONFIG_SYS_MALLOC_LEN=0x900000
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CONFIG_TARGET_MVEBU_ALLEYCAT5=y
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CONFIG_ENV_SIZE=0x10000
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CONFIG_ENV_OFFSET=0x400000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="ac5-98dx35xx-rd"
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CONFIG_SYS_LOAD_ADDR=0x202000000
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CONFIG_SYS_MEMTEST_START=0x200800000
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CONFIG_SYS_MEMTEST_END=0x200ffffff
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=-1
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CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_ARCH_EARLY_INIT_R=y
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CONFIG_ARCH_MISC_INIT=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_MVEBU_BUBT=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_UBI=y
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CONFIG_MAC_PARTITION=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_CLK=y
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CONFIG_CLK_MVEBU=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_MVTWSI=y
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CONFIG_MISC=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_XENON=y
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CONFIG_MTD=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_GIGE=y
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CONFIG_MVNETA=y
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CONFIG_MVMDIO=y
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CONFIG_PHY=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_ARMADA_8K=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_RTC=y
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CONFIG_DM_SCSI=y
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CONFIG_SYS_NS16550=y
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CONFIG_MVEBU_A3700_SPI=y
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CONFIG_DM_THERMAL=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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42
include/configs/mvebu_alleycat-5.h
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42
include/configs/mvebu_alleycat-5.h
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@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Marvell International Ltd
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*/
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#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
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#define _CONFIG_MVEBU_ALLEYCAY_5_H
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#include <asm/arch/soc.h>
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/* additions for new ARM relocation support */
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#define CONFIG_SYS_SDRAM_BASE 0x200000000
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
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115200, 230400, 460800, 921600 }
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/* Default Env vars */
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#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */
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#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_GATEWAYIP 0.0.0.0
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#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"kernel_addr_r=0x202000000\0" \
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"fdt_addr_r=0x201000000\0" \
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"ramdisk_addr_r=0x206000000\0" \
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"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_SYS_TCLK 325000000
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#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
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