Embedded_Projects/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Xilinx changes for v2023.10-rc1

Browse Source 
global:
 - Use proper U-Boot project name
 
 Fix sparse warnings in zynqmp-clk, zynqmp handoff, board
 
 cmd:
 - Cover incorrect 0 length entries
 
 Versal NET:
 - Add bootmode logic
 - Support SPP production version
 - Add loadpdi command
 
 ZynqMP:
 - Clear pmufw node command ID handling
 - Change power domain behavior around zynqmp_pmufw_node()
 - Fix zynqmp cmd return values and pmufw command
 - Fix R5 tcm init and modes
 
 mmc:
 - Sync Versal NET emmc DT binding
 
 pcie:
 - Add support for ZynqMP PCIe root port
 
 video:
 - Add support for ZynqMP DP
 
 tools:
 - Fix debug message in relocate-rela
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZIcDaAAKCRDKSWXLKUoM
 IZmlAKCbiI7CS8ngZpbzOIuMveebNn1jYgCghyl20Bb2zWoNy+sIY2fPIO9mwx4=
 =wPDv
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.10-rc1

global:
- Use proper U-Boot project name

Fix sparse warnings in zynqmp-clk, zynqmp handoff, board

cmd:
- Cover incorrect 0 length entries

Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command

ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes

mmc:
- Sync Versal NET emmc DT binding

pcie:
- Add support for ZynqMP PCIe root port

video:
- Add support for ZynqMP DP

tools:
- Fix debug message in relocate-rela
This commit is contained in:
Tom Rini 2023-06-12 16:42:37 -04:00
commit 7da82de916
97 changed files with 3757 additions and 236 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -343,6 +343,7 @@ F: drivers/rtc/armada38x.c
F: drivers/spi/kirkwood_spi.c
F: drivers/spi/mvebu_a3700_spi.c
F: drivers/pci/pcie_dw_mvebu.c
F: drivers/pci/pcie-xilinx-nwl.c
F: drivers/watchdog/armada-37xx-wdt.c
F: drivers/watchdog/orion_wdt.c
F: include/configs/mv-common.h
@ -755,6 +756,7 @@ F: drivers/spi/zynq_qspi.c
F: drivers/spi/zynq_spi.c
F: drivers/timer/cadence-ttc.c
F: drivers/video/seps525.c
F: drivers/video/zynqmp/
F: drivers/watchdog/cdns_wdt.c
F: include/zynqmppl.h
F: include/zynqmp_firmware.h

2
arch/Kconfig.nxp
View File

@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH
default ""
help
Set the key hash for U-Boot here if public/private key pair used to
sign U-boot are different from the SRK hash put in the fuse. Example
sign U-Boot are different from the SRK hash put in the fuse. Example
of a key hash is
41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
Otherwise leave this empty.

2
arch/arc/include/asm/io.h
View File

@ -80,7 +80,7 @@ static inline void sync(void)
/*
* We add memory barriers for __raw_readX / __raw_writeX accessors same way as
* it is done for readX and writeX accessors as lots of U-boot driver uses
* it is done for readX and writeX accessors as lots of U-Boot driver uses
* __raw_readX / __raw_writeX instead of proper accessor with barrier.
*/
#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })

2
arch/arm/cpu/armv7/Kconfig
View File

@ -110,7 +110,7 @@ config ARMV7_LPAE
config ARMV7_SET_CORTEX_SMPEN
bool
help
Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
config SPL_ARMV7_SET_CORTEX_SMPEN
bool

2
arch/arm/cpu/armv8/Kconfig
View File

@ -145,7 +145,7 @@ config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
help
PSCI is Power State Coordination Interface defined by ARM.
The PSCI in U-boot provides a general framework and each platform
The PSCI in U-Boot provides a general framework and each platform
can implement their own specific PSCI functions.
Say Y here to enable PSCI support on ARMv8 platform.

2
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
View File

@ -125,7 +125,7 @@ mcinitcmd: This environment variable is defined to initiate MC and DPL deploymen
from the location where it is stored(NOR, NAND, SD, SATA, USB)during
u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
will be null and MC will not be booted and DPL will not be applied
during U-boot booting.However the MC, DPC and DPL can be applied from
during U-Boot booting.However the MC, DPC and DPL can be applied from
console independently.
The variable needs to be set from the console once and then on
rebooting the parameters set in the variable will automatically be

2
arch/arm/dts/fsl-ls1028a.dtsi
View File

@ -51,7 +51,7 @@
idle-states {
/*
* PSCI node is not added default, U-boot will add missing
* PSCI node is not added default, U-Boot will add missing
* parts if it determines to use PSCI.
*/
entry-method = "psci";

2
arch/arm/dts/meson-g12-common-u-boot.dtsi
View File

@ -5,7 +5,7 @@
*/
/ {
/* Keep HW order from U-boot */
/* Keep HW order from U-Boot */
aliases {
/delete-property/ mmc0;
/delete-property/ mmc1;

2
arch/arm/dts/meson-gx-u-boot.dtsi
View File

@ -5,7 +5,7 @@
*/
/ {
/* Keep HW order from U-boot */
/* Keep HW order from U-Boot */
aliases {
/delete-property/ mmc0;
/delete-property/ mmc1;

2
arch/arm/dts/rk3328-evb-u-boot.dtsi
View File

@ -41,7 +41,7 @@
};
&gmac2phy {
/* Integrated PHY unsupported by U-boot */
/* Integrated PHY unsupported by U-Boot */
status = "broken";
};

2
arch/arm/dts/rk3328.dtsi
View File

@ -984,7 +984,7 @@
};
/*
* U-boot Specific Change
* U-Boot Specific Change
*
* The OTG controller must come after the USB host pair for it
* to work. This is likely due to lack of support for the USB

2
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
View File

@ -22,7 +22,7 @@
*
* -PCIe
* -there is a range of stream IDs set aside for PCI in this
* file. U-boot will scan the PCI bus and for each device discovered:
* file. U-Boot will scan the PCI bus and for each device discovered:
* -allocate a streamID
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
* -set a msi-map entry in the PEXn controller node in the

2
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View File

@ -23,7 +23,7 @@
*
* -PCIe
* -there is a range of stream IDs set aside for PCI in this
* file. U-boot will scan the PCI bus and for each device discovered:
* file. U-Boot will scan the PCI bus and for each device discovered:
* -allocate a streamID
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
* -set a msi-map entry in the PEXn controller node in the

22
arch/arm/mach-versal-net/include/mach/hardware.h
View File

@ -27,7 +27,13 @@ struct iou_scntrs_regs {
u32 base_frequency_id_register; /* 0x20 */
};
struct crp_regs {
u32 reserved0[128];
u32 boot_mode_usr; /* 0x200 */
};
#define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000
#define VERSAL_NET_CRP_BASEADDR 0xF1260000
#define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
@ -36,6 +42,7 @@ struct iou_scntrs_regs {
#define IOU_SCNTRS_CONTROL_EN 1
#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
#define PMC_TAP 0xF11A0000
@ -44,11 +51,26 @@ struct iou_scntrs_regs {
#define PMC_TAP_VERSION (PMC_TAP + 0x4)
# define PMC_VERSION_MASK GENMASK(7, 0)
# define PS_VERSION_MASK GENMASK(15, 8)
# define PS_VERSION_PRODUCTION 0x20
# define RTL_VERSION_MASK GENMASK(23, 16)
# define PLATFORM_MASK GENMASK(27, 24)
# define PLATFORM_VERSION_MASK GENMASK(31, 28)
#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
/* Bootmode setting values */
#define BOOT_MODES_MASK 0x0000000F
#define QSPI_MODE_24BIT 0x00000001
#define QSPI_MODE_32BIT 0x00000002
#define SD_MODE 0x00000003 /* sd 0 */
#define SD_MODE1 0x00000005 /* sd 1 */
#define EMMC_MODE 0x00000006
#define USB_MODE 0x00000007
#define OSPI_MODE 0x00000008
#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
#define BOOT_MODE_ALT_SHIFT 12
enum versal_net_platform {
VERSAL_NET_SILICON = 0,
VERSAL_NET_SPP = 1,

1
arch/arm/mach-versal/include/mach/sys_proto.h
View File

@ -10,6 +10,7 @@ enum {
TCM_SPLIT,
};
void initialize_tcm(bool mode);
void tcm_init(u8 mode);
void mem_map_fill(void);

8
arch/arm/mach-versal/mp.c
View File

@ -23,7 +23,7 @@
#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
void set_r5_halt_mode(u8 halt, u8 mode)
static void set_r5_halt_mode(u8 halt, u8 mode)
{
u32 tmp;
@ -44,7 +44,7 @@ void set_r5_halt_mode(u8 halt, u8 mode)
}
}
void set_r5_tcm_mode(u8 mode)
static void set_r5_tcm_mode(u8 mode)
{
u32 tmp;
@ -62,7 +62,7 @@ void set_r5_tcm_mode(u8 mode)
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
void release_r5_reset(u8 mode)
static void release_r5_reset(u8 mode)
{
u32 tmp;
@ -77,7 +77,7 @@ void release_r5_reset(u8 mode)
writel(tmp, &crlapb_base->rst_cpu_r5);
}
void enable_clock_r5(void)
static void enable_clock_r5(void)
{
u32 tmp;

1
arch/arm/mach-zynqmp/handoff.c
View File

@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
/*
* atfhandoffparams

4
arch/arm/mach-zynqmp/mp.c
View File

@ -326,6 +326,10 @@ int cpu_release(u32 nr, int argc, char *const argv[])
flush_dcache_all();
if (!strncmp(argv[1], "lockstep", 8)) {
if (nr != ZYNQMP_CORE_RPU0) {
printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
return 1;
}
printf("R5 lockstep mode\n");
set_r5_reset(nr, LOCK);
set_r5_tcm_mode(LOCK);

2
board/bosch/acc/acc.c
View File

@ -542,7 +542,7 @@ int board_mmc_init(struct bd_info *bis)
gpio_direction_input(USDHC2_CD_GPIO);
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* (U-Boot device node) (Physical Port)
* mmc0 USDHC2
* mmc1 USDHC4
*/

2
board/bosch/shc/README
View File

@ -68,7 +68,7 @@ Netboot
- see also doc/SPL/README.am335x-network
- set the jumper into netboot mode
- compile the U-boot sources with:
- compile the U-Boot sources with:
make am335x_shc_netboot_defconfig
make all
- copy the images into your tftp boot directory

2
board/compulab/cl-som-imx7/cl-som-imx7.c
View File

@ -86,7 +86,7 @@ int board_mmc_init(struct bd_info *bis)
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc2 USDHC3 (eMMC)
*/

2
board/hisilicon/poplar/README
View File

@ -30,7 +30,7 @@ CONNECTORS One connector for Smart Card One connector for TSI
Note of warning:
================
U-boot has a *strong* dependency with the l-loader and the arm trusted firmware
U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware
repositories.
The boot sequence is:

2
board/isee/igep003x/board.c
View File

@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
* and control IGEP0034 green and red LEDs.
* U-boot configures these pins as input pullup to detect board revision:
* U-Boot configures these pins as input pullup to detect board revision:
* IGEP0034-LITE = 0b00
* IGEP0034 (FULL) = 0b01
* IGEP0033 = 0b1X

2
board/isee/igep00x0/igep00x0.c
View File

@ -47,7 +47,7 @@ U_BOOT_DRVINFO(igep_uart) = {
* IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
* IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
* this functionality is shared by USB HOST.
* Once USB reset is applied, U-boot configures these pins as input pullup to
* Once USB reset is applied, U-Boot configures these pins as input pullup to
* detect board and revision:
* IGEP0020-RF = 0b00
* IGEP0020-RC = 0b01

8
board/keymile/Kconfig
View File

@ -123,7 +123,7 @@ config SYS_IVM_EEPROM_PAGE_LEN
Page size of inventory in EEPROM.
config PG_WCOM_UBOOT_UPDATE_SUPPORTED
bool "Enable U-boot Field Fail-Safe Update Functionality"
bool "Enable U-Boot Field Fail-Safe Update Functionality"
select EVENT
default n
help
@ -132,7 +132,7 @@ config PG_WCOM_UBOOT_UPDATE_SUPPORTED
from parallel NOR flash.
config PG_WCOM_UBOOT_BOOTPACKAGE
bool "U-boot Is Part Of Factory Boot-Package Image"
bool "U-Boot Is Part Of Factory Boot-Package Image"
default n
help
Indicates that u-boot will be a part of the factory programmed
@ -140,7 +140,7 @@ config PG_WCOM_UBOOT_BOOTPACKAGE
Has to be set for original u-boot programmed at factory.
config PG_WCOM_UBOOT_UPDATE_TEXT_BASE
hex "Text Base For U-boot Programmed Outside Factory"
hex "Text Base For U-Boot Programmed Outside Factory"
default 0xFFFFFFFF
help
Text base of an updated u-boot that is not factory programmed but
@ -148,7 +148,7 @@ config PG_WCOM_UBOOT_UPDATE_TEXT_BASE
Has to be set for original u-boot programmed at factory.
config PG_WCOM_UBOOT_UPDATE
bool "U-boot Is Part Of Factory Boot-Package Image"
bool "U-Boot Is Part Of Factory Boot-Package Image"
default n
help
Indicates that u-boot will be a part of the embedded software and

2
board/keymile/README
View File

@ -1,4 +1,4 @@
Field Fail-Save U-boot Update
Field Fail-Save U-Boot Update
-----------------------------
Field Fail-Save u-boot update is a feature that allows save u-boot update
of FOX and XMC products that are rolled out in the field.

2
board/kontron/sl-mx6ul/spl.c
View File

@ -101,7 +101,7 @@ int board_mmc_init(struct bd_info *bis)
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/

18
board/phytec/pcm058/README
View File

@ -37,12 +37,12 @@ not supported.
Flashing U-Boot onto an SD card
-------------------------------
After a successful build, the generated SPL and U-boot binaries can be copied
After a successful build, the generated SPL and U-Boot binaries can be copied
to an SD card. Adjust the SD card device as necessary:
$ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1
This is equivalent to separately copying the SPL and U-boot using:
This is equivalent to separately copying the SPL and U-Boot using:
$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1
$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197
@ -50,11 +50,11 @@ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197
The default bootscripts expect a kernel fit-image file named "fitImage" in the
first partition and Linux ext4 rootfs in the second partition.
Flashing U-boot to the SPI Flash, for booting Linux from NAND
Flashing U-Boot to the SPI Flash, for booting Linux from NAND
-------------------------------------------------------------
The SD card created above can also be used to install the SPL and U-boot into
the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot.
The SD card created above can also be used to install the SPL and U-Boot into
the SPI flash. Boot U-Boot from the SD card as above, and stop at the autoboot.
Then, clear the SPI flash:
@ -64,13 +64,13 @@ Then, clear the SPI flash:
Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and
copy to the SPI. The SPL is expected at an offset of 0x400, and its size is
maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000
bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks,
bytes. Assume U-Boot should fit into 640KiB, therefore 0x500 512-byte blocks,
totalling 0xA0000 bytes. Adding these together:
=> mmc read ${loadaddr} 0x2 0x688
=> sf write ${loadaddr} 0x400 0xD1000
The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to
The SPL is located at offset 0x400, and U-Boot at 0x31400 in SPI flash, as to
match the SD Card layout. This would allow, instead of reading from the SD Card
above, with networking and TFTP correctly configured, the equivalent of:
@ -84,7 +84,7 @@ image) and "root" (which contains a ubifs root filesystem).
The "bootm_size" variable in the environment
--------------------------------------------
By default, U-boot relocates the device tree towards the upper end of the RAM,
By default, U-Boot relocates the device tree towards the upper end of the RAM,
which kernels using CONFIG_HIGHMEM=y may not be able to access during early
boot. With the bootm_size variable set to 0x30000000, U-boot relocates the
boot. With the bootm_size variable set to 0x30000000, U-Boot relocates the
device tree to below this address instead.

14
board/synopsys/hsdk/hsdk.c
View File

@ -583,7 +583,7 @@ enum hsdk_axi_masters {
*
* Please read ARC HS Development IC Specification, section 17.2 for more
* information about apertures configuration.
* NOTE: we intentionally modify default settings in U-boot. Default settings
* NOTE: we intentionally modify default settings in U-Boot. Default settings
* are specified in "Table 111 CREG Address Decoder register reset values".
*/
@ -942,7 +942,7 @@ static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc,
int ret;
if (board_mismatch()) {
printf("ERR: U-boot is not configured for this board!\n");
printf("ERR: U-Boot is not configured for this board!\n");
return CMD_RET_FAILURE;
}
@ -983,10 +983,10 @@ U_BOOT_CMD(
/*
* We may simply use static variable here to store init status, but we also want
* to avoid the situation when we reload U-boot via MDB after previous
* to avoid the situation when we reload U-Boot via MDB after previous
* init is done but HW reset (board reset) isn't done. So let's store the
* init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
* survive after U-boot is reloaded via MDB.
* survive after U-Boot is reloaded via MDB.
*/
#define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY)
/* must be equal to INIT_MARKER_REGISTER reset value */
@ -1008,7 +1008,7 @@ static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc,
int ret;
if (board_mismatch()) {
printf("ERR: U-boot is not configured for this board!\n");
printf("ERR: U-Boot is not configured for this board!\n");
return CMD_RET_FAILURE;
}
@ -1258,11 +1258,11 @@ int checkboard(void)
printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
if (board_mismatch())
printf("WARN: U-boot is configured NOT for this board but for %s!\n",
printf("WARN: U-Boot is configured NOT for this board but for %s!\n",
board_name(get_board_type_config()));
reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");
printf("U-Boot autostart: %s\n", reg ? "enabled" : "disabled");
return 0;
};

7
board/xilinx/common/board.h
View File

@ -11,4 +11,11 @@ int board_late_init_xilinx(void);
int xilinx_read_eeprom(void);
char *board_name_decode(void);
bool board_detection(void);
char *soc_name_decode(void);
bool soc_detection(void);
#endif /* BOARD_XILINX_COMMON_BOARD_H */

8
board/xilinx/versal-net/Kconfig
View File

@ -6,4 +6,12 @@
if ARCH_VERSAL_NET
config CMD_VERSAL_NET
bool "Enable Versal NET specific commands"
default y
depends on ZYNQMP_FIRMWARE
help
Select this to enable Versal NET specific commands.
Commands like versalnet loadpdi are enabled by this.
endif

1
board/xilinx/versal-net/Makefile
View File

@ -7,3 +7,4 @@
#
obj-y := board.o
obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o

149
board/xilinx/versal-net/board.c
View File

@ -10,6 +10,7 @@
#include <cpu_func.h>
#include <fdtdec.h>
#include <init.h>
#include <env_internal.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
@ -74,32 +75,45 @@ char *soc_name_decode(void)
bool soc_detection(void)
{
u32 version;
u32 version, ps_version;
version = readl(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version);
ps_version = FIELD_GET(PS_VERSION_MASK, version);
debug("idcode %x, version %x, usercode %x\n",
readl(PMC_TAP_IDCODE), version,
readl(PMC_TAP_USERCODE));
debug("pmc_ver %lx, ps version %lx, rtl version %lx\n",
debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
FIELD_GET(PMC_VERSION_MASK, version),
FIELD_GET(PS_VERSION_MASK, version),
ps_version,
FIELD_GET(RTL_VERSION_MASK, version));
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
if (platform_id == VERSAL_NET_SPP ||
platform_id == VERSAL_NET_EMU) {
/*
* 9 is diff for
* 0 means 0.9 version
* 1 means 1.0 version
* 2 means 1.1 version
* etc,
*/
platform_version += 9;
if (ps_version == PS_VERSION_PRODUCTION) {
/*
* ES1 version ends at 1.9 version where there was +9
* used because of IPP/SPP conversion. Production
* version have platform_version started from 0 again
* that's why adding +20 to continue with the same line.
* It means the last ES1 version ends at 1.9 version and
* new PRODUCTION line starts at 2.0.
*/
platform_version += 20;
} else {
/*
* 9 is diff for
* 0 means 0.9 version
* 1 means 1.0 version
* 2 means 1.1 version
* etc,
*/
platform_version += 9;
}
}
debug("Platform id: %d version: %d.%d\n", platform_id,
@ -165,8 +179,32 @@ int board_early_init_r(void)
return 0;
}
static u8 versal_net_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
reg = readl(&crp_base->boot_mode_usr);
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
return bootmode;
}
int board_late_init(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
const char *mode;
char *new_targets;
char *env_targets;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
@ -175,6 +213,95 @@ int board_late_init(void)
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
bootmode = versal_net_get_bootmode();
puts("Bootmode: ");
switch (bootmode) {
case USB_MODE:
puts("USB_MODE\n");
mode = "usb_dfu0 usb_dfu1";
break;
case JTAG_MODE:
puts("JTAG_MODE\n");
mode = "jtag pxe dhcp";
break;
case QSPI_MODE_24BIT:
puts("QSPI_MODE_24\n");
mode = "xspi0";
break;
case QSPI_MODE_32BIT:
puts("QSPI_MODE_32\n");
mode = "xspi0";
break;
case OSPI_MODE:
puts("OSPI_MODE\n");
mode = "xspi0";
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
mode = "mmc";
bootseq = dev_seq(dev);
break;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1040000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
bootseq = dev_seq(dev);
break;
case SD1_LSHFT_MODE:
puts("LVL_SHFT_");
fallthrough;
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
bootseq = dev_seq(dev);
break;
default:
mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
if (bootseq >= 0) {
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
debug("Bootseq len: %x\n", bootseq_len);
}
/*
* One terminating char + one byte for space between mode
* and default boot_targets
*/
env_targets = env_get("boot_targets");
if (env_targets)
env_targets_len = strlen(env_targets);
new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
bootseq_len);
if (!new_targets)
return -ENOMEM;
if (bootseq >= 0)
sprintf(new_targets, "%s%x %s", mode, bootseq,
env_targets ? env_targets : "");
else
sprintf(new_targets, "%s %s", mode,
env_targets ? env_targets : "");
env_set("boot_targets", new_targets);
return board_late_init_xilinx();
}

81
board/xilinx/versal-net/cmds.c Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <cpu_func.h>
#include <command.h>
#include <common.h>
#include <log.h>
#include <memalign.h>
#include <versalpl.h>
#include <zynqmp_firmware.h>
/**
* do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command
* @cmdtp: Command data struct pointer
* @flag: Command flag
* @argc: Command-line argument count
* @argv: Array of command-line arguments
*
* Processes the Versal NET load pdi command
*
* Return: return 0 on success, Error value if command fails.
* CMD_RET_USAGE incase of incorrect/missing parameters.
*/
static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
u32 buf_lo, buf_hi;
u32 ret_payload[PAYLOAD_ARG_CNT];
ulong addr, *pdi_buf;
size_t len;
int ret;
if (argc != cmdtp->maxargs) {
debug("pdi_load: incorrect parameters passed\n");
return CMD_RET_USAGE;
}
addr = simple_strtol(argv[1], NULL, 16);
if (!addr) {
debug("pdi_load: zero pdi_data address\n");
return CMD_RET_USAGE;
}
len = hextoul(argv[2], NULL);
if (!len) {
debug("pdi_load: zero size\n");
return CMD_RET_USAGE;
}
pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
if ((ulong)addr != (ulong)pdi_buf) {
memcpy((void *)pdi_buf, (void *)addr, len);
debug("Pdi addr:0x%lx aligned to 0x%lx\n",
addr, (ulong)pdi_buf);
}
flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
buf_lo = lower_32_bits((ulong)pdi_buf);
buf_hi = upper_32_bits((ulong)pdi_buf);
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
buf_hi, 0, ret_payload);
if (ret)
printf("PDI load failed with err: 0x%08x\n", ret);
return cmd_process_error(cmdtp, ret);
}
static char versalnet_help_text[] =
"loadpdi addr len - Load pdi image\n"
"load pdi image at ddr address 'addr' with pdi image size 'len'\n"
;
U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text,
U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
do_versalnet_load_pdi));

26
board/xilinx/zynqmp/cmds.c
View File

@ -187,6 +187,11 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc != cmdtp->maxargs)
return CMD_RET_USAGE;
if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) {
printf("mode param should be lockstep or split\n");
return CMD_RET_FAILURE;
}
mode = hextoul(argv[2], NULL);
if (mode != TCM_LOCK && mode != TCM_SPLIT) {
printf("Mode should be either 0(lock)/1(split)\n");
@ -211,15 +216,24 @@ static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
if (!strncmp(argv[2], "node", 4)) {
u32 id;
int ret;
if (!strncmp(argv[3], "close", 5))
return zynqmp_pmufw_config_close();
id = dectoul(argv[3], NULL);
if (!id) {
printf("Incorrect ID passed\n");
return CMD_RET_USAGE;
}
printf("Enable permission for node ID %d\n", id);
return zynqmp_pmufw_node(id);
ret = zynqmp_pmufw_node(id);
if (ret == -ENODEV)
ret = 0;
return ret;
}
addr = hextoul(argv[2], NULL);
@ -390,17 +404,17 @@ static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct cmd_tbl *c;
int ret = CMD_RET_USAGE;
if (argc < 2)
return CMD_RET_USAGE;
c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0],
ARRAY_SIZE(cmd_zynqmp_sub));
if (c)
return c->cmd(c, flag, argc, argv);
else
return CMD_RET_USAGE;
ret = c->cmd(c, flag, argc, argv);
return cmd_process_error(c, ret);
}
/***************************************************/
@ -429,7 +443,7 @@ static char zynqmp_help_text[] =
" lock(0)/split(1)\n"
#endif
"zynqmp pmufw address size - load PMU FW configuration object\n"
"zynqmp pmufw node <id> - load PMU FW configuration object\n"
"zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n"
"zynqmp pmufw node close - disable config object loading\n"
" node: keyword, id: NODE_ID in decimal format\n"
"zynqmp rsa srcaddr srclen mod exp rsaop -\n"

2
boot/boot_fit.c
View File

@ -67,7 +67,7 @@ void *locate_dtb_in_fit(const void *fit)
header = (struct legacy_img_hdr *)fit;
if (image_get_magic(header) != FDT_MAGIC) {
debug("No FIT image appended to U-boot\n");
debug("No FIT image appended to U-Boot\n");
return NULL;
}

2
cmd/ufs.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/**
* ufs.c - UFS specific U-boot commands
* ufs.c - UFS specific U-Boot commands
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
*

2
common/spl/spl.c
View File

@ -321,7 +321,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image,
spl_image->fdt_addr = (void *)dt_data;
if (spl_image->os == IH_OS_U_BOOT) {
/* HACK: U-boot expects FDT at a specific address */
/* HACK: U-Boot expects FDT at a specific address */
fdt_hack = spl_image->load_addr + spl_image->size;
fdt_hack = (fdt_hack + 3) & ~3;
debug("Relocating FDT to %p\n", spl_image->fdt_addr);

2
common/spl/spl_mmc.c
View File

@ -250,7 +250,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
return ret;
if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) {
puts("Expected image is not found. Trying to start U-boot\n");
puts("Expected image is not found. Trying to start U-Boot\n");
return -ENOENT;
}

2
doc/README.pcap
View File

@ -1,6 +1,6 @@
PCAP:
U-boot supports live Ethernet packet capture in PCAP(2.4) format.
U-Boot supports live Ethernet packet capture in PCAP(2.4) format.
This is enabled by CONFIG_CMD_PCAP.
The capture is stored on physical memory, and should be copied to

2
doc/README.s5p4418
View File

@ -38,7 +38,7 @@ The source code for (the used?) LUbuntu 16.04 can be found at [5].
Links
=====
[1] FriendlyArm U-boot v2016.01:
[1] FriendlyArm U-Boot v2016.01:
https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01

4
doc/SPL/README.spl-secure-boot
View File

@ -12,7 +12,7 @@ Methodology
The SPL image is responsible for loading the next stage boot loader, which is
the main u-boot image. For secure boot process on these platforms ROM verifies
SPL image, so to continue chain of trust SPL image verifies U-boot image using
SPL image, so to continue chain of trust SPL image verifies U-Boot image using
spl_validate_uboot(). This function uses QorIQ Trust Architecture header
(appended to U-boot image) to validate the U-boot binary just before passing
(appended to U-Boot image) to validate the U-Boot binary just before passing
control to it.

2
doc/board/amlogic/p201.rst
View File

@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre:
$ make
$ export FIPDIR=$PWD/fip
Go back to mainline U-boot source tree then :
Go back to mainline U-Boot source tree then :
.. code-block:: bash

2
doc/board/amlogic/p212.rst
View File

@ -50,7 +50,7 @@ the git tree published by the board vendor:
$ make
$ export FIPDIR=$PWD/fip
Go back to mainline U-boot source tree then :
Go back to mainline U-Boot source tree then :
.. code-block:: bash

2
doc/board/amlogic/s400.rst
View File

@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre:
$ make
$ export FIPDIR=$PWD/fip
Go back to mainline U-boot source tree then :
Go back to mainline U-Boot source tree then :
.. code-block:: bash

2
doc/board/emulation/qemu-arm.rst
View File

@ -54,7 +54,7 @@ Note that for some odd reason qemu-system-aarch64 needs to be explicitly
told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument
ensures that output appears on the terminal. Use Ctrl-A X to quit.
Additional persistent U-boot environment support can be added as follows:
Additional persistent U-Boot environment support can be added as follows:
- Create envstore.img using qemu-img::

2
doc/board/nxp/ls1046ardb.rst
View File

@ -150,7 +150,7 @@ Then, launch openocd like::
openocd -f u-boot.tcl
You should see the U-boot SPL banner followed by the banner for U-Boot proper
You should see the U-Boot SPL banner followed by the banner for U-Boot proper
in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a
long time. If you don't see it, something has gone wrong. After a while, you
should see the prompt. You can load an image using semihosting by running::

2
doc/board/nxp/mx6sabresd.rst
View File

@ -53,7 +53,7 @@ This will generate the SPL and u-boot-dtb.img binaries.
- Boot first from SD card as shown in the previous section
In U-boot change the eMMC partition config::
In U-Boot change the eMMC partition config::
=> mmc partconf 2 1 0 0

6
doc/board/rockchip/rockchip.rst
View File

@ -333,12 +333,12 @@ Note:
Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support.
If all other boot options fail then it enters into a BootROM mode on the USB OTG port.
This method loads TPL/SPL on NAND with U-boot and kernel on SD card.
This method loads TPL/SPL on NAND with U-Boot and kernel on SD card.
SD Card
^^^^^^^
U-boot expects a GPT partition map and a boot directory structure with files on the SD card.
U-Boot expects a GPT partition map and a boot directory structure with files on the SD card.
.. code-block:: none
@ -363,7 +363,7 @@ Boot partition:
zImage
rk3066a-mk808.dtb
To write a U-boot image to the SD card (assumed to be /dev/sda):
To write a U-Boot image to the SD card (assumed to be /dev/sda):
.. code-block:: bash

2
doc/board/sifive/unmatched.rst
View File

@ -558,7 +558,7 @@ for partitions one through three respectively.
--new=3:10280:10535 --change-name=3:env --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \
/dev/mtdblock0
Write U-boot SPL and U-boot to their partitions.
Write U-Boot SPL and U-Boot to their partitions.
.. code-block:: none

2
doc/board/st/stm32mp1.rst
View File

@ -345,7 +345,7 @@ Build Procedure
- BL33=u-boot-nodtb.bin
- BL33_CFG=u-boot.dtb
You can also update a existing FIP after U-boot compilation with fiptool,
You can also update a existing FIP after U-Boot compilation with fiptool,
a tool provided by TF-A_::
# fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb fip-stm32mp157c-ev1.bin

10
doc/board/xen/xenguest_arm64.rst
View File

@ -6,7 +6,7 @@ Xen guest ARM64 board
This board specification
------------------------
This board is to be run as a virtual Xen [1] guest with U-boot as its primary
This board is to be run as a virtual Xen [1] guest with U-Boot as its primary
bootloader. Xen is a type 1 hypervisor that allows multiple operating systems
to run simultaneously on a single physical server. Xen is capable of running
virtual machines in both full virtualization and para-virtualization (PV)
@ -16,7 +16,7 @@ Paravirtualized drivers are a special type of device drivers that are used in
a guest system in the Xen domain and perform I/O operations using a special
interface provided by the virtualization system and the host system.
Xen support for U-boot is implemented by introducing a new Xen guest ARM64
Xen support for U-Boot is implemented by introducing a new Xen guest ARM64
board and porting essential drivers from MiniOS [3] as well as some of the work
previously done by NXP [4]:
@ -39,7 +39,7 @@ previously done by NXP [4]:
Board limitations
-----------------
1. U-boot runs without MMU enabled at the early stages.
1. U-Boot runs without MMU enabled at the early stages.
According to Xen on ARM ABI (xen/include/public/arch-arm.h): all memory
which is shared with other entities in the system (including the hypervisor
and other guests) must reside in memory which is mapped as Normal Inner
@ -54,14 +54,14 @@ Board limitations
2. No serial console until MMU is up.
Because data cache maintenance is required until the MMU setup the
early/debug serial console is not implemented. Therefore, we do not have
usual prints like U-boot’s banner etc. until the serial driver is
usual prints like U-Boot’s banner etc. until the serial driver is
initialized.
3. Single RAM bank supported.
If a Xen guest is given much memory it is possible that Xen allocates two
memory banks for it. The first one is allocated under 4GB address space and
in some cases may represent the whole guest’s memory. It is assumed that
U-boot most likely won’t require high memory bank for its work andlaunching
U-Boot most likely won’t require high memory bank for its work andlaunching
OS, so it is enough to take the first one.

2
doc/develop/driver-model/bind.rst
View File

@ -7,7 +7,7 @@ Binding/unbinding a driver
This document aims to describe the bind and unbind commands.
For debugging purpose, it should be useful to bind or unbind a driver from
the U-boot command line.
the U-Boot command line.
The unbind command calls the remove device driver callback and unbind the
device from its driver.

6
doc/develop/driver-model/fs_firmware_loader.rst
View File

@ -92,9 +92,9 @@ For example of getting DT phandle from /chosen and creating instance:
if (ret)
return ret;
Firmware loader driver is also designed to support U-boot environment
Firmware loader driver is also designed to support U-Boot environment
variables, so all these data from FDT can be overwritten
through the U-boot environment variable during run time.
through the U-Boot environment variable during run time.
For examples:
@ -110,7 +110,7 @@ fw_ubi_volume:
When above environment variables are set, environment values would be
used instead of data from FDT.
The benefit of this design allows user to change storage attribute data
at run time through U-boot console and saving the setting as default
at run time through U-Boot console and saving the setting as default
environment values in the storage for the next power cycle, so no
compilation is required for both driver and FDT.

2
doc/develop/uefi/uefi.rst
View File

@ -357,7 +357,7 @@ bit in OsIndications variable with
=> setenv -e -nv -bs -rt -v OsIndications =0x0000000000000004
Since U-boot doesn't currently support SetVariable at runtime, its value
Since U-Boot doesn't currently support SetVariable at runtime, its value
won't be taken over across the reboot. If this is the case, you can skip
this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
set.

2
doc/usage/cmd/source.rst
View File

@ -161,7 +161,7 @@ The boot scripts (boot.scr) is created with:
mkimage -T script -n 'Test script' -d boot.txt boot.scr
The script can be execute in U-boot like this:
The script can be execute in U-Boot like this:
.. code-block::

2
doc/usage/dfu.rst
View File

@ -9,7 +9,7 @@ Overview
The Device Firmware Upgrade (DFU) allows to download and upload firmware
to/from U-Boot connected over USB.
U-boot follows the Universal Serial Bus Device Class Specification for
U-Boot follows the Universal Serial Bus Device Class Specification for
Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org).
U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu

2
drivers/clk/clk-mux.c
View File

@ -184,7 +184,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
if (!mux)
return ERR_PTR(-ENOMEM);
/* U-boot specific assignments */
/* U-Boot specific assignments */
mux->parent_names = parent_names;
mux->num_parents = num_parents;

1
drivers/clk/clk_zynqmp.c
View File

@ -691,6 +691,7 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
case topsw_lsbus:
case sata_ref ... gpu_pp1_ref:
two_divs = true;
fallthrough;
case cpu_r5:
case dbg_fpd:
case ams_ref:

48
drivers/firmware/firmware-zynqmp.c
View File

@ -23,10 +23,10 @@
#define XST_PM_NO_ACCESS 2002L
#define XST_PM_ALREADY_CONFIGURED 2009L
struct zynqmp_power {
static struct zynqmp_power {
struct mbox_chan tx_chan;
struct mbox_chan rx_chan;
} zynqmp_power = {};
} zynqmp_power __section(".data");
#define NODE_ID_LOCATION 5
@ -63,29 +63,32 @@ static unsigned int xpm_configobject_close[] = {
int zynqmp_pmufw_config_close(void)
{
zynqmp_pmufw_load_config_object(xpm_configobject_close,
sizeof(xpm_configobject_close));
return 0;
return zynqmp_pmufw_load_config_object(xpm_configobject_close,
sizeof(xpm_configobject_close));
}
int zynqmp_pmufw_node(u32 id)
{
static bool skip_config;
int ret;
static bool check = true;
static bool permission = true;
if (skip_config)
if (check) {
check = false;
if (zynqmp_pmufw_node(NODE_OCM_BANK_0) == -EACCES) {
printf("PMUFW: No permission to change config object\n");
permission = false;
}
}
if (!permission)
return 0;
/* Record power domain id */
xpm_configobject[NODE_ID_LOCATION] = id;
ret = zynqmp_pmufw_load_config_object(xpm_configobject,
sizeof(xpm_configobject));
if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
skip_config = true;
return 0;
return zynqmp_pmufw_load_config_object(xpm_configobject,
sizeof(xpm_configobject));
}
static int do_pm_probe(void)
@ -235,8 +238,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
*
* @cfg_obj: Pointer to the configuration object
* @size: Size of @cfg_obj in bytes
* Return: 0 on success otherwise negative errno. If the config object
* is not loadable returns positive errno XST_PM_NO_ACCESS(2002)
* Return: 0 on success otherwise negative errno.
*/
int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
{
@ -251,10 +253,6 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
0, ret_payload);
if (err == XST_PM_NO_ACCESS) {
if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) {
printf("PMUFW: No permission to change config object\n");
return err;
}
return -EACCES;
}
@ -298,9 +296,6 @@ static int zynqmp_power_probe(struct udevice *dev)
ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
ret & ZYNQMP_PM_VERSION_MINOR_MASK);
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
zynqmp_pmufw_node(NODE_OCM_BANK_0);
return 0;
};
@ -320,7 +315,8 @@ U_BOOT_DRIVER(zynqmp_power) = {
int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload)
{
debug("%s at EL%d, API ID: 0x%0x\n", __func__, current_el(), api_id);
debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n",
__func__, current_el(), api_id, arg0, arg1, arg2, arg3);
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
#if defined(CONFIG_ZYNQMP_IPI)
@ -398,7 +394,7 @@ static int zynqmp_firmware_bind(struct udevice *dev)
}
}
return dm_scan_fdt_dev(dev);
return 0;
}
U_BOOT_DRIVER(zynqmp_firmware) = {

2
drivers/gpio/gpio-fxl6408.c
View File

@ -27,7 +27,7 @@
* https://patchwork.kernel.org/patch/9148419/
* - the Toradex version by Max Krummenacher <max.krummenacher@toradex.com>:
* http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx
* - the U-boot PCA953x driver by Peng Fan <van.freenix@gmail.com>:
* - the U-Boot PCA953x driver by Peng Fan <van.freenix@gmail.com>:
* drivers/gpio/pca953x_gpio.c
*
* TODO:

10
drivers/mmc/zynq_sdhci.c
View File

@ -873,7 +873,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
if (ret)
return ret;
} else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
device_is_compatible(dev, "xlnx,versal-net-emmc")) {
if (mmc->clock >= MIN_PHY_CLK_HZ)
if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
@ -948,7 +948,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
}
if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
device_is_compatible(dev, "xlnx,versal-net-emmc")) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
@ -1102,7 +1102,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
}
}
#endif
if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
if (device_is_compatible(dev, "xlnx,versal-net-emmc"))
priv->internal_phy_reg = true;
ret = clk_get_by_index(dev, 0, &clk);
@ -1136,7 +1136,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
device_is_compatible(dev, "xlnx,versal-net-emmc"))
host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
@ -1219,7 +1219,7 @@ static int arasan_sdhci_bind(struct udevice *dev)
static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-8.9a" },
{ .compatible = "xlnx,versal-net-5.1-emmc" },
{ .compatible = "xlnx,versal-net-emmc" },
{ }
};

6
drivers/mtd/nand/raw/Kconfig
View File

@ -553,7 +553,7 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
bool "Enable use of 1st stage bootloader timing for NAND"
depends on NAND_ZYNQ
help
This flag prevent U-boot reconfigure NAND flash controller and reuse
This flag prevent U-Boot reconfigure NAND flash controller and reuse
the NAND timing from 1st stage bootloader.
config NAND_OCTEONTX
@ -732,10 +732,10 @@ config SYS_NAND_BAD_BLOCK_POS
default 5 if HAS_NAND_SMALL_BADBLOCK_POS
config SYS_NAND_U_BOOT_LOCATIONS
bool "Define U-boot binaries locations in NAND"
bool "Define U-Boot binaries locations in NAND"
help
Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
This option should not be enabled when compiling U-boot for boards
This option should not be enabled when compiling U-Boot for boards
defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
file.

4
drivers/mtd/nand/raw/fsl_ifc_spl.c
View File

@ -275,8 +275,8 @@ void nand_boot(void)
#ifdef CONFIG_CHAIN_OF_TRUST
/*
* U-Boot header is appended at end of U-boot image, so
* calculate U-boot header address using U-boot header size.
* U-Boot header is appended at end of U-Boot image, so
* calculate U-Boot header address using U-Boot header size.
*/
#define FSL_U_BOOT_HDR_ADDR \
((CFG_SYS_NAND_U_BOOT_START + \

2
drivers/net/pfe_eth/pfe_hw.c
View File

@ -814,7 +814,7 @@ static inline void class_set_config(struct class_cfg *cfg)
writel(0x1, CLASS_AXI_CTRL);
/*Make Util AXI transactions non-bufferable */
/*Util is disabled in U-boot, do it from here */
/*Util is disabled in U-Boot, do it from here */
writel(0x1, UTIL_AXI_CTRL);
}

7
drivers/pci/Kconfig
View File

@ -374,4 +374,11 @@ config PCIE_UNIPHIER
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
config PCIE_XILINX_NWL
bool "Xilinx NWL PCIe controller"
depends on ARCH_ZYNQMP
help
Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
controller as Root Port.
endif

1
drivers/pci/Makefile
View File

@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o

352
drivers/pci/pcie-xilinx-nwl.c Normal file
View File

@ -0,0 +1,352 @@
// SPDX-License-Identifier: GPL-2.0
/*
* PCIe host bridge driver for Xilinx / AMD ZynqMP NWL PCIe Bridge
*
* Based on the Linux driver which is:
* (C) Copyright 2014 - 2015, Xilinx, Inc.
*
* Author: Stefan Roese <sr@denx.de>
*/
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <mapmem.h>
#include <pci.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/ioport.h>
/* Bridge core config registers */
#define BRCFG_PCIE_RX0 0x00000000
#define BRCFG_PCIE_RX1 0x00000004
#define BRCFG_INTERRUPT 0x00000010
#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
/* Egress - Bridge translation registers */
#define E_BREG_CAPABILITIES 0x00000200
#define E_BREG_CONTROL 0x00000208
#define E_BREG_BASE_LO 0x00000210
#define E_BREG_BASE_HI 0x00000214
#define E_ECAM_CAPABILITIES 0x00000220
#define E_ECAM_CONTROL 0x00000228
#define E_ECAM_BASE_LO 0x00000230
#define E_ECAM_BASE_HI 0x00000234
#define I_ISUB_CONTROL 0x000003E8
#define SET_ISUB_CONTROL BIT(0)
/* Rxed msg fifo - Interrupt status registers */
#define MSGF_MISC_STATUS 0x00000400
#define MSGF_MISC_MASK 0x00000404
#define MSGF_LEG_STATUS 0x00000420
#define MSGF_LEG_MASK 0x00000424
#define MSGF_MSI_STATUS_LO 0x00000440
#define MSGF_MSI_STATUS_HI 0x00000444
#define MSGF_MSI_MASK_LO 0x00000448
#define MSGF_MSI_MASK_HI 0x0000044C
/* Msg filter mask bits */
#define CFG_ENABLE_PM_MSG_FWD BIT(1)
#define CFG_ENABLE_INT_MSG_FWD BIT(2)
#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
CFG_ENABLE_INT_MSG_FWD | \
CFG_ENABLE_ERR_MSG_FWD)
/* Misc interrupt status mask bits */
#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
#define MSGF_MISC_SR_MASTER_ERR BIT(5)
#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
#define MSGF_MISC_SR_FATAL_AER BIT(16)
#define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
#define MSGF_MISC_SR_CORR_AER BIT(18)
#define MSGF_MISC_SR_UR_DETECT BIT(20)
#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
#define MSGF_MISC_SR_FATAL_DEV BIT(23)
#define MSGF_MISC_SR_LINK_DOWN BIT(24)
#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
MSGF_MISC_SR_RXMSG_OVER | \
MSGF_MISC_SR_SLAVE_ERR | \
MSGF_MISC_SR_MASTER_ERR | \
MSGF_MISC_SR_I_ADDR_ERR | \
MSGF_MISC_SR_E_ADDR_ERR | \
MSGF_MISC_SR_FATAL_AER | \
MSGF_MISC_SR_NON_FATAL_AER | \
MSGF_MISC_SR_CORR_AER | \
MSGF_MISC_SR_UR_DETECT | \
MSGF_MISC_SR_NON_FATAL_DEV | \
MSGF_MISC_SR_FATAL_DEV | \
MSGF_MISC_SR_LINK_DOWN | \
MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
MSGF_MSIC_SR_LINK_BWIDTH)
/* Legacy interrupt status mask bits */
#define MSGF_LEG_SR_INTA BIT(0)
#define MSGF_LEG_SR_INTB BIT(1)
#define MSGF_LEG_SR_INTC BIT(2)
#define MSGF_LEG_SR_INTD BIT(3)
#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
/* MSI interrupt status mask bits */
#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
/* Bridge config interrupt mask */
#define BRCFG_INTERRUPT_MASK BIT(0)
#define BREG_PRESENT BIT(0)
#define BREG_ENABLE BIT(0)
#define BREG_ENABLE_FORCE BIT(1)
/* E_ECAM status mask bits */
#define E_ECAM_PRESENT BIT(0)
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
#define NWL_ECAM_VALUE_DEFAULT 12
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
/* Readin the PS_LINKUP */
#define PS_LINKUP_OFFSET 0x00000238
#define PCIE_PHY_LINKUP_BIT BIT(0)
#define PHY_RDY_LINKUP_BIT BIT(1)
/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES 10
#define LINK_WAIT_USLEEP_MIN 90000
#define LINK_WAIT_USLEEP_MAX 100000
struct nwl_pcie {
struct udevice *dev;
void __iomem *breg_base;
void __iomem *pcireg_base;
void __iomem *ecam_base;
phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
phys_addr_t phys_ecam_base; /* Physical Configuration Base */
u32 ecam_value;
};
static int nwl_pcie_config_address(const struct udevice *bus,
pci_dev_t bdf, uint offset,
void **paddress)
{
struct nwl_pcie *pcie = dev_get_priv(bus);
void *addr;
addr = pcie->ecam_base;
addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(bus),
PCI_DEV(bdf), PCI_FUNC(bdf), offset);
*paddress = addr;
return 0;
}
static int nwl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
{
return pci_generic_mmap_read_config(bus, nwl_pcie_config_address,
bdf, offset, valuep, size);
}
static int nwl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
{
return pci_generic_mmap_write_config(bus, nwl_pcie_config_address,
bdf, offset, value, size);
}
static const struct dm_pci_ops nwl_pcie_ops = {
.read_config = nwl_pcie_read_config,
.write_config = nwl_pcie_write_config,
};
static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
{
return readl(pcie->breg_base + off);
}
static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
{
writel(val, pcie->breg_base + off);
}
static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
{
if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
return true;
return false;
}
static bool nwl_phy_link_up(struct nwl_pcie *pcie)
{
if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
return true;
return false;
}
static int nwl_wait_for_link(struct nwl_pcie *pcie)
{
struct udevice *dev = pcie->dev;
int retries;
/* check if the link is up or not */
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
if (nwl_phy_link_up(pcie))
return 0;
udelay(LINK_WAIT_USLEEP_MIN);
}
dev_warn(dev, "PHY link never came up\n");
return -ETIMEDOUT;
}
static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
{
struct udevice *dev = pcie->dev;
u32 breg_val, ecam_val;
int err;
breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
if (!breg_val) {
dev_err(dev, "BREG is not present\n");
return breg_val;
}
/* Write bridge_off to breg base */
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
E_BREG_BASE_LO);
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
E_BREG_BASE_HI);
/* Enable BREG */
nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
E_BREG_CONTROL);
/* Disable DMA channel registers */
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
/* Enable Ingress subtractive decode translation */
nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
/* Enable msg filtering details */
nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
BRCFG_PCIE_RX_MSG_FILTER);
err = nwl_wait_for_link(pcie);
if (err)
return err;
ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
if (!ecam_val) {
dev_err(dev, "ECAM is not present\n");
return ecam_val;
}
/* Enable ECAM */
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
(pcie->ecam_value << E_ECAM_SIZE_SHIFT),
E_ECAM_CONTROL);
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
E_ECAM_BASE_LO);
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
E_ECAM_BASE_HI);
if (nwl_pcie_link_up(pcie))
dev_info(dev, "Link is UP\n");
else
dev_info(dev, "Link is DOWN\n");
/* Disable all misc interrupts */
nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
/* Clear pending misc interrupts */
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
/* Disable all legacy interrupts */
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
/* Clear pending legacy interrupts */
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
return 0;
}
static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
{
struct udevice *dev = pcie->dev;
struct resource res;
int ret;
ret = dev_read_resource_byname(dev, "breg", &res);
if (ret)
return ret;
pcie->breg_base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(pcie->breg_base))
return PTR_ERR(pcie->breg_base);
pcie->phys_breg_base = res.start;
ret = dev_read_resource_byname(dev, "cfg", &res);
if (ret)
return ret;
pcie->ecam_base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(pcie->ecam_base))
return PTR_ERR(pcie->ecam_base);
pcie->phys_ecam_base = res.start;
return 0;
}
static int nwl_pcie_probe(struct udevice *dev)
{
struct nwl_pcie *pcie = dev_get_priv(dev);
int err;
pcie->dev = dev;
pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
err = nwl_pcie_parse_dt(pcie);
if (err) {
dev_err(dev, "Parsing DT failed\n");
return err;
}
err = nwl_pcie_bridge_init(pcie);
if (err) {
dev_err(dev, "HW Initialization failed\n");
return err;
}
return 0;
}
static const struct udevice_id nwl_pcie_of_match[] = {
{ .compatible = "xlnx,nwl-pcie-2.11", },
{ /* sentinel */ }
};
U_BOOT_DRIVER(nwl_pcie) = {
.name = "nwl-pcie",
.id = UCLASS_PCI,
.of_match = nwl_pcie_of_match,
.probe = nwl_pcie_probe,
.priv_auto = sizeof(struct nwl_pcie),
.ops = &nwl_pcie_ops,
};

2
drivers/phy/marvell/comphy_cp110.c
View File

@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
/* Used to distinguish between different possible callers (U-boot/Linux) */
/* Used to distinguish between different possible callers (U-Boot/Linux) */
#define COMPHY_CALLER_UBOOT (0x1 << 21)
#define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12)

11
drivers/power/domain/zynqmp-power-domain.c
View File

@ -23,12 +23,17 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
static int zynqmp_power_domain_request(struct power_domain *power_domain)
{
int ret = 0;
dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id);
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
return zynqmp_pmufw_node(power_domain->id);
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
ret = zynqmp_pmufw_node(power_domain->id);
if (ret == -ENODEV)
ret = 0;
}
return 0;
return ret;
}
static int zynqmp_power_domain_free(struct power_domain *power_domain)

2
drivers/spi/spi-qup.c
View File

@ -9,7 +9,7 @@
* Author: Robert Marko <robert.marko@sartura.hr>
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*
* Based on stock U-boot and Linux drivers
* Based on stock U-Boot and Linux drivers
*/
#include <asm/gpio.h>

9
drivers/video/Kconfig
View File

@ -740,14 +740,7 @@ config VIDEO_SEPS525
Enable support for the Syncoam PM-OLED display driver (RGB 160x128).
Currently driver is supporting only SPI interface.
config VIDEO_ZYNQMP_DPSUB
bool "Enable video support for ZynqMP Display Port"
depends on ZYNQMP_POWER_DOMAIN
help
Enable support for Xilinx ZynqMP Display Port. Currently this file
is used as placeholder for driver. The main reason is to record
compatible string and calling power domain driver.
source "drivers/video/zynqmp/Kconfig"
source "drivers/video/nexell/Kconfig"
config CONSOLE_SCROLL_LINES

2
drivers/video/Makefile
View File

@ -73,7 +73,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
obj-$(CONFIG_VIDEO_VESA) += vesa.o
obj-$(CONFIG_VIDEO_SEPS525) += seps525.o
obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o
obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/
obj-y += bridge/
obj-y += sunxi/

10
drivers/video/video-uclass.c
View File

@ -220,14 +220,20 @@ u32 video_index_to_colour(struct video_priv *priv, unsigned int idx)
break;
case VIDEO_BPP32:
if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
if (priv->format == VIDEO_X2R10G10B10)
switch (priv->format) {
case VIDEO_X2R10G10B10:
return (colours[idx].r << 22) |
(colours[idx].g << 12) |
(colours[idx].b << 2);
else
case VIDEO_RGBA8888:
return (colours[idx].r << 24) |
(colours[idx].g << 16) |
(colours[idx].b << 8) | 0xff;
default:
return (colours[idx].r << 16) |
(colours[idx].g << 8) |
(colours[idx].b << 0);
}
}
break;
default:

36
drivers/video/video_bmp.c
View File

@ -42,6 +42,18 @@ static u32 get_bmp_col_x2r10g10b10(struct bmp_color_table_entry *cte)
(cte->blue << 2U));
}
/**
* get_bmp_col_rgba8888() - Convert a colour-table entry into a rgba8888 pixel value
*
* Return: value to write to the rgba8888 frame buffer for this palette entry
*/
static u32 get_bmp_col_rgba8888(struct bmp_color_table_entry *cte)
{
return ((cte->red) |
(cte->green << 8U) |
(cte->blue << 16U) | 0xff << 24U);
}
/**
* write_pix8() - Write a pixel from a BMP image into the framebuffer
*
@ -71,6 +83,8 @@ static void write_pix8(u8 *fb, uint bpix, enum video_format eformat,
*fb++ = cte->blue;
} else if (eformat == VIDEO_X2R10G10B10) {
*(u32 *)fb = get_bmp_col_x2r10g10b10(cte);
} else if (eformat == VIDEO_RGBA8888) {
*(u32 *)fb = get_bmp_col_rgba8888(cte);
} else {
*fb++ = cte->blue;
*fb++ = cte->green;
@ -382,6 +396,17 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
*fb++ = (pix >> 8) & 0xff;
*fb++ = (pix >> 16) & 0xff;
*fb++ = pix >> 24;
} else if (eformat == VIDEO_RGBA8888) {
u32 pix;
pix = *bmap++ << 8U; /* blue */
pix |= *bmap++ << 16U; /* green */
pix |= *bmap++ << 24U; /* red */
*fb++ = (pix >> 24) & 0xff;
*fb++ = (pix >> 16) & 0xff;
*fb++ = (pix >> 8) & 0xff;
*fb++ = 0xff;
} else {
*fb++ = *bmap++;
*fb++ = *bmap++;
@ -409,6 +434,17 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
*fb++ = (pix >> 8) & 0xff;
*fb++ = (pix >> 16) & 0xff;
*fb++ = pix >> 24;
} else if (eformat == VIDEO_RGBA8888) {
u32 pix;
pix = *bmap++ << 8U; /* blue */
pix |= *bmap++ << 16U; /* green */
pix |= *bmap++ << 24U; /* red */
bmap++;
*fb++ = (pix >> 24) & 0xff;
*fb++ = (pix >> 16) & 0xff;
*fb++ = (pix >> 8) & 0xff;
*fb++ = 0xff; /* opacity */
} else {
*fb++ = *bmap++;
*fb++ = *bmap++;

8
drivers/video/zynqmp/Kconfig Normal file
View File

@ -0,0 +1,8 @@
config VIDEO_ZYNQMP_DPSUB
bool "Enable video support for ZynqMP Display Port"
depends on ZYNQMP_POWER_DOMAIN
help
Enable support for Xilinx ZynqMP Display Port. Currently this file
is used as placeholder for driver. The main reason is to record
compatible string and calling power domain driver.

5
drivers/video/zynqmp/Makefile Normal file
View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (C) 2023, Advanced Micro Devices, Inc.
obj-y += zynqmp_dpsub.o

2225
drivers/video/zynqmp/zynqmp_dpsub.c Normal file
View File

File diff suppressed because it is too large Load Diff

680
drivers/video/zynqmp/zynqmp_dpsub.h Normal file
View File

@ -0,0 +1,680 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023, Advanced Micro Devices, Inc.
*
*/
#ifndef _VIDEO_ZYNQMP_DPSUB_H
#define _VIDEO_ZYNQMP_DPSUB_H
enum video_mode {
VIDC_VM_640x480_60_P = 0,
VIDC_VM_1024x768_60_P = 1,
};
enum {
LANE_COUNT_1 = 1,
LANE_COUNT_2 = 2,
};
enum {
LINK_RATE_162GBPS = 0x06,
LINK_RATE_270GBPS = 0x0A,
LINK_RATE_540GBPS = 0x14,
};
enum video_color_depth {
VIDC_BPC_6 = 6,
VIDC_BPC_8 = 8,
VIDC_BPC_10 = 10,
VIDC_BPC_12 = 12,
VIDC_BPC_14 = 14,
VIDC_BPC_16 = 16,
VIDC_BPC_NUM_SUPPORTED = 6,
VIDC_BPC_UNKNOWN
};
enum video_color_encoding {
DP_CENC_RGB = 0,
DP_CENC_YONLY,
};
enum dp_dma_channel_type {
VIDEO_CHAN,
GRAPHICS_CHAN,
};
enum dp_dma_channel_state {
DPDMA_DISABLE,
DPDMA_ENABLE,
DPDMA_IDLE,
DPDMA_PAUSE
};
enum link_training_states {
TS_CLOCK_RECOVERY,
TS_CHANNEL_EQUALIZATION,
TS_ADJUST_LINK_RATE,
TS_ADJUST_LANE_COUNT,
TS_FAILURE,
TS_SUCCESS
};
enum video_frame_rate {
VIDC_FR_60HZ = 60,
VIDC_FR_NUM_SUPPORTED = 2,
VIDC_FR_UNKNOWN
};
enum av_buf_video_modes {
INTERLEAVED,
SEMIPLANAR
};
enum av_buf_video_format {
RGBA8888 = 1,
};
enum av_buf_video_stream {
AVBUF_VIDSTREAM1_LIVE,
AVBUF_VIDSTREAM1_NONLIVE,
AVBUF_VIDSTREAM1_TPG,
AVBUF_VIDSTREAM1_NONE,
};
enum av_buf_gfx_stream {
AVBUF_VIDSTREAM2_DISABLEGFX = 0x0,
AVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4,
AVBUF_VIDSTREAM2_LIVE_GFX = 0x8,
AVBUF_VIDSTREAM2_NONE = 0xC0,
};
/**
* struct aux_transaction - Description of an AUX channel transaction
* @cmd_code: Command code of the transaction
* @num_bytes: The number of bytes in the transaction's payload data
* @address: The DPCD address of the transaction
* @data: Payload data of the AUX channel transaction
*/
struct aux_transaction {
u16 cmd_code;
u8 num_bytes;
u32 address;
u8 *data;
};
/**
* struct link_config - Description of link configuration
* @lane_count: Currently selected lane count for this link
* @link_rate: Currently selected link rate for this link
* @scrambler_en: Flag to determine whether the scrambler is
* enabled for this link
* @enhanced_framing_mode: Flag to determine whether enhanced framing
* mode is active for this link
* @max_lane_count: Maximum lane count for this link
* @max_link_rate: Maximum link rate for this link
* @support_enhanced_framing_mode: Flag to indicate whether the link supports
* enhanced framing mode
* @vs_level: Voltage swing for each lane
* @pe_level: Pre-emphasis/cursor level for each lane
* @pattern: The current pattern currently in use over the main link
*/
struct link_config {
u8 lane_count;
u8 link_rate;
u8 scrambler_en;
u8 enhanced_framing_mode;
u8 max_lane_count;
u8 max_link_rate;
u8 support_enhanced_framing_mode;
u8 support_downspread_control;
u8 vs_level;
u8 pe_level;
u8 pattern;
};
struct video_timing {
u16 h_active;
u16 h_front_porch;
u16 h_sync_width;
u16 h_back_porch;
u16 h_total;
bool h_sync_polarity;
u16 v_active;
u16 f0_pv_front_porch;
u16 f0_pv_sync_width;
u16 f0_pv_back_porch;
u16 f0_pv_total;
u16 f1_v_front_porch;
u16 f1_v_sync_width;
u16 f1_v_back_porch;
u16 f1_v_total;
bool v_sync_polarity;
};
struct video_timing_mode {
enum video_mode vid_mode;
char name[21];
enum video_frame_rate frame_rate;
struct video_timing video_timing;
};
/*
* struct main_stream_attributes - Main Stream Attributes (MSA)
* @pixel_clock_hz: The pixel clock of the stream (in Hz)
* @h_start: Horizontal blank start (in pixels)
* @v_start: Vertical blank start (in lines).
* @misc0: Miscellaneous stream attributes 0
* @misc1: Miscellaneous stream attributes 1
* @n_vid N value for the video stream
* @user_pixel_width: The width of the user data input port.
* @data_per_plane: Used to translate the number of pixels per
* line to the native internal 16-bit datapath.
* @avg_bytes_per_tu: Average number of bytes per transfer unit,
* scaled up by a factor of 1000.
* @transfer_unit_size: Size of the transfer unit in the
* framing logic.
* @init_wait: Number of initial wait cycles at the start
* of a new line by the framing logic.
* @bits_per_color: Number of bits per color component.
* @component_format: The component format currently in
* use by the video stream.
* @dynamic_range: The dynamic range currently in use
* by the video stream.
* @y_cb_cr_colorimetry: The YCbCr colorimetry currently in
* use by the video stream.
* @synchronous_clock_mode: Synchronous clock mode is currently
* in use by the video stream.
*/
struct main_stream_attributes {
struct video_timing_mode vid_timing_mode;
u32 pixel_clock_hz;
u32 h_start;
u32 v_start;
u32 misc0;
u32 misc1;
u32 n_vid;
u32 user_pixel_width;
u32 data_per_lane;
u32 avg_bytes_per_tu;
u32 transfer_unit_size;
u32 init_wait;
u32 bits_per_color;
u8 component_format;
u8 dynamic_range;
u8 y_cb_cr_colorimetry;
u8 synchronous_clock_mode;
};
struct av_buf_vid_attribute {
enum av_buf_video_format video_format;
u8 value;
enum av_buf_video_modes mode;
u32 sf[3];
u8 sampling_en;
u8 is_rgb;
u8 swap;
u8 bpp;
};
struct av_buf_mode {
enum av_buf_video_stream video_src;
enum av_buf_gfx_stream gfx_src;
u8 video_clk;
};
struct dp_dma_descriptor {
u32 control;
u32 dscr_id;
u32 xfer_size;
u32 line_size_stride;
u32 lsb_timestamp;
u32 msb_timestamp;
u32 addr_ext;
u32 next_desr;
u32 src_addr;
u32 addr_ext_23;
u32 addr_ext_45;
u32 src_addr2;
u32 src_addr3;
u32 src_addr4;
u32 src_addr5;
u32 crc;
};
struct dp_dma_channel {
struct dp_dma_descriptor *cur;
};
struct dp_dma_frame_buffer {
u64 address;
u32 size;
u32 stride;
u32 line_size;
};
struct dp_dma_gfx_channel {
struct dp_dma_channel channel;
u8 trigger_status;
u8 av_buf_en;
struct dp_dma_frame_buffer *frame_buffer;
};
struct dp_dma {
phys_addr_t base_addr;
struct dp_dma_gfx_channel gfx;
};
/**
* struct zynqmp_dpsub_priv - Private structure
* @dev: Device uclass for video_ops
*/
struct zynqmp_dpsub_priv {
phys_addr_t base_addr;
u32 clock;
struct av_buf_vid_attribute *non_live_graphics;
struct av_buf_mode av_mode;
struct dp_dma_frame_buffer frame_buffer;
struct link_config link_config;
struct main_stream_attributes msa_config;
struct dp_dma *dp_dma;
enum video_mode video_mode;
enum video_color_depth bpc;
enum video_color_encoding color_encode;
u32 pix_clk;
u8 dpcd_rx_caps[16];
u8 lane_status_ajd_reqs[6];
u8 sink_count;
u8 use_max_lane_count;
u8 use_max_link_rate;
u8 lane_count;
u8 link_rate;
u8 use_max_cfg_caps;
u8 en_sync_clk_mode;
};
/**************************** Variable Definitions ****************************/
#define TRAINING_PATTERN_SET 0x000C
#define TRAINING_PATTERN_SET_OFF 0x0
#define SCRAMBLING_DISABLE 0x0014
#define TRAINING_PATTERN_SET_TP1 0x1
#define TRAINING_PATTERN_SET_TP2 0x2
#define TRAINING_PATTERN_SET_TP3 0x3
#define AVBUF_BUF_4BIT_SF 0x11111
#define AVBUF_BUF_5BIT_SF 0x10842
#define AVBUF_BUF_6BIT_SF 0x10410
#define AVBUF_BUF_8BIT_SF 0x10101
#define AVBUF_BUF_10BIT_SF 0x10040
#define AVBUF_BUF_12BIT_SF 0x10000
#define AVBUF_BUF_6BPC 0x000
#define AVBUF_BUF_8BPC 0x001
#define AVBUF_BUF_10BPC 0x010
#define AVBUF_BUF_12BPC 0x011
#define AVBUF_CHBUF3 0x0000B01C
#define AVBUF_CHBUF3_BURST_LEN_SHIFT 2
#define AVBUF_CHBUF3_FLUSH_MASK 0x00000002
#define AVBUF_CHBUF0_EN_MASK 0x00000001
#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070
#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0x0000000C
#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0x00000003
#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070
#define AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0x0000B200
#define AVBUF_V_BLEND_LAYER1_CONTROL 0x0000A01C
#define AVBUF_V_BLEND_IN2CSC_COEFF0 0x0000A080
#define AVBUF_BUF_FORMAT 0x0000B000
#define AVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0x0000001F
#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0x00000F00
#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8
#define AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1
#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4
#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT 0x0000A014
#define AVBUF_V_BLEND_RGB2YCBCR_COEFF0 0x0000A020
#define AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0x0000A074
#define AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16
#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1
#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0x0000A00C
#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT 1
#define DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT 3
#define DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT 4
#define DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK 0x00000080
#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422 0x1
#define AVBUF_PL_CLK 0x0
#define AVBUF_PS_CLK 0x1
#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2
#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0
#define AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1
#define AVBUF_BUF_AUD_VID_CLK_SOURCE 0x0000B120
#define AVBUF_BUF_SRST_REG 0x0000B124
#define AVBUF_BUF_SRST_REG_VID_RST_MASK 0x00000002
#define AVBUF_CLK_FPD_BASEADDR 0xFD1A0000
#define AVBUF_CLK_LPD_BASEADDR 0xFF5E0000
#define AVBUF_LPD_CTRL_OFFSET 16
#define AVBUF_FPD_CTRL_OFFSET 12
#define AVBUF_EXTERNAL_DIVIDER 2
#define AVBUF_VIDEO_REF_CTRL 0x00000070
#define AVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007
#define AVBUF_VPLL_SRC_SEL 0
#define AVBUF_DPLL_SRC_SEL 2
#define AVBUF_RPLL_TO_FPD_SRC_SEL 3
#define AVBUF_INPUT_REF_CLK 3333333333
#define AVBUF_PLL_OUT_FREQ 1450000000
#define AVBUF_INPUT_FREQ_PRECISION 100
#define AVBUF_PRECISION 16
#define AVBUF_SHIFT_DECIMAL BIT(16)
#define AVBUF_DECIMAL (AVBUF_SHIFT_DECIMAL - 1)
#define AVBUF_ENABLE_BIT 1
#define AVBUF_DISABLE_BIT 0
#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3
#define AVBUF_PLL_CTRL_FBDIV_SHIFT 8
#define AVBUF_PLL_CTRL_DIV2_SHIFT 16
#define AVBUF_PLL_CTRL_PRE_SRC_SHIFT 20
#define AVBUF_PLL_CTRL 0x00000020
#define AVBUF_PLL_CFG_CP_SHIFT 5
#define AVBUF_PLL_CFG_RES_SHIFT 0
#define AVBUF_PLL_CFG_LFHF_SHIFT 10
#define AVBUF_PLL_CFG_LOCK_DLY_SHIFT 25
#define AVBUF_PLL_CFG_LOCK_CNT_SHIFT 13
#define AVBUF_PLL_FRAC_CFG 0x00000028
#define AVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31
#define AVBUF_PLL_FRAC_CFG_DATA_SHIFT 0
#define AVBUF_PLL_CTRL_RESET_MASK 0x00000001
#define AVBUF_PLL_CTRL_RESET_SHIFT 0
#define AVBUF_PLL_STATUS 0x00000044
#define AVBUF_REG_OFFSET 4
#define AVBUF_PLL_CTRL_BYPASS_MASK 0x00000008
#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3
#define AVBUF_DOMAIN_SWITCH_CTRL 0x00000044
#define AVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00
#define AVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8
#define AVBUF_PLL_CFG 0x00000024
#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0
#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000
#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24
#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000
#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00
#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000
#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24
#define DP_INTERRUPT_SIG_STATE 0x0130
#define DP_INTR_STATUS 0x03A0
#define DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001
#define DP_INTR_HPD_EVENT_MASK 0x00000002
#define DP_INTR_HPD_PULSE_DETECTED_MASK 0x00000010
#define DP_HPD_DURATION 0x0150
#define DP_FORCE_SCRAMBLER_RESET 0x00C0
#define DP_ENABLE_MAIN_STREAM 0x0084
#define DP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50
#define DP_0_LINK_RATE 20
#define DP_0_LANE_COUNT 1
#define DP_ENHANCED_FRAME_EN 0x0008
#define DP_LANE_COUNT_SET 0x0004
#define DP_LINK_BW_SET_162GBPS 0x06
#define DP_LINK_BW_SET_270GBPS 0x0A
#define DP_LINK_BW_SET_540GBPS 0x14
#define DP_LINK_BW_SET 0x0000
#define DP_DOWNSPREAD_CTRL 0x0018
#define DP_SCRAMBLING_DISABLE 0x0014
#define DP_AUX_CMD_READ 0x9
#define DP_AUX_CMD_WRITE 0x8
#define DP_AUX_CMD_I2C_READ 0x1
#define DP_AUX_CMD_I2C_READ_MOT 0x5
#define DP_AUX_CMD_I2C_WRITE 0x0
#define DP_AUX_CMD_I2C_WRITE_MOT 0x4
#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002
#define DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004
#define DP_REPLY_STATUS 0x014C
#define DP_AUX_MAX_TIMEOUT_COUNT 50
#define DP_AUX_MAX_DEFER_COUNT 50
#define DP_AUX_ADDRESS 0x0108
#define DP_AUX_WRITE_FIFO 0x0104
#define DP_AUX_CMD 0x0100
#define DP_AUX_CMD_SHIFT 8
#define DP_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F
#define DP_AUX_REPLY_CODE 0x0138
#define DP_AUX_REPLY_CODE_DEFER 0x2
#define DP_AUX_REPLY_CODE_I2C_DEFER 0x8
#define DP_AUX_REPLY_CODE_NACK 0x1
#define DP_AUX_REPLY_CODE_I2C_NACK 0x4
#define DP_REPLY_DATA_COUNT 0x0148
#define DP_AUX_REPLY_DATA 0x0134
#define DP_LANE_COUNT_SET_1 0x01
#define DP_LANE_COUNT_SET_2 0x02
#define DP_MAXIMUM_PE_LEVEL 2
#define DP_MAXIMUM_VS_LEVEL 3
#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB 0x0
#define DP_MAIN_STREAM_MISC0_BDC_6BPC 0x0
#define DP_MAIN_STREAM_MISC0_BDC_8BPC 0x1
#define DP_MAIN_STREAM_MISC0_BDC_10BPC 0x2
#define DP_MAIN_STREAM_MISC0_BDC_12BPC 0x3
#define DP_MAIN_STREAM_MISC0_BDC_16BPC 0x4
#define DP_MAIN_STREAM_MISC0_BDC_SHIFT 5
#define DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK 0x0010000
#define DP_PHY_CONFIG_PHY_RESET_MASK 0x0000001
#define DP_ENABLE_MAIN_STREAM 0x0084
#define DP_SOFT_RESET 0x001C
#define DP_MAIN_STREAM_HTOTAL 0x0180
#define DP_MAIN_STREAM_VTOTAL 0x0184
#define DP_MAIN_STREAM_POLARITY 0x0188
#define DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT 1
#define DP_MAIN_STREAM_HSWIDTH 0x018C
#define DP_MAIN_STREAM_VSWIDTH 0x0190
#define DP_MAIN_STREAM_HRES 0x0194
#define DP_MAIN_STREAM_VRES 0x0198
#define DP_MAIN_STREAM_HSTART 0x019C
#define DP_MAIN_STREAM_VSTART 0x01A0
#define DP_MAIN_STREAM_MISC0 0x01A4
#define DP_MAIN_STREAM_MISC1 0x01A8
#define DP_M_VID 0x01AC
#define DP_N_VID 0x01B4
#define DP_USER_PIXEL_WIDTH 0x01B8
#define DP_USER_DATA_COUNT_PER_LANE 0x01BC
#define DP_TU_SIZE 0x01B0
#define DP_MIN_BYTES_PER_TU 0x01C4
#define DP_FRAC_BYTES_PER_TU 0x01C8
#define DP_INIT_WAIT 0x01CC
#define DP_PHY_CLOCK_SELECT_162GBPS 0x1
#define DP_PHY_CLOCK_SELECT_270GBPS 0x3
#define DP_PHY_CLOCK_SELECT_540GBPS 0x5
#define DP_PHY_STATUS 0x0280
#define DP_PHY_STATUS_ALL_LANES_READY_MASK 0x00000013
#define DP_PHY_STATUS_GT_PLL_LOCK_MASK 0x00000010
#define DP_PHY_STATUS_RESET_LANE_0_DONE_MASK 0x00000001
#define DP_INTR_HPD_IRQ_MASK 0x00000001
#define DP_INTR_MASK 0x03A4
#define DP_DP_ENABLE 0x1
#define DP_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003
#define DP_PHY_CLOCK_SELECT 0x0234
#define DP_AUX_CLK_DIVIDER_VAL_MASK 0x000000FF
#define DP_AUX_CLK_DIVIDER 0x010C
#define DP_DISABLE 0x0
#define DP_ENABLE 0x0080
#define DP_SOFT_RESET_EN 0x1
#define DP_PHY_CONFIG 0x0200
#define DP_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001
#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002
#define DP_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008
#define DP_AUX_MAX_WAIT 20000
#define DP_DPCD_SINK_COUNT 0x00200
#define DP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
#define DP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
#define DP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
#define DP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
#define DP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
#define DP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
#define DP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
#define DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK 0x01
#define DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
#define DP_DPCD_TRAINING_LANE0_SET 0x00103
#define DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
#define DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
#define DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
#define DP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
#define DP_DPCD_RECEIVER_CAP_FIELD_START 0x00000
#define DP_DPCD_MAX_LINK_RATE 0x00001
#define DP_DPCD_MAX_LANE_COUNT 0x00002
#define DP_DPCD_MAX_LANE_COUNT_MASK 0x1F
#define DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
#define DP_DPCD_MAX_DOWNSPREAD 0x00003
#define DP_DPCD_MAX_DOWNSPREAD_MASK 0x01
#define DP_DPCD_LANE_COUNT_SET 0x00101
#define DP_DPCD_ENHANCED_FRAME_EN_MASK 0x80
#define DP_DPCD_LINK_BW_SET 0x00100
#define DP_DPCD_DOWNSPREAD_CTRL 0x00107
#define DP_DPCD_SPREAD_AMP_MASK 0x10
#define DP_DPCD_LANE_COUNT_SET_MASK 0x1F
#define DP_DPCD_TPS3_SUPPORT_MASK 0x40
#define DP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
#define DP_DPCD_SINK_COUNT_HIGH_MASK 0x80
#define DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1
#define DP_DPCD_SINK_COUNT_LOW_MASK 0x3F
#define DP_DPCD_TP_SET 0x00102
#define SERDES_BASEADDR 0xFD400000
#define SERDES_L0_TX_MARGININGF 0x0CC0
#define SERDES_L0_TX_DEEMPHASIS 0x0048
#define SERDES_LANE_OFFSET 0x4000
#define DPDMA_TRIGGER_EN 1U
#define DPDMA_RETRIGGER_EN 2U
#define DPDMA_DESC_PREAMBLE 0xA5U
#define DPDMA_DESC_IGNR_DONE 0x400U
#define DPDMA_DESC_LAST_FRAME 0x200000U
#define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT 18
#define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH 32U
#define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT 16U
#define DPDMA_CH0_DSCR_STRT_ADDR 0X0204U
#define DPDMA_CH_OFFSET 0x100U
#define DPDMA_CH0_CNTL 0x0218U
#define DPDMA_CH3_CNTL 0x0518U
#define DPDMA_CH0_DSCR_STRT_ADDRE 0x0200U
#define DPDMA_CH3_DSCR_STRT_ADDR 0x0504
#define DPDMA_CH3_DSCR_STRT_ADDRE 0x0500
#define DPDMA_CH_CNTL_EN_MASK 0x1U
#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U
#define DPDMA_GBL 0x0104U
#define DPDMA_GBL_TRG_CH3_MASK 0x8
#define DPDMA_TRIGGER_DONE 0U
#define DPDMA_CH_CNTL_EN_MASK 0x1U
#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U
#define DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT 10U
#define DPDMA_CH_CNTL_QOS_DATA_RD_MASK 0x3C00U
#define DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT 6U
#define DPDMA_CH_CNTL_QOS_DSCR_RD_MASK 0x03C0U
#define DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT 2U
#define DPDMA_CH_CNTL_QOS_DSCR_WR_MASK 0x3CU
#define DPDMA_CH_OFFSET 0x100U
#define DPDMA_WAIT_TIMEOUT 10000U
#define DPDMA_AUDIO_ALIGNMENT 128U
#define DPDMA_VIDEO_CHANNEL0 0U
#define DPDMA_VIDEO_CHANNEL1 1U
#define DPDMA_VIDEO_CHANNEL2 2U
#define DPDMA_GRAPHICS_CHANNEL 3U
#define DPDMA_AUDIO_CHANNEL0 4U
#define DPDMA_AUDIO_CHANNEL1 5U
#define DPDMA_DESC_PREAMBLE 0xA5U
#define DPDMA_DESC_IGNR_DONE 0x400U
#define DPDMA_DESC_UPDATE 0x200U
#define DPDMA_DESC_COMP_INTR 0x100U
#define DPDMA_DESC_LAST_FRAME 0x200000U
#define DPDMA_DESC_DONE_SHIFT 31U
#define DPDMA_QOS_MIN 4U
#define DPDMA_QOS_MAX 11U
#define DPDMA_BASE_ADDRESS 0xFD4C0000
#define DPDMA_ISR 0x0004U
#define DPDMA_IEN 0x000CU
#define DPDMA_ISR_VSYNC_INT_MASK 0x08000000
#define CLK_FPD_BASEADDR 0xFD1A0000
#define VIDEO_REF_CTRL 0x00000070
#define VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007
#define PLL_OUT_FREQ 1450000000
#define INPUT_FREQ_PRECISION 100
#define PRECISION 16
#define SHIFT_DECIMAL BIT(16)
#define ENABLE_BIT 1
#define DISABLE_BIT 0
#define PLL_CTRL_BYPASS_SHIFT 3
#define PLL_CTRL_FBDIV_SHIFT 8
#define PLL_CTRL_DIV2_SHIFT 16
#define PLL_CTRL_PRE_SRC_SHIFT 20
#define PLL_CTRL 0x00000020
#define VPLL_CTRL 0x00000038
#define PLL_CFG 0x00000024
#define VPLL 2
#define VPLL_CFG 0x0000003C
#define VPLL_CFG_CP 4
#define VPLL_CFG_RES 6
#define VPLL_CFG_LFHF 3
#define VPLL_CFG_LOCK_DLY 63
#define VPLL_CFG_LOCK_CNT 600
#define PLL_STATUS_VPLL_LOCK 2
#define PLL_CFG_CP_SHIFT 5
#define PLL_CFG_RES_SHIFT 0
#define PLL_CFG_LFHF_SHIFT 10
#define PLL_CFG_LOCK_DLY_SHIFT 25
#define PLL_CFG_LOCK_CNT_SHIFT 13
#define PLL_FRAC_CFG 0x00000028
#define VPLL_FRAC_CFG 0x00000040
#define PLL_FRAC_CFG_ENABLED_SHIFT 31
#define PLL_FRAC_CFG_DATA_SHIFT 0
#define PLL_CTRL_RESET_MASK 0x00000001
#define PLL_CTRL_RESET_SHIFT 0
#define PLL_STATUS 0x00000044
#define REG_OFFSET 4
#define PLL_CTRL_BYPASS_MASK 0x00000008
#define PLL_CTRL_BYPASS_SHIFT 3
#define DOMAIN_SWITCH_CTRL 0x00000044
#define DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00
#define DOMAIN_SWITCH_DIVISOR0_SHIFT 8
#define VIDEO_REF_CTRL_CLKACT_MASK 0x01000000
#define VIDEO_REF_CTRL_CLKACT_SHIFT 24
#define VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000
#define VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
#define VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00
#define VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
#define PSS_REF_CLK 0
#define FPD_CTRL_OFFSET 12
#define VIDC_VM_NUM_SUPPORTED 2
static const u32 vs[4][4] = {
{ 0x2a, 0x27, 0x24, 0x20 },
{ 0x27, 0x23, 0x20, 0xff },
{ 0x24, 0x20, 0xff, 0xff },
{ 0xff, 0xff, 0xff, 0xff },
};
static const u32 pe[4][4] = {
{ 0x02, 0x02, 0x02, 0x02 },
{ 0x01, 0x01, 0x01, 0xff },
{ 0x00, 0x00, 0xff, 0xff },
{ 0xff, 0xff, 0xff, 0xff },
};
const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] = {
{ VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ,
{640, 16, 96, 48, 800, 0,
480, 10, 2, 33, 525, 0, 0, 0, 0, 0} },
{ VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ,
{1024, 24, 136, 160, 1344, 0,
768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
};
const struct av_buf_vid_attribute avbuf_supported_formats[] = {
/* Non-Live Graphics formats */
{ RGBA8888, 0, INTERLEAVED,
{AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF},
0, 1, 0, 32},
};
#endif

66
drivers/video/zynqmp_dpsub.c
View File

@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Xilinx Inc.
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <video.h>
#include <dm/device_compat.h>
#define WIDTH 640
#define HEIGHT 480
/**
* struct zynqmp_dpsub_priv - Private structure
* @dev: Device uclass for video_ops
*/
struct zynqmp_dpsub_priv {
struct udevice *dev;
};
static int zynqmp_dpsub_probe(struct udevice *dev)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct zynqmp_dpsub_priv *priv = dev_get_priv(dev);
uc_priv->bpix = VIDEO_BPP16;
uc_priv->xsize = WIDTH;
uc_priv->ysize = HEIGHT;
uc_priv->rot = 0;
priv->dev = dev;
/* Only placeholder for power domain driver */
return 0;
}
static int zynqmp_dpsub_bind(struct udevice *dev)
{
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = WIDTH * HEIGHT * 16;
return 0;
}
static const struct video_ops zynqmp_dpsub_ops = {
};
static const struct udevice_id zynqmp_dpsub_ids[] = {
{ .compatible = "xlnx,zynqmp-dpsub-1.7" },
{ }
};
U_BOOT_DRIVER(zynqmp_dpsub_video) = {
.name = "zynqmp_dpsub_video",
.id = UCLASS_VIDEO,
.of_match = zynqmp_dpsub_ids,
.ops = &zynqmp_dpsub_ops,
.plat_auto = sizeof(struct video_uc_plat),
.bind = zynqmp_dpsub_bind,
.probe = zynqmp_dpsub_probe,
.priv_auto = sizeof(struct zynqmp_dpsub_priv),
};

4
dts/Kconfig
View File

@ -171,7 +171,7 @@ config OF_LIST
default DEFAULT_DEVICE_TREE
help
This option specifies a list of device tree files to use for DT
control. These will be packaged into a FIT. At run-time, U-boot
control. These will be packaged into a FIT. At run-time, U-Boot
or SPL will select the correct DT to use by examining the
hardware (e.g. reading a board ID value). This is a list of
device tree files (without the directory or .dtb suffix)
@ -254,7 +254,7 @@ config DTB_RESELECT
config MULTI_DTB_FIT
bool "Support embedding several DTBs in a FIT image for u-boot"
help
This option provides hooks to allow U-boot to parse an
This option provides hooks to allow U-Boot to parse an
appended FIT image and enable board specific code to then select
the correct DTB to be used. Use this if you need to support
multiple DTBs but don't use the SPL.

2
fs/btrfs/compat.h
View File

@ -46,7 +46,7 @@
/*
* Read data from device specified by @desc and @part
*
* U-boot equivalent of pread().
* U-Boot equivalent of pread().
*
* Return the bytes of data read.
* Return <0 for error.

2
fs/btrfs/extent-io.h
View File

@ -8,7 +8,7 @@
* Use pointer to provide better alignment.
* - Remove max_cache_size related interfaces
* Includes free_extent_buffer_nocache()
* As we don't cache eb in U-boot.
* As we don't cache eb in U-Boot.
* - Include headers
*
* Write related functions are kept as we still need to modify dummy extent

3
include/configs/xilinx_zynqmp.h
View File

@ -60,6 +60,9 @@
"scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_size_f=0x80000\0" \
"stdin=serial\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)

4
include/fsl_validate.h
View File

@ -275,9 +275,9 @@ int fsl_check_boot_mode_secure(void);
int fsl_setenv_chain_of_trust(void);
/*
* This function is used to validate the main U-boot binary from
* This function is used to validate the main U-Boot binary from
* SPL just before passing control to it using QorIQ Trust
* Architecture header (appended to U-boot image).
* Architecture header (appended to U-Boot image).
*/
void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr);

1
include/video.h
View File

@ -64,6 +64,7 @@ enum video_log2_bpp {
enum video_format {
VIDEO_UNKNOWN,
VIDEO_RGBA8888,
VIDEO_X8B8G8R8,
VIDEO_X8R8G8B8,
VIDEO_X2R10G10B10,

2
include/zynqmp_firmware.h
View File

@ -35,7 +35,7 @@ enum pm_api_id {
PM_FPGA_LOAD = 22,
PM_FPGA_GET_STATUS = 23,
PM_GET_CHIPID = 24,
/* ID 25 is been used by U-boot to process secure boot images */
/* ID 25 is been used by U-Boot to process secure boot images */
/* Secure library generic API functions */
PM_SECURE_SHA = 26,
PM_SECURE_RSA = 27,

2
test/py/tests/test_android/test_avb.py
View File

@ -5,7 +5,7 @@
# Android Verified Boot 2.0 Test
"""
This tests Android Verified Boot 2.0 support in U-boot:
This tests Android Verified Boot 2.0 support in U-Boot:
For additional details about how to build proper vbmeta partition
check doc/android/avb2.rst

2
test/py/tests/test_cat/conftest.py
View File

@ -13,7 +13,7 @@ def cat_data(u_boot_config):
"""Set up a file system to be used in cat tests
Args:
u_boot_config -- U-boot configuration.
u_boot_config -- U-Boot configuration.
"""
mnt_point = u_boot_config.persistent_data_dir + '/test_cat'
image_path = u_boot_config.persistent_data_dir + '/cat.img'

2
test/py/tests/test_efi_bootmgr/conftest.py
View File

@ -12,7 +12,7 @@ def efi_bootmgr_data(u_boot_config):
"""Set up a file system to be used in UEFI bootmanager tests.
Args:
u_boot_config -- U-boot configuration.
u_boot_config -- U-Boot configuration.
Return:
A path to disk image to be used for testing

2
test/py/tests/test_efi_capsule/conftest.py
View File

@ -17,7 +17,7 @@ def efi_capsule_data(request, u_boot_config):
for testing.
request -- Pytest request object.
u_boot_config -- U-boot configuration.
u_boot_config -- U-Boot configuration.
"""
mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
data_dir = mnt_point + CAPSULE_DATA_DIR

4
test/py/tests/test_efi_secboot/conftest.py
View File

@ -14,7 +14,7 @@ def efi_boot_env(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A path to disk image to be used for testing
@ -139,7 +139,7 @@ def efi_boot_env_intca(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A path to disk image to be used for testing

2
test/py/tests/test_eficonfig/conftest.py
View File

@ -14,7 +14,7 @@ def efi_eficonfig_data(u_boot_config):
tests
Args:
u_boot_config -- U-boot configuration.
u_boot_config -- U-Boot configuration.
Return:
A path to disk image to be used for testing

12
test/py/tests/test_fs/conftest.py
View File

@ -97,7 +97,7 @@ def pytest_generate_tests(metafunc):
# Helper functions
#
def fstype_to_ubname(fs_type):
"""Convert a file system type to an U-boot specific string
"""Convert a file system type to an U-Boot specific string
A generated string can be used as part of file system related commands
or a config name in u-boot. Currently fat16 and fat32 are handled
@ -217,7 +217,7 @@ def fs_obj_basic(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A fixture for basic fs test, i.e. a triplet of file system type,
@ -339,7 +339,7 @@ def fs_obj_ext(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A fixture for extended fs test, i.e. a triplet of file system type,
@ -440,7 +440,7 @@ def fs_obj_mkdir(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A fixture for mkdir test, i.e. a duplet of file system type and
@ -471,7 +471,7 @@ def fs_obj_unlink(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A fixture for unlink test, i.e. a duplet of file system type and
@ -551,7 +551,7 @@ def fs_obj_symlink(request, u_boot_config):
Args:
request: Pytest request object.
u_boot_config: U-boot configuration.
u_boot_config: U-Boot configuration.
Return:
A fixture for basic fs test, i.e. a triplet of file system type,

2
test/py/tests/test_scp03.py
View File

@ -5,7 +5,7 @@
# SCP03 command test
"""
This tests SCP03 command in U-boot.
This tests SCP03 command in U-Boot.
For additional details check doc/usage/scp03.rst
"""

2
test/py/tests/test_xxd/conftest.py
View File

@ -13,7 +13,7 @@ def xxd_data(u_boot_config):
"""Set up a file system to be used in xxd tests
Args:
u_boot_config -- U-boot configuration.
u_boot_config -- U-Boot configuration.
"""
mnt_point = u_boot_config.persistent_data_dir + '/test_xxd'
image_path = u_boot_config.persistent_data_dir + '/xxd.img'

2
tools/relocate-rela.c
View File

@ -521,7 +521,7 @@ static int rela_elf32(char **argv, FILE *f)
uint32_t pos = rela_start + sizeof(Elf32_Rela) * i;
uint32_t addr, pos_dyn;
debug("\nPossition:\t%d/0x%x\n", i, pos);
debug("\nPosition:\t%d/0x%x\n", i, pos);
if (fseek(f, pos, SEEK_SET) < 0) {
fprintf(stderr, "%s: %s: seek to %" PRIx32